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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-27 21:42:37 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:53:35 +0200 |
| commit | fc7dd515374455f07cdd24b8bad3c7952e812bff (patch) | |
| tree | c7effaf4cd80c7e7854d4276b67dc721e6a9ac9d /tools/perf/scripts/python | |
| parent | clk: renesas: r9a09g056: Add XSPI clock/reset (diff) | |
| download | wireguard-linux-fc7dd515374455f07cdd24b8bad3c7952e812bff.tar.xz wireguard-linux-fc7dd515374455f07cdd24b8bad3c7952e812bff.zip | |
clk: renesas: r9a09g057: Add XSPI clock/reset
Add clock and reset entries for the XSPI interface on the R9A09G057 SoC.
While at it, rename CLK_PLLCM33_DIV4_PLLCM33 to CLK_PLLCM33_GEAR to align
with the terminology used in the hardware manual.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions