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| author |   André Draszik <andre.draszik@linaro.org> | 2025-06-03 16:43:20 +0100 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-06-10 10:21:21 +0200 |
| commit | ca243e653f71d8c4724a68c9033923f945b1084d (patch) | |
| tree | b2f0a29cfad83945135540fcf6168be7b9e3b29f /tools/perf/scripts | |
| parent | clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD (diff) | |
| download | wireguard-linux-ca243e653f71d8c4724a68c9033923f945b1084d.tar.xz wireguard-linux-ca243e653f71d8c4724a68c9033923f945b1084d.zip | |
clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
The alternate parent clock for this mux is mout_pll_usb, not the pll
itself.
Fixes: 1891e4d48755 ("clk: samsung: gs101: add support for cmu_hsi0")
Cc: stable@vger.kernel.org
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250603-samsung-clk-fixes-v1-2-49daf1ff4592@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts')
0 files changed, 0 insertions, 0 deletions