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| author |   James Morse <james.morse@arm.com> | 2022-09-30 14:19:59 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2022-10-07 14:42:20 +0100 |
| commit | 171df58028bf4649460fb146a56a58dcb0c8f75a (patch) | |
| tree | f2d404265dbde354b2f6768c8c66e3eab4015e19 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | arm64/sysreg: Fix typo in SCTR_EL1.SPINTMASK (diff) | |
| download | wireguard-linux-171df58028bf4649460fb146a56a58dcb0c8f75a.tar.xz wireguard-linux-171df58028bf4649460fb146a56a58dcb0c8f75a.zip | |
arm64: errata: Add Cortex-A55 to the repeat tlbi list
Cortex-A55 is affected by an erratum where in rare circumstances the
CPUs may not handle a race between a break-before-make sequence on one
CPU, and another CPU accessing the same page. This could allow a store
to a page that has been unmapped.
Work around this by adding the affected CPUs to the list that needs
TLB sequences to be done twice.
Signed-off-by: James Morse <james.morse@arm.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220930131959.3082594-1-james.morse@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions