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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:13 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:42:55 +0200 |
| commit | 8684a24caa3d59d9ba03f1e6f9653b49ac78ec04 (patch) | |
| tree | 71099ca8724746fd598c231e541cd2d917af07e1 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core (diff) | |
| download | wireguard-linux-8684a24caa3d59d9ba03f1e6f9653b49ac78ec04.tar.xz wireguard-linux-8684a24caa3d59d9ba03f1e6f9653b49ac78ec04.zip | |
ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions