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| author |   Stephen Boyd <sboyd@codeaurora.org> | 2015-08-25 15:55:28 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-08-25 15:55:28 -0700 |
| commit | a7c602bf42f943e717eed92165ebfa6dbaba3029 (patch) | |
| tree | 3c32bc1572acb102ba86c53005ca83cf0c632fd1 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | clk: qcom: Fix MSM8916 prng clock enable bit (diff) | |
| parent | clk: tegra: Add the DFLL as a possible parent of the cclk_g clock (diff) | |
| download | wireguard-linux-a7c602bf42f943e717eed92165ebfa6dbaba3029.tar.xz wireguard-linux-a7c602bf42f943e717eed92165ebfa6dbaba3029.zip | |
Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.3-rc1
This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions