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author | 2022-05-25 22:04:25 +0300 | |
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committer | 2022-06-27 11:27:10 +0200 | |
commit | cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b (patch) | |
tree | 900c2f3b78f284399c97c8810703c943486ac6af /tools/perf/util/scripting-engines/trace-event-python.c | |
parent | Merge tag 'intel-pinctrl-v5.19-3' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes (diff) | |
download | wireguard-linux-cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b.tar.xz wireguard-linux-cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b.zip |
pinctrl: sunxi: sunxi_pconf_set: use correct offset
Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
Previous implementation used absolute pin numbering and it was incorrect
for R_PIO pinctrl.
It's necessary to take into account the base pin number.
Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set")
Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220525190423.410609-1-andrey.lalaev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions