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author | 2013-09-13 09:57:50 -0400 | |
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committer | 2013-09-15 20:27:49 -0400 | |
commit | ce7b30e02578dda6b2263b05308c640f3b57d32c (patch) | |
tree | a2a80afda62aae00b89c3ebd64d9b4f803654fb1 /tools/perf/util/scripting-engines/trace-event-python.c | |
parent | drm/radeon/dpm/rs780: use drm_mode_vrefresh() (diff) | |
download | wireguard-linux-ce7b30e02578dda6b2263b05308c640f3b57d32c.tar.xz wireguard-linux-ce7b30e02578dda6b2263b05308c640f3b57d32c.zip |
drm/radeon/dpm/rs780: add some sanity checking to sclk scaling
Since the clock scaling is based on fb divider adjustments,
make sure the other pll parameters are the same.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions