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| author |   Florian Fainelli <f.fainelli@gmail.com> | 2017-03-09 10:51:20 -0800 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2017-03-15 14:57:50 -0700 |
| commit | d47b51ad31e21ab8129da64d42e2fc48e7a215eb (patch) | |
| tree | 3f25bbe459e0ecf6af7bd25de4efad08f730afde /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: brcmstb: Enable ARCH_HAS_HOLES_MEMORYMODEL (diff) | |
| download | wireguard-linux-d47b51ad31e21ab8129da64d42e2fc48e7a215eb.tar.xz wireguard-linux-d47b51ad31e21ab8129da64d42e2fc48e7a215eb.zip | |
ARM: brcmstb: Add entry for 7260
BCM7260 has the same UART base address as 7268, order the entries by
ascending chip number and alias the 7268 definition to the 7260
definition.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions