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| author |   Marc Zyngier <maz@kernel.org> | 2022-07-10 09:51:20 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-07-10 09:51:20 +0100 |
| commit | d4a930a08c2664662e08e9a895c4d10fd30c04d9 (patch) | |
| tree | 6c2a5712d2bcd43d19130bffd04685a3e4e26524 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | Merge branch irq/stm32-exti-updates into irq/irqchip-next (diff) | |
| parent | irqchip/sifive-plic: Separate the enable and mask operations (diff) | |
| download | wireguard-linux-d4a930a08c2664662e08e9a895c4d10fd30c04d9.tar.xz wireguard-linux-d4a930a08c2664662e08e9a895c4d10fd30c04d9.zip | |
Merge branch irq/plic-masking into irq/irqchip-next
* irq/plic-masking:
: .
: SiFive PLIC optimisations from Samuel Holland:
:
: "This series removes the spinlocks and cpumask operations from the PLIC
: driver's hot path. As far as I know, using the priority to mask
: interrupts is an intended usage and will work on all existing
: implementations. [...]"
: .
irqchip/sifive-plic: Separate the enable and mask operations
irqchip/sifive-plic: Make better use of the effective affinity mask
PCI: hv: Take a const cpumask in hv_compose_msi_req_get_cpu()
genirq: Provide an IRQ affinity mask in non-SMP configs
genirq: Return a const cpumask from irq_data_get_affinity_mask
genirq: Add and use an irq_data_update_affinity helper
genirq: Refactor accessors to use irq_data_get_affinity_mask
genirq: Drop redundant irq_init_effective_affinity
genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP
genirq: GENERIC_IRQ_IPI depends on SMP
irqchip/mips-gic: Only register IPI domain when SMP is enabled
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions