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| author |   Tero Kristo <t-kristo@ti.com> | 2014-10-03 16:57:11 +0300 |
|---|---|---|
| committer |   Paul Walmsley <paul@pwsan.com> | 2014-11-13 09:26:16 -0700 |
| commit | d539efa37f1f789339699c941e72e320d12d5f28 (patch) | |
| tree | 8256b57b68bd582e1d8440be29cb6bb74d53abc2 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: OMAP3: clock: use clk_features flags for omap3 DPLL4 checks (diff) | |
| download | wireguard-linux-d539efa37f1f789339699c941e72e320d12d5f28.tar.xz wireguard-linux-d539efa37f1f789339699c941e72e320d12d5f28.zip | |
ARM: OMAP3: clock: add new rate changing logic support for noncore DPLLs
Currently, DPLL code hides the re-parenting within its internals, which
is wrong. This needs to be exposed to the common clock code via
determine_rate and set_rate_and_parent APIs. This patch adds support
for these, which will be taken into use in the following patches.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions