diff options
| author |   Stephen Warren <swarren@nvidia.com> | 2012-02-14 13:39:39 -0700 |
|---|---|---|
| committer |   Olof Johansson <olof@lixom.net> | 2012-02-26 14:24:51 -0800 |
| commit | f35b431dde39fb40944d1024f08d88fbf04a3193 (patch) | |
| tree | 5a8f1dbb1e82cbfa5a50db981e1e68580f1b598d /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | ARM: tegra: paz00: fix wrong UART port on mini-pcie plug (diff) | |
| download | wireguard-linux-f35b431dde39fb40944d1024f08d88fbf04a3193.tar.xz wireguard-linux-f35b431dde39fb40944d1024f08d88fbf04a3193.zip | |
ARM: tegra: select required CPU and L2 errata options
The ARM IP revisions in Tegra are:
Tegra20: CPU r1p1, PL310 r2p0
Tegra30: CPU A01=r2p7/>=A02=r2p9, NEON r2p3-50, PL310 r3p1-50
Based on work by Olof Johansson, although the actual list of errata is
somewhat different here, since I added a bunch more and removed one PL310
erratum that doesn't seem applicable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cc: stable@vger.kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions