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authorKan Liang <kan.liang@linux.intel.com>2023-01-04 12:13:48 -0800
committerArnaldo Carvalho de Melo <acme@redhat.com>2023-02-03 17:24:02 -0300
commitd7d213e04cf83318681f24870f1144e50d5c91bb (patch)
tree8d1886bcb767c03cd12d788cf76b10af2d33735f /tools/perf/util/sort.c
parentperf lock contention: Support filters for different aggregation (diff)
downloadwireguard-linux-d7d213e04cf83318681f24870f1144e50d5c91bb.tar.xz
wireguard-linux-d7d213e04cf83318681f24870f1144e50d5c91bb.zip
perf report: Support Retire Latency
The Retire Latency field is added in the var3_w of the PERF_SAMPLE_WEIGHT_STRUCT. The Retire Latency reports pipeline stall of this instruction compared to the previous instruction in cycles. That's quite useful to display the information with perf mem report. The p_stage_cyc for Power is also from the var3_w. Union the p_stage_cyc and retire_lat to share the code. Implement X86 specific codes to display the X86 specific header. Add a new sort key retire_lat for the Retire Latency. Reviewed-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Link: http://lore.kernel.org/lkml/20230104201349.1451191-8-kan.liang@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/util/sort.c')
-rw-r--r--tools/perf/util/sort.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c
index d7d0f997873a..4a648231fe72 100644
--- a/tools/perf/util/sort.c
+++ b/tools/perf/util/sort.c
@@ -2133,6 +2133,8 @@ static struct sort_dimension common_sort_dimensions[] = {
DIM(SORT_LOCAL_PIPELINE_STAGE_CYC, "local_p_stage_cyc", sort_local_p_stage_cyc),
DIM(SORT_GLOBAL_PIPELINE_STAGE_CYC, "p_stage_cyc", sort_global_p_stage_cyc),
DIM(SORT_ADDR, "addr", sort_addr),
+ DIM(SORT_LOCAL_RETIRE_LAT, "local_retire_lat", sort_local_p_stage_cyc),
+ DIM(SORT_GLOBAL_RETIRE_LAT, "retire_lat", sort_global_p_stage_cyc),
};
#undef DIM