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| author |   Shiji Yang <yangshiji66@outlook.com> | 2026-02-24 10:22:50 +0800 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2026-04-01 21:51:02 +0200 |
| commit | 43985a62bab9d35e5e9af41118ce2f44c01b97d2 (patch) | |
| tree | 5cae3a42f76d4f6c3f72f55f8b6612edcf219a65 /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com | |
| parent | MIPS: Loongson64: env: Check UARTs passed by LEFI cautiously (diff) | |
mips: ralink: update CPU clock index
Update CPU clock index to match the clock driver changes.
Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions