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authorZhi Li <lizhi2@eswincomputing.com>2026-05-18 10:21:37 +0800
committerPaolo Abeni <pabeni@redhat.com>2026-05-21 11:58:17 +0200
commit6872fb088edc1a3c36792b301f8e4a1c35dd7c35 (patch)
tree8a61d704a68892b25b26223ee44628729543dd98 /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com
parentnet: stmmac: eswin: fix HSP CSR init ordering after clock enable (diff)
net: stmmac: eswin: clear TXD and RXD delay registers during initialization
Clear the TXD and RXD delay control registers during EIC7700 DWMAC initialization. These registers may retain values programmed by the bootloader. If left unchanged, residual delays can alter the effective RGMII timing seen by the MAC and override the configuration described by the device tree. This may violate the expected RGMII timing model and can cause link instability or prevent the Ethernet controller from operating correctly. Explicitly clearing these registers ensures that the MAC delay settings are determined solely by the kernel configuration. The corresponding register offsets are optional, and the registers are only cleared when the offsets are provided in the device tree. Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver") Signed-off-by: Zhi Li <lizhi2@eswincomputing.com> Link: https://patch.msgid.link/20260518022137.464-1-lizhi2@eswincomputing.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
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