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| author |   Dave Jiang <dave.jiang@intel.com> | 2026-04-03 12:18:23 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-04-03 12:18:23 -0700 |
| commit | 7aacc625576d4dc9c7d8a687f168ff72b30ca353 (patch) | |
| tree | 4ca6d40a9f9f165362275dc80cea9cfedb6dfe9f /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com | |
| parent | Merge branch 'for-7.1/cxl-consolidate-endpoint' into cxl-for-next (diff) | |
| parent | cxl/region: Factor out interleave granularity setup (diff) | |
Merge branch 'for-7.1/cxl-type2-support' into cxl-for-next
Prep patches for CXL type2 accelerator basic support
cxl/region: Factor out interleave granularity setup
cxl/region: Factor out interleave ways setup
cxl: Make region type based on endpoint type
cxl/pci: Remove redundant cxl_pci_find_port() call
cxl: Move pci generic code from cxl_pci to core/cxl_pci
cxl: export internal structs for external Type2 drivers
cxl: support Type2 when initializing cxl_dev_state
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions