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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2026-03-24 11:43:09 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-26 19:40:14 +0100 |
| commit | 867fb0bc60602cb3c2458fcd25c841650d37563f (patch) | |
| tree | 322484d1bc485b7213a618d6b10b698348096e93 /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com | |
| parent | clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries (diff) | |
clk: renesas: rzg2l: Add helper for mod clock enable/disable
Refactor rzg2l_mod_clock_endisable() by extracting its logic into a new
helper function rzg2l_mod_clock_endisable_helper(), which accepts an
additional set_mstop_state boolean parameter. This allows callers to
control whether the module stop state is updated alongside the clock
enable/disable operation. No functional change for existing callers.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260324114329.268249-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions