aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com
diff options
context:
space:
mode:
authorMarek Vasut <marek.vasut+renesas@mailbox.org>2026-03-26 05:24:01 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2026-04-27 11:14:30 +0200
commitca743e8ac2b41c295d5ee12ed231fccb52161a0b (patch)
treea01db2e22bae8465628f1b0694843264a3a44406 /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com
parentarm64: dts: renesas: rz-smarc-cru-csi-ov5645: Fix missing cells and reg in CSI2 subnode (diff)
arm64: dts: renesas: rz-smarc-du-adv7513-smarc: Fix missing cells and reg in DU subnode
Add missing cells and reg DT property in the DU subnode to fix the following DTC W=1 warning: arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi:29.10-33.5: Warning (unit_address_vs_reg): /fragment@1/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260326042411.215241-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions