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| author |   Marek Vasut <marek.vasut+renesas@mailbox.org> | 2026-03-26 05:23:58 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2026-04-27 11:14:30 +0200 |
| commit | d289b5f56ab7fe939dc5bfc87c856b46fe5def38 (patch) | |
| tree | e68b4b5a9b0dc491609cfe2565b37cc2306a04d7 /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com | |
| parent | arm64: dts: renesas: r8a78000: Fix SCIF brg_int clocks (diff) | |
arm64: dts: renesas: draak/ebisu-panel: Fix missing cells and reg in DTO
Add missing cells and reg DT property in the Draak/Ebisu panel DTO to
fix the following DTC W=1 warning:
arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso:30.10-34.5: Warning (unit_address_vs_reg): /fragment@2/__overlay__/ports/port@1: node has a unit name, but no reg or ranges property
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260326042411.215241-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions