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| author |   Svyatoslav Ryhel <clamor95@gmail.com> | 2026-02-02 10:05:26 +0200 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2026-02-05 17:16:24 +0100 |
| commit | e5b250214aa402e079de566e10f6e01223fd26bd (patch) | |
| tree | 4f0f18cbbaf5af164e06e3efb124c61a937cb97c /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com | |
| parent | usb: phy: tegra: parametrize HSIC PTS value (diff) | |
usb: phy: tegra: parametrize PORTSC1 register offset
The PORTSC1 register has a different offset in Tegra20 compared to
Tegra30+, yet they share a crucial set of registers required for HSIC
functionality. Reflect this register offset change in the SoC config.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://patch.msgid.link/20260202080526.23487-5-clamor95@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions