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authorAlexander Stein <alexander.stein@ew.tq-group.com>2026-03-17 13:19:52 +0100
committerAbel Vesa <abel.vesa@oss.qualcomm.com>2026-03-18 17:04:31 +0200
commitfca8688a6798f6fee6b86ce0bc39d1cd0b1c8b8a (patch)
tree16658fedadc7a125b4f9bd7f9aae1a8ae4ffe467 /tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com
parentdt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad (diff)
clk: imx: pll14xx: Use unsigned format specifier
The debug outputs use %d for clock rates resulting in negative clock rate during rate calculation. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://patch.msgid.link/20260317121953.1100619-1-alexander.stein@ew.tq-group.com Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Diffstat (limited to 'tools/testing/selftests/dm-verity/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions