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| author |   Andrew Jones <ajones@ventanamicro.com> | 2023-12-13 18:09:56 +0100 |
|---|---|---|
| committer |   Anup Patel <anup@brainfault.org> | 2023-12-29 12:31:47 +0530 |
| commit | 6ccf119a4cc886678099a3526f37db98b67024d7 (patch) | |
| tree | 3775c08b15df38cc0a51bfd8e8d6718487b238d4 /tools/testing/selftests/kvm/lib/riscv/processor.c | |
| parent | RISC-V: KVM: Make SBI uapi consistent with ISA uapi (diff) | |
| download | wireguard-linux-6ccf119a4cc886678099a3526f37db98b67024d7.tar.xz wireguard-linux-6ccf119a4cc886678099a3526f37db98b67024d7.zip | |
KVM: riscv: selftests: Add RISCV_SBI_EXT_REG
While adding RISCV_SBI_EXT_REG(), acknowledge that some registers
have subtypes and extend __kvm_reg_id() to take a subtype field.
Then, update all macros to set the new field appropriately. The
general CSR macro gets renamed to include "GENERAL", but the other
macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'tools/testing/selftests/kvm/lib/riscv/processor.c')
| -rw-r--r-- | tools/testing/selftests/kvm/lib/riscv/processor.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index d146ca71e0c0..6c25f7843ef4 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -201,7 +201,7 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; satp |= SATP_MODE_48; - vcpu_set_reg(vcpu, RISCV_CSR_REG(satp), satp); + vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); } void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent) @@ -315,7 +315,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); /* Setup default exception vector of guest */ - vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap); + vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)guest_unexp_trap); return vcpu; } |