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290 files changed, 98743 insertions, 2629 deletions
diff --git a/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp b/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp new file mode 100644 index 000000000000..00fa04c76ff3 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-driver-firmware-zynqmp @@ -0,0 +1,103 @@ +What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs* +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + Read/Write PMU global general storage register value, + GLOBAL_GEN_STORAGE{0:3}. + Global general storage register that can be used + by system to pass information between masters. + + The register is reset during system or power-on + resets. Three registers are used by the FSBL and + other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0 + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs* +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + Read/Write PMU persistent global general storage register + value, PERS_GLOB_GEN_STORAGE{0:3}. + Persistent global general storage register that + can be used by system to pass information between + masters. + + This register is only reset by the power-on reset + and maintains its value through a system reset. + Four registers are used by the FSBL and other Xilinx + software products: PERS_GLOB_GEN_STORAGE{4:7}. + Register is reset only by a POR reset. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0 + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + This sysfs interface allows to set the shutdown scope for the + next shutdown request. When the next shutdown is performed, the + platform specific portion of PSCI-system_off can use the chosen + shutdown scope. + + Following are available shutdown scopes(subtypes): + + subsystem: Only the APU along with all of its peripherals + not used by other processing units will be + shut down. This may result in the FPD power + domain being shut down provided that no other + processing unit uses FPD peripherals or DRAM. + ps_only: The complete PS will be shut down, including the + RPU, PMU, etc. Only the PL domain (FPGA) + remains untouched. + system: The complete system/device is shut down. + + Usage: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + # echo <scope> > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + + Example: + # cat /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + # echo "subsystem" > /sys/devices/platform/firmware\:zynqmp-firmware/shutdown_scope + +Users: Xilinx + +What: /sys/devices/platform/firmware\:zynqmp-firmware/health_status +Date: March 2020 +KernelVersion: 5.6 +Contact: "Jolly Shah" <jollys@xilinx.com> +Description: + This sysfs interface allows to set the health status. If PMUFW + is compiled with CHECK_HEALTHY_BOOT, it will check the healthy + bit on FPD WDT expiration. If healthy bit is set by a user + application running in Linux, PMUFW will do APU only restart. If + healthy bit is not set during FPD WDT expiration, PMUFW will do + system restart. + + Usage: + Set healthy bit + # echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status + + Unset healthy bit + # echo 0 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status + +Users: Xilinx diff --git a/Documentation/ABI/testing/debugfs-driver-habanalabs b/Documentation/ABI/testing/debugfs-driver-habanalabs index a73601c5121e..f6d9c2a8d528 100644 --- a/Documentation/ABI/testing/debugfs-driver-habanalabs +++ b/Documentation/ABI/testing/debugfs-driver-habanalabs @@ -8,6 +8,16 @@ Description: Sets the device address to be used for read or write through only when the IOMMU is disabled. The acceptable value is a string that starts with "0x" +What: /sys/kernel/debug/habanalabs/hl<n>/clk_gate +Date: May 2020 +KernelVersion: 5.8 +Contact: oded.gabbay@gmail.com +Description: Allow the root user to disable/enable in runtime the clock + gating mechanism in Gaudi. Due to how Gaudi is built, the + clock gating needs to be disabled in order to access the + registers of the TPC and MME engines. This is sometimes needed + during debug by the user and hence the user needs this option + What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers Date: Jan 2019 KernelVersion: 5.1 @@ -150,3 +160,10 @@ KernelVersion: 5.1 Contact: oded.gabbay@gmail.com Description: Displays a list with information about all the active virtual address mappings per ASID + +What: /sys/kernel/debug/habanalabs/hl<n>/stop_on_err +Date: Mar 2020 +KernelVersion: 5.6 +Contact: oded.gabbay@gmail.com +Description: Sets the stop-on_error option for the device engines. Value of + "0" is for disable, otherwise enable. diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme b/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme new file mode 100644 index 000000000000..c9278a3b3df1 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-dfl_fme @@ -0,0 +1,104 @@ +What: /sys/bus/event_source/devices/dfl_fmeX/format +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. Attribute group to describe the magic bits + that go into perf_event_attr.config for a particular pmu. + (See ABI/testing/sysfs-bus-event_source-devices-format). + + Each attribute under this group defines a bit range of the + perf_event_attr.config. All supported attributes are listed + below. + + event = "config:0-11" - event ID + evtype = "config:12-15" - event type + portid = "config:16-23" - event source + + For example, + + fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff" + + It shows this fab_mmio_read is a fabric type (0x02) event with + 0x06 local event id for overall monitoring (portid=0xff). + +What: /sys/bus/event_source/devices/dfl_fmeX/cpumask +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. This file always returns cpu which the PMU is bound + for access to all fme pmu performance monitoring events. + +What: /sys/bus/event_source/devices/dfl_fmeX/events +Date: April 2020 +KernelVersion: 5.8 +Contact: Wu Hao <hao.wu@intel.com> +Description: Read-only. Attribute group to describe performance monitoring + events specific to fme. Each attribute in this group describes + a single performance monitoring event supported by this fme pmu. + The name of the file is the name of the event. + (See ABI/testing/sysfs-bus-event_source-devices-events). + + All supported performance monitoring events are listed below. + + Basic events (evtype=0x00) + + clock = "event=0x00,evtype=0x00,portid=0xff" + + Cache events (evtype=0x01) + + cache_read_hit = "event=0x00,evtype=0x01,portid=0xff" + cache_read_miss = "event=0x01,evtype=0x01,portid=0xff" + cache_write_hit = "event=0x02,evtype=0x01,portid=0xff" + cache_write_miss = "event=0x03,evtype=0x01,portid=0xff" + cache_hold_request = "event=0x05,evtype=0x01,portid=0xff" + cache_data_write_port_contention = + "event=0x06,evtype=0x01,portid=0xff" + cache_tag_write_port_contention = + "event=0x07,evtype=0x01,portid=0xff" + cache_tx_req_stall = "event=0x08,evtype=0x01,portid=0xff" + cache_rx_req_stall = "event=0x09,evtype=0x01,portid=0xff" + cache_eviction = "event=0x0a,evtype=0x01,portid=0xff" + + Fabric events (evtype=0x02) + + fab_pcie0_read = "event=0x00,evtype=0x02,portid=0xff" + fab_pcie0_write = "event=0x01,evtype=0x02,portid=0xff" + fab_pcie1_read = "event=0x02,evtype=0x02,portid=0xff" + fab_pcie1_write = "event=0x03,evtype=0x02,portid=0xff" + fab_upi_read = "event=0x04,evtype=0x02,portid=0xff" + fab_upi_write = "event=0x05,evtype=0x02,portid=0xff" + fab_mmio_read = "event=0x06,evtype=0x02,portid=0xff" + fab_mmio_write = "event=0x07,evtype=0x02,portid=0xff" + fab_port_pcie0_read = "event=0x00,evtype=0x02,portid=?" + fab_port_pcie0_write = "event=0x01,evtype=0x02,portid=?" + fab_port_pcie1_read = "event=0x02,evtype=0x02,portid=?" + fab_port_pcie1_write = "event=0x03,evtype=0x02,portid=?" + fab_port_upi_read = "event=0x04,evtype=0x02,portid=?" + fab_port_upi_write = "event=0x05,evtype=0x02,portid=?" + fab_port_mmio_read = "event=0x06,evtype=0x02,portid=?" + fab_port_mmio_write = "event=0x07,evtype=0x02,portid=?" + + VTD events (evtype=0x03) + + vtd_port_read_transaction = "event=0x00,evtype=0x03,portid=?" + vtd_port_write_transaction = "event=0x01,evtype=0x03,portid=?" + vtd_port_devtlb_read_hit = "event=0x02,evtype=0x03,portid=?" + vtd_port_devtlb_write_hit = "event=0x03,evtype=0x03,portid=?" + vtd_port_devtlb_4k_fill = "event=0x04,evtype=0x03,portid=?" + vtd_port_devtlb_2m_fill = "event=0x05,evtype=0x03,portid=?" + vtd_port_devtlb_1g_fill = "event=0x06,evtype=0x03,portid=?" + + VTD SIP events (evtype=0x04) + + vtd_sip_iotlb_4k_hit = "event=0x00,evtype=0x04,portid=0xff" + vtd_sip_iotlb_2m_hit = "event=0x01,evtype=0x04,portid=0xff" + vtd_sip_iotlb_1g_hit = "event=0x02,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l3_hit = "event=0x03,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l4_hit = "event=0x04,evtype=0x04,portid=0xff" + vtd_sip_rcc_hit = "event=0x05,evtype=0x04,portid=0xff" + vtd_sip_iotlb_4k_miss = "event=0x06,evtype=0x04,portid=0xff" + vtd_sip_iotlb_2m_miss = "event=0x07,evtype=0x04,portid=0xff" + vtd_sip_iotlb_1g_miss = "event=0x08,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l3_miss = "event=0x09,evtype=0x04,portid=0xff" + vtd_sip_slpwc_l4_miss = "event=0x0a,evtype=0x04,portid=0xff" + vtd_sip_rcc_miss = "event=0x0b,evtype=0x04,portid=0xff" diff --git a/Documentation/ABI/testing/sysfs-bus-soundwire-master b/Documentation/ABI/testing/sysfs-bus-soundwire-master new file mode 100644 index 000000000000..46ef038d8722 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-soundwire-master @@ -0,0 +1,23 @@ +What: /sys/bus/soundwire/devices/sdw-master-N/revision + /sys/bus/soundwire/devices/sdw-master-N/clk_stop_modes + /sys/bus/soundwire/devices/sdw-master-N/clk_freq + /sys/bus/soundwire/devices/sdw-master-N/clk_gears + /sys/bus/soundwire/devices/sdw-master-N/default_col + /sys/bus/soundwire/devices/sdw-master-N/default_frame_rate + /sys/bus/soundwire/devices/sdw-master-N/default_row + /sys/bus/soundwire/devices/sdw-master-N/dynamic_shape + /sys/bus/soundwire/devices/sdw-master-N/err_threshold + /sys/bus/soundwire/devices/sdw-master-N/max_clk_freq + +Date: April 2020 + +Contact: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> + Bard Liao <yung-chuan.liao@linux.intel.com> + Vinod Koul <vkoul@kernel.org> + +Description: SoundWire Master-N DisCo properties. + These properties are defined by MIPI DisCo Specification + for SoundWire. They define various properties of the Master + and are used by the bus to configure the Master. clk_stop_modes + is a bitmask for simplifications and combines the + clock-stop-mode0 and clock-stop-mode1 properties. diff --git a/Documentation/ABI/testing/sysfs-bus-soundwire-slave b/Documentation/ABI/testing/sysfs-bus-soundwire-slave new file mode 100644 index 000000000000..db4c9511d1aa --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-soundwire-slave @@ -0,0 +1,91 @@ +What: /sys/bus/soundwire/devices/sdw:.../dev-properties/mipi_revision + /sys/bus/soundwire/devices/sdw:.../dev-properties/wake_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/test_mode_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/clk_stop_mode1 + /sys/bus/soundwire/devices/sdw:.../dev-properties/simple_clk_stop_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/clk_stop_timeout + /sys/bus/soundwire/devices/sdw:.../dev-properties/ch_prep_timeout + /sys/bus/soundwire/devices/sdw:.../dev-properties/reset_behave + /sys/bus/soundwire/devices/sdw:.../dev-properties/high_PHY_capable + /sys/bus/soundwire/devices/sdw:.../dev-properties/paging_support + /sys/bus/soundwire/devices/sdw:.../dev-properties/bank_delay_support + /sys/bus/soundwire/devices/sdw:.../dev-properties/p15_behave + /sys/bus/soundwire/devices/sdw:.../dev-properties/master_count + /sys/bus/soundwire/devices/sdw:.../dev-properties/source_ports + /sys/bus/soundwire/devices/sdw:.../dev-properties/sink_ports + +Date: May 2020 + +Contact: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> + Bard Liao <yung-chuan.liao@linux.intel.com> + Vinod Koul <vkoul@kernel.org> + +Description: SoundWire Slave DisCo properties. + These properties are defined by MIPI DisCo Specification + for SoundWire. They define various properties of the + SoundWire Slave and are used by the bus to configure + the Slave + + +What: /sys/bus/soundwire/devices/sdw:.../dp0/max_word + /sys/bus/soundwire/devices/sdw:.../dp0/min_word + /sys/bus/soundwire/devices/sdw:.../dp0/words + /sys/bus/soundwire/devices/sdw:.../dp0/BRA_flow_controlled + /sys/bus/soundwire/devices/sdw:.../dp0/simple_ch_prep_sm + /sys/bus/soundwire/devices/sdw:.../dp0/imp_def_interrupts + +Date: May 2020 + +Contact: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> + Bard Liao <yung-chuan.liao@linux.intel.com> + Vinod Koul <vkoul@kernel.org> + +Description: SoundWire Slave Data Port-0 DisCo properties. + These properties are defined by MIPI DisCo Specification + for the SoundWire. They define various properties of the + Data port 0 are used by the bus to configure the Data Port 0. + + +What: /sys/bus/soundwire/devices/sdw:.../dpN_src/max_word + /sys/bus/soundwire/devices/sdw:.../dpN_src/min_word + /sys/bus/soundwire/devices/sdw:.../dpN_src/words + /sys/bus/soundwire/devices/sdw:.../dpN_src/type + /sys/bus/soundwire/devices/sdw:.../dpN_src/max_grouping + /sys/bus/soundwire/devices/sdw:.../dpN_src/simple_ch_prep_sm + /sys/bus/soundwire/devices/sdw:.../dpN_src/ch_prep_timeout + /sys/bus/soundwire/devices/sdw:.../dpN_src/imp_def_interrupts + /sys/bus/soundwire/devices/sdw:.../dpN_src/min_ch + /sys/bus/soundwire/devices/sdw:.../dpN_src/max_ch + /sys/bus/soundwire/devices/sdw:.../dpN_src/channels + /sys/bus/soundwire/devices/sdw:.../dpN_src/ch_combinations + /sys/bus/soundwire/devices/sdw:.../dpN_src/max_async_buffer + /sys/bus/soundwire/devices/sdw:.../dpN_src/block_pack_mode + /sys/bus/soundwire/devices/sdw:.../dpN_src/port_encoding + + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_word + /sys/bus/soundwire/devices/sdw:.../dpN_sink/min_word + /sys/bus/soundwire/devices/sdw:.../dpN_sink/words + /sys/bus/soundwire/devices/sdw:.../dpN_sink/type + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_grouping + /sys/bus/soundwire/devices/sdw:.../dpN_sink/simple_ch_prep_sm + /sys/bus/soundwire/devices/sdw:.../dpN_sink/ch_prep_timeout + /sys/bus/soundwire/devices/sdw:.../dpN_sink/imp_def_interrupts + /sys/bus/soundwire/devices/sdw:.../dpN_sink/min_ch + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_ch + /sys/bus/soundwire/devices/sdw:.../dpN_sink/channels + /sys/bus/soundwire/devices/sdw:.../dpN_sink/ch_combinations + /sys/bus/soundwire/devices/sdw:.../dpN_sink/max_async_buffer + /sys/bus/soundwire/devices/sdw:.../dpN_sink/block_pack_mode + /sys/bus/soundwire/devices/sdw:.../dpN_sink/port_encoding + +Date: May 2020 + +Contact: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> + Bard Liao <yung-chuan.liao@linux.intel.com> + Vinod Koul <vkoul@kernel.org> + +Description: SoundWire Slave Data Source/Sink Port-N DisCo properties. + These properties are defined by MIPI DisCo Specification + for SoundWire. They define various properties of the + Source/Sink Data port N and are used by the bus to configure + the Data Port N. diff --git a/Documentation/ABI/testing/sysfs-driver-habanalabs b/Documentation/ABI/testing/sysfs-driver-habanalabs index 782df74042ed..1a14bf9b22ba 100644 --- a/Documentation/ABI/testing/sysfs-driver-habanalabs +++ b/Documentation/ABI/testing/sysfs-driver-habanalabs @@ -10,6 +10,23 @@ KernelVersion: 5.1 Contact: oded.gabbay@gmail.com Description: Version of the application running on the device's CPU +What: /sys/class/habanalabs/hl<n>/clk_max_freq_mhz +Date: Jun 2019 +KernelVersion: not yet upstreamed +Contact: oded.gabbay@gmail.com +Description: Allows the user to set the maximum clock frequency, in MHz. + The device clock might be set to lower value than the maximum. + The user should read the clk_cur_freq_mhz to see the actual + frequency value of the device clock. This property is valid + only for the Gaudi ASIC family + +What: /sys/class/habanalabs/hl<n>/clk_cur_freq_mhz +Date: Jun 2019 +KernelVersion: not yet upstreamed +Contact: oded.gabbay@gmail.com +Description: Displays the current frequency, in MHz, of the device clock. + This property is valid only for the Gaudi ASIC family + What: /sys/class/habanalabs/hl<n>/cpld_ver Date: Jan 2019 KernelVersion: 5.1 diff --git a/Documentation/ABI/testing/sysfs-driver-w1_therm b/Documentation/ABI/testing/sysfs-driver-w1_therm new file mode 100644 index 000000000000..076659d506f2 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-w1_therm @@ -0,0 +1,116 @@ +What: /sys/bus/w1/devices/.../alarms +Date: May 2020 +Contact: Akira Shimahara <akira215corp@gmail.com> +Description: + (RW) read or write TH and TL (Temperature High an Low) alarms. + Values shall be space separated and in the device range + (typical -55 degC to 125 degC), if not values will be trimmed + to device min/max capabilities. Values are integer as they are + stored in a 8bit register in the device. Lowest value is + automatically put to TL. Once set, alarms could be search at + master level, refer to Documentation/w1/w1_generic.rst for + detailed information +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../eeprom +Date: May 2020 +Contact: Akira Shimahara <akira215corp@gmail.com> +Description: + (WO) writing that file will either trigger a save of the + device data to its embedded EEPROM, either restore data + embedded in device EEPROM. Be aware that devices support + limited EEPROM writing cycles (typical 50k) + * 'save': save device RAM to EEPROM + * 'restore': restore EEPROM data in device RAM +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../ext_power +Date: May 2020 +Contact: Akira Shimahara <akira215corp@gmail.com> +Description: + (RO) return the power status by asking the device + * '0': device parasite powered + * '1': device externally powered + * '-xx': xx is kernel error when reading power status +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../resolution +Date: May 2020 +Contact: Akira Shimahara <akira215corp@gmail.com> +Description: + (RW) get or set the device resolution (on supported devices, + if not, this entry is not present). Note that the resolution + will be changed only in device RAM, so it will be cleared when + power is lost. Trigger a 'save' to EEPROM command to keep + values after power-on. Read or write are : + * '9..12': device resolution in bit + or resolution to set in bit + * '-xx': xx is kernel error when reading the resolution + * Anything else: do nothing +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../temperature +Date: May 2020 +Contact: Akira Shimahara <akira215corp@gmail.com> +Description: + (RO) return the temperature in 1/1000 degC. + * If a bulk read has been triggered, it will directly + return the temperature computed when the bulk read + occurred, if available. If not yet available, nothing + is returned (a debug kernel message is sent), you + should retry later on. + * If no bulk read has been triggered, it will trigger + a conversion and send the result. Note that the + conversion duration depend on the resolution (if + device support this feature). It takes 94ms in 9bits + resolution, 750ms for 12bits. +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/.../w1_slave +Date: May 2020 +Contact: Akira Shimahara <akira215corp@gmail.com> +Description: + (RW) return the temperature in 1/1000 degC. + *read*: return 2 lines with the hexa output data sent on the + bus, return the CRC check and temperature in 1/1000 degC + *write* : + * '0' : save the 2 or 3 bytes to the device EEPROM + (i.e. TH, TL and config register) + * '9..12' : set the device resolution in RAM + (if supported) + * Anything else: do nothing + refer to Documentation/w1/slaves/w1_therm.rst for detailed + information. +Users: any user space application which wants to communicate with + w1_term device + + +What: /sys/bus/w1/devices/w1_bus_masterXX/therm_bulk_read +Date: May 2020 +Contact: Akira Shimahara <akira215corp@gmail.com> +Description: + (RW) trigger a bulk read conversion. read the status + *read*: + * '-1': conversion in progress on at least 1 sensor + * '1' : conversion complete but at least one sensor + value has not been read yet + * '0' : no bulk operation. Reading temperature will + trigger a conversion on each device + *write*: 'trigger': trigger a bulk read on all supporting + devices on the bus + Note that if a bulk read is sent but one sensor is not read + immediately, the next access to temperature on this device + will return the temperature measured at the time of issue + of the bulk read command (not the current temperature). +Users: any user space application which wants to communicate with + w1_term device diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt index 1fa66065acc6..6eff1afd8daf 100644 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt @@ -23,7 +23,7 @@ Required properties: The svc node has the following mandatory properties, must be located under the firmware node. -- compatible: "intel,stratix10-svc" +- compatible: "intel,stratix10-svc" or "intel,agilex-svc" - method: smc or hvc smc - Secure Monitor Call hvc - Hypervisor Call diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt index 6e03f79287fb..0f874137ca46 100644 --- a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt +++ b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt @@ -4,7 +4,8 @@ Required properties: The fpga_mgr node has the following mandatory property, must be located under firmware/svc node. -- compatible : should contain "intel,stratix10-soc-fpga-mgr" +- compatible : should contain "intel,stratix10-soc-fpga-mgr" or + "intel,agilex-soc-fpga-mgr" Example: diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml new file mode 100644 index 000000000000..ff09550ad959 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic i.MX bus frequency device + +maintainers: + - Leonard Crestez <leonard.crestez@nxp.com> + +description: | + The i.MX SoC family has multiple buses for which clock frequency (and + sometimes voltage) can be adjusted. + + Some of those buses expose register areas mentioned in the memory maps as GPV + ("Global Programmers View") but not all. Access to this area might be denied + for normal (non-secure) world. + + The buses are based on externally licensed IPs such as ARM NIC-301 and + Arteris FlexNOC but DT bindings are specific to the integration of these bus + interconnect IPs into imx SOCs. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx8mn-nic + - fsl,imx8mm-nic + - fsl,imx8mq-nic + - const: fsl,imx8m-nic + - items: + - enum: + - fsl,imx8mn-noc + - fsl,imx8mm-noc + - fsl,imx8mq-noc + - const: fsl,imx8m-noc + - const: fsl,imx8m-nic + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + operating-points-v2: true + opp-table: true + + fsl,ddrc: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + Phandle to DDR Controller. + + '#interconnect-cells': + description: + If specified then also act as an interconnect provider. Should only be + set once per soc on the main noc. + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + #include <dt-bindings/interconnect/imx8mm.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + noc: interconnect@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + #interconnect-cells = <1>; + fsl,ddrc = <&ddrc>; + + operating-points-v2 = <&noc_opp_table>; + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + }; diff --git a/Documentation/driver-api/soundwire/stream.rst b/Documentation/driver-api/soundwire/stream.rst index 8bceece51554..1b386076402c 100644 --- a/Documentation/driver-api/soundwire/stream.rst +++ b/Documentation/driver-api/soundwire/stream.rst @@ -75,8 +75,33 @@ Slaves are using single port. :: | (Data) | +---------------+ +Example 4: Stereo Stream with L and R channels is rendered by +Master. Both of the L and R channels are received by two different +Slaves. Master and both Slaves are using single port handling +L+R. Each Slave device processes the L + R data locally, typically +based on static configuration or dynamic orientation, and may drive +one or more speakers. :: -Example 4: Stereo Stream with L and R channel is rendered by two different + +---------------+ Clock Signal +---------------+ + | Master +---------+------------------------+ Slave | + | Interface | | | Interface | + | | | | 1 | + | | | Data Signal | | + | L + R +---+------------------------------+ L + R | + | (Data) | | | Data Direction | (Data) | + +---------------+ | | +-------------> +---------------+ + | | + | | + | | +---------------+ + | +----------------------> | Slave | + | | Interface | + | | 2 | + | | | + +----------------------------> | L + R | + | (Data) | + +---------------+ + +Example 5: Stereo Stream with L and R channel is rendered by two different Ports of the Master and is received by only single Port of the Slave interface. :: @@ -101,7 +126,7 @@ interface. :: +--------------------+ | | +----------------+ -Example 5: Stereo Stream with L and R channel is rendered by 2 Masters, each +Example 6: Stereo Stream with L and R channel is rendered by 2 Masters, each rendering one channel, and is received by two different Slaves, each receiving one channel. Both Masters and both Slaves are using single port. :: @@ -123,12 +148,70 @@ receiving one channel. Both Masters and both Slaves are using single port. :: | (Data) | Data Direction | (Data) | +---------------+ +-----------------------> +---------------+ -Note: In multi-link cases like above, to lock, one would acquire a global +Example 7: Stereo Stream with L and R channel is rendered by 2 +Masters, each rendering both channels. Each Slave receives L + R. This +is the same application as Example 4 but with Slaves placed on +separate links. :: + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 1 | | 1 | + | | Data Signal | | + | L + R +----------------------------------+ L + R | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 2 | | 2 | + | | Data Signal | | + | L + R +----------------------------------+ L + R | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + +Example 8: 4-channel Stream is rendered by 2 Masters, each rendering a +2 channels. Each Slave receives 2 channels. :: + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 1 | | 1 | + | | Data Signal | | + | L1 + R1 +----------------------------------+ L1 + R1 | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + + +---------------+ Clock Signal +---------------+ + | Master +----------------------------------+ Slave | + | Interface | | Interface | + | 2 | | 2 | + | | Data Signal | | + | L2 + R2 +----------------------------------+ L2 + R2 | + | (Data) | Data Direction | (Data) | + +---------------+ +-----------------------> +---------------+ + +Note1: In multi-link cases like above, to lock, one would acquire a global lock and then go on locking bus instances. But, in this case the caller framework(ASoC DPCM) guarantees that stream operations on a card are always serialized. So, there is no race condition and hence no need for global lock. +Note2: A Slave device may be configured to receive all channels +transmitted on a link for a given Stream (Example 4) or just a subset +of the data (Example 3). The configuration of the Slave device is not +handled by a SoundWire subsystem API, but instead by the +snd_soc_dai_set_tdm_slot() API. The platform or machine driver will +typically configure which of the slots are used. For Example 4, the +same slots would be used by all Devices, while for Example 3 the Slave +Device1 would use e.g. Slot 0 and Slave device2 slot 1. + +Note3: Multiple Sink ports can extract the same information for the +same bitSlots in the SoundWire frame, however multiple Source ports +shall be configured with different bitSlot configurations. This is the +same limitation as with I2S/PCM TDM usages. + SoundWire Stream Management flow ================================ diff --git a/Documentation/driver-api/soundwire/summary.rst b/Documentation/driver-api/soundwire/summary.rst index 8193125a2bfb..01dcb954f6d7 100644 --- a/Documentation/driver-api/soundwire/summary.rst +++ b/Documentation/driver-api/soundwire/summary.rst @@ -101,10 +101,11 @@ Following is the Bus API to register the SoundWire Bus: .. code-block:: c - int sdw_add_bus_master(struct sdw_bus *bus) + int sdw_bus_master_add(struct sdw_bus *bus, + struct device *parent, + struct fwnode_handle) { - if (!bus->dev) - return -ENODEV; + sdw_master_device_add(bus, parent, fwnode); mutex_init(&bus->lock); INIT_LIST_HEAD(&bus->slaves); diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 094fc8aacd8e..978c4af416a4 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -118,6 +118,11 @@ More functions are exposed through sysfs management information (current temperature, thresholds, threshold status, etc.). + Performance reporting + performance counters are exposed through perf PMU APIs. Standard perf tool + can be used to monitor all available perf events. Please see performance + counter section below for more detailed information. + FIU - PORT ========== @@ -378,6 +383,85 @@ The device nodes used for ioctl() or mmap() can be referenced through:: /sys/class/fpga_region/<regionX>/<dfl-port.n>/dev +Performance Counters +==================== +Performance reporting is one private feature implemented in FME. It could +supports several independent, system-wide, device counter sets in hardware to +monitor and count for performance events, including "basic", "cache", "fabric", +"vtd" and "vtd_sip" counters. Users could use standard perf tool to monitor +FPGA cache hit/miss rate, transaction number, interface clock counter of AFU +and other FPGA performance events. + +Different FPGA devices may have different counter sets, depending on hardware +implementation. E.g., some discrete FPGA cards don't have any cache. User could +use "perf list" to check which perf events are supported by target hardware. + +In order to allow user to use standard perf API to access these performance +counters, driver creates a perf PMU, and related sysfs interfaces in +/sys/bus/event_source/devices/dfl_fme* to describe available perf events and +configuration options. + +The "format" directory describes the format of the config field of struct +perf_event_attr. There are 3 bitfields for config: "evtype" defines which type +the perf event belongs to; "event" is the identity of the event within its +category; "portid" is introduced to decide counters set to monitor on FPGA +overall data or a specific port. + +The "events" directory describes the configuration templates for all available +events which can be used with perf tool directly. For example, fab_mmio_read +has the configuration "event=0x06,evtype=0x02,portid=0xff", which shows this +event belongs to fabric type (0x02), the local event id is 0x06 and it is for +overall monitoring (portid=0xff). + +Example usage of perf:: + + $# perf list |grep dfl_fme + + dfl_fme0/fab_mmio_read/ [Kernel PMU event] + <...> + dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] + <...> + + $# perf stat -a -e dfl_fme0/fab_mmio_read/ <command> + or + $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0xff/ <command> + or + $# perf stat -a -e dfl_fme0/config=0xff2006/ <command> + +Another example, fab_port_mmio_read monitors mmio read of a specific port. So +its configuration template is "event=0x06,evtype=0x01,portid=?". The portid +should be explicitly set. + +Its usage of perf:: + + $# perf stat -a -e dfl_fme0/fab_port_mmio_read,portid=0x0/ <command> + or + $# perf stat -a -e dfl_fme0/event=0x06,evtype=0x02,portid=0x0/ <command> + or + $# perf stat -a -e dfl_fme0/config=0x2006/ <command> + +Please note for fabric counters, overall perf events (fab_*) and port perf +events (fab_port_*) actually share one set of counters in hardware, so it can't +monitor both at the same time. If this set of counters is configured to monitor +overall data, then per port perf data is not supported. See below example:: + + $# perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,\ + portid=0/ sleep 1 + + Performance counter stats for 'system wide': + + 3 dfl_fme0/fab_mmio_read/ + <not supported> dfl_fme0/fab_port_mmio_write,portid=0x0/ + + 1.001750904 seconds time elapsed + +The driver also provides a "cpumask" sysfs attribute, which contains only one +CPU id used to access these perf events. Counting on multiple CPU is not allowed +since they are system-wide counters on FPGA device. + +The current driver does not support sampling. So "perf record" is unsupported. + + Add new FIUs support ==================== It's possible that developers made some new function blocks (FIUs) under this diff --git a/Documentation/trace/coresight/coresight-ect.rst b/Documentation/trace/coresight/coresight-ect.rst index a93e52abcf46..a68732c5c6d6 100644 --- a/Documentation/trace/coresight/coresight-ect.rst +++ b/Documentation/trace/coresight/coresight-ect.rst @@ -73,7 +73,7 @@ capable of generating or using trigger signals.:: >$ ls /sys/bus/coresight/devices/etm0/cti_cpu0 channels ctmid enable nr_trigger_cons mgmt power powered regs - subsystem triggers0 triggers1 uevent + connections subsystem triggers0 triggers1 uevent *Key file items are:-* * ``enable``: enables/disables the CTI. Read to determine current state. @@ -89,6 +89,9 @@ capable of generating or using trigger signals.:: * ``channels``: Contains the channel API - CTI main programming interface. * ``regs``: Gives access to the raw programmable CTI regs. * ``mgmt``: the standard CoreSight management registers. + * ``connections``: Links to connected *CoreSight* devices. The number of + links can be 0 to ``nr_trigger_cons``. Actual number given by ``nr_links`` + in this directory. triggers<N> directories diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index 108600ee1e12..0b73acb44efa 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -241,6 +241,91 @@ to the newer scheme, to give a confirmation that what you see on your system is not unexpected. One must use the "names" as they appear on the system under specified locations. +Topology Representation +----------------------- + +Each CoreSight component has a ``connections`` directory which will contain +links to other CoreSight components. This allows the user to explore the trace +topology and for larger systems, determine the most appropriate sink for a +given source. The connection information can also be used to establish +which CTI devices are connected to a given component. This directory contains a +``nr_links`` attribute detailing the number of links in the directory. + +For an ETM source, in this case ``etm0`` on a Juno platform, a typical +arrangement will be:: + + linaro-developer:~# ls - l /sys/bus/coresight/devices/etm0/connections + <file details> cti_cpu0 -> ../../../23020000.cti/cti_cpu0 + <file details> nr_links + <file details> out:0 -> ../../../230c0000.funnel/funnel2 + +Following the out port to ``funnel2``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel2/connections + <file details> in:0 -> ../../../23040000.etm/etm0 + <file details> in:1 -> ../../../23140000.etm/etm3 + <file details> in:2 -> ../../../23240000.etm/etm4 + <file details> in:3 -> ../../../23340000.etm/etm5 + <file details> nr_links + <file details> out:0 -> ../../../20040000.funnel/funnel0 + +And again to ``funnel0``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel0/connections + <file details> in:0 -> ../../../220c0000.funnel/funnel1 + <file details> in:1 -> ../../../230c0000.funnel/funnel2 + <file details> nr_links + <file details> out:0 -> ../../../20010000.etf/tmc_etf0 + +Finding the first sink ``tmc_etf0``. This can be used to collect data +as a sink, or as a link to propagate further along the chain:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etf0/connections + <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0 + <file details> in:0 -> ../../../20040000.funnel/funnel0 + <file details> nr_links + <file details> out:0 -> ../../../20150000.funnel/funnel4 + +via ``funnel4``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/funnel4/connections + <file details> in:0 -> ../../../20010000.etf/tmc_etf0 + <file details> in:1 -> ../../../20140000.etf/tmc_etf1 + <file details> nr_links + <file details> out:0 -> ../../../20120000.replicator/replicator0 + +and a ``replicator0``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/replicator0/connections + <file details> in:0 -> ../../../20150000.funnel/funnel4 + <file details> nr_links + <file details> out:0 -> ../../../20030000.tpiu/tpiu0 + <file details> out:1 -> ../../../20070000.etr/tmc_etr0 + +Arriving at the final sink in the chain, ``tmc_etr0``:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/tmc_etr0/connections + <file details> cti_sys0 -> ../../../20020000.cti/cti_sys0 + <file details> in:0 -> ../../../20120000.replicator/replicator0 + <file details> nr_links + +As described below, when using sysfs it is sufficient to enable a sink and +a source for successful trace. The framework will correctly enable all +intermediate links as required. + +Note: ``cti_sys0`` appears in two of the connections lists above. +CTIs can connect to multiple devices and are arranged in a star topology +via the CTM. See (:doc:`coresight-ect`) [#fourth]_ for further details. +Looking at this device we see 4 connections:: + + linaro-developer:~# ls -l /sys/bus/coresight/devices/cti_sys0/connections + <file details> nr_links + <file details> stm0 -> ../../../20100000.stm/stm0 + <file details> tmc_etf0 -> ../../../20010000.etf/tmc_etf0 + <file details> tmc_etr0 -> ../../../20070000.etr/tmc_etr0 + <file details> tpiu0 -> ../../../20030000.tpiu/tpiu0 + + How to use the tracer modules ----------------------------- diff --git a/Documentation/w1/slaves/w1_therm.rst b/Documentation/w1/slaves/w1_therm.rst index 90531c340a07..cc4edae17751 100644 --- a/Documentation/w1/slaves/w1_therm.rst +++ b/Documentation/w1/slaves/w1_therm.rst @@ -26,20 +26,31 @@ W1_THERM_DS1825 0x3B W1_THERM_DS28EA00 0x42 ==================== ==== -Support is provided through the sysfs w1_slave file. Each open and +Support is provided through the sysfs w1_slave file. Each open and read sequence will initiate a temperature conversion then provide two -lines of ASCII output. The first line contains the nine hex bytes +lines of ASCII output. The first line contains the nine hex bytes read along with a calculated crc value and YES or NO if it matched. -If the crc matched the returned values are retained. The second line +If the crc matched the returned values are retained. The second line displays the retained values along with a temperature in millidegrees Centigrade after t=. -Parasite powered devices are limited to one slave performing a -temperature conversion at a time. If none of the devices are parasite -powered it would be possible to convert all the devices at the same -time and then go back to read individual sensors. That isn't -currently supported. The driver also doesn't support reduced -precision (which would also reduce the conversion time) when reading values. +Alternatively, temperature can be read using temperature sysfs, it +return only temperature in millidegrees Centigrade. + +A bulk read of all devices on the bus could be done writing 'trigger' +in the therm_bulk_read sysfs entry at w1_bus_master level. This will +sent the convert command on all devices on the bus, and if parasite +powered devices are detected on the bus (and strong pullup is enable +in the module), it will drive the line high during the longer conversion +time required by parasited powered device on the line. Reading +therm_bulk_read will return 0 if no bulk conversion pending, +-1 if at least one sensor still in conversion, 1 if conversion is complete +but at least one sensor value has not been read yet. Result temperature is +then accessed by reading the temperature sysfs entry of each device, which +may return empty if conversion is still in progress. Note that if a bulk +read is sent but one sensor is not read immediately, the next access to +temperature on this device will return the temperature measured at the +time of issue of the bulk read command (not the current temperature). Writing a value between 9 and 12 to the sysfs w1_slave file will change the precision of the sensor for the next readings. This value is in (volatile) @@ -49,6 +60,27 @@ To store the current precision configuration into EEPROM, the value 0 has to be written to the sysfs w1_slave file. Since the EEPROM has a limited amount of writes (>50k), this command should be used wisely. +Alternatively, resolution can be set or read (value from 9 to 12) using the +dedicated resolution sysfs entry on each device. This sysfs entry is not +present for devices not supporting this feature. Driver will adjust the +correct conversion time for each device regarding to its resolution setting. +In particular, strong pullup will be applied if required during the conversion +duration. + +The write-only sysfs entry eeprom is an alternative for EEPROM operations: + * 'save': will save device RAM to EEPROM + * 'restore': will restore EEPROM data in device RAM. + +ext_power syfs entry allow tho check the power status of each device. + * '0': device parasite powered + * '1': device externally powered + +sysfs alarms allow read or write TH and TL (Temperature High an Low) alarms. +Values shall be space separated and in the device range (typical -55 degC +to 125 degC). Values are integer as they are store in a 8bit register in +the device. Lowest value is automatically put to TL.Once set, alarms could +be search at master level. + The module parameter strong_pullup can be set to 0 to disable the strong pullup, 1 to enable autodetection or 2 to force strong pullup. In case of autodetection, the driver will use the "READ POWER SUPPLY" diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index d8c44d3ca15a..f52de8f7806a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -539,12 +539,12 @@ firmware { svc { - compatible = "intel,stratix10-svc"; + compatible = "intel,agilex-svc"; method = "smc"; memory-region = <&service_reserved>; fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; + compatible = "intel,agilex-soc-fpga-mgr"; }; }; }; diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index 9ecad74183a3..7cf566aafe1f 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -650,7 +650,7 @@ static int binderfs_fill_super(struct super_block *sb, struct fs_context *fc) struct binderfs_info *info; struct binderfs_mount_opts *ctx = fc->fs_private; struct inode *inode = NULL; - struct binderfs_device device_info = { 0 }; + struct binderfs_device device_info = {}; const char *name; size_t len; @@ -747,7 +747,7 @@ static const struct fs_context_operations binderfs_fs_context_ops = { static int binderfs_init_fs_context(struct fs_context *fc) { - struct binderfs_mount_opts *ctx = fc->fs_private; + struct binderfs_mount_opts *ctx; ctx = kzalloc(sizeof(struct binderfs_mount_opts), GFP_KERNEL); if (!ctx) diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c index ebad5eb48e5a..0b38014d040e 100644 --- a/drivers/bus/mhi/core/boot.c +++ b/drivers/bus/mhi/core/boot.c @@ -43,10 +43,7 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, lower_32_bits(mhi_buf->dma_addr)); mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len); - sequence_id = prandom_u32() & BHIE_RXVECSTATUS_SEQNUM_BMSK; - - if (unlikely(!sequence_id)) - sequence_id = 1; + sequence_id = MHI_RANDOM_U32_NONZERO(BHIE_RXVECSTATUS_SEQNUM_BMSK); mhi_write_reg_field(mhi_cntrl, base, BHIE_RXVECDB_OFFS, BHIE_RXVECDB_SEQNUM_BMSK, BHIE_RXVECDB_SEQNUM_SHFT, @@ -121,7 +118,8 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) ee = mhi_get_exec_env(mhi_cntrl); } - dev_dbg(dev, "Waiting for image download completion, current EE: %s\n", + dev_dbg(dev, + "Waiting for RDDM image download via BHIe, current EE:%s\n", TO_MHI_EXEC_STR(ee)); while (retry--) { @@ -152,11 +150,14 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) int mhi_download_rddm_img(struct mhi_controller *mhi_cntrl, bool in_panic) { void __iomem *base = mhi_cntrl->bhie; + struct device *dev = &mhi_cntrl->mhi_dev->dev; u32 rx_status; if (in_panic) return __mhi_download_rddm_in_panic(mhi_cntrl); + dev_dbg(dev, "Waiting for RDDM image download via BHIe\n"); + /* Wait for the image download to complete */ wait_event_timeout(mhi_cntrl->state_event, mhi_read_reg_field(mhi_cntrl, base, @@ -174,8 +175,10 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, const struct mhi_buf *mhi_buf) { void __iomem *base = mhi_cntrl->bhie; + struct device *dev = &mhi_cntrl->mhi_dev->dev; rwlock_t *pm_lock = &mhi_cntrl->pm_lock; u32 tx_status, sequence_id; + int ret; read_lock_bh(pm_lock); if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { @@ -183,6 +186,9 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, return -EIO; } + sequence_id = MHI_RANDOM_U32_NONZERO(BHIE_TXVECSTATUS_SEQNUM_BMSK); + dev_dbg(dev, "Starting AMSS download via BHIe. Sequence ID:%u\n", + sequence_id); mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS, upper_32_bits(mhi_buf->dma_addr)); @@ -191,26 +197,25 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len); - sequence_id = prandom_u32() & BHIE_TXVECSTATUS_SEQNUM_BMSK; mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS, BHIE_TXVECDB_SEQNUM_BMSK, BHIE_TXVECDB_SEQNUM_SHFT, sequence_id); read_unlock_bh(pm_lock); /* Wait for the image download to complete */ - wait_event_timeout(mhi_cntrl->state_event, - MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) || - mhi_read_reg_field(mhi_cntrl, base, - BHIE_TXVECSTATUS_OFFS, - BHIE_TXVECSTATUS_STATUS_BMSK, - BHIE_TXVECSTATUS_STATUS_SHFT, - &tx_status) || tx_status, - msecs_to_jiffies(mhi_cntrl->timeout_ms)); - - if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + ret = wait_event_timeout(mhi_cntrl->state_event, + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) || + mhi_read_reg_field(mhi_cntrl, base, + BHIE_TXVECSTATUS_OFFS, + BHIE_TXVECSTATUS_STATUS_BMSK, + BHIE_TXVECSTATUS_STATUS_SHFT, + &tx_status) || tx_status, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) || + tx_status != BHIE_TXVECSTATUS_STATUS_XFER_COMPL) return -EIO; - return (tx_status == BHIE_TXVECSTATUS_STATUS_XFER_COMPL) ? 0 : -EIO; + return (!ret) ? -ETIMEDOUT : 0; } static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, @@ -239,14 +244,15 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, goto invalid_pm_state; } - dev_dbg(dev, "Starting SBL download via BHI\n"); + session_id = MHI_RANDOM_U32_NONZERO(BHI_TXDB_SEQNUM_BMSK); + dev_dbg(dev, "Starting SBL download via BHI. Session ID:%u\n", + session_id); mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH, upper_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW, lower_32_bits(dma_addr)); mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size); - session_id = prandom_u32() & BHI_TXDB_SEQNUM_BMSK; mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, session_id); read_unlock_bh(pm_lock); @@ -377,30 +383,18 @@ static void mhi_firmware_copy(struct mhi_controller *mhi_cntrl, } } -void mhi_fw_load_worker(struct work_struct *work) +void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) { - struct mhi_controller *mhi_cntrl; const struct firmware *firmware = NULL; struct image_info *image_info; - struct device *dev; + struct device *dev = &mhi_cntrl->mhi_dev->dev; const char *fw_name; void *buf; dma_addr_t dma_addr; size_t size; int ret; - mhi_cntrl = container_of(work, struct mhi_controller, fw_worker); - dev = &mhi_cntrl->mhi_dev->dev; - - dev_dbg(dev, "Waiting for device to enter PBL from: %s\n", - TO_MHI_EXEC_STR(mhi_cntrl->ee)); - - ret = wait_event_timeout(mhi_cntrl->state_event, - MHI_IN_PBL(mhi_cntrl->ee) || - MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), - msecs_to_jiffies(mhi_cntrl->timeout_ms)); - - if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { dev_err(dev, "Device MHI is not in valid state\n"); return; } @@ -446,7 +440,12 @@ void mhi_fw_load_worker(struct work_struct *work) release_firmware(firmware); /* Error or in EDL mode, we're done */ - if (ret || mhi_cntrl->ee == MHI_EE_EDL) + if (ret) { + dev_err(dev, "MHI did not load SBL, ret:%d\n", ret); + return; + } + + if (mhi_cntrl->ee == MHI_EE_EDL) return; write_lock_irq(&mhi_cntrl->pm_lock); @@ -474,8 +473,10 @@ fw_load_ee_pthru: if (!mhi_cntrl->fbc_download) return; - if (ret) + if (ret) { + dev_err(dev, "MHI did not enter READY state\n"); goto error_read; + } /* Wait for the SBL event */ ret = wait_event_timeout(mhi_cntrl->state_event, @@ -493,6 +494,8 @@ fw_load_ee_pthru: ret = mhi_fw_load_amss(mhi_cntrl, /* Vector table is the last entry */ &image_info->mhi_buf[image_info->entries - 1]); + if (ret) + dev_err(dev, "MHI did not load AMSS, ret:%d\n", ret); release_firmware(firmware); diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c index 1f8c82603179..e43a190a7a36 100644 --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c @@ -34,6 +34,8 @@ const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = { [DEV_ST_TRANSITION_READY] = "READY", [DEV_ST_TRANSITION_SBL] = "SBL", [DEV_ST_TRANSITION_MISSION_MODE] = "MISSION_MODE", + [DEV_ST_TRANSITION_SYS_ERR] = "SYS_ERR", + [DEV_ST_TRANSITION_DISABLE] = "DISABLE", }; const char * const mhi_state_str[MHI_STATE_MAX] = { @@ -835,8 +837,6 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, spin_lock_init(&mhi_cntrl->transition_lock); spin_lock_init(&mhi_cntrl->wlock); INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker); - INIT_WORK(&mhi_cntrl->syserr_worker, mhi_pm_sys_err_worker); - INIT_WORK(&mhi_cntrl->fw_worker, mhi_fw_load_worker); init_waitqueue_head(&mhi_cntrl->state_event); mhi_cmd = mhi_cntrl->mhi_cmd; @@ -864,6 +864,10 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl, mutex_init(&mhi_chan->mutex); init_completion(&mhi_chan->completion); rwlock_init(&mhi_chan->lock); + + /* used in setting bei field of TRE */ + mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; + mhi_chan->intmod = mhi_event->intmod; } if (mhi_cntrl->bounce_buf) { diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h index 095d95bc0e37..b1f640b75a94 100644 --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h @@ -386,6 +386,8 @@ enum dev_st_transition { DEV_ST_TRANSITION_READY, DEV_ST_TRANSITION_SBL, DEV_ST_TRANSITION_MISSION_MODE, + DEV_ST_TRANSITION_SYS_ERR, + DEV_ST_TRANSITION_DISABLE, DEV_ST_TRANSITION_MAX, }; @@ -452,6 +454,7 @@ enum mhi_pm_state { #define PRIMARY_CMD_RING 0 #define MHI_DEV_WAKE_DB 127 #define MHI_MAX_MTU 0xffff +#define MHI_RANDOM_U32_NONZERO(bmsk) (prandom_u32_max(bmsk) + 1) enum mhi_er_type { MHI_ER_TYPE_INVALID = 0x0, @@ -586,7 +589,7 @@ enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, enum dev_st_transition state); void mhi_pm_st_worker(struct work_struct *work); -void mhi_pm_sys_err_worker(struct work_struct *work); +void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl); void mhi_fw_load_worker(struct work_struct *work); int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl); void mhi_ctrl_ev_task(unsigned long data); @@ -627,6 +630,7 @@ int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl); void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl); void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, struct image_info *img_info); +void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl); int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan); int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, @@ -670,8 +674,7 @@ irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev); irqreturn_t mhi_intvec_handler(int irq_number, void *dev); int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, - void *buf, void *cb, size_t buf_len, enum mhi_flags flags); - + struct mhi_buf_info *info, enum mhi_flags flags); int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, struct mhi_buf_info *buf_info); int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c index 97e06cc586e4..1f622ce6be8b 100644 --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c @@ -258,7 +258,7 @@ int mhi_destroy_device(struct device *dev, void *data) return 0; } -static void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) +void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) { struct mhi_driver *mhi_drv; @@ -270,6 +270,7 @@ static void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) if (mhi_drv->status_cb) mhi_drv->status_cb(mhi_dev, cb_reason); } +EXPORT_SYMBOL_GPL(mhi_notify); /* Bind MHI channels to MHI devices */ void mhi_create_devices(struct mhi_controller *mhi_cntrl) @@ -368,30 +369,37 @@ irqreturn_t mhi_irq_handler(int irq_number, void *dev) return IRQ_HANDLED; } -irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev) +irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *priv) { - struct mhi_controller *mhi_cntrl = dev; + struct mhi_controller *mhi_cntrl = priv; + struct device *dev = &mhi_cntrl->mhi_dev->dev; enum mhi_state state = MHI_STATE_MAX; enum mhi_pm_state pm_state = 0; enum mhi_ee_type ee = 0; write_lock_irq(&mhi_cntrl->pm_lock); - if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { - state = mhi_get_mhi_state(mhi_cntrl); - ee = mhi_cntrl->ee; - mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { + write_unlock_irq(&mhi_cntrl->pm_lock); + goto exit_intvec; } + state = mhi_get_mhi_state(mhi_cntrl); + ee = mhi_cntrl->ee; + mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + dev_dbg(dev, "local ee:%s device ee:%s dev_state:%s\n", + TO_MHI_EXEC_STR(mhi_cntrl->ee), TO_MHI_EXEC_STR(ee), + TO_MHI_STATE_STR(state)); + if (state == MHI_STATE_SYS_ERR) { - dev_dbg(&mhi_cntrl->mhi_dev->dev, "System error detected\n"); + dev_dbg(dev, "System error detected\n"); pm_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_DETECT); } write_unlock_irq(&mhi_cntrl->pm_lock); - /* If device in RDDM don't bother processing SYS error */ - if (mhi_cntrl->ee == MHI_EE_RDDM) { - if (mhi_cntrl->ee != ee) { + /* If device supports RDDM don't bother processing SYS error */ + if (mhi_cntrl->rddm_image) { + if (mhi_cntrl->ee == MHI_EE_RDDM && mhi_cntrl->ee != ee) { mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_RDDM); wake_up_all(&mhi_cntrl->state_event); } @@ -405,7 +413,7 @@ irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev) if (MHI_IN_PBL(ee)) mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_FATAL_ERROR); else - schedule_work(&mhi_cntrl->syserr_worker); + mhi_pm_sys_err_handler(mhi_cntrl); } exit_intvec: @@ -513,7 +521,10 @@ static int parse_xfer_event(struct mhi_controller *mhi_cntrl, mhi_cntrl->unmap_single(mhi_cntrl, buf_info); result.buf_addr = buf_info->cb_buf; - result.bytes_xferd = xfer_len; + + /* truncate to buf len if xfer_len is larger */ + result.bytes_xferd = + min_t(u16, xfer_len, buf_info->len); mhi_del_ring_element(mhi_cntrl, buf_ring); mhi_del_ring_element(mhi_cntrl, tre_ring); local_rp = tre_ring->rp; @@ -597,7 +608,9 @@ static int parse_rsc_event(struct mhi_controller *mhi_cntrl, result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? -EOVERFLOW : 0; - result.bytes_xferd = xfer_len; + + /* truncate to buf len if xfer_len is larger */ + result.bytes_xferd = min_t(u16, xfer_len, buf_info->len); result.buf_addr = buf_info->cb_buf; result.dir = mhi_chan->dir; @@ -722,13 +735,18 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, { enum mhi_pm_state new_state; + /* skip SYS_ERROR handling if RDDM supported */ + if (mhi_cntrl->ee == MHI_EE_RDDM || + mhi_cntrl->rddm_image) + break; + dev_dbg(dev, "System error detected\n"); write_lock_irq(&mhi_cntrl->pm_lock); new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_DETECT); write_unlock_irq(&mhi_cntrl->pm_lock); if (new_state == MHI_PM_SYS_ERR_DETECT) - schedule_work(&mhi_cntrl->syserr_worker); + mhi_pm_sys_err_handler(mhi_cntrl); break; } default: @@ -774,9 +792,18 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, } case MHI_PKT_TYPE_TX_EVENT: chan = MHI_TRE_GET_EV_CHID(local_rp); - mhi_chan = &mhi_cntrl->mhi_chan[chan]; - parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); - event_quota--; + + WARN_ON(chan >= mhi_cntrl->max_chan); + + /* + * Only process the event ring elements whose channel + * ID is within the maximum supported range. + */ + if (chan < mhi_cntrl->max_chan) { + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } break; default: dev_err(dev, "Unhandled event type: %d\n", type); @@ -819,14 +846,23 @@ int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, enum mhi_pkt_type type = MHI_TRE_GET_EV_TYPE(local_rp); chan = MHI_TRE_GET_EV_CHID(local_rp); - mhi_chan = &mhi_cntrl->mhi_chan[chan]; - - if (likely(type == MHI_PKT_TYPE_TX_EVENT)) { - parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); - event_quota--; - } else if (type == MHI_PKT_TYPE_RSC_TX_EVENT) { - parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); - event_quota--; + + WARN_ON(chan >= mhi_cntrl->max_chan); + + /* + * Only process the event ring elements whose channel + * ID is within the maximum supported range. + */ + if (chan < mhi_cntrl->max_chan) { + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + + if (likely(type == MHI_PKT_TYPE_TX_EVENT)) { + parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } else if (type == MHI_PKT_TYPE_RSC_TX_EVENT) { + parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } } mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); @@ -896,7 +932,7 @@ void mhi_ctrl_ev_task(unsigned long data) } write_unlock_irq(&mhi_cntrl->pm_lock); if (pm_state == MHI_PM_SYS_ERR_DETECT) - schedule_work(&mhi_cntrl->syserr_worker); + mhi_pm_sys_err_handler(mhi_cntrl); } } @@ -918,9 +954,7 @@ int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? mhi_dev->ul_chan : mhi_dev->dl_chan; struct mhi_ring *tre_ring = &mhi_chan->tre_ring; - struct mhi_ring *buf_ring = &mhi_chan->buf_ring; - struct mhi_buf_info *buf_info; - struct mhi_tre *mhi_tre; + struct mhi_buf_info buf_info = { }; int ret; /* If MHI host pre-allocates buffers then client drivers cannot queue */ @@ -945,27 +979,15 @@ int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, /* Toggle wake to exit out of M2 */ mhi_cntrl->wake_toggle(mhi_cntrl); - /* Generate the TRE */ - buf_info = buf_ring->wp; + buf_info.v_addr = skb->data; + buf_info.cb_buf = skb; + buf_info.len = len; - buf_info->v_addr = skb->data; - buf_info->cb_buf = skb; - buf_info->wp = tre_ring->wp; - buf_info->dir = mhi_chan->dir; - buf_info->len = len; - ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); - if (ret) - goto map_error; - - mhi_tre = tre_ring->wp; - - mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); - mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); - mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(1, 1, 0, 0); - - /* increment WP */ - mhi_add_ring_element(mhi_cntrl, tre_ring); - mhi_add_ring_element(mhi_cntrl, buf_ring); + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &buf_info, mflags); + if (unlikely(ret)) { + read_unlock_bh(&mhi_cntrl->pm_lock); + return ret; + } if (mhi_chan->dir == DMA_TO_DEVICE) atomic_inc(&mhi_cntrl->pending_pkts); @@ -979,11 +1001,6 @@ int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, read_unlock_bh(&mhi_cntrl->pm_lock); return 0; - -map_error: - read_unlock_bh(&mhi_cntrl->pm_lock); - - return ret; } EXPORT_SYMBOL_GPL(mhi_queue_skb); @@ -995,9 +1012,8 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, mhi_dev->dl_chan; struct device *dev = &mhi_cntrl->mhi_dev->dev; struct mhi_ring *tre_ring = &mhi_chan->tre_ring; - struct mhi_ring *buf_ring = &mhi_chan->buf_ring; - struct mhi_buf_info *buf_info; - struct mhi_tre *mhi_tre; + struct mhi_buf_info buf_info = { }; + int ret; /* If MHI host pre-allocates buffers then client drivers cannot queue */ if (mhi_chan->pre_alloc) @@ -1024,25 +1040,16 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, /* Toggle wake to exit out of M2 */ mhi_cntrl->wake_toggle(mhi_cntrl); - /* Generate the TRE */ - buf_info = buf_ring->wp; - WARN_ON(buf_info->used); - buf_info->p_addr = mhi_buf->dma_addr; - buf_info->pre_mapped = true; - buf_info->cb_buf = mhi_buf; - buf_info->wp = tre_ring->wp; - buf_info->dir = mhi_chan->dir; - buf_info->len = len; - - mhi_tre = tre_ring->wp; - - mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); - mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len); - mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(1, 1, 0, 0); + buf_info.p_addr = mhi_buf->dma_addr; + buf_info.cb_buf = mhi_buf; + buf_info.pre_mapped = true; + buf_info.len = len; - /* increment WP */ - mhi_add_ring_element(mhi_cntrl, tre_ring); - mhi_add_ring_element(mhi_cntrl, buf_ring); + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &buf_info, mflags); + if (unlikely(ret)) { + read_unlock_bh(&mhi_cntrl->pm_lock); + return ret; + } if (mhi_chan->dir == DMA_TO_DEVICE) atomic_inc(&mhi_cntrl->pending_pkts); @@ -1060,7 +1067,7 @@ int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, EXPORT_SYMBOL_GPL(mhi_queue_dma); int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, - void *buf, void *cb, size_t buf_len, enum mhi_flags flags) + struct mhi_buf_info *info, enum mhi_flags flags) { struct mhi_ring *buf_ring, *tre_ring; struct mhi_tre *mhi_tre; @@ -1072,15 +1079,22 @@ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, tre_ring = &mhi_chan->tre_ring; buf_info = buf_ring->wp; - buf_info->v_addr = buf; - buf_info->cb_buf = cb; + WARN_ON(buf_info->used); + buf_info->pre_mapped = info->pre_mapped; + if (info->pre_mapped) + buf_info->p_addr = info->p_addr; + else + buf_info->v_addr = info->v_addr; + buf_info->cb_buf = info->cb_buf; buf_info->wp = tre_ring->wp; buf_info->dir = mhi_chan->dir; - buf_info->len = buf_len; + buf_info->len = info->len; - ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); - if (ret) - return ret; + if (!info->pre_mapped) { + ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); + if (ret) + return ret; + } eob = !!(flags & MHI_EOB); eot = !!(flags & MHI_EOT); @@ -1089,7 +1103,7 @@ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, mhi_tre = tre_ring->wp; mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); - mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_len); + mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(info->len); mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(bei, eot, eob, chain); /* increment WP */ @@ -1106,6 +1120,7 @@ int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? mhi_dev->ul_chan : mhi_dev->dl_chan; struct mhi_ring *tre_ring; + struct mhi_buf_info buf_info = { }; unsigned long flags; int ret; @@ -1121,7 +1136,11 @@ int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, if (mhi_is_ring_full(mhi_cntrl, tre_ring)) return -ENOMEM; - ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf, buf, len, mflags); + buf_info.v_addr = buf; + buf_info.cb_buf = buf; + buf_info.len = len; + + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &buf_info, mflags); if (unlikely(ret)) return ret; @@ -1322,7 +1341,7 @@ int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, while (nr_el--) { void *buf; - + struct mhi_buf_info info = { }; buf = kmalloc(len, GFP_KERNEL); if (!buf) { ret = -ENOMEM; @@ -1330,8 +1349,10 @@ int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, } /* Prepare transfer descriptors */ - ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf, buf, - len, MHI_EOT); + info.v_addr = buf; + info.cb_buf = buf; + info.len = len; + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &info, MHI_EOT); if (ret) { kfree(buf); goto error_pre_alloc; diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c index dc83d65f7784..796098078083 100644 --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c @@ -288,14 +288,18 @@ int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl) for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { struct mhi_ring *tre_ring = &mhi_chan->tre_ring; - write_lock_irq(&mhi_chan->lock); - if (mhi_chan->db_cfg.reset_req) + if (mhi_chan->db_cfg.reset_req) { + write_lock_irq(&mhi_chan->lock); mhi_chan->db_cfg.db_mode = true; + write_unlock_irq(&mhi_chan->lock); + } + + read_lock_irq(&mhi_chan->lock); /* Only ring DB if ring is not empty */ if (tre_ring->base && tre_ring->wp != tre_ring->rp) mhi_ring_chan_db(mhi_cntrl, mhi_chan); - write_unlock_irq(&mhi_chan->lock); + read_unlock_irq(&mhi_chan->lock); } mhi_cntrl->wake_put(mhi_cntrl, false); @@ -449,19 +453,8 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, to_mhi_pm_state_str(transition_state)); /* We must notify MHI control driver so it can clean up first */ - if (transition_state == MHI_PM_SYS_ERR_PROCESS) { - /* - * If controller supports RDDM, we do not process - * SYS error state, instead we will jump directly - * to RDDM state - */ - if (mhi_cntrl->rddm_image) { - dev_dbg(dev, - "Controller supports RDDM, so skip SYS_ERR\n"); - return; - } + if (transition_state == MHI_PM_SYS_ERR_PROCESS) mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR); - } mutex_lock(&mhi_cntrl->pm_mutex); write_lock_irq(&mhi_cntrl->pm_lock); @@ -527,8 +520,6 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, mutex_unlock(&mhi_cntrl->pm_mutex); dev_dbg(dev, "Waiting for all pending threads to complete\n"); wake_up_all(&mhi_cntrl->state_event); - flush_work(&mhi_cntrl->st_worker); - flush_work(&mhi_cntrl->fw_worker); dev_dbg(dev, "Reset all active channels and remove MHI devices\n"); device_for_each_child(mhi_cntrl->cntrl_dev, NULL, mhi_destroy_device); @@ -608,13 +599,17 @@ int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, } /* SYS_ERR worker */ -void mhi_pm_sys_err_worker(struct work_struct *work) +void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl) { - struct mhi_controller *mhi_cntrl = container_of(work, - struct mhi_controller, - syserr_worker); + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + /* skip if controller supports RDDM */ + if (mhi_cntrl->rddm_image) { + dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n"); + return; + } - mhi_pm_disable_transition(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS); + mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR); } /* Device State Transition worker */ @@ -643,7 +638,7 @@ void mhi_pm_st_worker(struct work_struct *work) mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); write_unlock_irq(&mhi_cntrl->pm_lock); if (MHI_IN_PBL(mhi_cntrl->ee)) - wake_up_all(&mhi_cntrl->state_event); + mhi_fw_load_handler(mhi_cntrl); break; case DEV_ST_TRANSITION_SBL: write_lock_irq(&mhi_cntrl->pm_lock); @@ -662,6 +657,14 @@ void mhi_pm_st_worker(struct work_struct *work) case DEV_ST_TRANSITION_READY: mhi_ready_state_transition(mhi_cntrl); break; + case DEV_ST_TRANSITION_SYS_ERR: + mhi_pm_disable_transition + (mhi_cntrl, MHI_PM_SYS_ERR_PROCESS); + break; + case DEV_ST_TRANSITION_DISABLE: + mhi_pm_disable_transition + (mhi_cntrl, MHI_PM_SHUTDOWN_PROCESS); + break; default: break; } @@ -669,6 +672,149 @@ void mhi_pm_st_worker(struct work_struct *work) } } +int mhi_pm_suspend(struct mhi_controller *mhi_cntrl) +{ + struct mhi_chan *itr, *tmp; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + enum mhi_pm_state new_state; + int ret; + + if (mhi_cntrl->pm_state == MHI_PM_DISABLE) + return -EINVAL; + + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + return -EIO; + + /* Return busy if there are any pending resources */ + if (atomic_read(&mhi_cntrl->dev_wake)) + return -EBUSY; + + /* Take MHI out of M2 state */ + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_get(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M0 || + mhi_cntrl->dev_state == MHI_STATE_M1 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Could not enter M0/M1 state"); + return -EIO; + } + + write_lock_irq(&mhi_cntrl->pm_lock); + + if (atomic_read(&mhi_cntrl->dev_wake)) { + write_unlock_irq(&mhi_cntrl->pm_lock); + return -EBUSY; + } + + dev_info(dev, "Allowing M3 transition\n"); + new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER); + if (new_state != MHI_PM_M3_ENTER) { + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_err(dev, + "Error setting to PM state: %s from: %s\n", + to_mhi_pm_state_str(MHI_PM_M3_ENTER), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Set MHI to M3 and wait for completion */ + mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3); + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_info(dev, "Wait for M3 completion\n"); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M3 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Did not enter M3 state, MHI state: %s, PM state: %s\n", + TO_MHI_STATE_STR(mhi_cntrl->dev_state), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Notify clients about entering LPM */ + list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { + mutex_lock(&itr->mutex); + if (itr->mhi_dev) + mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER); + mutex_unlock(&itr->mutex); + } + + return 0; +} +EXPORT_SYMBOL_GPL(mhi_pm_suspend); + +int mhi_pm_resume(struct mhi_controller *mhi_cntrl) +{ + struct mhi_chan *itr, *tmp; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + enum mhi_pm_state cur_state; + int ret; + + dev_info(dev, "Entered with PM state: %s, MHI state: %s\n", + to_mhi_pm_state_str(mhi_cntrl->pm_state), + TO_MHI_STATE_STR(mhi_cntrl->dev_state)); + + if (mhi_cntrl->pm_state == MHI_PM_DISABLE) + return 0; + + if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) + return -EIO; + + /* Notify clients about exiting LPM */ + list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { + mutex_lock(&itr->mutex); + if (itr->mhi_dev) + mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT); + mutex_unlock(&itr->mutex); + } + + write_lock_irq(&mhi_cntrl->pm_lock); + cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT); + if (cur_state != MHI_PM_M3_EXIT) { + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_info(dev, + "Error setting to PM state: %s from: %s\n", + to_mhi_pm_state_str(MHI_PM_M3_EXIT), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + /* Set MHI to M0 and wait for completion */ + mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0); + write_unlock_irq(&mhi_cntrl->pm_lock); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->dev_state == MHI_STATE_M0 || + MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { + dev_err(dev, + "Did not enter M0 state, MHI state: %s, PM state: %s\n", + TO_MHI_STATE_STR(mhi_cntrl->dev_state), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + return -EIO; + } + + return 0; +} +EXPORT_SYMBOL_GPL(mhi_pm_resume); + int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl) { int ret; @@ -760,6 +906,7 @@ static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl, int mhi_async_power_up(struct mhi_controller *mhi_cntrl) { + enum mhi_state state; enum mhi_ee_type current_ee; enum dev_st_transition next_state; struct device *dev = &mhi_cntrl->mhi_dev->dev; @@ -829,13 +976,36 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) goto error_bhi_offset; } + state = mhi_get_mhi_state(mhi_cntrl); + if (state == MHI_STATE_SYS_ERR) { + mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); + ret = wait_event_timeout(mhi_cntrl->state_event, + MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) || + mhi_read_reg_field(mhi_cntrl, + mhi_cntrl->regs, + MHICTRL, + MHICTRL_RESET_MASK, + MHICTRL_RESET_SHIFT, + &val) || + !val, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + if (ret) { + ret = -EIO; + dev_info(dev, "Failed to reset MHI due to syserr state\n"); + goto error_bhi_offset; + } + + /* + * device cleares INTVEC as part of RESET processing, + * re-program it + */ + mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0); + } + /* Transition to next state */ next_state = MHI_IN_PBL(current_ee) ? DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY; - if (next_state == DEV_ST_TRANSITION_PBL) - schedule_work(&mhi_cntrl->fw_worker); - mhi_queue_state_transition(mhi_cntrl, next_state); mutex_unlock(&mhi_cntrl->pm_mutex); @@ -876,7 +1046,12 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful) to_mhi_pm_state_str(MHI_PM_LD_ERR_FATAL_DETECT), to_mhi_pm_state_str(mhi_cntrl->pm_state)); } - mhi_pm_disable_transition(mhi_cntrl, MHI_PM_SHUTDOWN_PROCESS); + + mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE); + + /* Wait for shutdown to complete */ + flush_work(&mhi_cntrl->st_worker); + mhi_deinit_free_irq(mhi_cntrl); if (!mhi_cntrl->pre_init) { diff --git a/drivers/char/mem.c b/drivers/char/mem.c index 43dd0891ca1e..31cae88a730b 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -31,11 +31,15 @@ #include <linux/uio.h> #include <linux/uaccess.h> #include <linux/security.h> +#include <linux/pseudo_fs.h> +#include <uapi/linux/magic.h> +#include <linux/mount.h> #ifdef CONFIG_IA64 # include <linux/efi.h> #endif +#define DEVMEM_MINOR 1 #define DEVPORT_MINOR 4 static inline unsigned long size_inside_page(unsigned long start, @@ -805,12 +809,64 @@ static loff_t memory_lseek(struct file *file, loff_t offset, int orig) return ret; } +static struct inode *devmem_inode; + +#ifdef CONFIG_IO_STRICT_DEVMEM +void revoke_devmem(struct resource *res) +{ + struct inode *inode = READ_ONCE(devmem_inode); + + /* + * Check that the initialization has completed. Losing the race + * is ok because it means drivers are claiming resources before + * the fs_initcall level of init and prevent /dev/mem from + * establishing mappings. + */ + if (!inode) + return; + + /* + * The expectation is that the driver has successfully marked + * the resource busy by this point, so devmem_is_allowed() + * should start returning false, however for performance this + * does not iterate the entire resource range. + */ + if (devmem_is_allowed(PHYS_PFN(res->start)) && + devmem_is_allowed(PHYS_PFN(res->end))) { + /* + * *cringe* iomem=relaxed says "go ahead, what's the + * worst that can happen?" + */ + return; + } + + unmap_mapping_range(inode->i_mapping, res->start, resource_size(res), 1); +} +#endif + static int open_port(struct inode *inode, struct file *filp) { + int rc; + if (!capable(CAP_SYS_RAWIO)) return -EPERM; - return security_locked_down(LOCKDOWN_DEV_MEM); + rc = security_locked_down(LOCKDOWN_DEV_MEM); + if (rc) + return rc; + + if (iminor(inode) != DEVMEM_MINOR) + return 0; + + /* + * Use a unified address space to have a single point to manage + * revocations when drivers want to take over a /dev/mem mapped + * range. + */ + inode->i_mapping = devmem_inode->i_mapping; + filp->f_mapping = inode->i_mapping; + + return 0; } #define zero_lseek null_lseek @@ -885,7 +941,7 @@ static const struct memdev { fmode_t fmode; } devlist[] = { #ifdef CONFIG_DEVMEM - [1] = { "mem", 0, &mem_fops, FMODE_UNSIGNED_OFFSET }, + [DEVMEM_MINOR] = { "mem", 0, &mem_fops, FMODE_UNSIGNED_OFFSET }, #endif #ifdef CONFIG_DEVKMEM [2] = { "kmem", 0, &kmem_fops, FMODE_UNSIGNED_OFFSET }, @@ -939,6 +995,45 @@ static char *mem_devnode(struct device *dev, umode_t *mode) static struct class *mem_class; +static int devmem_fs_init_fs_context(struct fs_context *fc) +{ + return init_pseudo(fc, DEVMEM_MAGIC) ? 0 : -ENOMEM; +} + +static struct file_system_type devmem_fs_type = { + .name = "devmem", + .owner = THIS_MODULE, + .init_fs_context = devmem_fs_init_fs_context, + .kill_sb = kill_anon_super, +}; + +static int devmem_init_inode(void) +{ + static struct vfsmount *devmem_vfs_mount; + static int devmem_fs_cnt; + struct inode *inode; + int rc; + + rc = simple_pin_fs(&devmem_fs_type, &devmem_vfs_mount, &devmem_fs_cnt); + if (rc < 0) { + pr_err("Cannot mount /dev/mem pseudo filesystem: %d\n", rc); + return rc; + } + + inode = alloc_anon_inode(devmem_vfs_mount->mnt_sb); + if (IS_ERR(inode)) { + rc = PTR_ERR(inode); + pr_err("Cannot allocate inode for /dev/mem: %d\n", rc); + simple_release_fs(&devmem_vfs_mount, &devmem_fs_cnt); + return rc; + } + + /* publish /dev/mem initialized */ + WRITE_ONCE(devmem_inode, inode); + + return 0; +} + static int __init chr_dev_init(void) { int minor; @@ -960,6 +1055,8 @@ static int __init chr_dev_init(void) */ if ((minor == DEVPORT_MINOR) && !arch_has_dev_port()) continue; + if ((minor == DEVMEM_MINOR) && devmem_init_inode() != 0) + continue; device_create(mem_class, NULL, MKDEV(MEM_MAJOR, minor), NULL, devlist[minor].name); diff --git a/drivers/char/tlclk.c b/drivers/char/tlclk.c index 6d81bb3bb503..896a3550fba9 100644 --- a/drivers/char/tlclk.c +++ b/drivers/char/tlclk.c @@ -777,17 +777,21 @@ static int __init tlclk_init(void) { int ret; + telclk_interrupt = (inb(TLCLK_REG7) & 0x0f); + + alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL); + if (!alarm_events) { + ret = -ENOMEM; + goto out1; + } + ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops); if (ret < 0) { printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major); + kfree(alarm_events); return ret; } tlclk_major = ret; - alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL); - if (!alarm_events) { - ret = -ENOMEM; - goto out1; - } /* Read telecom clock IRQ number (Set by BIOS) */ if (!request_region(TLCLK_BASE, 8, "telco_clock")) { @@ -796,7 +800,6 @@ static int __init tlclk_init(void) ret = -EBUSY; goto out2; } - telclk_interrupt = (inb(TLCLK_REG7) & 0x0f); if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */ printk(KERN_ERR "telclk_interrupt = 0x%x non-mcpbl0010 hw.\n", @@ -837,8 +840,8 @@ out3: release_region(TLCLK_BASE, 8); out2: kfree(alarm_events); -out1: unregister_chrdev(tlclk_major, "telco_clock"); +out1: return ret; } diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c index 83b236f20fff..10c9b889324f 100644 --- a/drivers/clk/zynqmp/clk-gate-zynqmp.c +++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c @@ -37,9 +37,8 @@ static int zynqmp_clk_gate_enable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = gate->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_enable(clk_id); + ret = zynqmp_pm_clock_enable(clk_id); if (ret) pr_warn_once("%s() clock enabled failed for %s, ret = %d\n", @@ -58,9 +57,8 @@ static void zynqmp_clk_gate_disable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = gate->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_disable(clk_id); + ret = zynqmp_pm_clock_disable(clk_id); if (ret) pr_warn_once("%s() clock disable failed for %s, ret = %d\n", @@ -79,9 +77,8 @@ static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = gate->clk_id; int state, ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getstate(clk_id, &state); + ret = zynqmp_pm_clock_getstate(clk_id, &state); if (ret) { pr_warn_once("%s() clock get state failed for %s, ret = %d\n", __func__, clk_name, ret); diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 0af8f74c5fa5..06194149be83 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -47,9 +47,8 @@ static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) u32 clk_id = mux->clk_id; u32 val; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getparent(clk_id, &val); + ret = zynqmp_pm_clock_getparent(clk_id, &val); if (ret) pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n", @@ -71,9 +70,8 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = mux->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_setparent(clk_id, index); + ret = zynqmp_pm_clock_setparent(clk_id, index); if (ret) pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n", diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index 10e89f23880b..5eed5ce10179 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -134,7 +134,6 @@ static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id, static struct zynqmp_clock *clock; static struct clk_hw_onecell_data *zynqmp_data; static unsigned int clock_max_idx; -static const struct zynqmp_eemi_ops *eemi_ops; /** * zynqmp_is_valid_clock() - Check whether clock is valid or not @@ -206,7 +205,7 @@ static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks) qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); *nclocks = ret_payload[1]; return ret; @@ -231,7 +230,7 @@ static int zynqmp_pm_clock_get_name(u32 clock_id, qdata.qid = PM_QID_CLOCK_GET_NAME; qdata.arg1 = clock_id; - eemi_ops->query_data(qdata, ret_payload); + zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, ret_payload, sizeof(*response)); return 0; @@ -265,7 +264,7 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, qdata.arg1 = clock_id; qdata.arg2 = index; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, &ret_payload[1], sizeof(*response)); return ret; @@ -296,7 +295,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS; qdata.arg1 = clk_id; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); if (ret) return ERR_PTR(ret); @@ -339,7 +338,7 @@ static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, qdata.arg1 = clock_id; qdata.arg2 = index; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, &ret_payload[1], sizeof(*response)); return ret; @@ -364,7 +363,7 @@ static int zynqmp_pm_clock_get_attributes(u32 clock_id, qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES; qdata.arg1 = clock_id; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); memcpy(response, &ret_payload[1], sizeof(*response)); return ret; @@ -738,10 +737,6 @@ static int zynqmp_clock_probe(struct platform_device *pdev) int ret; struct device *dev = &pdev->dev; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - ret = zynqmp_clk_setup(dev->of_node); return ret; diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 4be2cc76aa2e..8eed715707e3 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -83,9 +83,8 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 div, value; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getdivider(clk_id, &div); + ret = zynqmp_pm_clock_getdivider(clk_id, &div); if (ret) pr_warn_once("%s() get divider failed for %s, ret = %d\n", @@ -163,11 +162,10 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 bestdiv; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { - ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); + ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); if (ret) pr_warn_once("%s() get divider failed for %s, ret = %d\n", @@ -219,7 +217,6 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, u32 div_type = divider->div_type; u32 value, div; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); if (div_type == TYPE_DIV1) { @@ -233,7 +230,7 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) div = __ffs(div); - ret = eemi_ops->clock_setdivider(clk_id, div); + ret = zynqmp_pm_clock_setdivider(clk_id, div); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", @@ -258,7 +255,6 @@ static const struct clk_ops zynqmp_clk_divider_ops = { */ u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); struct zynqmp_pm_query_data qdata = {0}; u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -266,7 +262,7 @@ u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; qdata.arg1 = clk_id; qdata.arg2 = type; - ret = eemi_ops->query_data(qdata, ret_payload); + ret = zynqmp_pm_query_data(qdata, ret_payload); /* * To maintain backward compatibility return maximum possible value * (0xFFFF) if query for max divisor is not successful. diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 89b599530105..92f449ed38e5 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -50,10 +50,8 @@ static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_MODE, clk_id, 0, - ret_payload); + ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload); if (ret) pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -73,14 +71,13 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) const char *clk_name = clk_hw_get_name(hw); int ret; u32 mode; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (on) mode = PLL_MODE_FRAC; else mode = PLL_MODE_INT; - ret = eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_MODE, clk_id, mode, NULL); + ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode); if (ret) pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -139,17 +136,15 @@ static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, unsigned long rate, frac; u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getdivider(clk_id, &fbdiv); + ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); if (ret) pr_warn_once("%s() get divider failed for %s, ret = %d\n", __func__, clk_name, ret); rate = parent_rate * fbdiv; if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { - eemi_ops->ioctl(0, IOCTL_GET_PLL_FRAC_DATA, clk_id, 0, - ret_payload); + zynqmp_pm_get_pll_frac_data(clk_id, ret_payload); data = ret_payload[1]; frac = (parent_rate * data) / FRAC_DIV; rate = rate + frac; @@ -177,7 +172,6 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, u32 fbdiv; long rate_div, frac, m, f; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) { rate_div = (rate * FRAC_DIV) / parent_rate; @@ -187,21 +181,21 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, rate = parent_rate * m; frac = (parent_rate * f) / FRAC_DIV; - ret = eemi_ops->clock_setdivider(clk_id, m); + ret = zynqmp_pm_clock_setdivider(clk_id, m); if (ret == -EUSERS) WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name); else if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", __func__, clk_name, ret); - eemi_ops->ioctl(0, IOCTL_SET_PLL_FRAC_DATA, clk_id, f, NULL); + zynqmp_pm_set_pll_frac_data(clk_id, f); return rate + frac; } fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); - ret = eemi_ops->clock_setdivider(clk_id, fbdiv); + ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv); if (ret) pr_warn_once("%s() set divider failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -222,9 +216,8 @@ static int zynqmp_pll_is_enabled(struct clk_hw *hw) u32 clk_id = clk->clk_id; unsigned int state; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - ret = eemi_ops->clock_getstate(clk_id, &state); + ret = zynqmp_pm_clock_getstate(clk_id, &state); if (ret) { pr_warn_once("%s() clock get state failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -246,12 +239,11 @@ static int zynqmp_pll_enable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = clk->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (zynqmp_pll_is_enabled(hw)) return 0; - ret = eemi_ops->clock_enable(clk_id); + ret = zynqmp_pm_clock_enable(clk_id); if (ret) pr_warn_once("%s() clock enable failed for %s, ret = %d\n", __func__, clk_name, ret); @@ -269,12 +261,11 @@ static void zynqmp_pll_disable(struct clk_hw *hw) const char *clk_name = clk_hw_get_name(hw); u32 clk_id = clk->clk_id; int ret; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); if (!zynqmp_pll_is_enabled(hw)) return; - ret = eemi_ops->clock_disable(clk_id); + ret = zynqmp_pm_clock_disable(clk_id); if (ret) pr_warn_once("%s() clock disable failed for %s, ret = %d\n", __func__, clk_name, ret); diff --git a/drivers/crypto/xilinx/zynqmp-aes-gcm.c b/drivers/crypto/xilinx/zynqmp-aes-gcm.c index 09f7f468eef8..cd11558893cd 100644 --- a/drivers/crypto/xilinx/zynqmp-aes-gcm.c +++ b/drivers/crypto/xilinx/zynqmp-aes-gcm.c @@ -46,7 +46,6 @@ struct zynqmp_aead_drv_ctx { } alg; struct device *dev; struct crypto_engine *engine; - const struct zynqmp_eemi_ops *eemi_ops; }; struct zynqmp_aead_hw_req { @@ -80,21 +79,15 @@ static int zynqmp_aes_aead_cipher(struct aead_request *req) struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead); struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); struct device *dev = tfm_ctx->dev; - struct aead_alg *alg = crypto_aead_alg(aead); - struct zynqmp_aead_drv_ctx *drv_ctx; struct zynqmp_aead_hw_req *hwreq; dma_addr_t dma_addr_data, dma_addr_hw_req; unsigned int data_size; unsigned int status; + int ret; size_t dma_size; char *kbuf; int err; - drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); - - if (!drv_ctx->eemi_ops->aes) - return -ENOTSUPP; - if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY) dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE + GCM_AES_IV_SIZE; @@ -136,9 +129,12 @@ static int zynqmp_aes_aead_cipher(struct aead_request *req) hwreq->key = 0; } - drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status); + ret = zynqmp_pm_aes_engine(dma_addr_hw_req, &status); - if (status) { + if (ret) { + dev_err(dev, "ERROR: AES PM API failed\n"); + err = ret; + } else if (status) { switch (status) { case ZYNQMP_AES_GCM_TAG_MISMATCH_ERR: dev_err(dev, "ERROR: Gcm Tag mismatch\n"); @@ -388,12 +384,6 @@ static int zynqmp_aes_aead_probe(struct platform_device *pdev) else return -ENODEV; - aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(aes_drv_ctx.eemi_ops)) { - dev_err(dev, "Failed to get ZynqMP EEMI interface\n"); - return PTR_ERR(aes_drv_ctx.eemi_ops); - } - err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK)); if (err < 0) { dev_err(dev, "No usable DMA configuration\n"); diff --git a/drivers/dca/dca-sysfs.c b/drivers/dca/dca-sysfs.c index eb25627b059d..21ebd0af268b 100644 --- a/drivers/dca/dca-sysfs.c +++ b/drivers/dca/dca-sysfs.c @@ -24,9 +24,7 @@ int dca_sysfs_add_req(struct dca_provider *dca, struct device *dev, int slot) cd = device_create(dca_class, dca->cd, MKDEV(0, slot + 1), NULL, "requester%d", req_count++); - if (IS_ERR(cd)) - return PTR_ERR(cd); - return 0; + return PTR_ERR_OR_ZERO(cd); } void dca_sysfs_remove_req(struct dca_provider *dca, int slot) diff --git a/drivers/extcon/extcon-adc-jack.c b/drivers/extcon/extcon-adc-jack.c index ad02dc6747a4..0317b614b680 100644 --- a/drivers/extcon/extcon-adc-jack.c +++ b/drivers/extcon/extcon-adc-jack.c @@ -124,7 +124,7 @@ static int adc_jack_probe(struct platform_device *pdev) for (i = 0; data->adc_conditions[i].id != EXTCON_NONE; i++); data->num_conditions = i; - data->chan = iio_channel_get(&pdev->dev, pdata->consumer_channel); + data->chan = devm_iio_channel_get(&pdev->dev, pdata->consumer_channel); if (IS_ERR(data->chan)) return PTR_ERR(data->chan); @@ -164,7 +164,6 @@ static int adc_jack_remove(struct platform_device *pdev) free_irq(data->irq, data); cancel_work_sync(&data->handler.work); - iio_channel_release(data->chan); return 0; } diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c index 7401733db08b..aae82db542a5 100644 --- a/drivers/extcon/extcon-arizona.c +++ b/drivers/extcon/extcon-arizona.c @@ -1460,7 +1460,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) if (!info->input) { dev_err(arizona->dev, "Can't allocate input dev\n"); ret = -ENOMEM; - goto err_register; + return ret; } info->input->name = "Headset"; @@ -1492,7 +1492,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) if (ret != 0) { dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", pdata->micd_pol_gpio, ret); - goto err_register; + return ret; } info->micd_pol_gpio = gpio_to_desc(pdata->micd_pol_gpio); @@ -1515,7 +1515,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) dev_err(arizona->dev, "Failed to get microphone polarity GPIO: %d\n", ret); - goto err_register; + return ret; } } @@ -1672,7 +1672,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) if (ret != 0) { dev_err(&pdev->dev, "Failed to get JACKDET rise IRQ: %d\n", ret); - goto err_gpio; + goto err_pm; } ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1); @@ -1721,14 +1721,14 @@ static int arizona_extcon_probe(struct platform_device *pdev) dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", ret); - pm_runtime_put(&pdev->dev); - ret = input_register_device(info->input); if (ret) { dev_err(&pdev->dev, "Can't register input device: %d\n", ret); goto err_hpdet; } + pm_runtime_put(&pdev->dev); + return 0; err_hpdet: @@ -1743,10 +1743,11 @@ err_rise_wake: arizona_set_irq_wake(arizona, jack_irq_rise, 0); err_rise: arizona_free_irq(arizona, jack_irq_rise, info); +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); err_gpio: gpiod_put(info->micd_pol_gpio); -err_register: - pm_runtime_disable(&pdev->dev); return ret; } diff --git a/drivers/extcon/extcon-max14577.c b/drivers/extcon/extcon-max14577.c index 32f663436e6e..cc47d626095c 100644 --- a/drivers/extcon/extcon-max14577.c +++ b/drivers/extcon/extcon-max14577.c @@ -782,9 +782,19 @@ static const struct platform_device_id max14577_muic_id[] = { }; MODULE_DEVICE_TABLE(platform, max14577_muic_id); +static const struct of_device_id of_max14577_muic_dt_match[] = { + { .compatible = "maxim,max14577-muic", + .data = (void *)MAXIM_DEVICE_TYPE_MAX14577, }, + { .compatible = "maxim,max77836-muic", + .data = (void *)MAXIM_DEVICE_TYPE_MAX77836, }, + { }, +}; +MODULE_DEVICE_TABLE(of, of_max14577_muic_dt_match); + static struct platform_driver max14577_muic_driver = { .driver = { .name = "max14577-muic", + .of_match_table = of_max14577_muic_dt_match, }, .probe = max14577_muic_probe, .remove = max14577_muic_remove, diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index 2dfbfec572f9..0a6438cbb3f3 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -900,7 +900,7 @@ int extcon_register_notifier(struct extcon_dev *edev, unsigned int id, struct notifier_block *nb) { unsigned long flags; - int ret, idx = -EINVAL; + int ret, idx; if (!edev || !nb) return -EINVAL; diff --git a/drivers/firmware/stratix10-rsu.c b/drivers/firmware/stratix10-rsu.c index f8533338b018..4379475c99ed 100644 --- a/drivers/firmware/stratix10-rsu.c +++ b/drivers/firmware/stratix10-rsu.c @@ -72,7 +72,7 @@ static void rsu_status_callback(struct stratix10_svc_client *client, struct stratix10_rsu_priv *priv = client->priv; struct arm_smccc_res *res = (struct arm_smccc_res *)data->kaddr1; - if (data->status == BIT(SVC_STATUS_RSU_OK)) { + if (data->status == BIT(SVC_STATUS_OK)) { priv->status.version = FIELD_GET(RSU_VERSION_MASK, res->a2); priv->status.state = FIELD_GET(RSU_STATE_MASK, res->a2); @@ -108,9 +108,9 @@ static void rsu_command_callback(struct stratix10_svc_client *client, { struct stratix10_rsu_priv *priv = client->priv; - if (data->status == BIT(SVC_STATUS_RSU_NO_SUPPORT)) + if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) dev_warn(client->dev, "Secure FW doesn't support notify\n"); - else if (data->status == BIT(SVC_STATUS_RSU_ERROR)) + else if (data->status == BIT(SVC_STATUS_ERROR)) dev_err(client->dev, "Failure, returned status is %lu\n", BIT(data->status)); @@ -133,9 +133,9 @@ static void rsu_retry_callback(struct stratix10_svc_client *client, struct stratix10_rsu_priv *priv = client->priv; unsigned int *counter = (unsigned int *)data->kaddr1; - if (data->status == BIT(SVC_STATUS_RSU_OK)) + if (data->status == BIT(SVC_STATUS_OK)) priv->retry_counter = *counter; - else if (data->status == BIT(SVC_STATUS_RSU_NO_SUPPORT)) + else if (data->status == BIT(SVC_STATUS_NO_SUPPORT)) dev_warn(client->dev, "Secure FW doesn't support retry\n"); else dev_err(client->dev, "Failed to get retry counter %lu\n", diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index d5f0769f3761..e0db8dbfc9d1 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -214,7 +214,7 @@ static void svc_thread_cmd_data_claim(struct stratix10_svc_controller *ctrl, complete(&ctrl->complete_status); break; } - cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_DONE); + cb_data->status = BIT(SVC_STATUS_BUFFER_DONE); cb_data->kaddr1 = svc_pa_to_va(res.a1); cb_data->kaddr2 = (res.a2) ? svc_pa_to_va(res.a2) : NULL; @@ -227,7 +227,7 @@ static void svc_thread_cmd_data_claim(struct stratix10_svc_controller *ctrl, __func__); } } while (res.a0 == INTEL_SIP_SMC_STATUS_OK || - res.a0 == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY || + res.a0 == INTEL_SIP_SMC_STATUS_BUSY || wait_for_completion_timeout(&ctrl->complete_status, timeout)); } @@ -250,7 +250,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, cb_data->kaddr1 = NULL; cb_data->kaddr2 = NULL; cb_data->kaddr3 = NULL; - cb_data->status = BIT(SVC_STATUS_RECONFIG_ERROR); + cb_data->status = BIT(SVC_STATUS_ERROR); pr_debug("%s: polling config status\n", __func__); @@ -259,7 +259,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, ctrl->invoke_fn(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, 0, 0, 0, 0, 0, 0, 0, &res); if ((res.a0 == INTEL_SIP_SMC_STATUS_OK) || - (res.a0 == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR)) + (res.a0 == INTEL_SIP_SMC_STATUS_ERROR)) break; /* @@ -271,7 +271,7 @@ static void svc_thread_cmd_config_status(struct stratix10_svc_controller *ctrl, } if (res.a0 == INTEL_SIP_SMC_STATUS_OK && count_in_sec) - cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED); + cb_data->status = BIT(SVC_STATUS_COMPLETED); p_data->chan->scl->receive_cb(p_data->chan->scl, cb_data); } @@ -294,24 +294,18 @@ static void svc_thread_recv_status_ok(struct stratix10_svc_data *p_data, switch (p_data->command) { case COMMAND_RECONFIG: - cb_data->status = BIT(SVC_STATUS_RECONFIG_REQUEST_OK); + case COMMAND_RSU_UPDATE: + case COMMAND_RSU_NOTIFY: + cb_data->status = BIT(SVC_STATUS_OK); break; case COMMAND_RECONFIG_DATA_SUBMIT: - cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED); - break; - case COMMAND_NOOP: - cb_data->status = BIT(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED); - cb_data->kaddr1 = svc_pa_to_va(res.a1); + cb_data->status = BIT(SVC_STATUS_BUFFER_SUBMITTED); break; case COMMAND_RECONFIG_STATUS: - cb_data->status = BIT(SVC_STATUS_RECONFIG_COMPLETED); - break; - case COMMAND_RSU_UPDATE: - case COMMAND_RSU_NOTIFY: - cb_data->status = BIT(SVC_STATUS_RSU_OK); + cb_data->status = BIT(SVC_STATUS_COMPLETED); break; case COMMAND_RSU_RETRY: - cb_data->status = BIT(SVC_STATUS_RSU_OK); + cb_data->status = BIT(SVC_STATUS_OK); cb_data->kaddr1 = &res.a1; break; default: @@ -430,9 +424,9 @@ static int svc_normal_to_secure_thread(void *data) if (pdata->command == COMMAND_RSU_STATUS) { if (res.a0 == INTEL_SIP_SMC_RSU_ERROR) - cbdata->status = BIT(SVC_STATUS_RSU_ERROR); + cbdata->status = BIT(SVC_STATUS_ERROR); else - cbdata->status = BIT(SVC_STATUS_RSU_OK); + cbdata->status = BIT(SVC_STATUS_OK); cbdata->kaddr1 = &res; cbdata->kaddr2 = NULL; @@ -445,7 +439,7 @@ static int svc_normal_to_secure_thread(void *data) case INTEL_SIP_SMC_STATUS_OK: svc_thread_recv_status_ok(pdata, cbdata, res); break; - case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: + case INTEL_SIP_SMC_STATUS_BUSY: switch (pdata->command) { case COMMAND_RECONFIG_DATA_SUBMIT: svc_thread_cmd_data_claim(ctrl, @@ -460,33 +454,13 @@ static int svc_normal_to_secure_thread(void *data) break; } break; - case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED: + case INTEL_SIP_SMC_STATUS_REJECTED: pr_debug("%s: STATUS_REJECTED\n", __func__); break; - case INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: + case INTEL_SIP_SMC_STATUS_ERROR: case INTEL_SIP_SMC_RSU_ERROR: pr_err("%s: STATUS_ERROR\n", __func__); - switch (pdata->command) { - /* for FPGA mgr */ - case COMMAND_RECONFIG_DATA_CLAIM: - case COMMAND_RECONFIG: - case COMMAND_RECONFIG_DATA_SUBMIT: - case COMMAND_RECONFIG_STATUS: - cbdata->status = - BIT(SVC_STATUS_RECONFIG_ERROR); - break; - - /* for RSU */ - case COMMAND_RSU_STATUS: - case COMMAND_RSU_UPDATE: - case COMMAND_RSU_NOTIFY: - case COMMAND_RSU_RETRY: - cbdata->status = - BIT(SVC_STATUS_RSU_ERROR); - break; - } - - cbdata->status = BIT(SVC_STATUS_RECONFIG_ERROR); + cbdata->status = BIT(SVC_STATUS_ERROR); cbdata->kaddr1 = NULL; cbdata->kaddr2 = NULL; cbdata->kaddr3 = NULL; @@ -502,7 +476,7 @@ static int svc_normal_to_secure_thread(void *data) if ((pdata->command == COMMAND_RSU_RETRY) || (pdata->command == COMMAND_RSU_NOTIFY)) { cbdata->status = - BIT(SVC_STATUS_RSU_NO_SUPPORT); + BIT(SVC_STATUS_NO_SUPPORT); cbdata->kaddr1 = NULL; cbdata->kaddr2 = NULL; cbdata->kaddr3 = NULL; diff --git a/drivers/firmware/xilinx/zynqmp-debug.c b/drivers/firmware/xilinx/zynqmp-debug.c index 43bc6cfdab45..99606b34975e 100644 --- a/drivers/firmware/xilinx/zynqmp-debug.c +++ b/drivers/firmware/xilinx/zynqmp-debug.c @@ -85,14 +85,13 @@ static int get_pm_api_id(char *pm_api_req, u32 *pm_id) static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); u32 pm_api_version; int ret; struct zynqmp_pm_query_data qdata = {0}; switch (pm_id) { case PM_GET_API_VERSION: - ret = eemi_ops->get_api_version(&pm_api_version); + ret = zynqmp_pm_get_api_version(&pm_api_version); sprintf(debugfs_buf, "PM-API Version = %d.%d\n", pm_api_version >> 16, pm_api_version & 0xffff); break; @@ -102,7 +101,7 @@ static int process_api_request(u32 pm_id, u64 *pm_api_arg, u32 *pm_api_ret) qdata.arg2 = pm_api_arg[2]; qdata.arg3 = pm_api_arg[3]; - ret = eemi_ops->query_data(qdata, pm_api_ret); + ret = zynqmp_pm_query_data(qdata, pm_api_ret); if (ret) break; diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 41b65164a367..8d1ff2454e2e 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -2,7 +2,7 @@ /* * Xilinx Zynq MPSoC Firmware layer * - * Copyright (C) 2014-2018 Xilinx, Inc. + * Copyright (C) 2014-2020 Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> * Davorin Mista <davorin.mista@aggios.com> @@ -24,8 +24,6 @@ #include <linux/firmware/xlnx-zynqmp.h> #include "zynqmp-debug.h" -static const struct zynqmp_eemi_ops *eemi_ops_tbl; - static bool feature_check_enabled; static u32 zynqmp_pm_features[PM_API_MAX]; @@ -219,7 +217,7 @@ static u32 pm_tz_version; * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_get_api_version(u32 *version) +int zynqmp_pm_get_api_version(u32 *version) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -237,6 +235,7 @@ static int zynqmp_pm_get_api_version(u32 *version) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_get_api_version); /** * zynqmp_pm_get_chipid - Get silicon ID registers @@ -246,7 +245,7 @@ static int zynqmp_pm_get_api_version(u32 *version) * Return: Returns the status of the operation and the idcode and version * registers in @idcode and @version. */ -static int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) +int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -260,6 +259,7 @@ static int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid); /** * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version @@ -324,7 +324,7 @@ static int get_set_conduit_method(struct device_node *np) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) +int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) { int ret; @@ -338,6 +338,7 @@ static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) */ return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_query_data); /** * zynqmp_pm_clock_enable() - Enable the clock for given id @@ -348,10 +349,11 @@ static int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_enable(u32 clock_id) +int zynqmp_pm_clock_enable(u32 clock_id) { return zynqmp_pm_invoke_fn(PM_CLOCK_ENABLE, clock_id, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_enable); /** * zynqmp_pm_clock_disable() - Disable the clock for given id @@ -362,10 +364,11 @@ static int zynqmp_pm_clock_enable(u32 clock_id) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_disable(u32 clock_id) +int zynqmp_pm_clock_disable(u32 clock_id) { return zynqmp_pm_invoke_fn(PM_CLOCK_DISABLE, clock_id, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_disable); /** * zynqmp_pm_clock_getstate() - Get the clock state for given id @@ -377,7 +380,7 @@ static int zynqmp_pm_clock_disable(u32 clock_id) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) +int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -388,6 +391,7 @@ static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getstate); /** * zynqmp_pm_clock_setdivider() - Set the clock divider for given id @@ -399,11 +403,12 @@ static int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETDIVIDER, clock_id, divider, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setdivider); /** * zynqmp_pm_clock_getdivider() - Get the clock divider for given id @@ -415,7 +420,7 @@ static int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) +int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -426,6 +431,7 @@ static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getdivider); /** * zynqmp_pm_clock_setrate() - Set the clock rate for given id @@ -436,13 +442,14 @@ static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) +int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETRATE, clock_id, lower_32_bits(rate), upper_32_bits(rate), 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setrate); /** * zynqmp_pm_clock_getrate() - Get the clock rate for given id @@ -454,7 +461,7 @@ static int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) +int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -465,6 +472,7 @@ static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getrate); /** * zynqmp_pm_clock_setparent() - Set the clock parent for given id @@ -475,11 +483,12 @@ static int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) +int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) { return zynqmp_pm_invoke_fn(PM_CLOCK_SETPARENT, clock_id, parent_id, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_setparent); /** * zynqmp_pm_clock_getparent() - Get the clock parent for given id @@ -491,7 +500,7 @@ static int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) +int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -502,48 +511,191 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getparent); /** - * zynqmp_is_valid_ioctl() - Check whether IOCTL ID is valid or not - * @ioctl_id: IOCTL ID + * zynqmp_pm_set_pll_frac_mode() - PM API for set PLL mode + * + * @clk_id: PLL clock ID + * @mode: PLL mode (PLL_MODE_FRAC/PLL_MODE_INT) + * + * This function sets PLL mode * - * Return: 1 if IOCTL is valid else 0 + * Return: Returns status, either success or error+reason */ -static inline int zynqmp_is_valid_ioctl(u32 ioctl_id) +int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) { - switch (ioctl_id) { - case IOCTL_SD_DLL_RESET: - case IOCTL_SET_SD_TAPDELAY: - case IOCTL_SET_PLL_FRAC_MODE: - case IOCTL_GET_PLL_FRAC_MODE: - case IOCTL_SET_PLL_FRAC_DATA: - case IOCTL_GET_PLL_FRAC_DATA: - return 1; - default: - return 0; - } + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_PLL_FRAC_MODE, + clk_id, mode, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_mode); /** - * zynqmp_pm_ioctl() - PM IOCTL API for device control and configs - * @node_id: Node ID of the device - * @ioctl_id: ID of the requested IOCTL - * @arg1: Argument 1 to requested IOCTL call - * @arg2: Argument 2 to requested IOCTL call - * @out: Returned output value + * zynqmp_pm_get_pll_frac_mode() - PM API for get PLL mode + * + * @clk_id: PLL clock ID + * @mode: PLL mode * - * This function calls IOCTL to firmware for device control and configuration. + * This function return current PLL mode * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, - u32 *out) +int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) { - if (!zynqmp_is_valid_ioctl(ioctl_id)) - return -EINVAL; + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_GET_PLL_FRAC_MODE, + clk_id, 0, mode); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_mode); + +/** + * zynqmp_pm_set_pll_frac_data() - PM API for setting pll fraction data + * + * @clk_id: PLL clock ID + * @data: fraction data + * + * This function sets fraction data. + * It is valid for fraction mode only. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_PLL_FRAC_DATA, + clk_id, data, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_pll_frac_data); + +/** + * zynqmp_pm_get_pll_frac_data() - PM API for getting pll fraction data + * + * @clk_id: PLL clock ID + * @data: fraction data + * + * This function returns fraction data value. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_GET_PLL_FRAC_DATA, + clk_id, 0, data); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_data); + +/** + * zynqmp_pm_set_sd_tapdelay() - Set tap delay for the SD device + * + * @node_id Node ID of the device + * @type Type of tap delay to set (input/output) + * @value Value to set fot the tap delay + * + * This function sets input/output tap delay for the SD device. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, + type, value, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_tapdelay); + +/** + * zynqmp_pm_sd_dll_reset() - Reset DLL logic + * + * @node_id Node ID of the device + * @type Reset type + * + * This function resets DLL logic for the SD device. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, + type, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset); + +/** + * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs) + * @index GGS register index + * @value Register value to be written + * + * This function writes value to GGS register. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_write_ggs(u32 index, u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_GGS, + index, value, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_write_ggs); + +/** + * zynqmp_pm_write_ggs() - PM API for reading global general storage (ggs) + * @index GGS register index + * @value Register value to be written + * + * This function returns GGS register value. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_read_ggs(u32 index, u32 *value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_GGS, + index, 0, value); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_read_ggs); + +/** + * zynqmp_pm_write_pggs() - PM API for writing persistent global general + * storage (pggs) + * @index PGGS register index + * @value Register value to be written + * + * This function writes value to PGGS register. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_write_pggs(u32 index, u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_WRITE_PGGS, index, value, + NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_write_pggs); + +/** + * zynqmp_pm_write_pggs() - PM API for reading persistent global general + * storage (pggs) + * @index PGGS register index + * @value Register value to be written + * + * This function returns PGGS register value. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_read_pggs(u32 index, u32 *value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_READ_PGGS, index, 0, + value); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs); - return zynqmp_pm_invoke_fn(PM_IOCTL, node_id, ioctl_id, - arg1, arg2, out); +/** + * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status + * @value Status value to be written + * + * This function sets healthy bit value to indicate boot health status + * to firmware. + * + * @return Returns status, either success or error+reason + */ +int zynqmp_pm_set_boot_health_status(u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_BOOT_HEALTH_STATUS, + value, 0, NULL); } /** @@ -554,12 +706,13 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, - const enum zynqmp_pm_reset_action assert_flag) +int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, + const enum zynqmp_pm_reset_action assert_flag) { return zynqmp_pm_invoke_fn(PM_RESET_ASSERT, reset, assert_flag, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_reset_assert); /** * zynqmp_pm_reset_get_status - Get status of the reset @@ -568,8 +721,7 @@ static int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, - u32 *status) +int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -583,6 +735,7 @@ static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_reset_get_status); /** * zynqmp_pm_fpga_load - Perform the fpga load @@ -597,12 +750,12 @@ static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_fpga_load(const u64 address, const u32 size, - const u32 flags) +int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address), upper_32_bits(address), size, flags, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_load); /** * zynqmp_pm_fpga_get_status - Read value from PCAP status register @@ -613,7 +766,7 @@ static int zynqmp_pm_fpga_load(const u64 address, const u32 size, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_fpga_get_status(u32 *value) +int zynqmp_pm_fpga_get_status(u32 *value) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -626,6 +779,7 @@ static int zynqmp_pm_fpga_get_status(u32 *value) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); /** * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller @@ -636,10 +790,11 @@ static int zynqmp_pm_fpga_get_status(u32 *value) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_init_finalize(void) +int zynqmp_pm_init_finalize(void) { return zynqmp_pm_invoke_fn(PM_PM_INIT_FINALIZE, 0, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_init_finalize); /** * zynqmp_pm_set_suspend_mode() - Set system suspend mode @@ -649,10 +804,11 @@ static int zynqmp_pm_init_finalize(void) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_set_suspend_mode(u32 mode) +int zynqmp_pm_set_suspend_mode(u32 mode) { return zynqmp_pm_invoke_fn(PM_SET_SUSPEND_MODE, mode, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_set_suspend_mode); /** * zynqmp_pm_request_node() - Request a node with specific capabilities @@ -666,13 +822,13 @@ static int zynqmp_pm_set_suspend_mode(u32 mode) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack) +int zynqmp_pm_request_node(const u32 node, const u32 capabilities, + const u32 qos, const enum zynqmp_pm_request_ack ack) { return zynqmp_pm_invoke_fn(PM_REQUEST_NODE, node, capabilities, qos, ack, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_request_node); /** * zynqmp_pm_release_node() - Release a node @@ -684,10 +840,11 @@ static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_release_node(const u32 node) +int zynqmp_pm_release_node(const u32 node) { return zynqmp_pm_invoke_fn(PM_RELEASE_NODE, node, 0, 0, 0, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_release_node); /** * zynqmp_pm_set_requirement() - PM call to set requirement for PM slaves @@ -701,13 +858,14 @@ static int zynqmp_pm_release_node(const u32 node) * * Return: Returns status, either success or error+reason */ -static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack) +int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack) { return zynqmp_pm_invoke_fn(PM_SET_REQUIREMENT, node, capabilities, qos, ack, NULL); } +EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement); /** * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using @@ -717,7 +875,7 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, * * Return: Returns status, either success or error code. */ -static int zynqmp_pm_aes_engine(const u64 address, u32 *out) +int zynqmp_pm_aes_engine(const u64 address, u32 *out) { u32 ret_payload[PAYLOAD_ARG_CNT]; int ret; @@ -732,47 +890,304 @@ static int zynqmp_pm_aes_engine(const u64 address, u32 *out) return ret; } +EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine); -static const struct zynqmp_eemi_ops eemi_ops = { - .get_api_version = zynqmp_pm_get_api_version, - .get_chipid = zynqmp_pm_get_chipid, - .query_data = zynqmp_pm_query_data, - .clock_enable = zynqmp_pm_clock_enable, - .clock_disable = zynqmp_pm_clock_disable, - .clock_getstate = zynqmp_pm_clock_getstate, - .clock_setdivider = zynqmp_pm_clock_setdivider, - .clock_getdivider = zynqmp_pm_clock_getdivider, - .clock_setrate = zynqmp_pm_clock_setrate, - .clock_getrate = zynqmp_pm_clock_getrate, - .clock_setparent = zynqmp_pm_clock_setparent, - .clock_getparent = zynqmp_pm_clock_getparent, - .ioctl = zynqmp_pm_ioctl, - .reset_assert = zynqmp_pm_reset_assert, - .reset_get_status = zynqmp_pm_reset_get_status, - .init_finalize = zynqmp_pm_init_finalize, - .set_suspend_mode = zynqmp_pm_set_suspend_mode, - .request_node = zynqmp_pm_request_node, - .release_node = zynqmp_pm_release_node, - .set_requirement = zynqmp_pm_set_requirement, - .fpga_load = zynqmp_pm_fpga_load, - .fpga_get_status = zynqmp_pm_fpga_get_status, - .aes = zynqmp_pm_aes_engine, +/** + * zynqmp_pm_system_shutdown - PM call to request a system shutdown or restart + * @type: Shutdown or restart? 0 for shutdown, 1 for restart + * @subtype: Specifies which system should be restarted or shut down + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) +{ + return zynqmp_pm_invoke_fn(PM_SYSTEM_SHUTDOWN, type, subtype, + 0, 0, NULL); +} + +/** + * struct zynqmp_pm_shutdown_scope - Struct for shutdown scope + * @subtype: Shutdown subtype + * @name: Matching string for scope argument + * + * This struct encapsulates mapping between shutdown scope ID and string. + */ +struct zynqmp_pm_shutdown_scope { + const enum zynqmp_pm_shutdown_subtype subtype; + const char *name; +}; + +static struct zynqmp_pm_shutdown_scope shutdown_scopes[] = { + [ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM] = { + .subtype = ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM, + .name = "subsystem", + }, + [ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY] = { + .subtype = ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY, + .name = "ps_only", + }, + [ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM] = { + .subtype = ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM, + .name = "system", + }, }; +static struct zynqmp_pm_shutdown_scope *selected_scope = + &shutdown_scopes[ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM]; + /** - * zynqmp_pm_get_eemi_ops - Get eemi ops functions + * zynqmp_pm_is_shutdown_scope_valid - Check if shutdown scope string is valid + * @scope_string: Shutdown scope string * - * Return: Pointer of eemi_ops structure + * Return: Return pointer to matching shutdown scope struct from + * array of available options in system if string is valid, + * otherwise returns NULL. */ -const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) +static struct zynqmp_pm_shutdown_scope* + zynqmp_pm_is_shutdown_scope_valid(const char *scope_string) +{ + int count; + + for (count = 0; count < ARRAY_SIZE(shutdown_scopes); count++) + if (sysfs_streq(scope_string, shutdown_scopes[count].name)) + return &shutdown_scopes[count]; + + return NULL; +} + +static ssize_t shutdown_scope_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(shutdown_scopes); i++) { + if (&shutdown_scopes[i] == selected_scope) { + strcat(buf, "["); + strcat(buf, shutdown_scopes[i].name); + strcat(buf, "]"); + } else { + strcat(buf, shutdown_scopes[i].name); + } + strcat(buf, " "); + } + strcat(buf, "\n"); + + return strlen(buf); +} + +static ssize_t shutdown_scope_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + struct zynqmp_pm_shutdown_scope *scope; + + scope = zynqmp_pm_is_shutdown_scope_valid(buf); + if (!scope) + return -EINVAL; + + ret = zynqmp_pm_system_shutdown(ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY, + scope->subtype); + if (ret) { + pr_err("unable to set shutdown scope %s\n", buf); + return ret; + } + + selected_scope = scope; + + return count; +} + +static DEVICE_ATTR_RW(shutdown_scope); + +static ssize_t health_status_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int ret; + unsigned int value; + + ret = kstrtouint(buf, 10, &value); + if (ret) + return ret; + + ret = zynqmp_pm_set_boot_health_status(value); + if (ret) { + dev_err(device, "unable to set healthy bit value to %u\n", + value); + return ret; + } + + return count; +} + +static DEVICE_ATTR_WO(health_status); + +static ssize_t ggs_show(struct device *device, + struct device_attribute *attr, + char *buf, + u32 reg) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_read_ggs(reg, ret_payload); + if (ret) + return ret; + + return sprintf(buf, "0x%x\n", ret_payload[1]); +} + +static ssize_t ggs_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count, + u32 reg) +{ + long value; + int ret; + + if (reg >= GSS_NUM_REGS) + return -EINVAL; + + ret = kstrtol(buf, 16, &value); + if (ret) { + count = -EFAULT; + goto err; + } + + ret = zynqmp_pm_write_ggs(reg, value); + if (ret) + count = -EFAULT; +err: + return count; +} + +/* GGS register show functions */ +#define GGS0_SHOW(N) \ + ssize_t ggs##N##_show(struct device *device, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + return ggs_show(device, attr, buf, N); \ + } + +static GGS0_SHOW(0); +static GGS0_SHOW(1); +static GGS0_SHOW(2); +static GGS0_SHOW(3); + +/* GGS register store function */ +#define GGS0_STORE(N) \ + ssize_t ggs##N##_store(struct device *device, \ + struct device_attribute *attr, \ + const char *buf, \ + size_t count) \ + { \ + return ggs_store(device, attr, buf, count, N); \ + } + +static GGS0_STORE(0); +static GGS0_STORE(1); +static GGS0_STORE(2); +static GGS0_STORE(3); + +static ssize_t pggs_show(struct device *device, + struct device_attribute *attr, + char *buf, + u32 reg) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = zynqmp_pm_read_pggs(reg, ret_payload); + if (ret) + return ret; + + return sprintf(buf, "0x%x\n", ret_payload[1]); +} + +static ssize_t pggs_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count, + u32 reg) { - if (eemi_ops_tbl) - return eemi_ops_tbl; - else - return ERR_PTR(-EPROBE_DEFER); + long value; + int ret; + + if (reg >= GSS_NUM_REGS) + return -EINVAL; + ret = kstrtol(buf, 16, &value); + if (ret) { + count = -EFAULT; + goto err; + } + + ret = zynqmp_pm_write_pggs(reg, value); + if (ret) + count = -EFAULT; + +err: + return count; } -EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops); + +#define PGGS0_SHOW(N) \ + ssize_t pggs##N##_show(struct device *device, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + return pggs_show(device, attr, buf, N); \ + } + +#define PGGS0_STORE(N) \ + ssize_t pggs##N##_store(struct device *device, \ + struct device_attribute *attr, \ + const char *buf, \ + size_t count) \ + { \ + return pggs_store(device, attr, buf, count, N); \ + } + +/* PGGS register show functions */ +static PGGS0_SHOW(0); +static PGGS0_SHOW(1); +static PGGS0_SHOW(2); +static PGGS0_SHOW(3); + +/* PGGS register store functions */ +static PGGS0_STORE(0); +static PGGS0_STORE(1); +static PGGS0_STORE(2); +static PGGS0_STORE(3); + +/* GGS register attributes */ +static DEVICE_ATTR_RW(ggs0); +static DEVICE_ATTR_RW(ggs1); +static DEVICE_ATTR_RW(ggs2); +static DEVICE_ATTR_RW(ggs3); + +/* PGGS register attributes */ +static DEVICE_ATTR_RW(pggs0); +static DEVICE_ATTR_RW(pggs1); +static DEVICE_ATTR_RW(pggs2); +static DEVICE_ATTR_RW(pggs3); + +static struct attribute *zynqmp_firmware_attrs[] = { + &dev_attr_ggs0.attr, + &dev_attr_ggs1.attr, + &dev_attr_ggs2.attr, + &dev_attr_ggs3.attr, + &dev_attr_pggs0.attr, + &dev_attr_pggs1.attr, + &dev_attr_pggs2.attr, + &dev_attr_pggs3.attr, + &dev_attr_shutdown_scope.attr, + &dev_attr_health_status.attr, + NULL, +}; + +ATTRIBUTE_GROUPS(zynqmp_firmware); static int zynqmp_firmware_probe(struct platform_device *pdev) { @@ -820,11 +1235,6 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) pr_info("%s Trustzone version v%d.%d\n", __func__, pm_tz_version >> 16, pm_tz_version & 0xFFFF); - /* Assign eemi_ops_table */ - eemi_ops_tbl = &eemi_ops; - - zynqmp_pm_api_debugfs_init(); - ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, firmware_devs, ARRAY_SIZE(firmware_devs), NULL, 0, NULL); if (ret) { @@ -832,6 +1242,8 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) return ret; } + zynqmp_pm_api_debugfs_init(); + return of_platform_populate(dev->of_node, NULL, NULL, dev); } @@ -854,6 +1266,7 @@ static struct platform_driver zynqmp_firmware_driver = { .driver = { .name = "zynqmp_firmware", .of_match_table = zynqmp_firmware_of_match, + .dev_groups = zynqmp_firmware_groups, }, .probe = zynqmp_firmware_probe, .remove = zynqmp_firmware_remove, diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 72380e1d31c7..b2408a710662 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -156,7 +156,7 @@ config FPGA_DFL config FPGA_DFL_FME tristate "FPGA DFL FME Driver" - depends on FPGA_DFL && HWMON + depends on FPGA_DFL && HWMON && PERF_EVENTS help The FPGA Management Engine (FME) is a feature device implemented under Device Feature List (DFL) framework. Select this option to diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 4865b74b00a4..d8e21dfc6778 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o +dfl-fme-objs += dfl-fme-perf.o dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o dfl-afu-objs += dfl-afu-error.o diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl-afu-dma-region.c index d902acb36d14..02d8cbad1ae2 100644 --- a/drivers/fpga/dfl-afu-dma-region.c +++ b/drivers/fpga/dfl-afu-dma-region.c @@ -61,10 +61,10 @@ static int afu_dma_pin_pages(struct dfl_feature_platform_data *pdata, region->pages); if (pinned < 0) { ret = pinned; - goto put_pages; + goto free_pages; } else if (pinned != npages) { ret = -EFAULT; - goto free_pages; + goto put_pages; } dev_dbg(dev, "%d pages pinned\n", pinned); diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 65437b6a6842..b0c31789a909 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -561,14 +561,16 @@ static int afu_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; - - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = fdev; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = fdev; + } + mutex_unlock(&pdata->lock); - return 0; + return ret; } static int afu_release(struct inode *inode, struct file *filp) @@ -581,12 +583,14 @@ static int afu_release(struct inode *inode, struct file *filp) pdata = dev_get_platdata(&pdev->dev); mutex_lock(&pdata->lock); - __port_reset(pdev); - afu_dma_region_destroy(pdata); - mutex_unlock(&pdata->lock); - dfl_feature_dev_use_end(pdata); + if (!dfl_feature_dev_use_count(pdata)) { + __port_reset(pdev); + afu_dma_region_destroy(pdata); + } + mutex_unlock(&pdata->lock); + return 0; } @@ -746,6 +750,12 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return -EINVAL; } +static const struct vm_operations_struct afu_vma_ops = { +#ifdef CONFIG_HAVE_IOREMAP_PROT + .access = generic_access_phys, +#endif +}; + static int afu_mmap(struct file *filp, struct vm_area_struct *vma) { struct platform_device *pdev = filp->private_data; @@ -775,6 +785,9 @@ static int afu_mmap(struct file *filp, struct vm_area_struct *vma) !(region.flags & DFL_PORT_REGION_WRITE)) return -EPERM; + /* Support debug access to the mapping */ + vma->vm_ops = &afu_vma_ops; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); return remap_pfn_range(vma, vma->vm_start, diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index 1d4690c99268..fc210d4e1863 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -580,6 +580,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = { .ops = &fme_power_mgmt_ops, }, { + .id_table = fme_perf_id_table, + .ops = &fme_perf_ops, + }, + { .ops = NULL, }, }; @@ -600,14 +604,16 @@ static int fme_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; - - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = pdata; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = pdata; + } + mutex_unlock(&pdata->lock); - return 0; + return ret; } static int fme_release(struct inode *inode, struct file *filp) @@ -616,7 +622,10 @@ static int fme_release(struct inode *inode, struct file *filp) struct platform_device *pdev = pdata->dev; dev_dbg(&pdev->dev, "Device File Release\n"); + + mutex_lock(&pdata->lock); dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); return 0; } diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl-fme-perf.c new file mode 100644 index 000000000000..6ce1ed222ea4 --- /dev/null +++ b/drivers/fpga/dfl-fme-perf.c @@ -0,0 +1,1020 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA Management Engine (FME) Global Performance Reporting + * + * Copyright 2019 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei <luwei.kang@intel.com> + * Xiao Guangrong <guangrong.xiao@linux.intel.com> + * Wu Hao <hao.wu@intel.com> + * Xu Yilun <yilun.xu@intel.com> + * Joseph Grecco <joe.grecco@intel.com> + * Enno Luebbers <enno.luebbers@intel.com> + * Tim Whisonant <tim.whisonant@intel.com> + * Ananda Ravuri <ananda.ravuri@intel.com> + * Mitchel, Henry <henry.mitchel@intel.com> + */ + +#include <linux/perf_event.h> +#include "dfl.h" +#include "dfl-fme.h" + +/* + * Performance Counter Registers for Cache. + * + * Cache Events are listed below as CACHE_EVNT_*. + */ +#define CACHE_CTRL 0x8 +#define CACHE_RESET_CNTR BIT_ULL(0) +#define CACHE_FREEZE_CNTR BIT_ULL(8) +#define CACHE_CTRL_EVNT GENMASK_ULL(19, 16) +#define CACHE_EVNT_RD_HIT 0x0 +#define CACHE_EVNT_WR_HIT 0x1 +#define CACHE_EVNT_RD_MISS 0x2 +#define CACHE_EVNT_WR_MISS 0x3 +#define CACHE_EVNT_RSVD 0x4 +#define CACHE_EVNT_HOLD_REQ 0x5 +#define CACHE_EVNT_DATA_WR_PORT_CONTEN 0x6 +#define CACHE_EVNT_TAG_WR_PORT_CONTEN 0x7 +#define CACHE_EVNT_TX_REQ_STALL 0x8 +#define CACHE_EVNT_RX_REQ_STALL 0x9 +#define CACHE_EVNT_EVICTIONS 0xa +#define CACHE_EVNT_MAX CACHE_EVNT_EVICTIONS +#define CACHE_CHANNEL_SEL BIT_ULL(20) +#define CACHE_CHANNEL_RD 0 +#define CACHE_CHANNEL_WR 1 +#define CACHE_CNTR0 0x10 +#define CACHE_CNTR1 0x18 +#define CACHE_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define CACHE_CNTR_EVNT GENMASK_ULL(63, 60) + +/* + * Performance Counter Registers for Fabric. + * + * Fabric Events are listed below as FAB_EVNT_* + */ +#define FAB_CTRL 0x20 +#define FAB_RESET_CNTR BIT_ULL(0) +#define FAB_FREEZE_CNTR BIT_ULL(8) +#define FAB_CTRL_EVNT GENMASK_ULL(19, 16) +#define FAB_EVNT_PCIE0_RD 0x0 +#define FAB_EVNT_PCIE0_WR 0x1 +#define FAB_EVNT_PCIE1_RD 0x2 +#define FAB_EVNT_PCIE1_WR 0x3 +#define FAB_EVNT_UPI_RD 0x4 +#define FAB_EVNT_UPI_WR 0x5 +#define FAB_EVNT_MMIO_RD 0x6 +#define FAB_EVNT_MMIO_WR 0x7 +#define FAB_EVNT_MAX FAB_EVNT_MMIO_WR +#define FAB_PORT_ID GENMASK_ULL(21, 20) +#define FAB_PORT_FILTER BIT_ULL(23) +#define FAB_PORT_FILTER_DISABLE 0 +#define FAB_PORT_FILTER_ENABLE 1 +#define FAB_CNTR 0x28 +#define FAB_CNTR_EVNT_CNTR GENMASK_ULL(59, 0) +#define FAB_CNTR_EVNT GENMASK_ULL(63, 60) + +/* + * Performance Counter Registers for Clock. + * + * Clock Counter can't be reset or frozen by SW. + */ +#define CLK_CNTR 0x30 +#define BASIC_EVNT_CLK 0x0 +#define BASIC_EVNT_MAX BASIC_EVNT_CLK + +/* + * Performance Counter Registers for IOMMU / VT-D. + * + * VT-D Events are listed below as VTD_EVNT_* and VTD_SIP_EVNT_* + */ +#define VTD_CTRL 0x38 +#define VTD_RESET_CNTR BIT_ULL(0) +#define VTD_FREEZE_CNTR BIT_ULL(8) +#define VTD_CTRL_EVNT GENMASK_ULL(19, 16) +#define VTD_EVNT_AFU_MEM_RD_TRANS 0x0 +#define VTD_EVNT_AFU_MEM_WR_TRANS 0x1 +#define VTD_EVNT_AFU_DEVTLB_RD_HIT 0x2 +#define VTD_EVNT_AFU_DEVTLB_WR_HIT 0x3 +#define VTD_EVNT_DEVTLB_4K_FILL 0x4 +#define VTD_EVNT_DEVTLB_2M_FILL 0x5 +#define VTD_EVNT_DEVTLB_1G_FILL 0x6 +#define VTD_EVNT_MAX VTD_EVNT_DEVTLB_1G_FILL +#define VTD_CNTR 0x40 +#define VTD_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define VTD_CNTR_EVNT GENMASK_ULL(63, 60) + +#define VTD_SIP_CTRL 0x48 +#define VTD_SIP_RESET_CNTR BIT_ULL(0) +#define VTD_SIP_FREEZE_CNTR BIT_ULL(8) +#define VTD_SIP_CTRL_EVNT GENMASK_ULL(19, 16) +#define VTD_SIP_EVNT_IOTLB_4K_HIT 0x0 +#define VTD_SIP_EVNT_IOTLB_2M_HIT 0x1 +#define VTD_SIP_EVNT_IOTLB_1G_HIT 0x2 +#define VTD_SIP_EVNT_SLPWC_L3_HIT 0x3 +#define VTD_SIP_EVNT_SLPWC_L4_HIT 0x4 +#define VTD_SIP_EVNT_RCC_HIT 0x5 +#define VTD_SIP_EVNT_IOTLB_4K_MISS 0x6 +#define VTD_SIP_EVNT_IOTLB_2M_MISS 0x7 +#define VTD_SIP_EVNT_IOTLB_1G_MISS 0x8 +#define VTD_SIP_EVNT_SLPWC_L3_MISS 0x9 +#define VTD_SIP_EVNT_SLPWC_L4_MISS 0xa +#define VTD_SIP_EVNT_RCC_MISS 0xb +#define VTD_SIP_EVNT_MAX VTD_SIP_EVNT_SLPWC_L4_MISS +#define VTD_SIP_CNTR 0X50 +#define VTD_SIP_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define VTD_SIP_CNTR_EVNT GENMASK_ULL(63, 60) + +#define PERF_TIMEOUT 30 + +#define PERF_MAX_PORT_NUM 1U + +/** + * struct fme_perf_priv - priv data structure for fme perf driver + * + * @dev: parent device. + * @ioaddr: mapped base address of mmio region. + * @pmu: pmu data structure for fme perf counters. + * @id: id of this fme performance report private feature. + * @fab_users: current user number on fabric counters. + * @fab_port_id: used to indicate current working mode of fabric counters. + * @fab_lock: lock to protect fabric counters working mode. + * @cpu: active CPU to which the PMU is bound for accesses. + * @cpuhp_node: node for CPU hotplug notifier link. + * @cpuhp_state: state for CPU hotplug notification; + */ +struct fme_perf_priv { + struct device *dev; + void __iomem *ioaddr; + struct pmu pmu; + u64 id; + + u32 fab_users; + u32 fab_port_id; + spinlock_t fab_lock; + + unsigned int cpu; + struct hlist_node node; + enum cpuhp_state cpuhp_state; +}; + +/** + * struct fme_perf_event_ops - callbacks for fme perf events + * + * @event_init: callback invoked during event init. + * @event_destroy: callback invoked during event destroy. + * @read_counter: callback to read hardware counters. + */ +struct fme_perf_event_ops { + int (*event_init)(struct fme_perf_priv *priv, u32 event, u32 portid); + void (*event_destroy)(struct fme_perf_priv *priv, u32 event, + u32 portid); + u64 (*read_counter)(struct fme_perf_priv *priv, u32 event, u32 portid); +}; + +#define to_fme_perf_priv(_pmu) container_of(_pmu, struct fme_perf_priv, pmu) + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pmu *pmu = dev_get_drvdata(dev); + struct fme_perf_priv *priv; + + priv = to_fme_perf_priv(pmu); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(priv->cpu)); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *fme_perf_cpumask_attrs[] = { + &dev_attr_cpumask.attr, + NULL, +}; + +static struct attribute_group fme_perf_cpumask_group = { + .attrs = fme_perf_cpumask_attrs, +}; + +#define FME_EVENT_MASK GENMASK_ULL(11, 0) +#define FME_EVENT_SHIFT 0 +#define FME_EVTYPE_MASK GENMASK_ULL(15, 12) +#define FME_EVTYPE_SHIFT 12 +#define FME_EVTYPE_BASIC 0 +#define FME_EVTYPE_CACHE 1 +#define FME_EVTYPE_FABRIC 2 +#define FME_EVTYPE_VTD 3 +#define FME_EVTYPE_VTD_SIP 4 +#define FME_EVTYPE_MAX FME_EVTYPE_VTD_SIP +#define FME_PORTID_MASK GENMASK_ULL(23, 16) +#define FME_PORTID_SHIFT 16 +#define FME_PORTID_ROOT (0xffU) + +#define get_event(_config) FIELD_GET(FME_EVENT_MASK, _config) +#define get_evtype(_config) FIELD_GET(FME_EVTYPE_MASK, _config) +#define get_portid(_config) FIELD_GET(FME_PORTID_MASK, _config) + +PMU_FORMAT_ATTR(event, "config:0-11"); +PMU_FORMAT_ATTR(evtype, "config:12-15"); +PMU_FORMAT_ATTR(portid, "config:16-23"); + +static struct attribute *fme_perf_format_attrs[] = { + &format_attr_event.attr, + &format_attr_evtype.attr, + &format_attr_portid.attr, + NULL, +}; + +static struct attribute_group fme_perf_format_group = { + .name = "format", + .attrs = fme_perf_format_attrs, +}; + +/* + * There are no default events, but we need to create + * "events" group (with empty attrs) before updating + * it with detected events (using pmu->attr_update). + */ +static struct attribute *fme_perf_events_attrs_empty[] = { + NULL, +}; + +static struct attribute_group fme_perf_events_group = { + .name = "events", + .attrs = fme_perf_events_attrs_empty, +}; + +static const struct attribute_group *fme_perf_groups[] = { + &fme_perf_format_group, + &fme_perf_cpumask_group, + &fme_perf_events_group, + NULL, +}; + +static bool is_portid_root(u32 portid) +{ + return portid == FME_PORTID_ROOT; +} + +static bool is_portid_port(u32 portid) +{ + return portid < PERF_MAX_PORT_NUM; +} + +static bool is_portid_root_or_port(u32 portid) +{ + return is_portid_root(portid) || is_portid_port(portid); +} + +static u64 fme_read_perf_cntr_reg(void __iomem *addr) +{ + u32 low; + u64 v; + + /* + * For 64bit counter registers, the counter may increases and carries + * out of bit [31] between 2 32bit reads. So add extra reads to help + * to prevent this issue. This only happens in platforms which don't + * support 64bit read - readq is split into 2 readl. + */ + do { + v = readq(addr); + low = readl(addr); + } while (((u32)v) > low); + + return v; +} + +static int basic_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (event <= BASIC_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 basic_read_event_counter(struct fme_perf_priv *priv, + u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + + return fme_read_perf_cntr_reg(base + CLK_CNTR); +} + +static int cache_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= CACHE_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 cache_read_event_counter(struct fme_perf_priv *priv, + u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v, count; + u8 channel; + + if (event == CACHE_EVNT_WR_HIT || event == CACHE_EVNT_WR_MISS || + event == CACHE_EVNT_DATA_WR_PORT_CONTEN || + event == CACHE_EVNT_TAG_WR_PORT_CONTEN) + channel = CACHE_CHANNEL_WR; + else + channel = CACHE_CHANNEL_RD; + + /* set channel access type and cache event code. */ + v = readq(base + CACHE_CTRL); + v &= ~(CACHE_CHANNEL_SEL | CACHE_CTRL_EVNT); + v |= FIELD_PREP(CACHE_CHANNEL_SEL, channel); + v |= FIELD_PREP(CACHE_CTRL_EVNT, event); + writeq(v, base + CACHE_CTRL); + + if (readq_poll_timeout_atomic(base + CACHE_CNTR0, v, + FIELD_GET(CACHE_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched cache event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + CACHE_CNTR0); + count = FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); + v = fme_read_perf_cntr_reg(base + CACHE_CNTR1); + count += FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); + + return count; +} + +static bool is_fabric_event_supported(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + if (event > FAB_EVNT_MAX || !is_portid_root_or_port(portid)) + return false; + + if (priv->id == FME_FEATURE_ID_GLOBAL_DPERF && + (event == FAB_EVNT_PCIE1_RD || event == FAB_EVNT_UPI_RD || + event == FAB_EVNT_PCIE1_WR || event == FAB_EVNT_UPI_WR)) + return false; + + return true; +} + +static int fabric_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + int ret = 0; + u64 v; + + if (!is_fabric_event_supported(priv, event, portid)) + return -EINVAL; + + /* + * as fabric counter set only can be in either overall or port mode. + * In overall mode, it counts overall data for FPGA, and in port mode, + * it is configured to monitor on one individual port. + * + * so every time, a new event is initialized, driver checks + * current working mode and if someone is using this counter set. + */ + spin_lock(&priv->fab_lock); + if (priv->fab_users && priv->fab_port_id != portid) { + dev_dbg(priv->dev, "conflict fabric event monitoring mode.\n"); + ret = -EOPNOTSUPP; + goto exit; + } + + priv->fab_users++; + + /* + * skip if current working mode matches, otherwise change the working + * mode per input port_id, to monitor overall data or another port. + */ + if (priv->fab_port_id == portid) + goto exit; + + priv->fab_port_id = portid; + + v = readq(base + FAB_CTRL); + v &= ~(FAB_PORT_FILTER | FAB_PORT_ID); + + if (is_portid_root(portid)) { + v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_DISABLE); + } else { + v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_ENABLE); + v |= FIELD_PREP(FAB_PORT_ID, portid); + } + writeq(v, base + FAB_CTRL); + +exit: + spin_unlock(&priv->fab_lock); + return ret; +} + +static void fabric_event_destroy(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + spin_lock(&priv->fab_lock); + priv->fab_users--; + spin_unlock(&priv->fab_lock); +} + +static u64 fabric_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + v = readq(base + FAB_CTRL); + v &= ~FAB_CTRL_EVNT; + v |= FIELD_PREP(FAB_CTRL_EVNT, event); + writeq(v, base + FAB_CTRL); + + if (readq_poll_timeout_atomic(base + FAB_CNTR, v, + FIELD_GET(FAB_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched fab event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + FAB_CNTR); + return FIELD_GET(FAB_CNTR_EVNT_CNTR, v); +} + +static int vtd_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= VTD_EVNT_MAX && is_portid_port(portid)) + return 0; + + return -EINVAL; +} + +static u64 vtd_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + event += (portid * (VTD_EVNT_MAX + 1)); + + v = readq(base + VTD_CTRL); + v &= ~VTD_CTRL_EVNT; + v |= FIELD_PREP(VTD_CTRL_EVNT, event); + writeq(v, base + VTD_CTRL); + + if (readq_poll_timeout_atomic(base + VTD_CNTR, v, + FIELD_GET(VTD_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched vtd event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + VTD_CNTR); + return FIELD_GET(VTD_CNTR_EVNT_CNTR, v); +} + +static int vtd_sip_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= VTD_SIP_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 vtd_sip_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + v = readq(base + VTD_SIP_CTRL); + v &= ~VTD_SIP_CTRL_EVNT; + v |= FIELD_PREP(VTD_SIP_CTRL_EVNT, event); + writeq(v, base + VTD_SIP_CTRL); + + if (readq_poll_timeout_atomic(base + VTD_SIP_CNTR, v, + FIELD_GET(VTD_SIP_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched vtd sip event code in counter register\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + VTD_SIP_CNTR); + return FIELD_GET(VTD_SIP_CNTR_EVNT_CNTR, v); +} + +static struct fme_perf_event_ops fme_perf_event_ops[] = { + [FME_EVTYPE_BASIC] = {.event_init = basic_event_init, + .read_counter = basic_read_event_counter,}, + [FME_EVTYPE_CACHE] = {.event_init = cache_event_init, + .read_counter = cache_read_event_counter,}, + [FME_EVTYPE_FABRIC] = {.event_init = fabric_event_init, + .event_destroy = fabric_event_destroy, + .read_counter = fabric_read_event_counter,}, + [FME_EVTYPE_VTD] = {.event_init = vtd_event_init, + .read_counter = vtd_read_event_counter,}, + [FME_EVTYPE_VTD_SIP] = {.event_init = vtd_sip_event_init, + .read_counter = vtd_sip_read_event_counter,}, +}; + +static ssize_t fme_perf_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr; + unsigned long config; + char *ptr = buf; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + config = (unsigned long)eattr->var; + + ptr += sprintf(ptr, "event=0x%02x", (unsigned int)get_event(config)); + ptr += sprintf(ptr, ",evtype=0x%02x", (unsigned int)get_evtype(config)); + + if (is_portid_root(get_portid(config))) + ptr += sprintf(ptr, ",portid=0x%02x\n", FME_PORTID_ROOT); + else + ptr += sprintf(ptr, ",portid=?\n"); + + return (ssize_t)(ptr - buf); +} + +#define FME_EVENT_ATTR(_name) \ + __ATTR(_name, 0444, fme_perf_event_show, NULL) + +#define FME_PORT_EVENT_CONFIG(_event, _type) \ + (void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ + (((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK)) + +#define FME_EVENT_CONFIG(_event, _type) \ + (void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ + (((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK) | \ + (FME_PORTID_ROOT << FME_PORTID_SHIFT)) + +/* FME Perf Basic Events */ +#define FME_EVENT_BASIC(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_##_name = { \ + .attr = FME_EVENT_ATTR(_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_BASIC), \ +} + +FME_EVENT_BASIC(clock, BASIC_EVNT_CLK); + +static struct attribute *fme_perf_basic_events_attrs[] = { + &fme_perf_event_clock.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_basic_events_group = { + .name = "events", + .attrs = fme_perf_basic_events_attrs, +}; + +/* FME Perf Cache Events */ +#define FME_EVENT_CACHE(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_cache_##_name = { \ + .attr = FME_EVENT_ATTR(cache_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_CACHE), \ +} + +FME_EVENT_CACHE(read_hit, CACHE_EVNT_RD_HIT); +FME_EVENT_CACHE(read_miss, CACHE_EVNT_RD_MISS); +FME_EVENT_CACHE(write_hit, CACHE_EVNT_WR_HIT); +FME_EVENT_CACHE(write_miss, CACHE_EVNT_WR_MISS); +FME_EVENT_CACHE(hold_request, CACHE_EVNT_HOLD_REQ); +FME_EVENT_CACHE(tx_req_stall, CACHE_EVNT_TX_REQ_STALL); +FME_EVENT_CACHE(rx_req_stall, CACHE_EVNT_RX_REQ_STALL); +FME_EVENT_CACHE(eviction, CACHE_EVNT_EVICTIONS); +FME_EVENT_CACHE(data_write_port_contention, CACHE_EVNT_DATA_WR_PORT_CONTEN); +FME_EVENT_CACHE(tag_write_port_contention, CACHE_EVNT_TAG_WR_PORT_CONTEN); + +static struct attribute *fme_perf_cache_events_attrs[] = { + &fme_perf_event_cache_read_hit.attr.attr, + &fme_perf_event_cache_read_miss.attr.attr, + &fme_perf_event_cache_write_hit.attr.attr, + &fme_perf_event_cache_write_miss.attr.attr, + &fme_perf_event_cache_hold_request.attr.attr, + &fme_perf_event_cache_tx_req_stall.attr.attr, + &fme_perf_event_cache_rx_req_stall.attr.attr, + &fme_perf_event_cache_eviction.attr.attr, + &fme_perf_event_cache_data_write_port_contention.attr.attr, + &fme_perf_event_cache_tag_write_port_contention.attr.attr, + NULL, +}; + +static umode_t fme_perf_events_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct fme_perf_priv *priv = to_fme_perf_priv(pmu); + + return (priv->id == FME_FEATURE_ID_GLOBAL_IPERF) ? attr->mode : 0; +} + +static const struct attribute_group fme_perf_cache_events_group = { + .name = "events", + .attrs = fme_perf_cache_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +/* FME Perf Fabric Events */ +#define FME_EVENT_FABRIC(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_fab_##_name = { \ + .attr = FME_EVENT_ATTR(fab_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ +} + +#define FME_EVENT_FABRIC_PORT(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_fab_port_##_name = { \ + .attr = FME_EVENT_ATTR(fab_port_##_name), \ + .var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ +} + +FME_EVENT_FABRIC(pcie0_read, FAB_EVNT_PCIE0_RD); +FME_EVENT_FABRIC(pcie0_write, FAB_EVNT_PCIE0_WR); +FME_EVENT_FABRIC(pcie1_read, FAB_EVNT_PCIE1_RD); +FME_EVENT_FABRIC(pcie1_write, FAB_EVNT_PCIE1_WR); +FME_EVENT_FABRIC(upi_read, FAB_EVNT_UPI_RD); +FME_EVENT_FABRIC(upi_write, FAB_EVNT_UPI_WR); +FME_EVENT_FABRIC(mmio_read, FAB_EVNT_MMIO_RD); +FME_EVENT_FABRIC(mmio_write, FAB_EVNT_MMIO_WR); + +FME_EVENT_FABRIC_PORT(pcie0_read, FAB_EVNT_PCIE0_RD); +FME_EVENT_FABRIC_PORT(pcie0_write, FAB_EVNT_PCIE0_WR); +FME_EVENT_FABRIC_PORT(pcie1_read, FAB_EVNT_PCIE1_RD); +FME_EVENT_FABRIC_PORT(pcie1_write, FAB_EVNT_PCIE1_WR); +FME_EVENT_FABRIC_PORT(upi_read, FAB_EVNT_UPI_RD); +FME_EVENT_FABRIC_PORT(upi_write, FAB_EVNT_UPI_WR); +FME_EVENT_FABRIC_PORT(mmio_read, FAB_EVNT_MMIO_RD); +FME_EVENT_FABRIC_PORT(mmio_write, FAB_EVNT_MMIO_WR); + +static struct attribute *fme_perf_fabric_events_attrs[] = { + &fme_perf_event_fab_pcie0_read.attr.attr, + &fme_perf_event_fab_pcie0_write.attr.attr, + &fme_perf_event_fab_pcie1_read.attr.attr, + &fme_perf_event_fab_pcie1_write.attr.attr, + &fme_perf_event_fab_upi_read.attr.attr, + &fme_perf_event_fab_upi_write.attr.attr, + &fme_perf_event_fab_mmio_read.attr.attr, + &fme_perf_event_fab_mmio_write.attr.attr, + &fme_perf_event_fab_port_pcie0_read.attr.attr, + &fme_perf_event_fab_port_pcie0_write.attr.attr, + &fme_perf_event_fab_port_pcie1_read.attr.attr, + &fme_perf_event_fab_port_pcie1_write.attr.attr, + &fme_perf_event_fab_port_upi_read.attr.attr, + &fme_perf_event_fab_port_upi_write.attr.attr, + &fme_perf_event_fab_port_mmio_read.attr.attr, + &fme_perf_event_fab_port_mmio_write.attr.attr, + NULL, +}; + +static umode_t fme_perf_fabric_events_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct fme_perf_priv *priv = to_fme_perf_priv(pmu); + struct dev_ext_attribute *eattr; + unsigned long var; + + eattr = container_of(attr, struct dev_ext_attribute, attr.attr); + var = (unsigned long)eattr->var; + + if (is_fabric_event_supported(priv, get_event(var), get_portid(var))) + return attr->mode; + + return 0; +} + +static const struct attribute_group fme_perf_fabric_events_group = { + .name = "events", + .attrs = fme_perf_fabric_events_attrs, + .is_visible = fme_perf_fabric_events_visible, +}; + +/* FME Perf VTD Events */ +#define FME_EVENT_VTD_PORT(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_vtd_port_##_name = { \ + .attr = FME_EVENT_ATTR(vtd_port_##_name), \ + .var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_VTD), \ +} + +FME_EVENT_VTD_PORT(read_transaction, VTD_EVNT_AFU_MEM_RD_TRANS); +FME_EVENT_VTD_PORT(write_transaction, VTD_EVNT_AFU_MEM_WR_TRANS); +FME_EVENT_VTD_PORT(devtlb_read_hit, VTD_EVNT_AFU_DEVTLB_RD_HIT); +FME_EVENT_VTD_PORT(devtlb_write_hit, VTD_EVNT_AFU_DEVTLB_WR_HIT); +FME_EVENT_VTD_PORT(devtlb_4k_fill, VTD_EVNT_DEVTLB_4K_FILL); +FME_EVENT_VTD_PORT(devtlb_2m_fill, VTD_EVNT_DEVTLB_2M_FILL); +FME_EVENT_VTD_PORT(devtlb_1g_fill, VTD_EVNT_DEVTLB_1G_FILL); + +static struct attribute *fme_perf_vtd_events_attrs[] = { + &fme_perf_event_vtd_port_read_transaction.attr.attr, + &fme_perf_event_vtd_port_write_transaction.attr.attr, + &fme_perf_event_vtd_port_devtlb_read_hit.attr.attr, + &fme_perf_event_vtd_port_devtlb_write_hit.attr.attr, + &fme_perf_event_vtd_port_devtlb_4k_fill.attr.attr, + &fme_perf_event_vtd_port_devtlb_2m_fill.attr.attr, + &fme_perf_event_vtd_port_devtlb_1g_fill.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_vtd_events_group = { + .name = "events", + .attrs = fme_perf_vtd_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +/* FME Perf VTD SIP Events */ +#define FME_EVENT_VTD_SIP(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_vtd_sip_##_name = { \ + .attr = FME_EVENT_ATTR(vtd_sip_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_VTD_SIP), \ +} + +FME_EVENT_VTD_SIP(iotlb_4k_hit, VTD_SIP_EVNT_IOTLB_4K_HIT); +FME_EVENT_VTD_SIP(iotlb_2m_hit, VTD_SIP_EVNT_IOTLB_2M_HIT); +FME_EVENT_VTD_SIP(iotlb_1g_hit, VTD_SIP_EVNT_IOTLB_1G_HIT); +FME_EVENT_VTD_SIP(slpwc_l3_hit, VTD_SIP_EVNT_SLPWC_L3_HIT); +FME_EVENT_VTD_SIP(slpwc_l4_hit, VTD_SIP_EVNT_SLPWC_L4_HIT); +FME_EVENT_VTD_SIP(rcc_hit, VTD_SIP_EVNT_RCC_HIT); +FME_EVENT_VTD_SIP(iotlb_4k_miss, VTD_SIP_EVNT_IOTLB_4K_MISS); +FME_EVENT_VTD_SIP(iotlb_2m_miss, VTD_SIP_EVNT_IOTLB_2M_MISS); +FME_EVENT_VTD_SIP(iotlb_1g_miss, VTD_SIP_EVNT_IOTLB_1G_MISS); +FME_EVENT_VTD_SIP(slpwc_l3_miss, VTD_SIP_EVNT_SLPWC_L3_MISS); +FME_EVENT_VTD_SIP(slpwc_l4_miss, VTD_SIP_EVNT_SLPWC_L4_MISS); +FME_EVENT_VTD_SIP(rcc_miss, VTD_SIP_EVNT_RCC_MISS); + +static struct attribute *fme_perf_vtd_sip_events_attrs[] = { + &fme_perf_event_vtd_sip_iotlb_4k_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_2m_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_1g_hit.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l3_hit.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l4_hit.attr.attr, + &fme_perf_event_vtd_sip_rcc_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_4k_miss.attr.attr, + &fme_perf_event_vtd_sip_iotlb_2m_miss.attr.attr, + &fme_perf_event_vtd_sip_iotlb_1g_miss.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l3_miss.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l4_miss.attr.attr, + &fme_perf_event_vtd_sip_rcc_miss.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_vtd_sip_events_group = { + .name = "events", + .attrs = fme_perf_vtd_sip_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +static const struct attribute_group *fme_perf_events_groups[] = { + &fme_perf_basic_events_group, + &fme_perf_cache_events_group, + &fme_perf_fabric_events_group, + &fme_perf_vtd_events_group, + &fme_perf_vtd_sip_events_group, + NULL, +}; + +static struct fme_perf_event_ops *get_event_ops(u32 evtype) +{ + if (evtype > FME_EVTYPE_MAX) + return NULL; + + return &fme_perf_event_ops[evtype]; +} + +static void fme_perf_event_destroy(struct perf_event *event) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + + if (ops->event_destroy) + ops->event_destroy(priv, event->hw.idx, event->hw.config_base); +} + +static int fme_perf_event_init(struct perf_event *event) +{ + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + struct fme_perf_event_ops *ops; + u32 eventid, evtype, portid; + + /* test the event attr type check for PMU enumeration */ + if (event->attr.type != event->pmu->type) + return -ENOENT; + + /* + * fme counters are shared across all cores. + * Therefore, it does not support per-process mode. + * Also, it does not support event sampling mode. + */ + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + if (event->cpu < 0) + return -EINVAL; + + if (event->cpu != priv->cpu) + return -EINVAL; + + eventid = get_event(event->attr.config); + portid = get_portid(event->attr.config); + evtype = get_evtype(event->attr.config); + if (evtype > FME_EVTYPE_MAX) + return -EINVAL; + + hwc->event_base = evtype; + hwc->idx = (int)eventid; + hwc->config_base = portid; + + event->destroy = fme_perf_event_destroy; + + dev_dbg(priv->dev, "%s event=0x%x, evtype=0x%x, portid=0x%x,\n", + __func__, eventid, evtype, portid); + + ops = get_event_ops(evtype); + if (ops->event_init) + return ops->event_init(priv, eventid, portid); + + return 0; +} + +static void fme_perf_event_update(struct perf_event *event) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 now, prev, delta; + + now = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); + prev = local64_read(&hwc->prev_count); + delta = now - prev; + + local64_add(delta, &event->count); +} + +static void fme_perf_event_start(struct perf_event *event, int flags) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 count; + + count = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); + local64_set(&hwc->prev_count, count); +} + +static void fme_perf_event_stop(struct perf_event *event, int flags) +{ + fme_perf_event_update(event); +} + +static int fme_perf_event_add(struct perf_event *event, int flags) +{ + if (flags & PERF_EF_START) + fme_perf_event_start(event, flags); + + return 0; +} + +static void fme_perf_event_del(struct perf_event *event, int flags) +{ + fme_perf_event_stop(event, PERF_EF_UPDATE); +} + +static void fme_perf_event_read(struct perf_event *event) +{ + fme_perf_event_update(event); +} + +static void fme_perf_setup_hardware(struct fme_perf_priv *priv) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + /* read and save current working mode for fabric counters */ + v = readq(base + FAB_CTRL); + + if (FIELD_GET(FAB_PORT_FILTER, v) == FAB_PORT_FILTER_DISABLE) + priv->fab_port_id = FME_PORTID_ROOT; + else + priv->fab_port_id = FIELD_GET(FAB_PORT_ID, v); +} + +static int fme_perf_pmu_register(struct platform_device *pdev, + struct fme_perf_priv *priv) +{ + struct pmu *pmu = &priv->pmu; + char *name; + int ret; + + spin_lock_init(&priv->fab_lock); + + fme_perf_setup_hardware(priv); + + pmu->task_ctx_nr = perf_invalid_context; + pmu->attr_groups = fme_perf_groups; + pmu->attr_update = fme_perf_events_groups; + pmu->event_init = fme_perf_event_init; + pmu->add = fme_perf_event_add; + pmu->del = fme_perf_event_del; + pmu->start = fme_perf_event_start; + pmu->stop = fme_perf_event_stop; + pmu->read = fme_perf_event_read; + pmu->capabilities = PERF_PMU_CAP_NO_INTERRUPT | + PERF_PMU_CAP_NO_EXCLUDE; + + name = devm_kasprintf(priv->dev, GFP_KERNEL, "dfl_fme%d", pdev->id); + + ret = perf_pmu_register(pmu, name, -1); + if (ret) + return ret; + + return 0; +} + +static void fme_perf_pmu_unregister(struct fme_perf_priv *priv) +{ + perf_pmu_unregister(&priv->pmu); +} + +static int fme_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct fme_perf_priv *priv; + int target; + + priv = hlist_entry_safe(node, struct fme_perf_priv, node); + + if (cpu != priv->cpu) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + priv->cpu = target; + return 0; +} + +static int fme_perf_init(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct fme_perf_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->ioaddr = feature->ioaddr; + priv->id = feature->id; + priv->cpu = raw_smp_processor_id(); + + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/fpga/dfl_fme:online", + NULL, fme_perf_offline_cpu); + if (ret < 0) + return ret; + + priv->cpuhp_state = ret; + + /* Register the pmu instance for cpu hotplug */ + ret = cpuhp_state_add_instance_nocalls(priv->cpuhp_state, &priv->node); + if (ret) + goto cpuhp_instance_err; + + ret = fme_perf_pmu_register(pdev, priv); + if (ret) + goto pmu_register_err; + + feature->priv = priv; + return 0; + +pmu_register_err: + cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); +cpuhp_instance_err: + cpuhp_remove_multi_state(priv->cpuhp_state); + return ret; +} + +static void fme_perf_uinit(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct fme_perf_priv *priv = feature->priv; + + fme_perf_pmu_unregister(priv); + cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); + cpuhp_remove_multi_state(priv->cpuhp_state); +} + +const struct dfl_feature_id fme_perf_id_table[] = { + {.id = FME_FEATURE_ID_GLOBAL_IPERF,}, + {.id = FME_FEATURE_ID_GLOBAL_DPERF,}, + {0,} +}; + +const struct dfl_feature_ops fme_perf_ops = { + .init = fme_perf_init, + .uinit = fme_perf_uinit, +}; diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h index 6685c8ef965b..4195dd68193e 100644 --- a/drivers/fpga/dfl-fme.h +++ b/drivers/fpga/dfl-fme.h @@ -38,5 +38,7 @@ extern const struct dfl_feature_id fme_pr_mgmt_id_table[]; extern const struct dfl_feature_ops fme_global_err_ops; extern const struct dfl_feature_id fme_global_err_id_table[]; extern const struct attribute_group fme_global_err_group; +extern const struct dfl_feature_ops fme_perf_ops; +extern const struct dfl_feature_id fme_perf_id_table[]; #endif /* __DFL_FME_H */ diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 96a2b8274a33..990994874bf1 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -1079,6 +1079,7 @@ static int __init dfl_fpga_init(void) */ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1093,7 +1094,11 @@ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) goto put_dev_exit; } - ret = dfl_feature_dev_use_begin(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, true); + mutex_unlock(&pdata->lock); if (ret) goto put_dev_exit; @@ -1120,6 +1125,7 @@ EXPORT_SYMBOL_GPL(dfl_fpga_cdev_release_port); */ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1138,7 +1144,12 @@ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) if (ret) goto put_dev_exit; - dfl_feature_dev_use_end(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); + cdev->released_port_num--; put_dev_exit: put_device(&port_pdev->dev); diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 9f0e656de720..2f5d3052e36e 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -197,16 +197,16 @@ struct dfl_feature_driver { * feature dev (platform device)'s reources. * @ioaddr: mapped mmio resource address. * @ops: ops of this sub feature. + * @priv: priv data of this feature. */ struct dfl_feature { u64 id; int resource_index; void __iomem *ioaddr; const struct dfl_feature_ops *ops; + void *priv; }; -#define DEV_STATUS_IN_USE 0 - #define FEATURE_DEV_ID_UNUSED (-1) /** @@ -219,8 +219,9 @@ struct dfl_feature { * @dfl_cdev: ptr to container device. * @id: id used for this feature device. * @disable_count: count for port disable. + * @excl_open: set on feature device exclusive open. + * @open_count: count for feature device open. * @num: number for sub features. - * @dev_status: dev status (e.g. DEV_STATUS_IN_USE). * @private: ptr to feature dev private data. * @features: sub features of this feature dev. */ @@ -232,26 +233,46 @@ struct dfl_feature_platform_data { struct dfl_fpga_cdev *dfl_cdev; int id; unsigned int disable_count; - unsigned long dev_status; + bool excl_open; + int open_count; void *private; int num; - struct dfl_feature features[0]; + struct dfl_feature features[]; }; static inline -int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata) +int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, + bool excl) { - /* Test and set IN_USE flags to ensure file is exclusively used */ - if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status)) + if (pdata->excl_open) return -EBUSY; + if (excl) { + if (pdata->open_count) + return -EBUSY; + + pdata->excl_open = true; + } + pdata->open_count++; + return 0; } static inline void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) { - clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status); + pdata->excl_open = false; + + if (WARN_ON(pdata->open_count <= 0)) + return; + + pdata->open_count--; +} + +static inline +int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) +{ + return pdata->open_count; } static inline diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c index 56e112e14a10..8d689fea0dab 100644 --- a/drivers/fpga/ice40-spi.c +++ b/drivers/fpga/ice40-spi.c @@ -46,10 +46,16 @@ static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, struct spi_message message; struct spi_transfer assert_cs_then_reset_delay = { .cs_change = 1, - .delay_usecs = ICE40_SPI_RESET_DELAY + .delay = { + .value = ICE40_SPI_RESET_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; struct spi_transfer housekeeping_delay_then_release_cs = { - .delay_usecs = ICE40_SPI_HOUSEKEEPING_DELAY + .delay = { + .value = ICE40_SPI_HOUSEKEEPING_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; int ret; diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c index 4d8a87641587..b316369156fe 100644 --- a/drivers/fpga/machxo2-spi.c +++ b/drivers/fpga/machxo2-spi.c @@ -157,7 +157,8 @@ static int machxo2_cleanup(struct fpga_manager *mgr) spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) @@ -208,7 +209,8 @@ static int machxo2_write_init(struct fpga_manager *mgr, spi_message_init(&msg); tx[0].tx_buf = &enable; tx[0].len = sizeof(enable); - tx[0].delay_usecs = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.value = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[0], &msg); tx[1].tx_buf = &erase; @@ -269,7 +271,8 @@ static int machxo2_write(struct fpga_manager *mgr, const char *buf, spi_message_init(&msg); tx.tx_buf = payload; tx.len = MACHXO2_BUF_SIZE; - tx.delay_usecs = MACHXO2_HIGH_DELAY_USEC; + tx.delay.value = MACHXO2_HIGH_DELAY_USEC; + tx.delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx, &msg); ret = spi_sync(spi, &msg); if (ret) { @@ -317,7 +320,8 @@ static int machxo2_write_complete(struct fpga_manager *mgr, spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 215d33789c74..44b7c569d4dc 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -154,11 +154,11 @@ static void s10_receive_callback(struct stratix10_svc_client *client, * Here we set status bits as we receive them. Elsewhere, we always use * test_and_clear_bit() to check status in priv->status */ - for (i = 0; i <= SVC_STATUS_RECONFIG_ERROR; i++) + for (i = 0; i <= SVC_STATUS_ERROR; i++) if (status & (1 << i)) set_bit(i, &priv->status); - if (status & BIT(SVC_STATUS_RECONFIG_BUFFER_DONE)) { + if (status & BIT(SVC_STATUS_BUFFER_DONE)) { s10_unlock_bufs(priv, data->kaddr1); s10_unlock_bufs(priv, data->kaddr2); s10_unlock_bufs(priv, data->kaddr3); @@ -209,8 +209,7 @@ static int s10_ops_write_init(struct fpga_manager *mgr, } ret = 0; - if (!test_and_clear_bit(SVC_STATUS_RECONFIG_REQUEST_OK, - &priv->status)) { + if (!test_and_clear_bit(SVC_STATUS_OK, &priv->status)) { ret = -ETIMEDOUT; goto init_done; } @@ -323,17 +322,15 @@ static int s10_ops_write(struct fpga_manager *mgr, const char *buf, &priv->status_return_completion, S10_BUFFER_TIMEOUT); - if (test_and_clear_bit(SVC_STATUS_RECONFIG_BUFFER_DONE, - &priv->status) || - test_and_clear_bit(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED, + if (test_and_clear_bit(SVC_STATUS_BUFFER_DONE, &priv->status) || + test_and_clear_bit(SVC_STATUS_BUFFER_SUBMITTED, &priv->status)) { ret = 0; continue; } - if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR, - &priv->status)) { - dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n"); + if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { + dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); ret = -EFAULT; break; } @@ -393,13 +390,11 @@ static int s10_ops_write_complete(struct fpga_manager *mgr, timeout = ret; ret = 0; - if (test_and_clear_bit(SVC_STATUS_RECONFIG_COMPLETED, - &priv->status)) + if (test_and_clear_bit(SVC_STATUS_COMPLETED, &priv->status)) break; - if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR, - &priv->status)) { - dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n"); + if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { + dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); ret = -EFAULT; break; } @@ -482,7 +477,8 @@ static int s10_remove(struct platform_device *pdev) } static const struct of_device_id s10_of_match[] = { - { .compatible = "intel,stratix10-soc-fpga-mgr", }, + {.compatible = "intel,stratix10-soc-fpga-mgr"}, + {.compatible = "intel,agilex-soc-fpga-mgr"}, {}, }; diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index b8a88d21d038..4a1139e05280 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -40,16 +40,12 @@ static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, const char *buf, size_t size) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); struct zynqmp_fpga_priv *priv; dma_addr_t dma_addr; u32 eemi_flags = 0; char *kbuf; int ret; - if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_load) - return -ENXIO; - priv = mgr->priv; kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); @@ -63,7 +59,7 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG) eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL; - ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags); + ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags); dma_free_coherent(priv->dev, size, kbuf, dma_addr); @@ -78,13 +74,9 @@ static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr, static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - u32 status; - - if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_get_status) - return FPGA_MGR_STATE_UNKNOWN; + u32 status = 0; - eemi_ops->fpga_get_status(&status); + zynqmp_pm_fpga_get_status(&status); if (status & IXR_FPGA_DONE_MASK) return FPGA_MGR_STATE_OPERATING; diff --git a/drivers/gnss/serial.h b/drivers/gnss/serial.h index 980ffdc86c2a..621953f7821d 100644 --- a/drivers/gnss/serial.h +++ b/drivers/gnss/serial.h @@ -16,7 +16,7 @@ struct gnss_serial { struct gnss_device *gdev; speed_t speed; const struct gnss_serial_ops *ops; - unsigned long drvdata[0]; + unsigned long drvdata[]; }; enum gnss_serial_pm_state { diff --git a/drivers/gnss/sirf.c b/drivers/gnss/sirf.c index effed3a8d398..2ecb1d3e8eeb 100644 --- a/drivers/gnss/sirf.c +++ b/drivers/gnss/sirf.c @@ -439,14 +439,18 @@ static int sirf_probe(struct serdev_device *serdev) data->on_off = devm_gpiod_get_optional(dev, "sirf,onoff", GPIOD_OUT_LOW); - if (IS_ERR(data->on_off)) + if (IS_ERR(data->on_off)) { + ret = PTR_ERR(data->on_off); goto err_put_device; + } if (data->on_off) { data->wakeup = devm_gpiod_get_optional(dev, "sirf,wakeup", GPIOD_IN); - if (IS_ERR(data->wakeup)) + if (IS_ERR(data->wakeup)) { + ret = PTR_ERR(data->wakeup); goto err_put_device; + } ret = regulator_enable(data->vcc); if (ret) diff --git a/drivers/greybus/Kconfig b/drivers/greybus/Kconfig index b84fcaf8b105..aeea082f1418 100644 --- a/drivers/greybus/Kconfig +++ b/drivers/greybus/Kconfig @@ -3,7 +3,7 @@ menuconfig GREYBUS tristate "Greybus support" depends on SYSFS ---help--- - This option enables the Greybus driver core. Greybus is an + This option enables the Greybus driver core. Greybus is a hardware protocol that was designed to provide Unipro with a sane application layer. It was originally designed for the ARA project, a module phone system, but has shown up in other @@ -12,7 +12,7 @@ menuconfig GREYBUS Say Y here to enable support for these types of drivers. - To compile this code as a module, chose M here: the module + To compile this code as a module, choose M here: the module will be called greybus.ko if GREYBUS @@ -25,7 +25,7 @@ config GREYBUS_ES2 acts as a Greybus "host controller". This device is a bridge from a USB device to a Unipro network. - To compile this code as a module, chose M here: the module + To compile this code as a module, choose M here: the module will be called gb-es2.ko endif # GREYBUS diff --git a/drivers/greybus/arpc.h b/drivers/greybus/arpc.h index c8b83c5cfa79..b9ea81b55b29 100644 --- a/drivers/greybus/arpc.h +++ b/drivers/greybus/arpc.h @@ -21,7 +21,7 @@ struct arpc_request_message { __le16 id; /* RPC unique id */ __le16 size; /* Size in bytes of header + payload */ __u8 type; /* RPC type */ - __u8 data[0]; /* ARPC data */ + __u8 data[]; /* ARPC data */ } __packed; struct arpc_response_message { diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 0e3e72f0f510..19497d1d92bf 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -2,7 +2,8 @@ # # Makefile for CoreSight drivers. # -obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o coresight-platform.o +obj-$(CONFIG_CORESIGHT) += coresight.o coresight-etm-perf.o \ + coresight-platform.o coresight-sysfs.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o \ coresight-tmc-etf.o \ coresight-tmc-etr.o diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c index 2fdaeec80ee5..98f830c6ed50 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -2,11 +2,17 @@ /* * Copyright (c) 2019, The Linaro Limited. All rights reserved. */ +#include <linux/coresight.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/property.h> +#include <linux/slab.h> #include <dt-bindings/arm/coresight-cti-dt.h> -#include <linux/of.h> #include "coresight-cti.h" +#include "coresight-priv.h" /* Number of CTI signals in the v8 architecturally defined connection */ #define NR_V8PE_IN_SIGS 2 @@ -429,8 +435,7 @@ static int cti_plat_create_impdef_connections(struct device *dev, } /* get the hardware configuration & connection data. */ -int cti_plat_get_hw_data(struct device *dev, - struct cti_drvdata *drvdata) +static int cti_plat_get_hw_data(struct device *dev, struct cti_drvdata *drvdata) { int rc = 0; struct cti_device *cti_dev = &drvdata->ctidev; diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 1f8fb7c15e80..392757f3a019 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -4,7 +4,13 @@ * Author: Mike Leach <mike.leach@linaro.org> */ +#include <linux/atomic.h> #include <linux/coresight.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/spinlock.h> +#include <linux/sysfs.h> #include "coresight-cti.h" @@ -1036,8 +1042,8 @@ static int cti_create_con_sysfs_attr(struct device *dev, enum cti_conn_attr_type attr_type, int attr_idx) { - struct dev_ext_attribute *eattr = 0; - char *name = 0; + struct dev_ext_attribute *eattr; + char *name; eattr = devm_kzalloc(dev, sizeof(struct dev_ext_attribute), GFP_KERNEL); @@ -1139,7 +1145,7 @@ static int cti_create_con_attr_set(struct device *dev, int con_idx, } /* create the array of group pointers for the CTI sysfs groups */ -int cti_create_cons_groups(struct device *dev, struct cti_device *ctidev) +static int cti_create_cons_groups(struct device *dev, struct cti_device *ctidev) { int nr_groups; @@ -1156,8 +1162,8 @@ int cti_create_cons_groups(struct device *dev, struct cti_device *ctidev) int cti_create_cons_sysfs(struct device *dev, struct cti_drvdata *drvdata) { struct cti_device *ctidev = &drvdata->ctidev; - int err = 0, con_idx = 0, i; - struct cti_trig_con *tc = NULL; + int err, con_idx = 0, i; + struct cti_trig_con *tc; err = cti_create_cons_groups(dev, ctidev); if (err) diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c index aa6e0249bd70..40387d58c8e7 100644 --- a/drivers/hwtracing/coresight/coresight-cti.c +++ b/drivers/hwtracing/coresight/coresight-cti.c @@ -4,7 +4,22 @@ * Author: Mike Leach <mike.leach@linaro.org> */ +#include <linux/amba/bus.h> +#include <linux/atomic.h> +#include <linux/bits.h> +#include <linux/coresight.h> +#include <linux/cpu_pm.h> +#include <linux/cpuhotplug.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/pm_runtime.h> #include <linux/property.h> +#include <linux/spinlock.h> + +#include "coresight-priv.h" #include "coresight-cti.h" /** @@ -19,7 +34,7 @@ */ /* net of CTI devices connected via CTM */ -LIST_HEAD(ect_net); +static LIST_HEAD(ect_net); /* protect the list */ static DEFINE_MUTEX(ect_mutex); @@ -27,6 +42,12 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) +/* power management handling */ +static int nr_cti_cpu; + +/* quick lookup list for CPU bound CTIs when power handling */ +static struct cti_drvdata *cti_cpu_drvdata[NR_CPUS]; + /* * CTI naming. CTI bound to cores will have the name cti_cpu<N> where * N is the CPU ID. System CTIs will have the name cti_sys<I> where I @@ -116,6 +137,35 @@ cti_err_not_enabled: return rc; } +/* re-enable CTI on CPU when using CPU hotplug */ +static void cti_cpuhp_enable_hw(struct cti_drvdata *drvdata) +{ + struct cti_config *config = &drvdata->config; + struct device *dev = &drvdata->csdev->dev; + + pm_runtime_get_sync(dev->parent); + spin_lock(&drvdata->spinlock); + config->hw_powered = true; + + /* no need to do anything if no enable request */ + if (!atomic_read(&drvdata->config.enable_req_count)) + goto cti_hp_not_enabled; + + /* try to claim the device */ + if (coresight_claim_device(drvdata->base)) + goto cti_hp_not_enabled; + + cti_write_all_hw_regs(drvdata); + config->hw_enabled = true; + spin_unlock(&drvdata->spinlock); + return; + + /* did not re-enable due to no claim / no request */ +cti_hp_not_enabled: + spin_unlock(&drvdata->spinlock); + pm_runtime_put(dev->parent); +} + /* disable hardware */ static int cti_disable_hw(struct cti_drvdata *drvdata) { @@ -442,6 +492,34 @@ int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, return err; } +static bool cti_add_sysfs_link(struct cti_drvdata *drvdata, + struct cti_trig_con *tc) +{ + struct coresight_sysfs_link link_info; + int link_err = 0; + + link_info.orig = drvdata->csdev; + link_info.orig_name = tc->con_dev_name; + link_info.target = tc->con_dev; + link_info.target_name = dev_name(&drvdata->csdev->dev); + + link_err = coresight_add_sysfs_link(&link_info); + if (link_err) + dev_warn(&drvdata->csdev->dev, + "Failed to set CTI sysfs link %s<=>%s\n", + link_info.orig_name, link_info.target_name); + return !link_err; +} + +static void cti_remove_sysfs_link(struct cti_trig_con *tc) +{ + struct coresight_sysfs_link link_info; + + link_info.orig_name = tc->con_dev_name; + link_info.target = tc->con_dev; + coresight_remove_sysfs_link(&link_info); +} + /* * Look for a matching connection device name in the list of connections. * If found then swap in the csdev name, set trig con association pointer @@ -452,6 +530,8 @@ cti_match_fixup_csdev(struct cti_device *ctidev, const char *node_name, struct coresight_device *csdev) { struct cti_trig_con *tc; + struct cti_drvdata *drvdata = container_of(ctidev, struct cti_drvdata, + ctidev); list_for_each_entry(tc, &ctidev->trig_cons, node) { if (tc->con_dev_name) { @@ -459,7 +539,12 @@ cti_match_fixup_csdev(struct cti_device *ctidev, const char *node_name, /* match: so swap in csdev name & dev */ tc->con_dev_name = dev_name(&csdev->dev); tc->con_dev = csdev; - return true; + /* try to set sysfs link */ + if (cti_add_sysfs_link(drvdata, tc)) + return true; + /* link failed - remove CTI reference */ + tc->con_dev = NULL; + break; } } } @@ -522,6 +607,7 @@ void cti_remove_assoc_from_csdev(struct coresight_device *csdev) ctidev = &ctidrv->ctidev; list_for_each_entry(tc, &ctidev->trig_cons, node) { if (tc->con_dev == csdev->ect_dev) { + cti_remove_sysfs_link(tc); tc->con_dev = NULL; break; } @@ -543,10 +629,16 @@ static void cti_update_conn_xrefs(struct cti_drvdata *drvdata) struct cti_device *ctidev = &drvdata->ctidev; list_for_each_entry(tc, &ctidev->trig_cons, node) { - if (tc->con_dev) - /* set tc->con_dev->ect_dev */ - coresight_set_assoc_ectdev_mutex(tc->con_dev, + if (tc->con_dev) { + /* if we can set the sysfs link */ + if (cti_add_sysfs_link(drvdata, tc)) + /* set the CTI/csdev association */ + coresight_set_assoc_ectdev_mutex(tc->con_dev, drvdata->csdev); + else + /* otherwise remove reference from CTI */ + tc->con_dev = NULL; + } } } @@ -559,7 +651,113 @@ static void cti_remove_conn_xrefs(struct cti_drvdata *drvdata) if (tc->con_dev) { coresight_set_assoc_ectdev_mutex(tc->con_dev, NULL); + cti_remove_sysfs_link(tc); + tc->con_dev = NULL; + } + } +} + +/** cti PM callbacks **/ +static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, + void *v) +{ + struct cti_drvdata *drvdata; + unsigned int cpu = smp_processor_id(); + int notify_res = NOTIFY_OK; + + if (!cti_cpu_drvdata[cpu]) + return NOTIFY_OK; + + drvdata = cti_cpu_drvdata[cpu]; + + if (WARN_ON_ONCE(drvdata->ctidev.cpu != cpu)) + return NOTIFY_BAD; + + spin_lock(&drvdata->spinlock); + + switch (cmd) { + case CPU_PM_ENTER: + /* CTI regs all static - we have a copy & nothing to save */ + drvdata->config.hw_powered = false; + if (drvdata->config.hw_enabled) + coresight_disclaim_device(drvdata->base); + break; + + case CPU_PM_ENTER_FAILED: + drvdata->config.hw_powered = true; + if (drvdata->config.hw_enabled) { + if (coresight_claim_device(drvdata->base)) + drvdata->config.hw_enabled = false; + } + break; + + case CPU_PM_EXIT: + /* write hardware registers to re-enable. */ + drvdata->config.hw_powered = true; + drvdata->config.hw_enabled = false; + + /* check enable reference count to enable HW */ + if (atomic_read(&drvdata->config.enable_req_count)) { + /* check we can claim the device as we re-power */ + if (coresight_claim_device(drvdata->base)) + goto cti_notify_exit; + + drvdata->config.hw_enabled = true; + cti_write_all_hw_regs(drvdata); + } + break; + + default: + notify_res = NOTIFY_DONE; + break; + } + +cti_notify_exit: + spin_unlock(&drvdata->spinlock); + return notify_res; +} + +static struct notifier_block cti_cpu_pm_nb = { + .notifier_call = cti_cpu_pm_notify, +}; + +/* CPU HP handlers */ +static int cti_starting_cpu(unsigned int cpu) +{ + struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu]; + + if (!drvdata) + return 0; + + cti_cpuhp_enable_hw(drvdata); + return 0; +} + +static int cti_dying_cpu(unsigned int cpu) +{ + struct cti_drvdata *drvdata = cti_cpu_drvdata[cpu]; + + if (!drvdata) + return 0; + + spin_lock(&drvdata->spinlock); + drvdata->config.hw_powered = false; + coresight_disclaim_device(drvdata->base); + spin_unlock(&drvdata->spinlock); + return 0; +} + +/* release PM registrations */ +static void cti_pm_release(struct cti_drvdata *drvdata) +{ + if (drvdata->ctidev.cpu >= 0) { + if (--nr_cti_cpu == 0) { + cpu_pm_unregister_notifier(&cti_cpu_pm_nb); + + cpuhp_remove_state_nocalls( + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING); } + cti_cpu_drvdata[drvdata->ctidev.cpu] = NULL; } } @@ -578,12 +776,12 @@ int cti_disable(struct coresight_device *csdev) return cti_disable_hw(drvdata); } -const struct coresight_ops_ect cti_ops_ect = { +static const struct coresight_ops_ect cti_ops_ect = { .enable = cti_enable, .disable = cti_disable, }; -const struct coresight_ops cti_ops = { +static const struct coresight_ops cti_ops = { .ect_ops = &cti_ops_ect, }; @@ -598,6 +796,7 @@ static void cti_device_release(struct device *dev) mutex_lock(&ect_mutex); cti_remove_conn_xrefs(drvdata); + cti_pm_release(drvdata); /* remove from the list */ list_for_each_entry_safe(ect_item, ect_tmp, &ect_net, node) { @@ -673,6 +872,24 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) goto err_out; } + /* setup CPU power management handling for CPU bound CTI devices. */ + if (drvdata->ctidev.cpu >= 0) { + cti_cpu_drvdata[drvdata->ctidev.cpu] = drvdata; + if (!nr_cti_cpu++) { + cpus_read_lock(); + ret = cpuhp_setup_state_nocalls_cpuslocked( + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, + "arm/coresight_cti:starting", + cti_starting_cpu, cti_dying_cpu); + + if (!ret) + ret = cpu_pm_register_notifier(&cti_cpu_pm_nb); + cpus_read_unlock(); + if (ret) + goto err_out; + } + } + /* create dynamic attributes for connections */ ret = cti_create_cons_sysfs(dev, drvdata); if (ret) { @@ -711,6 +928,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_out: + cti_pm_release(drvdata); return ret; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index 004df3ab9dd0..acf7b545e6b9 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -7,8 +7,14 @@ #ifndef _CORESIGHT_CORESIGHT_CTI_H #define _CORESIGHT_CORESIGHT_CTI_H -#include <asm/local.h> +#include <linux/coresight.h> +#include <linux/device.h> +#include <linux/fwnode.h> +#include <linux/list.h> #include <linux/spinlock.h> +#include <linux/sysfs.h> +#include <linux/types.h> + #include "coresight-priv.h" /* diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 3810290e6d07..03e3f2590191 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -717,7 +717,7 @@ static const struct attribute_group coresight_etb_mgmt_group = { .name = "mgmt", }; -const struct attribute_group *coresight_etb_groups[] = { +static const struct attribute_group *coresight_etb_groups[] = { &coresight_etb_group, &coresight_etb_mgmt_group, NULL, diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index e2cb6873c3f2..bf22dcfd3327 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -504,7 +504,7 @@ static int etm_enable_perf(struct coresight_device *csdev, static int etm_enable_sysfs(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct etm_enable_arg arg = { 0 }; + struct etm_enable_arg arg = { }; int ret; spin_lock(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index ce41482431f9..b673e738bc9a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -205,7 +205,7 @@ static ssize_t reset_store(struct device *dev, * started state. ARM recommends start-stop logic is set before * each trace run. */ - config->vinst_ctrl |= BIT(0); + config->vinst_ctrl = BIT(0); if (drvdata->nr_addr_cmp == true) { config->mode |= ETM_MODE_VIEWINST_STARTSTOP; /* SSSTATUS, bit[9] */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index a90d757f7043..747afc875f91 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -412,7 +412,7 @@ out: static int etm4_enable_sysfs(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - struct etm4_enable_arg arg = { 0 }; + struct etm4_enable_arg arg = { }; int ret; spin_lock(&drvdata->spinlock); @@ -791,7 +791,7 @@ static void etm4_set_default_config(struct etmv4_config *config) config->ts_ctrl = 0x0; /* TRCVICTLR::EVENT = 0x01, select the always on logic */ - config->vinst_ctrl |= BIT(0); + config->vinst_ctrl = BIT(0); } static u64 etm4_get_ns_access_type(struct etmv4_config *config) @@ -894,17 +894,8 @@ static void etm4_set_start_stop_filter(struct etmv4_config *config, static void etm4_set_default_filter(struct etmv4_config *config) { - u64 start, stop; - - /* - * Configure address range comparator '0' to encompass all - * possible addresses. - */ - start = 0x0; - stop = ~0x0; - - etm4_set_comparator_filter(config, start, stop, - ETM_DEFAULT_ADDR_COMP); + /* Trace everything 'default' filter achieved by no filtering */ + config->viiectlr = 0x0; /* * TRCVICTLR::SSSTATUS == 1, the start-stop logic is @@ -925,11 +916,9 @@ static void etm4_set_default(struct etmv4_config *config) /* * Make default initialisation trace everything * - * Select the "always true" resource selector on the - * "Enablign Event" line and configure address range comparator - * '0' to trace all the possible address range. From there - * configure the "include/exclude" engine to include address - * range comparator '0'. + * This is done by a minimum default config sufficient to enable + * full instruction trace - with a default filter for trace all + * achieved by having no filtering. */ etm4_set_default_config(config); etm4_set_default_filter(config); @@ -1527,6 +1516,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return 0; err_arch_supported: + etmdrvdata[drvdata->cpu] = NULL; if (--etm4_count == 0) { etm4_cpu_pm_unregister(); @@ -1552,10 +1542,13 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ + CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ - CS_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385 Cortex-A55 */ - CS_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385 Cortex-A75 */ + CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */ + CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ + CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ + CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ {}, }; diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 43418a2126ff..e4912abda3aa 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -87,6 +87,7 @@ static void of_coresight_get_ports_legacy(const struct device_node *node, int *nr_inport, int *nr_outport) { struct device_node *ep = NULL; + struct of_endpoint endpoint; int in = 0, out = 0; do { @@ -94,10 +95,16 @@ static void of_coresight_get_ports_legacy(const struct device_node *node, if (!ep) break; - if (of_coresight_legacy_ep_is_input(ep)) - in++; - else - out++; + if (of_graph_parse_endpoint(ep, &endpoint)) + continue; + + if (of_coresight_legacy_ep_is_input(ep)) { + in = (endpoint.port + 1 > in) ? + endpoint.port + 1 : in; + } else { + out = (endpoint.port + 1) > out ? + endpoint.port + 1 : out; + } } while (ep); @@ -137,9 +144,16 @@ of_coresight_count_ports(struct device_node *port_parent) { int i = 0; struct device_node *ep = NULL; + struct of_endpoint endpoint; + + while ((ep = of_graph_get_next_endpoint(port_parent, ep))) { + /* Defer error handling to parsing */ + if (of_graph_parse_endpoint(ep, &endpoint)) + continue; + if (endpoint.port + 1 > i) + i = endpoint.port + 1; + } - while ((ep = of_graph_get_next_endpoint(port_parent, ep))) - i++; return i; } @@ -191,14 +205,12 @@ static int of_coresight_get_cpu(struct device *dev) * Parses the local port, remote device name and the remote port. * * Returns : - * 1 - If the parsing is successful and a connection record - * was created for an output connection. * 0 - If the parsing completed without any fatal errors. * -Errno - Fatal error, abort the scanning. */ static int of_coresight_parse_endpoint(struct device *dev, struct device_node *ep, - struct coresight_connection *conn) + struct coresight_platform_data *pdata) { int ret = 0; struct of_endpoint endpoint, rendpoint; @@ -206,6 +218,7 @@ static int of_coresight_parse_endpoint(struct device *dev, struct device_node *rep = NULL; struct device *rdev = NULL; struct fwnode_handle *rdev_fwnode; + struct coresight_connection *conn; do { /* Parse the local port details */ @@ -232,6 +245,13 @@ static int of_coresight_parse_endpoint(struct device *dev, break; } + conn = &pdata->conns[endpoint.port]; + if (conn->child_fwnode) { + dev_warn(dev, "Duplicate output port %d\n", + endpoint.port); + ret = -EINVAL; + break; + } conn->outport = endpoint.port; /* * Hold the refcount to the target device. This could be @@ -244,7 +264,6 @@ static int of_coresight_parse_endpoint(struct device *dev, conn->child_fwnode = fwnode_handle_get(rdev_fwnode); conn->child_port = rendpoint.port; /* Connection record updated */ - ret = 1; } while (0); of_node_put(rparent); @@ -258,7 +277,6 @@ static int of_get_coresight_platform_data(struct device *dev, struct coresight_platform_data *pdata) { int ret = 0; - struct coresight_connection *conn; struct device_node *ep = NULL; const struct device_node *parent = NULL; bool legacy_binding = false; @@ -287,8 +305,6 @@ static int of_get_coresight_platform_data(struct device *dev, dev_warn_once(dev, "Uses obsolete Coresight DT bindings\n"); } - conn = pdata->conns; - /* Iterate through each output port to discover topology */ while ((ep = of_graph_get_next_endpoint(parent, ep))) { /* @@ -300,15 +316,9 @@ static int of_get_coresight_platform_data(struct device *dev, if (legacy_binding && of_coresight_legacy_ep_is_input(ep)) continue; - ret = of_coresight_parse_endpoint(dev, ep, conn); - switch (ret) { - case 1: - conn++; /* Fall through */ - case 0: - break; - default: + ret = of_coresight_parse_endpoint(dev, ep, pdata); + if (ret) return ret; - } } return 0; @@ -501,7 +511,7 @@ static inline bool acpi_validate_dsd_graph(const union acpi_object *graph) } /* acpi_get_dsd_graph - Find the _DSD Graph property for the given device. */ -const union acpi_object * +static const union acpi_object * acpi_get_dsd_graph(struct acpi_device *adev) { int i; @@ -564,7 +574,7 @@ acpi_validate_coresight_graph(const union acpi_object *cs_graph) * Returns the pointer to the CoreSight Graph Package when found. Otherwise * returns NULL. */ -const union acpi_object * +static const union acpi_object * acpi_get_coresight_graph(struct acpi_device *adev) { const union acpi_object *graph_list, *graph; @@ -647,6 +657,16 @@ static int acpi_coresight_parse_link(struct acpi_device *adev, * coresight_remove_match(). */ conn->child_fwnode = fwnode_handle_get(&r_adev->fwnode); + } else if (dir == ACPI_CORESIGHT_LINK_SLAVE) { + /* + * We are only interested in the port number + * for the input ports at this component. + * Store the port number in child_port. + */ + conn->child_port = fields[0].integer.value; + } else { + /* Invalid direction */ + return -EINVAL; } return dir; @@ -692,10 +712,20 @@ static int acpi_coresight_parse_graph(struct acpi_device *adev, return dir; if (dir == ACPI_CORESIGHT_LINK_MASTER) { - pdata->nr_outport++; + if (ptr->outport > pdata->nr_outport) + pdata->nr_outport = ptr->outport; ptr++; } else { - pdata->nr_inport++; + WARN_ON(pdata->nr_inport == ptr->child_port); + /* + * We do not track input port connections for a device. + * However we need the highest port number described, + * which can be recorded now and reuse this connection + * record for an output connection. Hence, do not move + * the ptr for input connections + */ + if (ptr->child_port > pdata->nr_inport) + pdata->nr_inport = ptr->child_port; } } @@ -704,8 +734,13 @@ static int acpi_coresight_parse_graph(struct acpi_device *adev, return rc; /* Copy the connection information to the final location */ - for (i = 0; i < pdata->nr_outport; i++) - pdata->conns[i] = conns[i]; + for (i = 0; conns + i < ptr; i++) { + int port = conns[i].outport; + + /* Duplicate output port */ + WARN_ON(pdata->conns[port].child_fwnode); + pdata->conns[port] = conns[i]; + } devm_kfree(&adev->dev, conns); return 0; @@ -822,7 +857,7 @@ coresight_get_platform_data(struct device *dev) error: if (!IS_ERR_OR_NULL(pdata)) /* Cleanup the connection information */ - coresight_release_platform_data(pdata); + coresight_release_platform_data(NULL, pdata); return ERR_PTR(ret); } EXPORT_SYMBOL_GPL(coresight_get_platform_data); diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 890f9a5c97c6..36c943ae94d5 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -153,6 +153,15 @@ struct coresight_device *coresight_get_sink_by_id(u32 id); struct list_head *coresight_build_path(struct coresight_device *csdev, struct coresight_device *sink); void coresight_release_path(struct list_head *path); +int coresight_add_sysfs_link(struct coresight_sysfs_link *info); +void coresight_remove_sysfs_link(struct coresight_sysfs_link *info); +int coresight_create_conns_sysfs_group(struct coresight_device *csdev); +void coresight_remove_conns_sysfs_group(struct coresight_device *csdev); +int coresight_make_links(struct coresight_device *orig, + struct coresight_connection *conn, + struct coresight_device *target); +void coresight_remove_links(struct coresight_device *orig, + struct coresight_connection *conn); #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X extern int etm_readl_cp14(u32 off, unsigned int *val); @@ -206,12 +215,16 @@ cti_remove_assoc_from_csdev(struct coresight_device *csdev) {} /* extract the data value from a UCI structure given amba_id pointer. */ static inline void *coresight_get_uci_data(const struct amba_id *id) { - if (id->data) - return ((struct amba_cs_uci_id *)(id->data))->data; - return 0; + struct amba_cs_uci_id *uci_id = id->data; + + if (!uci_id) + return NULL; + + return uci_id->data; } -void coresight_release_platform_data(struct coresight_platform_data *pdata); +void coresight_release_platform_data(struct coresight_device *csdev, + struct coresight_platform_data *pdata); struct coresight_device * coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode); void coresight_set_assoc_ectdev_mutex(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c new file mode 100644 index 000000000000..82afeaf2ccc4 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Limited, All rights reserved. + * Author: Mike Leach <mike.leach@linaro.org> + */ + +#include <linux/device.h> +#include <linux/kernel.h> + +#include "coresight-priv.h" + +/* + * Connections group - links attribute. + * Count of created links between coresight components in the group. + */ +static ssize_t nr_links_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct coresight_device *csdev = to_coresight_device(dev); + + return sprintf(buf, "%d\n", csdev->nr_links); +} +static DEVICE_ATTR_RO(nr_links); + +static struct attribute *coresight_conns_attrs[] = { + &dev_attr_nr_links.attr, + NULL, +}; + +static struct attribute_group coresight_conns_group = { + .attrs = coresight_conns_attrs, + .name = "connections", +}; + +/* + * Create connections group for CoreSight devices. + * This group will then be used to collate the sysfs links between + * devices. + */ +int coresight_create_conns_sysfs_group(struct coresight_device *csdev) +{ + int ret = 0; + + if (!csdev) + return -EINVAL; + + ret = sysfs_create_group(&csdev->dev.kobj, &coresight_conns_group); + if (ret) + return ret; + + csdev->has_conns_grp = true; + return ret; +} + +void coresight_remove_conns_sysfs_group(struct coresight_device *csdev) +{ + if (!csdev) + return; + + if (csdev->has_conns_grp) { + sysfs_remove_group(&csdev->dev.kobj, &coresight_conns_group); + csdev->has_conns_grp = false; + } +} + +int coresight_add_sysfs_link(struct coresight_sysfs_link *info) +{ + int ret = 0; + + if (!info) + return -EINVAL; + if (!info->orig || !info->target || + !info->orig_name || !info->target_name) + return -EINVAL; + if (!info->orig->has_conns_grp || !info->target->has_conns_grp) + return -EINVAL; + + /* first link orig->target */ + ret = sysfs_add_link_to_group(&info->orig->dev.kobj, + coresight_conns_group.name, + &info->target->dev.kobj, + info->orig_name); + if (ret) + return ret; + + /* second link target->orig */ + ret = sysfs_add_link_to_group(&info->target->dev.kobj, + coresight_conns_group.name, + &info->orig->dev.kobj, + info->target_name); + + /* error in second link - remove first - otherwise inc counts */ + if (ret) { + sysfs_remove_link_from_group(&info->orig->dev.kobj, + coresight_conns_group.name, + info->orig_name); + } else { + info->orig->nr_links++; + info->target->nr_links++; + } + + return ret; +} + +void coresight_remove_sysfs_link(struct coresight_sysfs_link *info) +{ + if (!info) + return; + if (!info->orig || !info->target || + !info->orig_name || !info->target_name) + return; + + sysfs_remove_link_from_group(&info->orig->dev.kobj, + coresight_conns_group.name, + info->orig_name); + + sysfs_remove_link_from_group(&info->target->dev.kobj, + coresight_conns_group.name, + info->target_name); + + info->orig->nr_links--; + info->target->nr_links--; +} + +/* + * coresight_make_links: Make a link for a connection from a @orig + * device to @target, represented by @conn. + * + * e.g, for devOrig[output_X] -> devTarget[input_Y] is represented + * as two symbolic links : + * + * /sys/.../devOrig/out:X -> /sys/.../devTarget/ + * /sys/.../devTarget/in:Y -> /sys/.../devOrig/ + * + * The link names are allocated for a device where it appears. i.e, the + * "out" link on the master and "in" link on the slave device. + * The link info is stored in the connection record for avoiding + * the reconstruction of names for removal. + */ +int coresight_make_links(struct coresight_device *orig, + struct coresight_connection *conn, + struct coresight_device *target) +{ + int ret = -ENOMEM; + char *outs = NULL, *ins = NULL; + struct coresight_sysfs_link *link = NULL; + + do { + outs = devm_kasprintf(&orig->dev, GFP_KERNEL, + "out:%d", conn->outport); + if (!outs) + break; + ins = devm_kasprintf(&target->dev, GFP_KERNEL, + "in:%d", conn->child_port); + if (!ins) + break; + link = devm_kzalloc(&orig->dev, + sizeof(struct coresight_sysfs_link), + GFP_KERNEL); + if (!link) + break; + + link->orig = orig; + link->target = target; + link->orig_name = outs; + link->target_name = ins; + + ret = coresight_add_sysfs_link(link); + if (ret) + break; + + conn->link = link; + + /* + * Install the device connection. This also indicates that + * the links are operational on both ends. + */ + conn->child_dev = target; + return 0; + } while (0); + + return ret; +} + +/* + * coresight_remove_links: Remove the sysfs links for a given connection @conn, + * from @orig device to @target device. See coresight_make_links() for more + * details. + */ +void coresight_remove_links(struct coresight_device *orig, + struct coresight_connection *conn) +{ + if (!orig || !conn->link) + return; + + coresight_remove_sysfs_link(conn->link); + + devm_kfree(&conn->child_dev->dev, conn->link->target_name); + devm_kfree(&orig->dev, conn->link->orig_name); + devm_kfree(&orig->dev, conn->link); + conn->link = NULL; + conn->child_dev = NULL; +} diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d0cc3985b72a..36cce2bfb744 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -596,13 +596,6 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) goto out; } - /* There is no point in reading a TMC in HW FIFO mode */ - mode = readl_relaxed(drvdata->base + TMC_MODE); - if (mode != TMC_MODE_CIRCULAR_BUFFER) { - ret = -EINVAL; - goto out; - } - /* Don't interfere if operated from Perf */ if (drvdata->mode == CS_MODE_PERF) { ret = -EINVAL; @@ -616,8 +609,15 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) } /* Disable the TMC if need be */ - if (drvdata->mode == CS_MODE_SYSFS) + if (drvdata->mode == CS_MODE_SYSFS) { + /* There is no point in reading a TMC in HW FIFO mode */ + mode = readl_relaxed(drvdata->base + TMC_MODE); + if (mode != TMC_MODE_CIRCULAR_BUFFER) { + ret = -EINVAL; + goto out; + } __tmc_etb_disable_hw(drvdata); + } drvdata->reading = true; out: diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c index 1cf82fa58289..39fba1d16e6e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.c +++ b/drivers/hwtracing/coresight/coresight-tmc.c @@ -361,7 +361,7 @@ static const struct attribute_group coresight_tmc_mgmt_group = { .name = "mgmt", }; -const struct attribute_group *coresight_tmc_groups[] = { +static const struct attribute_group *coresight_tmc_groups[] = { &coresight_tmc_group, &coresight_tmc_mgmt_group, NULL, diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c index c71553c09f8e..f3efbb3b2b4d 100644 --- a/drivers/hwtracing/coresight/coresight.c +++ b/drivers/hwtracing/coresight/coresight.c @@ -1031,7 +1031,7 @@ static void coresight_device_release(struct device *dev) static int coresight_orphan_match(struct device *dev, void *data) { - int i; + int i, ret = 0; bool still_orphan = false; struct coresight_device *csdev, *i_csdev; struct coresight_connection *conn; @@ -1053,49 +1053,62 @@ static int coresight_orphan_match(struct device *dev, void *data) for (i = 0; i < i_csdev->pdata->nr_outport; i++) { conn = &i_csdev->pdata->conns[i]; + /* Skip the port if FW doesn't describe it */ + if (!conn->child_fwnode) + continue; /* We have found at least one orphan connection */ if (conn->child_dev == NULL) { /* Does it match this newly added device? */ - if (conn->child_fwnode == csdev->dev.fwnode) - conn->child_dev = csdev; - else + if (conn->child_fwnode == csdev->dev.fwnode) { + ret = coresight_make_links(i_csdev, + conn, csdev); + if (ret) + return ret; + } else { /* This component still has an orphan */ still_orphan = true; + } } } i_csdev->orphan = still_orphan; /* - * Returning '0' ensures that all known component on the - * bus will be checked. + * Returning '0' in case we didn't encounter any error, + * ensures that all known component on the bus will be checked. */ return 0; } -static void coresight_fixup_orphan_conns(struct coresight_device *csdev) +static int coresight_fixup_orphan_conns(struct coresight_device *csdev) { - /* - * No need to check for a return value as orphan connection(s) - * are hooked-up with each newly added component. - */ - bus_for_each_dev(&coresight_bustype, NULL, + return bus_for_each_dev(&coresight_bustype, NULL, csdev, coresight_orphan_match); } -static void coresight_fixup_device_conns(struct coresight_device *csdev) +static int coresight_fixup_device_conns(struct coresight_device *csdev) { - int i; + int i, ret = 0; for (i = 0; i < csdev->pdata->nr_outport; i++) { struct coresight_connection *conn = &csdev->pdata->conns[i]; + if (!conn->child_fwnode) + continue; conn->child_dev = coresight_find_csdev_by_fwnode(conn->child_fwnode); - if (!conn->child_dev) + if (conn->child_dev) { + ret = coresight_make_links(csdev, conn, + conn->child_dev); + if (ret) + break; + } else { csdev->orphan = true; + } } + + return 0; } static int coresight_remove_match(struct device *dev, void *data) @@ -1118,12 +1131,12 @@ static int coresight_remove_match(struct device *dev, void *data) for (i = 0; i < iterator->pdata->nr_outport; i++) { conn = &iterator->pdata->conns[i]; - if (conn->child_dev == NULL) + if (conn->child_dev == NULL || conn->child_fwnode == NULL) continue; if (csdev->dev.fwnode == conn->child_fwnode) { iterator->orphan = true; - conn->child_dev = NULL; + coresight_remove_links(iterator, conn); /* * Drop the reference to the handle for the remote * device acquired in parsing the connections from @@ -1213,16 +1226,27 @@ postcore_initcall(coresight_init); * coresight_release_platform_data: Release references to the devices connected * to the output port of this device. */ -void coresight_release_platform_data(struct coresight_platform_data *pdata) +void coresight_release_platform_data(struct coresight_device *csdev, + struct coresight_platform_data *pdata) { int i; + struct coresight_connection *conns = pdata->conns; for (i = 0; i < pdata->nr_outport; i++) { - if (pdata->conns[i].child_fwnode) { - fwnode_handle_put(pdata->conns[i].child_fwnode); + /* If we have made the links, remove them now */ + if (csdev && conns[i].child_dev) + coresight_remove_links(csdev, &conns[i]); + /* + * Drop the refcount and clear the handle as this device + * is going away + */ + if (conns[i].child_fwnode) { + fwnode_handle_put(conns[i].child_fwnode); pdata->conns[i].child_fwnode = NULL; } } + if (csdev) + coresight_remove_conns_sysfs_group(csdev); } struct coresight_device *coresight_register(struct coresight_desc *desc) @@ -1304,11 +1328,19 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) mutex_lock(&coresight_mutex); - coresight_fixup_device_conns(csdev); - coresight_fixup_orphan_conns(csdev); - cti_add_assoc_to_csdev(csdev); + ret = coresight_create_conns_sysfs_group(csdev); + if (!ret) + ret = coresight_fixup_device_conns(csdev); + if (!ret) + ret = coresight_fixup_orphan_conns(csdev); + if (!ret) + cti_add_assoc_to_csdev(csdev); mutex_unlock(&coresight_mutex); + if (ret) { + coresight_unregister(csdev); + return ERR_PTR(ret); + } return csdev; @@ -1316,7 +1348,7 @@ err_free_csdev: kfree(csdev); err_out: /* Cleanup the connection information */ - coresight_release_platform_data(desc->pdata); + coresight_release_platform_data(NULL, desc->pdata); return ERR_PTR(ret); } EXPORT_SYMBOL_GPL(coresight_register); @@ -1326,7 +1358,7 @@ void coresight_unregister(struct coresight_device *csdev) etm_perf_del_symlink_sink(csdev); /* Remove references of that device in the topology */ coresight_remove_conns(csdev); - coresight_release_platform_data(csdev->pdata); + coresight_release_platform_data(csdev, csdev->pdata); device_unregister(&csdev->dev); } EXPORT_SYMBOL_GPL(coresight_unregister); diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index bfa4ca3ab7a9..5b7204ee2eb2 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig INTERCONNECT - tristate "On-Chip Interconnect management support" + bool "On-Chip Interconnect management support" help Support for management of the on-chip interconnects. @@ -11,6 +11,7 @@ menuconfig INTERCONNECT if INTERCONNECT +source "drivers/interconnect/imx/Kconfig" source "drivers/interconnect/qcom/Kconfig" endif diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index 725029ae7a2c..4825c287ca13 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -4,4 +4,5 @@ CFLAGS_core.o := -I$(src) icc-core-objs := core.o obj-$(CONFIG_INTERCONNECT) += icc-core.o +obj-$(CONFIG_INTERCONNECT_IMX) += imx/ obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 2c6515e3ecf1..ece2a579a9b0 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -158,6 +158,7 @@ static struct icc_path *path_init(struct device *dev, struct icc_node *dst, hlist_add_head(&path->reqs[i].req_node, &node->req_list); path->reqs[i].node = node; path->reqs[i].dev = dev; + path->reqs[i].enabled = true; /* reference to previous node was saved during path traversal */ node = node->reverse; } @@ -249,9 +250,12 @@ static int aggregate_requests(struct icc_node *node) if (p->pre_aggregate) p->pre_aggregate(node); - hlist_for_each_entry(r, &node->req_list, req_node) + hlist_for_each_entry(r, &node->req_list, req_node) { + if (!r->enabled) + continue; p->aggregate(node, r->tag, r->avg_bw, r->peak_bw, &node->avg_bw, &node->peak_bw); + } return 0; } @@ -350,10 +354,35 @@ static struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec) return node; } +static void devm_icc_release(struct device *dev, void *res) +{ + icc_put(*(struct icc_path **)res); +} + +struct icc_path *devm_of_icc_get(struct device *dev, const char *name) +{ + struct icc_path **ptr, *path; + + ptr = devres_alloc(devm_icc_release, sizeof(**ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + + path = of_icc_get(dev, name); + if (!IS_ERR(path)) { + *ptr = path; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return path; +} +EXPORT_SYMBOL_GPL(devm_of_icc_get); + /** - * of_icc_get() - get a path handle from a DT node based on name + * of_icc_get_by_index() - get a path handle from a DT node based on index * @dev: device pointer for the consumer device - * @name: interconnect path name + * @idx: interconnect path index * * This function will search for a path between two endpoints and return an * icc_path handle on success. Use icc_put() to release constraints when they @@ -365,13 +394,12 @@ static struct icc_node *of_icc_get_from_provider(struct of_phandle_args *spec) * Return: icc_path pointer on success or ERR_PTR() on error. NULL is returned * when the API is disabled or the "interconnects" DT property is missing. */ -struct icc_path *of_icc_get(struct device *dev, const char *name) +struct icc_path *of_icc_get_by_index(struct device *dev, int idx) { - struct icc_path *path = ERR_PTR(-EPROBE_DEFER); + struct icc_path *path; struct icc_node *src_node, *dst_node; - struct device_node *np = NULL; + struct device_node *np; struct of_phandle_args src_args, dst_args; - int idx = 0; int ret; if (!dev || !dev->of_node) @@ -391,12 +419,6 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) * lets support only global ids and extend this in the future if needed * without breaking DT compatibility. */ - if (name) { - idx = of_property_match_string(np, "interconnect-names", name); - if (idx < 0) - return ERR_PTR(idx); - } - ret = of_parse_phandle_with_args(np, "interconnects", "#interconnect-cells", idx * 2, &src_args); @@ -439,12 +461,8 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) return path; } - if (name) - path->name = kstrdup_const(name, GFP_KERNEL); - else - path->name = kasprintf(GFP_KERNEL, "%s-%s", - src_node->name, dst_node->name); - + path->name = kasprintf(GFP_KERNEL, "%s-%s", + src_node->name, dst_node->name); if (!path->name) { kfree(path); return ERR_PTR(-ENOMEM); @@ -452,6 +470,53 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) return path; } +EXPORT_SYMBOL_GPL(of_icc_get_by_index); + +/** + * of_icc_get() - get a path handle from a DT node based on name + * @dev: device pointer for the consumer device + * @name: interconnect path name + * + * This function will search for a path between two endpoints and return an + * icc_path handle on success. Use icc_put() to release constraints when they + * are not needed anymore. + * If the interconnect API is disabled, NULL is returned and the consumer + * drivers will still build. Drivers are free to handle this specifically, + * but they don't have to. + * + * Return: icc_path pointer on success or ERR_PTR() on error. NULL is returned + * when the API is disabled or the "interconnects" DT property is missing. + */ +struct icc_path *of_icc_get(struct device *dev, const char *name) +{ + struct device_node *np; + int idx = 0; + + if (!dev || !dev->of_node) + return ERR_PTR(-ENODEV); + + np = dev->of_node; + + /* + * When the consumer DT node do not have "interconnects" property + * return a NULL path to skip setting constraints. + */ + if (!of_find_property(np, "interconnects", NULL)) + return NULL; + + /* + * We use a combination of phandle and specifier for endpoint. For now + * lets support only global ids and extend this in the future if needed + * without breaking DT compatibility. + */ + if (name) { + idx = of_property_match_string(np, "interconnect-names", name); + if (idx < 0) + return ERR_PTR(idx); + } + + return of_icc_get_by_index(dev, idx); +} EXPORT_SYMBOL_GPL(of_icc_get); /** @@ -546,6 +611,39 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) } EXPORT_SYMBOL_GPL(icc_set_bw); +static int __icc_enable(struct icc_path *path, bool enable) +{ + int i; + + if (!path) + return 0; + + if (WARN_ON(IS_ERR(path) || !path->num_nodes)) + return -EINVAL; + + mutex_lock(&icc_lock); + + for (i = 0; i < path->num_nodes; i++) + path->reqs[i].enabled = enable; + + mutex_unlock(&icc_lock); + + return icc_set_bw(path, path->reqs[0].avg_bw, + path->reqs[0].peak_bw); +} + +int icc_enable(struct icc_path *path) +{ + return __icc_enable(path, true); +} +EXPORT_SYMBOL_GPL(icc_enable); + +int icc_disable(struct icc_path *path) +{ + return __icc_enable(path, false); +} +EXPORT_SYMBOL_GPL(icc_disable); + /** * icc_get() - return a handle for path between two endpoints * @dev: the device requesting the path @@ -908,12 +1006,7 @@ static int __init icc_init(void) return 0; } -static void __exit icc_exit(void) -{ - debugfs_remove_recursive(icc_debugfs_dir); -} -module_init(icc_init); -module_exit(icc_exit); +device_initcall(icc_init); MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>"); MODULE_DESCRIPTION("Interconnect Driver Core"); diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig new file mode 100644 index 000000000000..be2928362bb7 --- /dev/null +++ b/drivers/interconnect/imx/Kconfig @@ -0,0 +1,17 @@ +config INTERCONNECT_IMX + tristate "i.MX interconnect drivers" + depends on ARCH_MXC || COMPILE_TEST + help + Generic interconnect drivers for i.MX SOCs + +config INTERCONNECT_IMX8MM + tristate "i.MX8MM interconnect driver" + depends on INTERCONNECT_IMX + +config INTERCONNECT_IMX8MN + tristate "i.MX8MN interconnect driver" + depends on INTERCONNECT_IMX + +config INTERCONNECT_IMX8MQ + tristate "i.MX8MQ interconnect driver" + depends on INTERCONNECT_IMX diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile new file mode 100644 index 000000000000..21fd5233754f --- /dev/null +++ b/drivers/interconnect/imx/Makefile @@ -0,0 +1,9 @@ +imx-interconnect-objs := imx.o +imx8mm-interconnect-objs := imx8mm.o +imx8mq-interconnect-objs := imx8mq.o +imx8mn-interconnect-objs := imx8mn.o + +obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MQ) += imx8mq-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MN) += imx8mn-interconnect.o diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c new file mode 100644 index 000000000000..ac420f86008e --- /dev/null +++ b/drivers/interconnect/imx/imx.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon <abailon@baylibre.com> + * Author: Leonard Crestez <leonard.crestez@nxp.com> + */ + +#include <linux/device.h> +#include <linux/interconnect-provider.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/pm_qos.h> + +#include "imx.h" + +/* private icc_node data */ +struct imx_icc_node { + const struct imx_icc_node_desc *desc; + struct device *qos_dev; + struct dev_pm_qos_request qos_req; +}; + +static int imx_icc_node_set(struct icc_node *node) +{ + struct device *dev = node->provider->dev; + struct imx_icc_node *node_data = node->data; + u64 freq; + + if (!node_data->qos_dev) + return 0; + + freq = (node->avg_bw + node->peak_bw) * node_data->desc->adj->bw_mul; + do_div(freq, node_data->desc->adj->bw_div); + dev_dbg(dev, "node %s device %s avg_bw %ukBps peak_bw %ukBps min_freq %llukHz\n", + node->name, dev_name(node_data->qos_dev), + node->avg_bw, node->peak_bw, freq); + + if (freq > S32_MAX) { + dev_err(dev, "%s can't request more than S32_MAX freq\n", + node->name); + return -ERANGE; + } + + dev_pm_qos_update_request(&node_data->qos_req, freq); + + return 0; +} + +static int imx_icc_set(struct icc_node *src, struct icc_node *dst) +{ + return imx_icc_node_set(dst); +} + +/* imx_icc_node_destroy() - Destroy an imx icc_node, including private data */ +static void imx_icc_node_destroy(struct icc_node *node) +{ + struct imx_icc_node *node_data = node->data; + int ret; + + if (dev_pm_qos_request_active(&node_data->qos_req)) { + ret = dev_pm_qos_remove_request(&node_data->qos_req); + if (ret) + dev_warn(node->provider->dev, + "failed to remove qos request for %s\n", + dev_name(node_data->qos_dev)); + } + + put_device(node_data->qos_dev); + icc_node_del(node); + icc_node_destroy(node->id); +} + +static int imx_icc_node_init_qos(struct icc_provider *provider, + struct icc_node *node) +{ + struct imx_icc_node *node_data = node->data; + const struct imx_icc_node_adj_desc *adj = node_data->desc->adj; + struct device *dev = provider->dev; + struct device_node *dn = NULL; + struct platform_device *pdev; + + if (adj->main_noc) { + node_data->qos_dev = dev; + dev_dbg(dev, "icc node %s[%d] is main noc itself\n", + node->name, node->id); + } else { + dn = of_parse_phandle(dev->of_node, adj->phandle_name, 0); + if (!dn) { + dev_warn(dev, "Failed to parse %s\n", + adj->phandle_name); + return -ENODEV; + } + /* Allow scaling to be disabled on a per-node basis */ + if (!dn || !of_device_is_available(dn)) { + dev_warn(dev, "Missing property %s, skip scaling %s\n", + adj->phandle_name, node->name); + return 0; + } + + pdev = of_find_device_by_node(dn); + of_node_put(dn); + if (!pdev) { + dev_warn(dev, "node %s[%d] missing device for %pOF\n", + node->name, node->id, dn); + return -EPROBE_DEFER; + } + node_data->qos_dev = &pdev->dev; + dev_dbg(dev, "node %s[%d] has device node %pOF\n", + node->name, node->id, dn); + } + + return dev_pm_qos_add_request(node_data->qos_dev, + &node_data->qos_req, + DEV_PM_QOS_MIN_FREQUENCY, 0); +} + +static struct icc_node *imx_icc_node_add(struct icc_provider *provider, + const struct imx_icc_node_desc *node_desc) +{ + struct device *dev = provider->dev; + struct imx_icc_node *node_data; + struct icc_node *node; + int ret; + + node = icc_node_create(node_desc->id); + if (IS_ERR(node)) { + dev_err(dev, "failed to create node %d\n", node_desc->id); + return node; + } + + if (node->data) { + dev_err(dev, "already created node %s id=%d\n", + node_desc->name, node_desc->id); + return ERR_PTR(-EEXIST); + } + + node_data = devm_kzalloc(dev, sizeof(*node_data), GFP_KERNEL); + if (!node_data) { + icc_node_destroy(node->id); + return ERR_PTR(-ENOMEM); + } + + node->name = node_desc->name; + node->data = node_data; + node_data->desc = node_desc; + icc_node_add(node, provider); + + if (node_desc->adj) { + ret = imx_icc_node_init_qos(provider, node); + if (ret < 0) { + imx_icc_node_destroy(node); + return ERR_PTR(ret); + } + } + + return node; +} + +static void imx_icc_unregister_nodes(struct icc_provider *provider) +{ + struct icc_node *node, *tmp; + + list_for_each_entry_safe(node, tmp, &provider->nodes, node_list) + imx_icc_node_destroy(node); +} + +static int imx_icc_register_nodes(struct icc_provider *provider, + const struct imx_icc_node_desc *descs, + int count) +{ + struct icc_onecell_data *provider_data = provider->data; + int ret; + int i; + + for (i = 0; i < count; i++) { + struct icc_node *node; + const struct imx_icc_node_desc *node_desc = &descs[i]; + size_t j; + + node = imx_icc_node_add(provider, node_desc); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + if (ret != -EPROBE_DEFER) + dev_err(provider->dev, "failed to add %s: %d\n", + node_desc->name, ret); + goto err; + } + provider_data->nodes[node->id] = node; + + for (j = 0; j < node_desc->num_links; j++) { + ret = icc_link_create(node, node_desc->links[j]); + if (ret) { + dev_err(provider->dev, "failed to link node %d to %d: %d\n", + node->id, node_desc->links[j], ret); + goto err; + } + } + } + + return 0; + +err: + imx_icc_unregister_nodes(provider); + + return ret; +} + +static int get_max_node_id(struct imx_icc_node_desc *nodes, int nodes_count) +{ + int i, ret = 0; + + for (i = 0; i < nodes_count; ++i) + if (nodes[i].id > ret) + ret = nodes[i].id; + + return ret; +} + +int imx_icc_register(struct platform_device *pdev, + struct imx_icc_node_desc *nodes, int nodes_count) +{ + struct device *dev = &pdev->dev; + struct icc_onecell_data *data; + struct icc_provider *provider; + int max_node_id; + int ret; + + /* icc_onecell_data is indexed by node_id, unlike nodes param */ + max_node_id = get_max_node_id(nodes, nodes_count); + data = devm_kzalloc(dev, struct_size(data, nodes, max_node_id), + GFP_KERNEL); + if (!data) + return -ENOMEM; + data->num_nodes = max_node_id; + + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + provider->set = imx_icc_set; + provider->aggregate = icc_std_aggregate; + provider->xlate = of_icc_xlate_onecell; + provider->data = data; + provider->dev = dev->parent; + platform_set_drvdata(pdev, provider); + + ret = icc_provider_add(provider); + if (ret) { + dev_err(dev, "error adding interconnect provider: %d\n", ret); + return ret; + } + + ret = imx_icc_register_nodes(provider, nodes, nodes_count); + if (ret) + goto provider_del; + + return 0; + +provider_del: + icc_provider_del(provider); + return ret; +} +EXPORT_SYMBOL_GPL(imx_icc_register); + +int imx_icc_unregister(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + int ret; + + imx_icc_unregister_nodes(provider); + + ret = icc_provider_del(provider); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL_GPL(imx_icc_unregister); + +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h new file mode 100644 index 000000000000..75da51076c68 --- /dev/null +++ b/drivers/interconnect/imx/imx.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon <abailon@baylibre.com> + * Author: Leonard Crestez <leonard.crestez@nxp.com> + */ +#ifndef __DRIVERS_INTERCONNECT_IMX_H +#define __DRIVERS_INTERCONNECT_IMX_H + +#include <linux/kernel.h> + +#define IMX_ICC_MAX_LINKS 4 + +/* + * struct imx_icc_node_adj - Describe a dynamic adjustable node + */ +struct imx_icc_node_adj_desc { + unsigned int bw_mul, bw_div; + const char *phandle_name; + bool main_noc; +}; + +/* + * struct imx_icc_node - Describe an interconnect node + * @name: name of the node + * @id: an unique id to identify the node + * @links: an array of slaves' node id + * @num_links: number of id defined in links + */ +struct imx_icc_node_desc { + const char *name; + u16 id; + u16 links[IMX_ICC_MAX_LINKS]; + u16 num_links; + const struct imx_icc_node_adj_desc *adj; +}; + +#define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \ + { \ + .id = _id, \ + .name = _name, \ + .adj = _adj, \ + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .links = { __VA_ARGS__ }, \ + } + +#define DEFINE_BUS_MASTER(_name, _id, _dest_id) \ + DEFINE_BUS_INTERCONNECT(_name, _id, NULL, _dest_id) + +#define DEFINE_BUS_SLAVE(_name, _id, _adj) \ + DEFINE_BUS_INTERCONNECT(_name, _id, _adj) + +int imx_icc_register(struct platform_device *pdev, + struct imx_icc_node_desc *nodes, + int nodes_count); +int imx_icc_unregister(struct platform_device *pdev); + +#endif /* __DRIVERS_INTERCONNECT_IMX_H */ diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c new file mode 100644 index 000000000000..1083490bb391 --- /dev/null +++ b/drivers/interconnect/imx/imx8mm.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MM SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon <abailon@baylibre.com> + * Author: Leonard Crestez <leonard.crestez@nxp.com> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <dt-bindings/interconnect/imx8mm.h> + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mm_dram_adj = { + .bw_mul = 1, + .bw_div = 16, + .phandle_name = "fsl,ddrc", +}; + +static const struct imx_icc_node_adj_desc imx8mm_noc_adj = { + .bw_mul = 1, + .bw_div = 16, + .main_noc = true, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj, + IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC), + + /* VPUMIX */ + DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU), + DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC), + + /* DISPLAYMIX */ + DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI), + DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI), + DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC), + + /* HSIO */ + DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO), + DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO), + DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC), + + /* Audio */ + DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN), + + /* Ethernet */ + DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN), + + /* Other */ + DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL, + IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM), +}; + +static int imx8mm_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mm_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mm_icc_driver = { + .probe = imx8mm_icc_probe, + .remove = imx8mm_icc_remove, + .driver = { + .name = "imx8mm-interconnect", + }, +}; + +module_platform_driver(imx8mm_icc_driver); +MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:imx8mm-interconnect"); diff --git a/drivers/interconnect/imx/imx8mn.c b/drivers/interconnect/imx/imx8mn.c new file mode 100644 index 000000000000..ad97e55fd4e5 --- /dev/null +++ b/drivers/interconnect/imx/imx8mn.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MN SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <dt-bindings/interconnect/imx8mn.h> + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mn_dram_adj = { + .bw_mul = 1, + .bw_div = 4, + .phandle_name = "fsl,ddrc", +}; + +static const struct imx_icc_node_adj_desc imx8mn_noc_adj = { + .bw_mul = 1, + .bw_div = 4, + .main_noc = true, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MN_ICN_NOC, &imx8mn_noc_adj, + IMX8MN_ICS_DRAM, IMX8MN_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MN_ICS_DRAM, &imx8mn_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MN_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MN_ICM_A53, IMX8MN_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU", IMX8MN_ICM_GPU, IMX8MN_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MN_ICN_GPU, NULL, IMX8MN_ICN_NOC), + + /* DISPLAYMIX */ + DEFINE_BUS_MASTER("CSI1", IMX8MN_ICM_CSI1, IMX8MN_ICN_MIPI), + DEFINE_BUS_MASTER("CSI2", IMX8MN_ICM_CSI2, IMX8MN_ICN_MIPI), + DEFINE_BUS_MASTER("ISI", IMX8MN_ICM_ISI, IMX8MN_ICN_MIPI), + DEFINE_BUS_MASTER("LCDIF", IMX8MN_ICM_LCDIF, IMX8MN_ICN_MIPI), + DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MN_ICN_MIPI, NULL, IMX8MN_ICN_NOC), + + /* USB goes straight to NOC */ + DEFINE_BUS_MASTER("USB", IMX8MN_ICM_USB, IMX8MN_ICN_NOC), + + /* Audio */ + DEFINE_BUS_MASTER("SDMA2", IMX8MN_ICM_SDMA2, IMX8MN_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3", IMX8MN_ICM_SDMA3, IMX8MN_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MN_ICN_AUDIO, NULL, IMX8MN_ICN_MAIN), + + /* Ethernet */ + DEFINE_BUS_MASTER("ENET", IMX8MN_ICM_ENET, IMX8MN_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MN_ICN_ENET, NULL, IMX8MN_ICN_MAIN), + + /* Other */ + DEFINE_BUS_MASTER("SDMA1", IMX8MN_ICM_SDMA1, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MN_ICM_NAND, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MN_ICM_USDHC1, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MN_ICM_USDHC2, IMX8MN_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC3", IMX8MN_ICM_USDHC3, IMX8MN_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MN_ICN_MAIN, NULL, + IMX8MN_ICN_NOC, IMX8MN_ICS_OCRAM), +}; + +static int imx8mn_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mn_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mn_icc_driver = { + .probe = imx8mn_icc_probe, + .remove = imx8mn_icc_remove, + .driver = { + .name = "imx8mn-interconnect", + }, +}; + +module_platform_driver(imx8mn_icc_driver); +MODULE_ALIAS("platform:imx8mn-interconnect"); +MODULE_AUTHOR("Leonard Crestez <leonard.crestez@nxp.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/imx/imx8mq.c b/drivers/interconnect/imx/imx8mq.c new file mode 100644 index 000000000000..ba43a15aefec --- /dev/null +++ b/drivers/interconnect/imx/imx8mq.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MQ SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <dt-bindings/interconnect/imx8mq.h> + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mq_dram_adj = { + .bw_mul = 1, + .bw_div = 4, + .phandle_name = "fsl,ddrc", +}; + +static const struct imx_icc_node_adj_desc imx8mq_noc_adj = { + .bw_mul = 1, + .bw_div = 4, + .main_noc = true, +}; + +/* + * Describe bus masters, slaves and connections between them + * + * This is a simplified subset of the bus diagram, there are several other + * PL301 nics which are skipped/merged into PL301_MAIN + */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MQ_ICN_NOC, &imx8mq_noc_adj, + IMX8MQ_ICS_DRAM, IMX8MQ_ICN_MAIN), + + DEFINE_BUS_SLAVE("DRAM", IMX8MQ_ICS_DRAM, &imx8mq_dram_adj), + DEFINE_BUS_SLAVE("OCRAM", IMX8MQ_ICS_OCRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MQ_ICM_A53, IMX8MQ_ICN_NOC), + + /* VPUMIX */ + DEFINE_BUS_MASTER("VPU", IMX8MQ_ICM_VPU, IMX8MQ_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MQ_ICN_VIDEO, NULL, IMX8MQ_ICN_NOC), + + /* GPUMIX */ + DEFINE_BUS_MASTER("GPU", IMX8MQ_ICM_GPU, IMX8MQ_ICN_GPU), + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MQ_ICN_GPU, NULL, IMX8MQ_ICN_NOC), + + /* DISPMIX (only for DCSS) */ + DEFINE_BUS_MASTER("DC", IMX8MQ_ICM_DCSS, IMX8MQ_ICN_DCSS), + DEFINE_BUS_INTERCONNECT("PL301_DC", IMX8MQ_ICN_DCSS, NULL, IMX8MQ_ICN_NOC), + + /* USBMIX */ + DEFINE_BUS_MASTER("USB1", IMX8MQ_ICM_USB1, IMX8MQ_ICN_USB), + DEFINE_BUS_MASTER("USB2", IMX8MQ_ICM_USB2, IMX8MQ_ICN_USB), + DEFINE_BUS_INTERCONNECT("PL301_USB", IMX8MQ_ICN_USB, NULL, IMX8MQ_ICN_NOC), + + /* PL301_DISPLAY (IPs other than DCSS, inside SUPERMIX) */ + DEFINE_BUS_MASTER("CSI1", IMX8MQ_ICM_CSI1, IMX8MQ_ICN_DISPLAY), + DEFINE_BUS_MASTER("CSI2", IMX8MQ_ICM_CSI2, IMX8MQ_ICN_DISPLAY), + DEFINE_BUS_MASTER("LCDIF", IMX8MQ_ICM_LCDIF, IMX8MQ_ICN_DISPLAY), + DEFINE_BUS_INTERCONNECT("PL301_DISPLAY", IMX8MQ_ICN_DISPLAY, NULL, IMX8MQ_ICN_MAIN), + + /* AUDIO */ + DEFINE_BUS_MASTER("SDMA2", IMX8MQ_ICM_SDMA2, IMX8MQ_ICN_AUDIO), + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MQ_ICN_AUDIO, NULL, IMX8MQ_ICN_DISPLAY), + + /* ENET */ + DEFINE_BUS_MASTER("ENET", IMX8MQ_ICM_ENET, IMX8MQ_ICN_ENET), + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MQ_ICN_ENET, NULL, IMX8MQ_ICN_MAIN), + + /* OTHER */ + DEFINE_BUS_MASTER("SDMA1", IMX8MQ_ICM_SDMA1, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("NAND", IMX8MQ_ICM_NAND, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC1", IMX8MQ_ICM_USDHC1, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("USDHC2", IMX8MQ_ICM_USDHC2, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("PCIE1", IMX8MQ_ICM_PCIE1, IMX8MQ_ICN_MAIN), + DEFINE_BUS_MASTER("PCIE2", IMX8MQ_ICM_PCIE2, IMX8MQ_ICN_MAIN), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MQ_ICN_MAIN, NULL, + IMX8MQ_ICN_NOC, IMX8MQ_ICS_OCRAM), +}; + +static int imx8mq_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); +} + +static int imx8mq_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mq_icc_driver = { + .probe = imx8mq_icc_probe, + .remove = imx8mq_icc_remove, + .driver = { + .name = "imx8mq-interconnect", + }, +}; + +module_platform_driver(imx8mq_icc_driver); +MODULE_ALIAS("platform:imx8mq-interconnect"); +MODULE_AUTHOR("Leonard Crestez <leonard.crestez@nxp.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/internal.h b/drivers/interconnect/internal.h index bf18cb7239df..f5f82a5c939e 100644 --- a/drivers/interconnect/internal.h +++ b/drivers/interconnect/internal.h @@ -14,6 +14,7 @@ * @req_node: entry in list of requests for the particular @node * @node: the interconnect node to which this constraint applies * @dev: reference to the device that sets the constraints + * @enabled: indicates whether the path with this request is enabled * @tag: path tag (optional) * @avg_bw: an integer describing the average bandwidth in kBps * @peak_bw: an integer describing the peak bandwidth in kBps @@ -22,6 +23,7 @@ struct icc_req { struct hlist_node req_node; struct icc_node *node; struct device *dev; + bool enabled; u32 tag; u32 avg_bw; u32 peak_bw; diff --git a/drivers/misc/cardreader/rts5249.c b/drivers/misc/cardreader/rts5249.c index 1a81cda948c1..6c6c9e95a29f 100644 --- a/drivers/misc/cardreader/rts5249.c +++ b/drivers/misc/cardreader/rts5249.c @@ -347,31 +347,6 @@ static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) return rtsx_pci_send_cmd(pcr, 100); } -static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable) -{ - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - - if (pcr->aspm_enabled == enable) - return; - - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - if (enable) - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, - pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - if (!enable) - val = FORCE_ASPM_CTL0; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } - - pcr->aspm_enabled = enable; -} - static const struct pcr_ops rts5249_pcr_ops = { .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, .extra_init_hw = rts5249_extra_init_hw, @@ -384,7 +359,6 @@ static const struct pcr_ops rts5249_pcr_ops = { .card_power_off = rtsx_base_card_power_off, .switch_output_voltage = rtsx_base_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, - .set_aspm = rts5249_set_aspm, }; /* SD Pull Control Enable: @@ -471,7 +445,6 @@ void rts5249_init_params(struct rtsx_pcr *pcr) option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; - option->dev_aspm_mode = DEV_ASPM_DYNAMIC; option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF; option->ltr_l1off_snooze_sspwrgate = @@ -612,7 +585,6 @@ static const struct pcr_ops rts524a_pcr_ops = { .switch_output_voltage = rtsx_base_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, - .set_aspm = rts5249_set_aspm, }; void rts524a_init_params(struct rtsx_pcr *pcr) @@ -728,7 +700,6 @@ static const struct pcr_ops rts525a_pcr_ops = { .switch_output_voltage = rts525a_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, - .set_aspm = rts5249_set_aspm, }; void rts525a_init_params(struct rtsx_pcr *pcr) diff --git a/drivers/misc/cardreader/rts5260.c b/drivers/misc/cardreader/rts5260.c index 711054ebad74..7a9dbb778e84 100644 --- a/drivers/misc/cardreader/rts5260.c +++ b/drivers/misc/cardreader/rts5260.c @@ -570,30 +570,6 @@ static int rts5260_extra_init_hw(struct rtsx_pcr *pcr) return 0; } -static void rts5260_set_aspm(struct rtsx_pcr *pcr, bool enable) -{ - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - - if (pcr->aspm_enabled == enable) - return; - - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - if (enable) - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - if (!enable) - val = FORCE_ASPM_CTL0; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } - - pcr->aspm_enabled = enable; -} - static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) { struct rtsx_cr_option *option = &pcr->option; @@ -639,7 +615,6 @@ static const struct pcr_ops rts5260_pcr_ops = { .switch_output_voltage = rts5260_switch_output_voltage, .force_power_down = rtsx_base_force_power_down, .stop_cmd = rts5260_stop_cmd, - .set_aspm = rts5260_set_aspm, .set_l1off_cfg_sub_d0 = rts5260_set_l1off_cfg_sub_d0, .enable_ocp = rts5260_enable_ocp, .disable_ocp = rts5260_disable_ocp, @@ -683,7 +658,6 @@ void rts5260_init_params(struct rtsx_pcr *pcr) option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; - option->dev_aspm_mode = DEV_ASPM_DYNAMIC; option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; option->ltr_l1off_snooze_sspwrgate = diff --git a/drivers/misc/cardreader/rts5261.c b/drivers/misc/cardreader/rts5261.c index 78c3b1d424c3..195822ec858e 100644 --- a/drivers/misc/cardreader/rts5261.c +++ b/drivers/misc/cardreader/rts5261.c @@ -518,51 +518,22 @@ static int rts5261_extra_init_hw(struct rtsx_pcr *pcr) static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable) { - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - if (pcr->aspm_enabled == enable) return; - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - val = FORCE_ASPM_CTL0; - val |= (pcr->aspm_en & 0x02); - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - val = pcr->aspm_en; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); pcr->aspm_enabled = enable; } static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable) { - struct rtsx_cr_option *option = &pcr->option; - u8 val = 0; - if (pcr->aspm_enabled == enable) return; - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - val = 0; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; - - val = 0; - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - ASPM_MASK_NEG, val); - val = FORCE_ASPM_CTL0; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, 0); rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); udelay(10); pcr->aspm_enabled = enable; @@ -639,8 +610,13 @@ int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, if (initial_mode) { /* We use 250k(around) here, in initial stage */ - clk_divider = SD_CLK_DIVIDE_128; - card_clock = 30000000; + if (is_version(pcr, PID_5261, IC_VER_D)) { + clk_divider = SD_CLK_DIVIDE_256; + card_clock = 60000000; + } else { + clk_divider = SD_CLK_DIVIDE_128; + card_clock = 30000000; + } } else { clk_divider = SD_CLK_DIVIDE_0; } @@ -784,7 +760,6 @@ void rts5261_init_params(struct rtsx_pcr *pcr) option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; option->ltr_l1off_sspwrgate = 0x7F; option->ltr_l1off_snooze_sspwrgate = 0x78; - option->dev_aspm_mode = DEV_ASPM_DYNAMIC; option->ocp_en = 1; hw_param->interrupt_en |= SD_OC_INT_EN; diff --git a/drivers/misc/cardreader/rtsx_pcr.c b/drivers/misc/cardreader/rtsx_pcr.c index 55da6428ceb0..0d5928bc1b6d 100644 --- a/drivers/misc/cardreader/rtsx_pcr.c +++ b/drivers/misc/cardreader/rtsx_pcr.c @@ -55,16 +55,10 @@ static const struct pci_device_id rtsx_pci_ids[] = { MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); -static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr) -{ - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - 0xFC, pcr->aspm_en); -} - static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr) { - rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, - 0xFC, 0); + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, 0); } static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) @@ -85,32 +79,17 @@ static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency) { - if (pcr->ops->set_ltr_latency) - return pcr->ops->set_ltr_latency(pcr, latency); - else - return rtsx_comm_set_ltr_latency(pcr, latency); + return rtsx_comm_set_ltr_latency(pcr, latency); } static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable) { - struct rtsx_cr_option *option = &pcr->option; - if (pcr->aspm_enabled == enable) return; - if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { - if (enable) - rtsx_pci_enable_aspm(pcr); - else - rtsx_pci_disable_aspm(pcr); - } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { - u8 mask = FORCE_ASPM_VAL_MASK; - u8 val = 0; - - if (enable) - val = pcr->aspm_en; - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); - } + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, + enable ? pcr->aspm_en : 0); pcr->aspm_enabled = enable; } @@ -154,10 +133,7 @@ static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr) static void rtsx_pm_full_on(struct rtsx_pcr *pcr) { - if (pcr->ops->full_on) - pcr->ops->full_on(pcr); - else - rtsx_comm_pm_full_on(pcr); + rtsx_comm_pm_full_on(pcr); } void rtsx_pci_start_run(struct rtsx_pcr *pcr) @@ -1111,10 +1087,7 @@ static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr) static void rtsx_pm_power_saving(struct rtsx_pcr *pcr) { - if (pcr->ops->power_saving) - pcr->ops->power_saving(pcr); - else - rtsx_comm_pm_power_saving(pcr); + rtsx_comm_pm_power_saving(pcr); } static void rtsx_pci_idle_work(struct work_struct *work) diff --git a/drivers/misc/cardreader/rtsx_pcr.h b/drivers/misc/cardreader/rtsx_pcr.h index ed391df52f4f..024cbd998b2a 100644 --- a/drivers/misc/cardreader/rtsx_pcr.h +++ b/drivers/misc/cardreader/rtsx_pcr.h @@ -29,7 +29,6 @@ #define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC #define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8 #define CMD_TIMEOUT_DEF 100 -#define ASPM_MASK_NEG 0xFC #define MASK_8_BIT_DEF 0xFF #define SSC_CLOCK_STABLE_WAIT 130 diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index e3e085e33d46..7939c55daceb 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -904,6 +904,7 @@ static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, struct fastrpc_channel_ctx *cctx; struct fastrpc_user *fl = ctx->fl; struct fastrpc_msg *msg = &ctx->msg; + int ret; cctx = fl->cctx; msg->pid = fl->tgid; @@ -919,7 +920,13 @@ static int fastrpc_invoke_send(struct fastrpc_session_ctx *sctx, msg->size = roundup(ctx->msg_sz, PAGE_SIZE); fastrpc_context_get(ctx); - return rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); + ret = rpmsg_send(cctx->rpdev->ept, (void *)msg, sizeof(*msg)); + + if (ret) + fastrpc_context_put(ctx); + + return ret; + } static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel, @@ -1613,8 +1620,10 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) domains[domain_id]); data->miscdev.fops = &fastrpc_fops; err = misc_register(&data->miscdev); - if (err) + if (err) { + kfree(data); return err; + } kref_init(&data->refcount); diff --git a/drivers/misc/genwqe/card_utils.c b/drivers/misc/genwqe/card_utils.c index 2e1c4d2905e8..60460a053b2d 100644 --- a/drivers/misc/genwqe/card_utils.c +++ b/drivers/misc/genwqe/card_utils.c @@ -515,30 +515,6 @@ int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl) } /** - * genwqe_free_user_pages() - Give pinned pages back - * - * Documentation of get_user_pages is in mm/gup.c: - * - * If the page is written to, set_page_dirty (or set_page_dirty_lock, - * as appropriate) must be called after the page is finished with, and - * before put_page is called. - */ -static int genwqe_free_user_pages(struct page **page_list, - unsigned int nr_pages, int dirty) -{ - unsigned int i; - - for (i = 0; i < nr_pages; i++) { - if (page_list[i] != NULL) { - if (dirty) - set_page_dirty_lock(page_list[i]); - put_page(page_list[i]); - } - } - return 0; -} - -/** * genwqe_user_vmap() - Map user-space memory to virtual kernel memory * @cd: pointer to genwqe device * @m: mapping params @@ -597,18 +573,18 @@ int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr, m->dma_list = (dma_addr_t *)(m->page_list + m->nr_pages); /* pin user pages in memory */ - rc = get_user_pages_fast(data & PAGE_MASK, /* page aligned addr */ + rc = pin_user_pages_fast(data & PAGE_MASK, /* page aligned addr */ m->nr_pages, m->write ? FOLL_WRITE : 0, /* readable/writable */ m->page_list); /* ptrs to pages */ if (rc < 0) - goto fail_get_user_pages; + goto fail_pin_user_pages; - /* assumption: get_user_pages can be killed by signals. */ + /* assumption: pin_user_pages can be killed by signals. */ if (rc < m->nr_pages) { - genwqe_free_user_pages(m->page_list, rc, m->write); + unpin_user_pages_dirty_lock(m->page_list, rc, m->write); rc = -EFAULT; - goto fail_get_user_pages; + goto fail_pin_user_pages; } rc = genwqe_map_pages(cd, m->page_list, m->nr_pages, m->dma_list); @@ -618,9 +594,9 @@ int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr, return 0; fail_free_user_pages: - genwqe_free_user_pages(m->page_list, m->nr_pages, m->write); + unpin_user_pages_dirty_lock(m->page_list, m->nr_pages, m->write); - fail_get_user_pages: + fail_pin_user_pages: kfree(m->page_list); m->page_list = NULL; m->dma_list = NULL; @@ -650,8 +626,8 @@ int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m) genwqe_unmap_pages(cd, m->dma_list, m->nr_pages); if (m->page_list) { - genwqe_free_user_pages(m->page_list, m->nr_pages, m->write); - + unpin_user_pages_dirty_lock(m->page_list, m->nr_pages, + m->write); kfree(m->page_list); m->page_list = NULL; m->dma_list = NULL; diff --git a/drivers/misc/habanalabs/Makefile b/drivers/misc/habanalabs/Makefile index 482f6227dbba..421ebd903069 100644 --- a/drivers/misc/habanalabs/Makefile +++ b/drivers/misc/habanalabs/Makefile @@ -13,3 +13,6 @@ habanalabs-$(CONFIG_DEBUG_FS) += debugfs.o include $(src)/goya/Makefile habanalabs-y += $(HL_GOYA_FILES) + +include $(src)/gaudi/Makefile +habanalabs-y += $(HL_GAUDI_FILES) diff --git a/drivers/misc/habanalabs/command_buffer.c b/drivers/misc/habanalabs/command_buffer.c index 53fddbd8e693..02d13f71b1df 100644 --- a/drivers/misc/habanalabs/command_buffer.c +++ b/drivers/misc/habanalabs/command_buffer.c @@ -105,10 +105,9 @@ int hl_cb_create(struct hl_device *hdev, struct hl_cb_mgr *mgr, goto out_err; } - if (cb_size > HL_MAX_CB_SIZE) { - dev_err(hdev->dev, - "CB size %d must be less then %d\n", - cb_size, HL_MAX_CB_SIZE); + if (cb_size > SZ_2M) { + dev_err(hdev->dev, "CB size %d must be less than %d\n", + cb_size, SZ_2M); rc = -EINVAL; goto out_err; } @@ -211,7 +210,7 @@ int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data) { union hl_cb_args *args = data; struct hl_device *hdev = hpriv->hdev; - u64 handle; + u64 handle = 0; int rc; if (hl_device_disabled_or_in_reset(hdev)) { @@ -223,15 +222,26 @@ int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data) switch (args->in.op) { case HL_CB_OP_CREATE: - rc = hl_cb_create(hdev, &hpriv->cb_mgr, args->in.cb_size, - &handle, hpriv->ctx->asid); + if (args->in.cb_size > HL_MAX_CB_SIZE) { + dev_err(hdev->dev, + "User requested CB size %d must be less than %d\n", + args->in.cb_size, HL_MAX_CB_SIZE); + rc = -EINVAL; + } else { + rc = hl_cb_create(hdev, &hpriv->cb_mgr, + args->in.cb_size, &handle, + hpriv->ctx->asid); + } + memset(args, 0, sizeof(*args)); args->out.cb_handle = handle; break; + case HL_CB_OP_DESTROY: rc = hl_cb_destroy(hdev, &hpriv->cb_mgr, args->in.cb_handle); break; + default: rc = -ENOTTY; break; @@ -278,7 +288,7 @@ int hl_cb_mmap(struct hl_fpriv *hpriv, struct vm_area_struct *vma) cb = hl_cb_get(hdev, &hpriv->cb_mgr, handle); if (!cb) { dev_err(hdev->dev, - "CB mmap failed, no match to handle %d\n", handle); + "CB mmap failed, no match to handle 0x%x\n", handle); return -EINVAL; } @@ -347,7 +357,7 @@ struct hl_cb *hl_cb_get(struct hl_device *hdev, struct hl_cb_mgr *mgr, if (!cb) { spin_unlock(&mgr->cb_lock); dev_warn(hdev->dev, - "CB get failed, no match to handle %d\n", handle); + "CB get failed, no match to handle 0x%x\n", handle); return NULL; } diff --git a/drivers/misc/habanalabs/command_submission.c b/drivers/misc/habanalabs/command_submission.c index 409276b6374d..f82974a916c3 100644 --- a/drivers/misc/habanalabs/command_submission.c +++ b/drivers/misc/habanalabs/command_submission.c @@ -11,11 +11,33 @@ #include <linux/uaccess.h> #include <linux/slab.h> +#define HL_CS_FLAGS_SIG_WAIT (HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT) + static void job_wq_completion(struct work_struct *work); static long _hl_cs_wait_ioctl(struct hl_device *hdev, struct hl_ctx *ctx, u64 timeout_us, u64 seq); static void cs_do_release(struct kref *ref); +static void hl_sob_reset(struct kref *ref) +{ + struct hl_hw_sob *hw_sob = container_of(ref, struct hl_hw_sob, + kref); + struct hl_device *hdev = hw_sob->hdev; + + hdev->asic_funcs->reset_sob(hdev, hw_sob); +} + +void hl_sob_reset_error(struct kref *ref) +{ + struct hl_hw_sob *hw_sob = container_of(ref, struct hl_hw_sob, + kref); + struct hl_device *hdev = hw_sob->hdev; + + dev_crit(hdev->dev, + "SOB release shouldn't be called here, q_idx: %d, sob_id: %d\n", + hw_sob->q_idx, hw_sob->sob_id); +} + static const char *hl_fence_get_driver_name(struct dma_fence *fence) { return "HabanaLabs"; @@ -23,10 +45,10 @@ static const char *hl_fence_get_driver_name(struct dma_fence *fence) static const char *hl_fence_get_timeline_name(struct dma_fence *fence) { - struct hl_dma_fence *hl_fence = - container_of(fence, struct hl_dma_fence, base_fence); + struct hl_cs_compl *hl_cs_compl = + container_of(fence, struct hl_cs_compl, base_fence); - return dev_name(hl_fence->hdev->dev); + return dev_name(hl_cs_compl->hdev->dev); } static bool hl_fence_enable_signaling(struct dma_fence *fence) @@ -36,17 +58,47 @@ static bool hl_fence_enable_signaling(struct dma_fence *fence) static void hl_fence_release(struct dma_fence *fence) { - struct hl_dma_fence *hl_fence = - container_of(fence, struct hl_dma_fence, base_fence); + struct hl_cs_compl *hl_cs_cmpl = + container_of(fence, struct hl_cs_compl, base_fence); + struct hl_device *hdev = hl_cs_cmpl->hdev; + + if ((hl_cs_cmpl->type == CS_TYPE_SIGNAL) || + (hl_cs_cmpl->type == CS_TYPE_WAIT)) { - kfree_rcu(hl_fence, base_fence.rcu); + dev_dbg(hdev->dev, + "CS 0x%llx type %d finished, sob_id: %d, sob_val: 0x%x\n", + hl_cs_cmpl->cs_seq, + hl_cs_cmpl->type, + hl_cs_cmpl->hw_sob->sob_id, + hl_cs_cmpl->sob_val); + + /* + * A signal CS can get completion while the corresponding wait + * for signal CS is on its way to the PQ. The wait for signal CS + * will get stuck if the signal CS incremented the SOB to its + * max value and there are no pending (submitted) waits on this + * SOB. + * We do the following to void this situation: + * 1. The wait for signal CS must get a ref for the signal CS as + * soon as possible in cs_ioctl_signal_wait() and put it + * before being submitted to the PQ but after it incremented + * the SOB refcnt in init_signal_wait_cs(). + * 2. Signal/Wait for signal CS will decrement the SOB refcnt + * here. + * These two measures guarantee that the wait for signal CS will + * reset the SOB upon completion rather than the signal CS and + * hence the above scenario is avoided. + */ + kref_put(&hl_cs_cmpl->hw_sob->kref, hl_sob_reset); + } + + kfree_rcu(hl_cs_cmpl, base_fence.rcu); } static const struct dma_fence_ops hl_fence_ops = { .get_driver_name = hl_fence_get_driver_name, .get_timeline_name = hl_fence_get_timeline_name, .enable_signaling = hl_fence_enable_signaling, - .wait = dma_fence_default_wait, .release = hl_fence_release }; @@ -113,6 +165,7 @@ static int cs_parser(struct hl_fpriv *hpriv, struct hl_cs_job *job) if (!rc) { job->patched_cb = parser.patched_cb; job->job_cb_size = parser.patched_cb_size; + job->contains_dma_pkt = parser.contains_dma_pkt; spin_lock(&job->patched_cb->lock); job->patched_cb->cs_cnt++; @@ -259,6 +312,12 @@ static void cs_do_release(struct kref *ref) spin_unlock(&hdev->hw_queues_mirror_lock); } + } else if (cs->type == CS_TYPE_WAIT) { + /* + * In case the wait for signal CS was submitted, the put occurs + * in init_signal_wait_cs() right before hanging on the PQ. + */ + dma_fence_put(cs->signal_fence); } /* @@ -312,9 +371,9 @@ static void cs_timedout(struct work_struct *work) } static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, - struct hl_cs **cs_new) + enum hl_cs_type cs_type, struct hl_cs **cs_new) { - struct hl_dma_fence *fence; + struct hl_cs_compl *cs_cmpl; struct dma_fence *other = NULL; struct hl_cs *cs; int rc; @@ -326,25 +385,27 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, cs->ctx = ctx; cs->submitted = false; cs->completed = false; + cs->type = cs_type; INIT_LIST_HEAD(&cs->job_list); INIT_DELAYED_WORK(&cs->work_tdr, cs_timedout); kref_init(&cs->refcount); spin_lock_init(&cs->job_lock); - fence = kmalloc(sizeof(*fence), GFP_ATOMIC); - if (!fence) { + cs_cmpl = kmalloc(sizeof(*cs_cmpl), GFP_ATOMIC); + if (!cs_cmpl) { rc = -ENOMEM; goto free_cs; } - fence->hdev = hdev; - spin_lock_init(&fence->lock); - cs->fence = &fence->base_fence; + cs_cmpl->hdev = hdev; + cs_cmpl->type = cs->type; + spin_lock_init(&cs_cmpl->lock); + cs->fence = &cs_cmpl->base_fence; spin_lock(&ctx->cs_lock); - fence->cs_seq = ctx->cs_sequence; - other = ctx->cs_pending[fence->cs_seq & (HL_MAX_PENDING_CS - 1)]; + cs_cmpl->cs_seq = ctx->cs_sequence; + other = ctx->cs_pending[cs_cmpl->cs_seq & (HL_MAX_PENDING_CS - 1)]; if ((other) && (!dma_fence_is_signaled(other))) { spin_unlock(&ctx->cs_lock); dev_dbg(hdev->dev, @@ -353,16 +414,16 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, goto free_fence; } - dma_fence_init(&fence->base_fence, &hl_fence_ops, &fence->lock, + dma_fence_init(&cs_cmpl->base_fence, &hl_fence_ops, &cs_cmpl->lock, ctx->asid, ctx->cs_sequence); - cs->sequence = fence->cs_seq; + cs->sequence = cs_cmpl->cs_seq; - ctx->cs_pending[fence->cs_seq & (HL_MAX_PENDING_CS - 1)] = - &fence->base_fence; + ctx->cs_pending[cs_cmpl->cs_seq & (HL_MAX_PENDING_CS - 1)] = + &cs_cmpl->base_fence; ctx->cs_sequence++; - dma_fence_get(&fence->base_fence); + dma_fence_get(&cs_cmpl->base_fence); dma_fence_put(other); @@ -373,7 +434,7 @@ static int allocate_cs(struct hl_device *hdev, struct hl_ctx *ctx, return 0; free_fence: - kfree(fence); + kfree(cs_cmpl); free_cs: kfree(cs); return rc; @@ -499,8 +560,8 @@ struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, return job; } -static int _hl_cs_ioctl(struct hl_fpriv *hpriv, void __user *chunks, - u32 num_chunks, u64 *cs_seq) +static int cs_ioctl_default(struct hl_fpriv *hpriv, void __user *chunks, + u32 num_chunks, u64 *cs_seq) { struct hl_device *hdev = hpriv->hdev; struct hl_cs_chunk *cs_chunk_array; @@ -538,7 +599,7 @@ static int _hl_cs_ioctl(struct hl_fpriv *hpriv, void __user *chunks, /* increment refcnt for context */ hl_ctx_get(hdev, hpriv->ctx); - rc = allocate_cs(hdev, hpriv->ctx, &cs); + rc = allocate_cs(hdev, hpriv->ctx, CS_TYPE_DEFAULT, &cs); if (rc) { hl_ctx_put(hpriv->ctx); goto free_cs_chunk_array; @@ -652,13 +713,230 @@ out: return rc; } +static int cs_ioctl_signal_wait(struct hl_fpriv *hpriv, enum hl_cs_type cs_type, + void __user *chunks, u32 num_chunks, + u64 *cs_seq) +{ + struct hl_device *hdev = hpriv->hdev; + struct hl_ctx *ctx = hpriv->ctx; + struct hl_cs_chunk *cs_chunk_array, *chunk; + struct hw_queue_properties *hw_queue_prop; + struct dma_fence *sig_fence = NULL; + struct hl_cs_job *job; + struct hl_cs *cs; + struct hl_cb *cb; + u64 *signal_seq_arr = NULL, signal_seq; + u32 size_to_copy, q_idx, signal_seq_arr_len, cb_size; + int rc; + + *cs_seq = ULLONG_MAX; + + if (num_chunks > HL_MAX_JOBS_PER_CS) { + dev_err(hdev->dev, + "Number of chunks can NOT be larger than %d\n", + HL_MAX_JOBS_PER_CS); + rc = -EINVAL; + goto out; + } + + cs_chunk_array = kmalloc_array(num_chunks, sizeof(*cs_chunk_array), + GFP_ATOMIC); + if (!cs_chunk_array) { + rc = -ENOMEM; + goto out; + } + + size_to_copy = num_chunks * sizeof(struct hl_cs_chunk); + if (copy_from_user(cs_chunk_array, chunks, size_to_copy)) { + dev_err(hdev->dev, "Failed to copy cs chunk array from user\n"); + rc = -EFAULT; + goto free_cs_chunk_array; + } + + /* currently it is guaranteed to have only one chunk */ + chunk = &cs_chunk_array[0]; + q_idx = chunk->queue_index; + hw_queue_prop = &hdev->asic_prop.hw_queues_props[q_idx]; + + if ((q_idx >= HL_MAX_QUEUES) || + (hw_queue_prop->type != QUEUE_TYPE_EXT)) { + dev_err(hdev->dev, "Queue index %d is invalid\n", q_idx); + rc = -EINVAL; + goto free_cs_chunk_array; + } + + if (cs_type == CS_TYPE_WAIT) { + struct hl_cs_compl *sig_waitcs_cmpl; + + signal_seq_arr_len = chunk->num_signal_seq_arr; + + /* currently only one signal seq is supported */ + if (signal_seq_arr_len != 1) { + dev_err(hdev->dev, + "Wait for signal CS supports only one signal CS seq\n"); + rc = -EINVAL; + goto free_cs_chunk_array; + } + + signal_seq_arr = kmalloc_array(signal_seq_arr_len, + sizeof(*signal_seq_arr), + GFP_ATOMIC); + if (!signal_seq_arr) { + rc = -ENOMEM; + goto free_cs_chunk_array; + } + + size_to_copy = chunk->num_signal_seq_arr * + sizeof(*signal_seq_arr); + if (copy_from_user(signal_seq_arr, + u64_to_user_ptr(chunk->signal_seq_arr), + size_to_copy)) { + dev_err(hdev->dev, + "Failed to copy signal seq array from user\n"); + rc = -EFAULT; + goto free_signal_seq_array; + } + + /* currently it is guaranteed to have only one signal seq */ + signal_seq = signal_seq_arr[0]; + sig_fence = hl_ctx_get_fence(ctx, signal_seq); + if (IS_ERR(sig_fence)) { + dev_err(hdev->dev, + "Failed to get signal CS with seq 0x%llx\n", + signal_seq); + rc = PTR_ERR(sig_fence); + goto free_signal_seq_array; + } + + if (!sig_fence) { + /* signal CS already finished */ + rc = 0; + goto free_signal_seq_array; + } + + sig_waitcs_cmpl = + container_of(sig_fence, struct hl_cs_compl, base_fence); + + if (sig_waitcs_cmpl->type != CS_TYPE_SIGNAL) { + dev_err(hdev->dev, + "CS seq 0x%llx is not of a signal CS\n", + signal_seq); + dma_fence_put(sig_fence); + rc = -EINVAL; + goto free_signal_seq_array; + } + + if (dma_fence_is_signaled(sig_fence)) { + /* signal CS already finished */ + dma_fence_put(sig_fence); + rc = 0; + goto free_signal_seq_array; + } + } + + /* increment refcnt for context */ + hl_ctx_get(hdev, ctx); + + rc = allocate_cs(hdev, ctx, cs_type, &cs); + if (rc) { + if (cs_type == CS_TYPE_WAIT) + dma_fence_put(sig_fence); + hl_ctx_put(ctx); + goto free_signal_seq_array; + } + + /* + * Save the signal CS fence for later initialization right before + * hanging the wait CS on the queue. + */ + if (cs->type == CS_TYPE_WAIT) + cs->signal_fence = sig_fence; + + hl_debugfs_add_cs(cs); + + *cs_seq = cs->sequence; + + job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + goto put_cs; + } + + cb = hl_cb_kernel_create(hdev, PAGE_SIZE); + if (!cb) { + kfree(job); + rc = -EFAULT; + goto put_cs; + } + + if (cs->type == CS_TYPE_WAIT) + cb_size = hdev->asic_funcs->get_wait_cb_size(hdev); + else + cb_size = hdev->asic_funcs->get_signal_cb_size(hdev); + + job->id = 0; + job->cs = cs; + job->user_cb = cb; + job->user_cb->cs_cnt++; + job->user_cb_size = cb_size; + job->hw_queue_id = q_idx; + + /* + * No need in parsing, user CB is the patched CB. + * We call hl_cb_destroy() out of two reasons - we don't need the CB in + * the CB idr anymore and to decrement its refcount as it was + * incremented inside hl_cb_kernel_create(). + */ + job->patched_cb = job->user_cb; + job->job_cb_size = job->user_cb_size; + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT); + + cs->jobs_in_queue_cnt[job->hw_queue_id]++; + + list_add_tail(&job->cs_node, &cs->job_list); + + /* increment refcount as for external queues we get completion */ + cs_get(cs); + + hl_debugfs_add_job(hdev, job); + + rc = hl_hw_queue_schedule_cs(cs); + if (rc) { + if (rc != -EAGAIN) + dev_err(hdev->dev, + "Failed to submit CS %d.%llu to H/W queues, error %d\n", + ctx->asid, cs->sequence, rc); + goto free_cs_object; + } + + rc = HL_CS_STATUS_SUCCESS; + goto put_cs; + +free_cs_object: + cs_rollback(hdev, cs); + *cs_seq = ULLONG_MAX; + /* The path below is both for good and erroneous exits */ +put_cs: + /* We finished with the CS in this function, so put the ref */ + cs_put(cs); +free_signal_seq_array: + if (cs_type == CS_TYPE_WAIT) + kfree(signal_seq_arr); +free_cs_chunk_array: + kfree(cs_chunk_array); +out: + return rc; +} + int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) { struct hl_device *hdev = hpriv->hdev; union hl_cs_args *args = data; struct hl_ctx *ctx = hpriv->ctx; void __user *chunks_execute, *chunks_restore; - u32 num_chunks_execute, num_chunks_restore; + enum hl_cs_type cs_type; + u32 num_chunks_execute, num_chunks_restore, sig_wait_flags; u64 cs_seq = ULONG_MAX; int rc, do_ctx_switch; bool need_soft_reset = false; @@ -671,12 +949,44 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) goto out; } + sig_wait_flags = args->in.cs_flags & HL_CS_FLAGS_SIG_WAIT; + + if (unlikely(sig_wait_flags == HL_CS_FLAGS_SIG_WAIT)) { + dev_err(hdev->dev, + "Signal and wait CS flags are mutually exclusive, context %d\n", + ctx->asid); + rc = -EINVAL; + goto out; + } + + if (unlikely((sig_wait_flags & HL_CS_FLAGS_SIG_WAIT) && + (!hdev->supports_sync_stream))) { + dev_err(hdev->dev, "Sync stream CS is not supported\n"); + rc = -EINVAL; + goto out; + } + + if (args->in.cs_flags & HL_CS_FLAGS_SIGNAL) + cs_type = CS_TYPE_SIGNAL; + else if (args->in.cs_flags & HL_CS_FLAGS_WAIT) + cs_type = CS_TYPE_WAIT; + else + cs_type = CS_TYPE_DEFAULT; + chunks_execute = (void __user *) (uintptr_t) args->in.chunks_execute; num_chunks_execute = args->in.num_chunks_execute; - if (!num_chunks_execute) { + if (cs_type == CS_TYPE_DEFAULT) { + if (!num_chunks_execute) { + dev_err(hdev->dev, + "Got execute CS with 0 chunks, context %d\n", + ctx->asid); + rc = -EINVAL; + goto out; + } + } else if (num_chunks_execute != 1) { dev_err(hdev->dev, - "Got execute CS with 0 chunks, context %d\n", + "Sync stream CS mandates one chunk only, context %d\n", ctx->asid); rc = -EINVAL; goto out; @@ -722,7 +1032,7 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) "Need to run restore phase but restore CS is empty\n"); rc = 0; } else { - rc = _hl_cs_ioctl(hpriv, chunks_restore, + rc = cs_ioctl_default(hpriv, chunks_restore, num_chunks_restore, &cs_seq); } @@ -764,7 +1074,12 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data) } } - rc = _hl_cs_ioctl(hpriv, chunks_execute, num_chunks_execute, &cs_seq); + if (cs_type == CS_TYPE_DEFAULT) + rc = cs_ioctl_default(hpriv, chunks_execute, num_chunks_execute, + &cs_seq); + else + rc = cs_ioctl_signal_wait(hpriv, cs_type, chunks_execute, + num_chunks_execute, &cs_seq); out: if (rc != -EAGAIN) { @@ -796,6 +1111,10 @@ static long _hl_cs_wait_ioctl(struct hl_device *hdev, fence = hl_ctx_get_fence(ctx, seq); if (IS_ERR(fence)) { rc = PTR_ERR(fence); + if (rc == -EINVAL) + dev_notice_ratelimited(hdev->dev, + "Can't wait on seq %llu because current CS is at seq %llu\n", + seq, ctx->cs_sequence); } else if (fence) { rc = dma_fence_wait_timeout(fence, true, timeout); if (fence->error == -ETIMEDOUT) @@ -803,8 +1122,12 @@ static long _hl_cs_wait_ioctl(struct hl_device *hdev, else if (fence->error == -EIO) rc = -EIO; dma_fence_put(fence); - } else + } else { + dev_dbg(hdev->dev, + "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", + seq, ctx->cs_sequence); rc = 1; + } hl_ctx_put(ctx); diff --git a/drivers/misc/habanalabs/context.c b/drivers/misc/habanalabs/context.c index 2df6fb87e7ff..ec92b3506b1f 100644 --- a/drivers/misc/habanalabs/context.c +++ b/drivers/misc/habanalabs/context.c @@ -170,24 +170,16 @@ int hl_ctx_put(struct hl_ctx *ctx) struct dma_fence *hl_ctx_get_fence(struct hl_ctx *ctx, u64 seq) { - struct hl_device *hdev = ctx->hdev; struct dma_fence *fence; spin_lock(&ctx->cs_lock); if (seq >= ctx->cs_sequence) { - dev_notice_ratelimited(hdev->dev, - "Can't wait on seq %llu because current CS is at seq %llu\n", - seq, ctx->cs_sequence); spin_unlock(&ctx->cs_lock); return ERR_PTR(-EINVAL); } - if (seq + HL_MAX_PENDING_CS < ctx->cs_sequence) { - dev_dbg(hdev->dev, - "Can't wait on seq %llu because current CS is at seq %llu (Fence is gone)\n", - seq, ctx->cs_sequence); spin_unlock(&ctx->cs_lock); return NULL; } diff --git a/drivers/misc/habanalabs/debugfs.c b/drivers/misc/habanalabs/debugfs.c index 756d36ed5d95..3c8dcdfba20c 100644 --- a/drivers/misc/habanalabs/debugfs.c +++ b/drivers/misc/habanalabs/debugfs.c @@ -970,6 +970,98 @@ static ssize_t hl_device_write(struct file *f, const char __user *buf, return count; } +static ssize_t hl_clk_gate_read(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char tmp_buf[200]; + ssize_t rc; + + if (*ppos) + return 0; + + sprintf(tmp_buf, "%d\n", hdev->clock_gating); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_clk_gate_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + if (atomic_read(&hdev->in_reset)) { + dev_warn_ratelimited(hdev->dev, + "Can't change clock gating during reset\n"); + return 0; + } + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + if (value) { + hdev->clock_gating = 1; + if (hdev->asic_funcs->enable_clock_gating) + hdev->asic_funcs->enable_clock_gating(hdev); + } else { + if (hdev->asic_funcs->disable_clock_gating) + hdev->asic_funcs->disable_clock_gating(hdev); + hdev->clock_gating = 0; + } + + return count; +} + +static ssize_t hl_stop_on_err_read(struct file *f, char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + char tmp_buf[200]; + ssize_t rc; + + if (*ppos) + return 0; + + sprintf(tmp_buf, "%d\n", hdev->stop_on_err); + rc = simple_read_from_buffer(buf, strlen(tmp_buf) + 1, ppos, tmp_buf, + strlen(tmp_buf) + 1); + + return rc; +} + +static ssize_t hl_stop_on_err_write(struct file *f, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct hl_dbg_device_entry *entry = file_inode(f)->i_private; + struct hl_device *hdev = entry->hdev; + u32 value; + ssize_t rc; + + if (atomic_read(&hdev->in_reset)) { + dev_warn_ratelimited(hdev->dev, + "Can't change stop on error during reset\n"); + return 0; + } + + rc = kstrtouint_from_user(buf, count, 10, &value); + if (rc) + return rc; + + hdev->stop_on_err = value ? 1 : 0; + + hl_device_reset(hdev, false, false); + + return count; +} + static const struct file_operations hl_data32b_fops = { .owner = THIS_MODULE, .read = hl_data_read32, @@ -1015,6 +1107,18 @@ static const struct file_operations hl_device_fops = { .write = hl_device_write }; +static const struct file_operations hl_clk_gate_fops = { + .owner = THIS_MODULE, + .read = hl_clk_gate_read, + .write = hl_clk_gate_write +}; + +static const struct file_operations hl_stop_on_err_fops = { + .owner = THIS_MODULE, + .read = hl_stop_on_err_read, + .write = hl_stop_on_err_write +}; + static const struct hl_info_list hl_debugfs_list[] = { {"command_buffers", command_buffers_show, NULL}, {"command_submission", command_submission_show, NULL}, @@ -1152,6 +1256,18 @@ void hl_debugfs_add_device(struct hl_device *hdev) dev_entry, &hl_device_fops); + debugfs_create_file("clk_gate", + 0200, + dev_entry->root, + dev_entry, + &hl_clk_gate_fops); + + debugfs_create_file("stop_on_err", + 0644, + dev_entry->root, + dev_entry, + &hl_stop_on_err_fops); + for (i = 0, entry = dev_entry->entry_arr ; i < count ; i++, entry++) { ent = debugfs_create_file(hl_debugfs_list[i].name, diff --git a/drivers/misc/habanalabs/device.c b/drivers/misc/habanalabs/device.c index aef4de36b7aa..2b38a119704c 100644 --- a/drivers/misc/habanalabs/device.c +++ b/drivers/misc/habanalabs/device.c @@ -256,6 +256,10 @@ static int device_early_init(struct hl_device *hdev) goya_set_asic_funcs(hdev); strlcpy(hdev->asic_name, "GOYA", sizeof(hdev->asic_name)); break; + case ASIC_GAUDI: + gaudi_set_asic_funcs(hdev); + sprintf(hdev->asic_name, "GAUDI"); + break; default: dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type); @@ -603,6 +607,9 @@ int hl_device_set_debug_mode(struct hl_device *hdev, bool enable) hdev->in_debug = 0; + if (!hdev->hard_reset_pending) + hdev->asic_funcs->enable_clock_gating(hdev); + goto out; } @@ -613,6 +620,7 @@ int hl_device_set_debug_mode(struct hl_device *hdev, bool enable) goto out; } + hdev->asic_funcs->disable_clock_gating(hdev); hdev->in_debug = 1; out: @@ -718,7 +726,7 @@ disable_device: return rc; } -static void device_kill_open_processes(struct hl_device *hdev) +static int device_kill_open_processes(struct hl_device *hdev) { u16 pending_total, pending_cnt; struct hl_fpriv *hpriv; @@ -771,9 +779,7 @@ static void device_kill_open_processes(struct hl_device *hdev) ssleep(1); } - if (!list_empty(&hdev->fpriv_list)) - dev_crit(hdev->dev, - "Going to hard reset with open user contexts\n"); + return list_empty(&hdev->fpriv_list) ? 0 : -EBUSY; } static void device_hard_reset_pending(struct work_struct *work) @@ -793,6 +799,7 @@ static void device_hard_reset_pending(struct work_struct *work) * @hdev: pointer to habanalabs device structure * @hard_reset: should we do hard reset to all engines or just reset the * compute/dma engines + * @from_hard_reset_thread: is the caller the hard-reset thread * * Block future CS and wait for pending CS to be enqueued * Call ASIC H/W fini @@ -815,6 +822,11 @@ int hl_device_reset(struct hl_device *hdev, bool hard_reset, return 0; } + if ((!hard_reset) && (!hdev->supports_soft_reset)) { + dev_dbg(hdev->dev, "Doing hard-reset instead of soft-reset\n"); + hard_reset = true; + } + /* * Prevent concurrency in this function - only one reset should be * done at any given time. Only need to perform this if we didn't @@ -894,7 +906,12 @@ again: * process can't really exit until all its CSs are done, which * is what we do in cs rollback */ - device_kill_open_processes(hdev); + rc = device_kill_open_processes(hdev); + if (rc) { + dev_crit(hdev->dev, + "Failed to kill all open processes, stopping hard reset\n"); + goto out_err; + } /* Flush the Event queue workers to make sure no other thread is * reading or writing to registers during the reset @@ -1062,7 +1079,7 @@ out_err: */ int hl_device_init(struct hl_device *hdev, struct class *hclass) { - int i, rc, cq_ready_cnt; + int i, rc, cq_cnt, cq_ready_cnt; char *name; bool add_cdev_sysfs_on_err = false; @@ -1120,14 +1137,16 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) goto sw_fini; } + cq_cnt = hdev->asic_prop.completion_queues_count; + /* * Initialize the completion queues. Must be done before hw_init, * because there the addresses of the completion queues are being * passed as arguments to request_irq */ - hdev->completion_queue = - kcalloc(hdev->asic_prop.completion_queues_count, - sizeof(*hdev->completion_queue), GFP_KERNEL); + hdev->completion_queue = kcalloc(cq_cnt, + sizeof(*hdev->completion_queue), + GFP_KERNEL); if (!hdev->completion_queue) { dev_err(hdev->dev, "failed to allocate completion queues\n"); @@ -1135,10 +1154,9 @@ int hl_device_init(struct hl_device *hdev, struct class *hclass) goto hw_queues_destroy; } - for (i = 0, cq_ready_cnt = 0; - i < hdev->asic_prop.completion_queues_count; - i++, cq_ready_cnt++) { - rc = hl_cq_init(hdev, &hdev->completion_queue[i], i); + for (i = 0, cq_ready_cnt = 0 ; i < cq_cnt ; i++, cq_ready_cnt++) { + rc = hl_cq_init(hdev, &hdev->completion_queue[i], + hdev->asic_funcs->get_queue_id_for_cq(hdev, i)); if (rc) { dev_err(hdev->dev, "failed to initialize completion queue\n"); @@ -1325,11 +1343,12 @@ void hl_device_fini(struct hl_device *hdev) * This function is competing with the reset function, so try to * take the reset atomic and if we are already in middle of reset, * wait until reset function is finished. Reset function is designed - * to always finish (could take up to a few seconds in worst case). + * to always finish. However, in Gaudi, because of all the network + * ports, the hard reset could take between 10-30 seconds */ timeout = ktime_add_us(ktime_get(), - HL_PENDING_RESET_PER_SEC * 1000 * 1000 * 4); + HL_HARD_RESET_MAX_TIMEOUT * 1000 * 1000); rc = atomic_cmpxchg(&hdev->in_reset, 0, 1); while (rc) { usleep_range(50, 200); @@ -1375,7 +1394,9 @@ void hl_device_fini(struct hl_device *hdev) * can't really exit until all its CSs are done, which is what we * do in cs rollback */ - device_kill_open_processes(hdev); + rc = device_kill_open_processes(hdev); + if (rc) + dev_crit(hdev->dev, "Failed to kill all open processes\n"); hl_cb_pool_fini(hdev); diff --git a/drivers/misc/habanalabs/firmware_if.c b/drivers/misc/habanalabs/firmware_if.c index f5bd03171dac..baf790cf4b78 100644 --- a/drivers/misc/habanalabs/firmware_if.c +++ b/drivers/misc/habanalabs/firmware_if.c @@ -6,20 +6,22 @@ */ #include "habanalabs.h" +#include "include/hl_boot_if.h" #include <linux/firmware.h> #include <linux/genalloc.h> #include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/slab.h> /** - * hl_fw_push_fw_to_device() - Push FW code to device. + * hl_fw_load_fw_to_device() - Load F/W code to device's memory. * @hdev: pointer to hl_device structure. * * Copy fw code from firmware file to device memory. * * Return: 0 on success, non-zero for failure. */ -int hl_fw_push_fw_to_device(struct hl_device *hdev, const char *fw_name, +int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name, void __iomem *dst) { const struct firmware *fw; @@ -129,6 +131,68 @@ out: return rc; } +int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type) +{ + struct armcp_packet pkt; + long result; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.value = cpu_to_le64(event_type); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + HL_DEVICE_TIMEOUT_USEC, &result); + + if (rc) + dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type); + + return rc; +} + +int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, + size_t irq_arr_size) +{ + struct armcp_unmask_irq_arr_packet *pkt; + size_t total_pkt_size; + long result; + int rc; + + total_pkt_size = sizeof(struct armcp_unmask_irq_arr_packet) + + irq_arr_size; + + /* data should be aligned to 8 bytes in order to ArmCP to copy it */ + total_pkt_size = (total_pkt_size + 0x7) & ~0x7; + + /* total_pkt_size is casted to u16 later on */ + if (total_pkt_size > USHRT_MAX) { + dev_err(hdev->dev, "too many elements in IRQ array\n"); + return -EINVAL; + } + + pkt = kzalloc(total_pkt_size, GFP_KERNEL); + if (!pkt) + return -ENOMEM; + + pkt->length = cpu_to_le32(irq_arr_size / sizeof(irq_arr[0])); + memcpy(&pkt->irqs, irq_arr, irq_arr_size); + + pkt->armcp_pkt.ctl = cpu_to_le32(ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY << + ARMCP_PKT_CTL_OPCODE_SHIFT); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt, + total_pkt_size, HL_DEVICE_TIMEOUT_USEC, &result); + + if (rc) + dev_err(hdev->dev, "failed to unmask IRQ array\n"); + + kfree(pkt); + + return rc; +} + int hl_fw_test_cpu_queue(struct hl_device *hdev) { struct armcp_packet test_pkt = {}; @@ -286,3 +350,232 @@ out: return rc; } + +static void fw_read_errors(struct hl_device *hdev, u32 boot_err0_reg) +{ + u32 err_val; + + /* Some of the firmware status codes are deprecated in newer f/w + * versions. In those versions, the errors are reported + * in different registers. Therefore, we need to check those + * registers and print the exact errors. Moreover, there + * may be multiple errors, so we need to report on each error + * separately. Some of the error codes might indicate a state + * that is not an error per-se, but it is an error in production + * environment + */ + err_val = RREG32(boot_err0_reg); + if (!(err_val & CPU_BOOT_ERR0_ENABLED)) + return; + + if (err_val & CPU_BOOT_ERR0_DRAM_INIT_FAIL) + dev_err(hdev->dev, + "Device boot error - DRAM initialization failed\n"); + if (err_val & CPU_BOOT_ERR0_FIT_CORRUPTED) + dev_err(hdev->dev, "Device boot error - FIT image corrupted\n"); + if (err_val & CPU_BOOT_ERR0_TS_INIT_FAIL) + dev_err(hdev->dev, + "Device boot error - Thermal Sensor initialization failed\n"); + if (err_val & CPU_BOOT_ERR0_DRAM_SKIPPED) + dev_warn(hdev->dev, + "Device boot warning - Skipped DRAM initialization\n"); + if (err_val & CPU_BOOT_ERR0_BMC_WAIT_SKIPPED) + dev_warn(hdev->dev, + "Device boot error - Skipped waiting for BMC\n"); + if (err_val & CPU_BOOT_ERR0_NIC_DATA_NOT_RDY) + dev_err(hdev->dev, + "Device boot error - Serdes data from BMC not available\n"); + if (err_val & CPU_BOOT_ERR0_NIC_FW_FAIL) + dev_err(hdev->dev, + "Device boot error - NIC F/W initialization failed\n"); +} + +int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, + u32 boot_err0_reg, bool skip_bmc, + u32 cpu_timeout, u32 boot_fit_timeout) +{ + u32 status; + int rc; + + dev_info(hdev->dev, "Going to wait for device boot (up to %lds)\n", + cpu_timeout / USEC_PER_SEC); + + /* Wait for boot FIT request */ + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + status == CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT, + 10000, + boot_fit_timeout); + + if (rc) { + dev_dbg(hdev->dev, + "No boot fit request received, resuming boot\n"); + } else { + rc = hdev->asic_funcs->load_boot_fit_to_device(hdev); + if (rc) + goto out; + + /* Clear device CPU message status */ + WREG32(cpu_msg_status_reg, CPU_MSG_CLR); + + /* Signal device CPU that boot loader is ready */ + WREG32(msg_to_cpu_reg, KMD_MSG_FIT_RDY); + + /* Poll for CPU device ack */ + rc = hl_poll_timeout( + hdev, + cpu_msg_status_reg, + status, + status == CPU_MSG_OK, + 10000, + boot_fit_timeout); + + if (rc) { + dev_err(hdev->dev, + "Timeout waiting for boot fit load ack\n"); + goto out; + } + + /* Clear message */ + WREG32(msg_to_cpu_reg, KMD_MSG_NA); + } + + /* Make sure CPU boot-loader is running */ + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + (status == CPU_BOOT_STATUS_DRAM_RDY) || + (status == CPU_BOOT_STATUS_NIC_FW_RDY) || + (status == CPU_BOOT_STATUS_READY_TO_BOOT) || + (status == CPU_BOOT_STATUS_SRAM_AVAIL), + 10000, + cpu_timeout); + + /* Read U-Boot, preboot versions now in case we will later fail */ + hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_UBOOT); + hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_PREBOOT); + + /* Some of the status codes below are deprecated in newer f/w + * versions but we keep them here for backward compatibility + */ + if (rc) { + switch (status) { + case CPU_BOOT_STATUS_NA: + dev_err(hdev->dev, + "Device boot error - BTL did NOT run\n"); + break; + case CPU_BOOT_STATUS_IN_WFE: + dev_err(hdev->dev, + "Device boot error - Stuck inside WFE loop\n"); + break; + case CPU_BOOT_STATUS_IN_BTL: + dev_err(hdev->dev, + "Device boot error - Stuck in BTL\n"); + break; + case CPU_BOOT_STATUS_IN_PREBOOT: + dev_err(hdev->dev, + "Device boot error - Stuck in Preboot\n"); + break; + case CPU_BOOT_STATUS_IN_SPL: + dev_err(hdev->dev, + "Device boot error - Stuck in SPL\n"); + break; + case CPU_BOOT_STATUS_IN_UBOOT: + dev_err(hdev->dev, + "Device boot error - Stuck in u-boot\n"); + break; + case CPU_BOOT_STATUS_DRAM_INIT_FAIL: + dev_err(hdev->dev, + "Device boot error - DRAM initialization failed\n"); + break; + case CPU_BOOT_STATUS_UBOOT_NOT_READY: + dev_err(hdev->dev, + "Device boot error - u-boot stopped by user\n"); + break; + case CPU_BOOT_STATUS_TS_INIT_FAIL: + dev_err(hdev->dev, + "Device boot error - Thermal Sensor initialization failed\n"); + break; + default: + dev_err(hdev->dev, + "Device boot error - Invalid status code %d\n", + status); + break; + } + + rc = -EIO; + goto out; + } + + if (!hdev->fw_loading) { + dev_info(hdev->dev, "Skip loading FW\n"); + goto out; + } + + if (status == CPU_BOOT_STATUS_SRAM_AVAIL) + goto out; + + dev_info(hdev->dev, + "Loading firmware to device, may take some time...\n"); + + rc = hdev->asic_funcs->load_firmware_to_device(hdev); + if (rc) + goto out; + + if (skip_bmc) { + WREG32(msg_to_cpu_reg, KMD_MSG_SKIP_BMC); + + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + (status == CPU_BOOT_STATUS_BMC_WAITING_SKIPPED), + 10000, + cpu_timeout); + + if (rc) { + dev_err(hdev->dev, + "Failed to get ACK on skipping BMC, %d\n", + status); + WREG32(msg_to_cpu_reg, KMD_MSG_NA); + rc = -EIO; + goto out; + } + } + + WREG32(msg_to_cpu_reg, KMD_MSG_FIT_RDY); + + rc = hl_poll_timeout( + hdev, + cpu_boot_status_reg, + status, + (status == CPU_BOOT_STATUS_SRAM_AVAIL), + 10000, + cpu_timeout); + + /* Clear message */ + WREG32(msg_to_cpu_reg, KMD_MSG_NA); + + if (rc) { + if (status == CPU_BOOT_STATUS_FIT_CORRUPTED) + dev_err(hdev->dev, + "Device reports FIT image is corrupted\n"); + else + dev_err(hdev->dev, + "Device failed to load, %d\n", status); + + rc = -EIO; + goto out; + } + + dev_info(hdev->dev, "Successfully loaded firmware to device\n"); + +out: + fw_read_errors(hdev, boot_err0_reg); + + return rc; +} diff --git a/drivers/misc/habanalabs/gaudi/Makefile b/drivers/misc/habanalabs/gaudi/Makefile new file mode 100644 index 000000000000..f802cdc980ca --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +subdir-ccflags-y += -I$(src) + +HL_GAUDI_FILES := gaudi/gaudi.o gaudi/gaudi_hwmgr.o gaudi/gaudi_security.o \ + gaudi/gaudi_coresight.o diff --git a/drivers/misc/habanalabs/gaudi/gaudi.c b/drivers/misc/habanalabs/gaudi/gaudi.c new file mode 100644 index 000000000000..61f88e9884ce --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi.c @@ -0,0 +1,6748 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/hw_ip/mmu/mmu_general.h" +#include "include/hw_ip/mmu/mmu_v1_1.h" +#include "include/gaudi/gaudi_masks.h" +#include "include/gaudi/gaudi_fw_if.h" +#include "include/gaudi/gaudi_reg_map.h" +#include "include/gaudi/gaudi_async_ids_map_extended.h" + +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/firmware.h> +#include <linux/hwmon.h> +#include <linux/genalloc.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/iommu.h> +#include <linux/seq_file.h> + +/* + * Gaudi security scheme: + * + * 1. Host is protected by: + * - Range registers + * - MMU + * + * 2. DDR is protected by: + * - Range registers (protect the first 512MB) + * + * 3. Configuration is protected by: + * - Range registers + * - Protection bits + * + * MMU is always enabled. + * + * QMAN DMA channels 0,1,5 (PCI DMAN): + * - DMA is not secured. + * - PQ and CQ are secured. + * - CP is secured: The driver needs to parse CB but WREG should be allowed + * because of TDMA (tensor DMA). Hence, WREG is always not + * secured. + * + * When the driver needs to use DMA it will check that Gaudi is idle, set DMA + * channel 0 to be secured, execute the DMA and change it back to not secured. + * Currently, the driver doesn't use the DMA while there are compute jobs + * running. + * + * The current use cases for the driver to use the DMA are: + * - Clear SRAM on context switch (happens on context switch when device is + * idle) + * - MMU page tables area clear (happens on init) + * + * QMAN DMA 2-4,6,7, TPC, MME, NIC: + * PQ is secured and is located on the Host (HBM CON TPC3 bug) + * CQ, CP and the engine are not secured + * + */ + +#define GAUDI_BOOT_FIT_FILE "habanalabs/gaudi/gaudi-boot-fit.itb" +#define GAUDI_LINUX_FW_FILE "habanalabs/gaudi/gaudi-fit.itb" +#define GAUDI_TPC_FW_FILE "habanalabs/gaudi/gaudi_tpc.bin" + +#define GAUDI_DMA_POOL_BLK_SIZE 0x100 /* 256 bytes */ + +#define GAUDI_RESET_TIMEOUT_MSEC 1000 /* 1000ms */ +#define GAUDI_RESET_WAIT_MSEC 1 /* 1ms */ +#define GAUDI_CPU_RESET_WAIT_MSEC 200 /* 200ms */ +#define GAUDI_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ + +#define GAUDI_PLDM_RESET_WAIT_MSEC 1000 /* 1s */ +#define GAUDI_PLDM_HRESET_TIMEOUT_MSEC 20000 /* 20s */ +#define GAUDI_PLDM_SRESET_TIMEOUT_MSEC 14000 /* 14s */ +#define GAUDI_PLDM_TEST_QUEUE_WAIT_USEC 1000000 /* 1s */ +#define GAUDI_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100) +#define GAUDI_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) +#define GAUDI_PLDM_TPC_KERNEL_WAIT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) +#define GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC 1000000 /* 1s */ + +#define GAUDI_QMAN0_FENCE_VAL 0x72E91AB9 + +#define GAUDI_MAX_STRING_LEN 20 + +#define GAUDI_CB_POOL_CB_CNT 512 +#define GAUDI_CB_POOL_CB_SIZE 0x20000 /* 128KB */ + +#define GAUDI_ALLOC_CPU_MEM_RETRY_CNT 3 + +#define GAUDI_NUM_OF_TPC_INTR_CAUSE 20 + +#define GAUDI_NUM_OF_QM_ERR_CAUSE 16 + +#define GAUDI_NUM_OF_QM_ARB_ERR_CAUSE 3 + +#define GAUDI_ARB_WDT_TIMEOUT 0x400000 + +static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = { + "gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3", + "gaudi cq 1_0", "gaudi cq 1_1", "gaudi cq 1_2", "gaudi cq 1_3", + "gaudi cq 5_0", "gaudi cq 5_1", "gaudi cq 5_2", "gaudi cq 5_3", + "gaudi cpu eq" +}; + +static const u8 gaudi_dma_assignment[GAUDI_DMA_MAX] = { + [GAUDI_PCI_DMA_1] = 0, + [GAUDI_PCI_DMA_2] = 1, + [GAUDI_PCI_DMA_3] = 5, + [GAUDI_HBM_DMA_1] = 2, + [GAUDI_HBM_DMA_2] = 3, + [GAUDI_HBM_DMA_3] = 4, + [GAUDI_HBM_DMA_4] = 6, + [GAUDI_HBM_DMA_5] = 7 +}; + +static const u8 gaudi_cq_assignment[NUMBER_OF_CMPLT_QUEUES] = { + [0] = GAUDI_QUEUE_ID_DMA_0_0, + [1] = GAUDI_QUEUE_ID_DMA_0_1, + [2] = GAUDI_QUEUE_ID_DMA_0_2, + [3] = GAUDI_QUEUE_ID_DMA_0_3, + [4] = GAUDI_QUEUE_ID_DMA_1_0, + [5] = GAUDI_QUEUE_ID_DMA_1_1, + [6] = GAUDI_QUEUE_ID_DMA_1_2, + [7] = GAUDI_QUEUE_ID_DMA_1_3, + [8] = GAUDI_QUEUE_ID_DMA_5_0, + [9] = GAUDI_QUEUE_ID_DMA_5_1, + [10] = GAUDI_QUEUE_ID_DMA_5_2, + [11] = GAUDI_QUEUE_ID_DMA_5_3 +}; + +static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = { + [PACKET_WREG_32] = sizeof(struct packet_wreg32), + [PACKET_WREG_BULK] = sizeof(struct packet_wreg_bulk), + [PACKET_MSG_LONG] = sizeof(struct packet_msg_long), + [PACKET_MSG_SHORT] = sizeof(struct packet_msg_short), + [PACKET_CP_DMA] = sizeof(struct packet_cp_dma), + [PACKET_REPEAT] = sizeof(struct packet_repeat), + [PACKET_MSG_PROT] = sizeof(struct packet_msg_prot), + [PACKET_FENCE] = sizeof(struct packet_fence), + [PACKET_LIN_DMA] = sizeof(struct packet_lin_dma), + [PACKET_NOP] = sizeof(struct packet_nop), + [PACKET_STOP] = sizeof(struct packet_stop), + [PACKET_ARB_POINT] = sizeof(struct packet_arb_point), + [PACKET_WAIT] = sizeof(struct packet_wait), + [PACKET_LOAD_AND_EXE] = sizeof(struct packet_load_and_exe) +}; + +static const char * const +gaudi_tpc_interrupts_cause[GAUDI_NUM_OF_TPC_INTR_CAUSE] = { + "tpc_address_exceed_slm", + "tpc_div_by_0", + "tpc_spu_mac_overflow", + "tpc_spu_addsub_overflow", + "tpc_spu_abs_overflow", + "tpc_spu_fp_dst_nan_inf", + "tpc_spu_fp_dst_denorm", + "tpc_vpu_mac_overflow", + "tpc_vpu_addsub_overflow", + "tpc_vpu_abs_overflow", + "tpc_vpu_fp_dst_nan_inf", + "tpc_vpu_fp_dst_denorm", + "tpc_assertions", + "tpc_illegal_instruction", + "tpc_pc_wrap_around", + "tpc_qm_sw_err", + "tpc_hbw_rresp_err", + "tpc_hbw_bresp_err", + "tpc_lbw_rresp_err", + "tpc_lbw_bresp_err" +}; + +static const char * const +gaudi_qman_error_cause[GAUDI_NUM_OF_QM_ERR_CAUSE] = { + "PQ AXI HBW error", + "CQ AXI HBW error", + "CP AXI HBW error", + "CP error due to undefined OPCODE", + "CP encountered STOP OPCODE", + "CP AXI LBW error", + "CP WRREG32 or WRBULK returned error", + "N/A", + "FENCE 0 inc over max value and clipped", + "FENCE 1 inc over max value and clipped", + "FENCE 2 inc over max value and clipped", + "FENCE 3 inc over max value and clipped", + "FENCE 0 dec under min value and clipped", + "FENCE 1 dec under min value and clipped", + "FENCE 2 dec under min value and clipped", + "FENCE 3 dec under min value and clipped" +}; + +static const char * const +gaudi_qman_arb_error_cause[GAUDI_NUM_OF_QM_ARB_ERR_CAUSE] = { + "Choice push while full error", + "Choice Q watchdog error", + "MSG AXI LBW returned with error" +}; + +static enum hl_queue_type gaudi_queue_type[GAUDI_QUEUE_ID_SIZE] = { + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_0 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_1 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_2 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_0_3 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_0 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_1 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_2 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_1_3 */ + QUEUE_TYPE_CPU, /* GAUDI_QUEUE_ID_CPU_PQ */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_2_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_3_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_4_3 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_0 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_1 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_2 */ + QUEUE_TYPE_EXT, /* GAUDI_QUEUE_ID_DMA_5_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_6_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_DMA_7_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_0_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_MME_1_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_0_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_1_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_2_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_3_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_4_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_5_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_6_3 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_0 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_1 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_2 */ + QUEUE_TYPE_INT, /* GAUDI_QUEUE_ID_TPC_7_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_0_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_1_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_2_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_3_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_4_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_5_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_6_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_7_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_8_3 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_0 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_1 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_2 */ + QUEUE_TYPE_NA, /* GAUDI_QUEUE_ID_NIC_9_3 */ +}; + +static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid, + u64 phys_addr); +static int gaudi_send_job_on_qman0(struct hl_device *hdev, + struct hl_cs_job *job); +static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, + u32 size, u64 val); +static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel, + u32 tpc_id); +static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev); +static int gaudi_armcp_info_get(struct hl_device *hdev); +static void gaudi_disable_clock_gating(struct hl_device *hdev); +static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid); + +static int gaudi_get_fixed_properties(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + int i; + + if (GAUDI_QUEUE_ID_SIZE >= HL_MAX_QUEUES) { + dev_err(hdev->dev, + "Number of H/W queues must be smaller than %d\n", + HL_MAX_QUEUES); + return -EFAULT; + } + + for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) { + if (gaudi_queue_type[i] == QUEUE_TYPE_EXT) { + prop->hw_queues_props[i].type = QUEUE_TYPE_EXT; + prop->hw_queues_props[i].driver_only = 0; + prop->hw_queues_props[i].requires_kernel_cb = 1; + } else if (gaudi_queue_type[i] == QUEUE_TYPE_CPU) { + prop->hw_queues_props[i].type = QUEUE_TYPE_CPU; + prop->hw_queues_props[i].driver_only = 1; + prop->hw_queues_props[i].requires_kernel_cb = 0; + } else if (gaudi_queue_type[i] == QUEUE_TYPE_INT) { + prop->hw_queues_props[i].type = QUEUE_TYPE_INT; + prop->hw_queues_props[i].driver_only = 0; + prop->hw_queues_props[i].requires_kernel_cb = 0; + } else if (gaudi_queue_type[i] == QUEUE_TYPE_NA) { + prop->hw_queues_props[i].type = QUEUE_TYPE_NA; + prop->hw_queues_props[i].driver_only = 0; + prop->hw_queues_props[i].requires_kernel_cb = 0; + } + } + + for (; i < HL_MAX_QUEUES; i++) + prop->hw_queues_props[i].type = QUEUE_TYPE_NA; + + prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES; + + prop->dram_base_address = DRAM_PHYS_BASE; + prop->dram_size = GAUDI_HBM_SIZE_32GB; + prop->dram_end_address = prop->dram_base_address + + prop->dram_size; + prop->dram_user_base_address = DRAM_BASE_ADDR_USER; + + prop->sram_base_address = SRAM_BASE_ADDR; + prop->sram_size = SRAM_SIZE; + prop->sram_end_address = prop->sram_base_address + + prop->sram_size; + prop->sram_user_base_address = prop->sram_base_address + + SRAM_USER_BASE_OFFSET; + + prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR; + if (hdev->pldm) + prop->mmu_pgt_size = 0x800000; /* 8MB */ + else + prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE; + prop->mmu_pte_size = HL_PTE_SIZE; + prop->mmu_hop_table_size = HOP_TABLE_SIZE; + prop->mmu_hop0_tables_total_size = HOP0_TABLES_TOTAL_SIZE; + prop->dram_page_size = PAGE_SIZE_2MB; + + prop->pmmu.hop0_shift = HOP0_SHIFT; + prop->pmmu.hop1_shift = HOP1_SHIFT; + prop->pmmu.hop2_shift = HOP2_SHIFT; + prop->pmmu.hop3_shift = HOP3_SHIFT; + prop->pmmu.hop4_shift = HOP4_SHIFT; + prop->pmmu.hop0_mask = HOP0_MASK; + prop->pmmu.hop1_mask = HOP1_MASK; + prop->pmmu.hop2_mask = HOP2_MASK; + prop->pmmu.hop3_mask = HOP3_MASK; + prop->pmmu.hop4_mask = HOP4_MASK; + prop->pmmu.start_addr = VA_HOST_SPACE_START; + prop->pmmu.end_addr = + (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2) - 1; + prop->pmmu.page_size = PAGE_SIZE_4KB; + + /* PMMU and HPMMU are the same except of page size */ + memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); + prop->pmmu_huge.page_size = PAGE_SIZE_2MB; + + /* shifts and masks are the same in PMMU and DMMU */ + memcpy(&prop->dmmu, &prop->pmmu, sizeof(prop->pmmu)); + prop->dmmu.start_addr = (VA_HOST_SPACE_START + VA_HOST_SPACE_SIZE / 2); + prop->dmmu.end_addr = VA_HOST_SPACE_END; + prop->dmmu.page_size = PAGE_SIZE_2MB; + + prop->cfg_size = CFG_SIZE; + prop->max_asid = MAX_ASID; + prop->num_of_events = GAUDI_EVENT_SIZE; + prop->tpc_enabled_mask = TPC_ENABLED_MASK; + + prop->max_power_default = MAX_POWER_DEFAULT; + + prop->cb_pool_cb_cnt = GAUDI_CB_POOL_CB_CNT; + prop->cb_pool_cb_size = GAUDI_CB_POOL_CB_SIZE; + + prop->pcie_dbi_base_address = mmPCIE_DBI_BASE; + prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; + + strncpy(prop->armcp_info.card_name, GAUDI_DEFAULT_CARD_NAME, + CARD_NAME_MAX_LEN); + + return 0; +} + +static int gaudi_pci_bars_map(struct hl_device *hdev) +{ + static const char * const name[] = {"SRAM", "CFG", "HBM"}; + bool is_wc[3] = {false, false, true}; + int rc; + + rc = hl_pci_bars_map(hdev, name, is_wc); + if (rc) + return rc; + + hdev->rmmio = hdev->pcie_bar[CFG_BAR_ID] + + (CFG_BASE - SPI_FLASH_BASE_ADDR); + + return 0; +} + +static u64 gaudi_set_hbm_bar_base(struct hl_device *hdev, u64 addr) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u64 old_addr = addr; + int rc; + + if ((gaudi) && (gaudi->hbm_bar_cur_addr == addr)) + return old_addr; + + /* Inbound Region 2 - Bar 4 - Point to HBM */ + rc = hl_pci_set_dram_bar_base(hdev, 2, 4, addr); + if (rc) + return U64_MAX; + + if (gaudi) { + old_addr = gaudi->hbm_bar_cur_addr; + gaudi->hbm_bar_cur_addr = addr; + } + + return old_addr; +} + +static int gaudi_init_iatu(struct hl_device *hdev) +{ + int rc = 0; + + /* Inbound Region 1 - Bar 2 - Point to SPI FLASH */ + rc = hl_pci_iatu_write(hdev, 0x314, + lower_32_bits(SPI_FLASH_BASE_ADDR)); + rc |= hl_pci_iatu_write(hdev, 0x318, + upper_32_bits(SPI_FLASH_BASE_ADDR)); + rc |= hl_pci_iatu_write(hdev, 0x300, 0); + /* Enable + Bar match + match enable */ + rc |= hl_pci_iatu_write(hdev, 0x304, 0xC0080200); + + if (rc) + return -EIO; + + return hl_pci_init_iatu(hdev, SRAM_BASE_ADDR, DRAM_PHYS_BASE, + HOST_PHYS_BASE, HOST_PHYS_SIZE); +} + +static int gaudi_early_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct pci_dev *pdev = hdev->pdev; + int rc; + + rc = gaudi_get_fixed_properties(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to get fixed properties\n"); + return rc; + } + + /* Check BAR sizes */ + if (pci_resource_len(pdev, SRAM_BAR_ID) != SRAM_BAR_SIZE) { + dev_err(hdev->dev, + "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", + SRAM_BAR_ID, + (unsigned long long) pci_resource_len(pdev, + SRAM_BAR_ID), + SRAM_BAR_SIZE); + return -ENODEV; + } + + if (pci_resource_len(pdev, CFG_BAR_ID) != CFG_BAR_SIZE) { + dev_err(hdev->dev, + "Not " HL_NAME "? BAR %d size %llu, expecting %llu\n", + CFG_BAR_ID, + (unsigned long long) pci_resource_len(pdev, + CFG_BAR_ID), + CFG_BAR_SIZE); + return -ENODEV; + } + + prop->dram_pci_bar_size = pci_resource_len(pdev, HBM_BAR_ID); + + rc = hl_pci_init(hdev); + if (rc) + return rc; + + return 0; +} + +static int gaudi_early_fini(struct hl_device *hdev) +{ + hl_pci_fini(hdev); + + return 0; +} + +/** + * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values + * + * @hdev: pointer to hl_device structure + * + */ +static void gaudi_fetch_psoc_frequency(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + + prop->psoc_pci_pll_nr = RREG32(mmPSOC_PCI_PLL_NR); + prop->psoc_pci_pll_nf = RREG32(mmPSOC_PCI_PLL_NF); + prop->psoc_pci_pll_od = RREG32(mmPSOC_PCI_PLL_OD); + prop->psoc_pci_pll_div_factor = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1); +} + +static int _gaudi_init_tpc_mem(struct hl_device *hdev, + dma_addr_t tpc_kernel_src_addr, u32 tpc_kernel_size) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct packet_lin_dma *init_tpc_mem_pkt; + struct hl_cs_job *job; + struct hl_cb *cb; + u64 dst_addr; + u32 cb_size, ctl; + u8 tpc_id; + int rc; + + cb = hl_cb_kernel_create(hdev, PAGE_SIZE); + if (!cb) + return -EFAULT; + + init_tpc_mem_pkt = (struct packet_lin_dma *) (uintptr_t) + cb->kernel_address; + cb_size = sizeof(*init_tpc_mem_pkt); + memset(init_tpc_mem_pkt, 0, cb_size); + + init_tpc_mem_pkt->tsize = cpu_to_le32(tpc_kernel_size); + + ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) | + (1 << GAUDI_PKT_CTL_RB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT)); + + init_tpc_mem_pkt->ctl = cpu_to_le32(ctl); + + init_tpc_mem_pkt->src_addr = cpu_to_le64(tpc_kernel_src_addr); + dst_addr = (prop->sram_user_base_address & + GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >> + GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT; + init_tpc_mem_pkt->dst_addr |= cpu_to_le64(dst_addr); + + job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + goto release_cb; + } + + job->id = 0; + job->user_cb = cb; + job->user_cb->cs_cnt++; + job->user_cb_size = cb_size; + job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0; + job->patched_cb = job->user_cb; + job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot); + + hl_debugfs_add_job(hdev, job); + + rc = gaudi_send_job_on_qman0(hdev, job); + + if (rc) + goto free_job; + + for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) { + rc = gaudi_run_tpc_kernel(hdev, dst_addr, tpc_id); + if (rc) + break; + } + +free_job: + hl_userptr_delete_list(hdev, &job->userptr_list); + hl_debugfs_remove_job(hdev, job); + kfree(job); + cb->cs_cnt--; + +release_cb: + hl_cb_put(cb); + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT); + + return rc; +} + +/* + * gaudi_init_tpc_mem() - Initialize TPC memories. + * @hdev: Pointer to hl_device structure. + * + * Copy TPC kernel fw from firmware file and run it to initialize TPC memories. + * + * Return: 0 for success, negative value for error. + */ +static int gaudi_init_tpc_mem(struct hl_device *hdev) +{ + const struct firmware *fw; + size_t fw_size; + void *cpu_addr; + dma_addr_t dma_handle; + int rc; + + rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev); + if (rc) { + dev_err(hdev->dev, "Firmware file %s is not found!\n", + GAUDI_TPC_FW_FILE); + goto out; + } + + fw_size = fw->size; + cpu_addr = hdev->asic_funcs->asic_dma_alloc_coherent(hdev, fw_size, + &dma_handle, GFP_KERNEL | __GFP_ZERO); + if (!cpu_addr) { + dev_err(hdev->dev, + "Failed to allocate %zu of dma memory for TPC kernel\n", + fw_size); + rc = -ENOMEM; + goto out; + } + + memcpy(cpu_addr, fw->data, fw_size); + + rc = _gaudi_init_tpc_mem(hdev, dma_handle, fw_size); + + hdev->asic_funcs->asic_dma_free_coherent(hdev, fw->size, cpu_addr, + dma_handle); + +out: + release_firmware(fw); + return rc; +} + +static int gaudi_late_init(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + + rc = gaudi->armcp_info_get(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to get armcp info\n"); + return rc; + } + + rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_ENABLE_PCI_ACCESS); + if (rc) { + dev_err(hdev->dev, "Failed to enable PCI access from CPU\n"); + return rc; + } + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER); + + gaudi_fetch_psoc_frequency(hdev); + + rc = gaudi_mmu_clear_pgt_range(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to clear MMU page tables range\n"); + goto disable_pci_access; + } + + rc = gaudi_init_tpc_mem(hdev); + if (rc) { + dev_err(hdev->dev, "Failed to initialize TPC memories\n"); + goto disable_pci_access; + } + + return 0; + +disable_pci_access: + hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + + return rc; +} + +static void gaudi_late_fini(struct hl_device *hdev) +{ + const struct hwmon_channel_info **channel_info_arr; + int i = 0; + + if (!hdev->hl_chip_info->info) + return; + + channel_info_arr = hdev->hl_chip_info->info; + + while (channel_info_arr[i]) { + kfree(channel_info_arr[i]->config); + kfree(channel_info_arr[i]); + i++; + } + + kfree(channel_info_arr); + + hdev->hl_chip_info->info = NULL; +} + +static int gaudi_alloc_cpu_accessible_dma_mem(struct hl_device *hdev) +{ + dma_addr_t dma_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {}, end_addr; + void *virt_addr_arr[GAUDI_ALLOC_CPU_MEM_RETRY_CNT] = {}; + int i, j, rc = 0; + + /* + * The device CPU works with 40-bits addresses, while bit 39 must be set + * to '1' when accessing the host. + * Bits 49:39 of the full host address are saved for a later + * configuration of the HW to perform extension to 50 bits. + * Because there is a single HW register that holds the extension bits, + * these bits must be identical in all allocated range. + */ + + for (i = 0 ; i < GAUDI_ALLOC_CPU_MEM_RETRY_CNT ; i++) { + virt_addr_arr[i] = + hdev->asic_funcs->asic_dma_alloc_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + &dma_addr_arr[i], + GFP_KERNEL | __GFP_ZERO); + if (!virt_addr_arr[i]) { + rc = -ENOMEM; + goto free_dma_mem_arr; + } + + end_addr = dma_addr_arr[i] + HL_CPU_ACCESSIBLE_MEM_SIZE - 1; + if (GAUDI_CPU_PCI_MSB_ADDR(dma_addr_arr[i]) == + GAUDI_CPU_PCI_MSB_ADDR(end_addr)) + break; + } + + if (i == GAUDI_ALLOC_CPU_MEM_RETRY_CNT) { + dev_err(hdev->dev, + "MSB of CPU accessible DMA memory are not identical in all range\n"); + rc = -EFAULT; + goto free_dma_mem_arr; + } + + hdev->cpu_accessible_dma_mem = virt_addr_arr[i]; + hdev->cpu_accessible_dma_address = dma_addr_arr[i]; + hdev->cpu_pci_msb_addr = + GAUDI_CPU_PCI_MSB_ADDR(hdev->cpu_accessible_dma_address); + + GAUDI_PCI_TO_CPU_ADDR(hdev->cpu_accessible_dma_address); + +free_dma_mem_arr: + for (j = 0 ; j < i ; j++) + hdev->asic_funcs->asic_dma_free_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + virt_addr_arr[j], + dma_addr_arr[j]); + + return rc; +} + +static void gaudi_free_internal_qmans_pq_mem(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u32 i; + + for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) { + q = &gaudi->internal_qmans[i]; + if (!q->pq_kernel_addr) + continue; + hdev->asic_funcs->asic_dma_free_coherent(hdev, q->pq_size, + q->pq_kernel_addr, + q->pq_dma_addr); + } +} + +static int gaudi_alloc_internal_qmans_pq_mem(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + int rc, i; + + for (i = 0 ; i < GAUDI_QUEUE_ID_SIZE ; i++) { + if (gaudi_queue_type[i] != QUEUE_TYPE_INT) + continue; + + q = &gaudi->internal_qmans[i]; + + switch (i) { + case GAUDI_QUEUE_ID_DMA_2_0 ... GAUDI_QUEUE_ID_DMA_4_3: + case GAUDI_QUEUE_ID_DMA_6_0 ... GAUDI_QUEUE_ID_DMA_7_3: + q->pq_size = HBM_DMA_QMAN_SIZE_IN_BYTES; + break; + case GAUDI_QUEUE_ID_MME_0_0 ... GAUDI_QUEUE_ID_MME_1_3: + q->pq_size = MME_QMAN_SIZE_IN_BYTES; + break; + case GAUDI_QUEUE_ID_TPC_0_0 ... GAUDI_QUEUE_ID_TPC_7_3: + q->pq_size = TPC_QMAN_SIZE_IN_BYTES; + break; + default: + dev_err(hdev->dev, "Bad internal queue index %d", i); + rc = -EINVAL; + goto free_internal_qmans_pq_mem; + } + + q->pq_kernel_addr = hdev->asic_funcs->asic_dma_alloc_coherent( + hdev, q->pq_size, + &q->pq_dma_addr, + GFP_KERNEL | __GFP_ZERO); + if (!q->pq_kernel_addr) { + rc = -ENOMEM; + goto free_internal_qmans_pq_mem; + } + } + + return 0; + +free_internal_qmans_pq_mem: + gaudi_free_internal_qmans_pq_mem(hdev); + return rc; +} + +static int gaudi_sw_init(struct hl_device *hdev) +{ + struct gaudi_device *gaudi; + u32 i, event_id = 0; + int rc; + + /* Allocate device structure */ + gaudi = kzalloc(sizeof(*gaudi), GFP_KERNEL); + if (!gaudi) + return -ENOMEM; + + for (i = 0 ; i < ARRAY_SIZE(gaudi_irq_map_table) ; i++) { + if (gaudi_irq_map_table[i].valid) { + if (event_id == GAUDI_EVENT_SIZE) { + dev_err(hdev->dev, + "Event array exceeds the limit of %u events\n", + GAUDI_EVENT_SIZE); + rc = -EINVAL; + goto free_gaudi_device; + } + + gaudi->events[event_id++] = + gaudi_irq_map_table[i].fc_id; + } + } + + gaudi->armcp_info_get = gaudi_armcp_info_get; + + gaudi->max_freq_value = GAUDI_MAX_CLK_FREQ; + + hdev->asic_specific = gaudi; + + /* Create DMA pool for small allocations */ + hdev->dma_pool = dma_pool_create(dev_name(hdev->dev), + &hdev->pdev->dev, GAUDI_DMA_POOL_BLK_SIZE, 8, 0); + if (!hdev->dma_pool) { + dev_err(hdev->dev, "failed to create DMA pool\n"); + rc = -ENOMEM; + goto free_gaudi_device; + } + + rc = gaudi_alloc_cpu_accessible_dma_mem(hdev); + if (rc) + goto free_dma_pool; + + hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1); + if (!hdev->cpu_accessible_dma_pool) { + dev_err(hdev->dev, + "Failed to create CPU accessible DMA pool\n"); + rc = -ENOMEM; + goto free_cpu_dma_mem; + } + + rc = gen_pool_add(hdev->cpu_accessible_dma_pool, + (uintptr_t) hdev->cpu_accessible_dma_mem, + HL_CPU_ACCESSIBLE_MEM_SIZE, -1); + if (rc) { + dev_err(hdev->dev, + "Failed to add memory to CPU accessible DMA pool\n"); + rc = -EFAULT; + goto free_cpu_accessible_dma_pool; + } + + rc = gaudi_alloc_internal_qmans_pq_mem(hdev); + if (rc) + goto free_cpu_accessible_dma_pool; + + spin_lock_init(&gaudi->hw_queues_lock); + mutex_init(&gaudi->clk_gate_mutex); + + hdev->supports_sync_stream = true; + hdev->supports_coresight = true; + + return 0; + +free_cpu_accessible_dma_pool: + gen_pool_destroy(hdev->cpu_accessible_dma_pool); +free_cpu_dma_mem: + GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address, + hdev->cpu_pci_msb_addr); + hdev->asic_funcs->asic_dma_free_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); +free_dma_pool: + dma_pool_destroy(hdev->dma_pool); +free_gaudi_device: + kfree(gaudi); + return rc; +} + +static int gaudi_sw_fini(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + gaudi_free_internal_qmans_pq_mem(hdev); + + gen_pool_destroy(hdev->cpu_accessible_dma_pool); + + GAUDI_CPU_TO_PCI_ADDR(hdev->cpu_accessible_dma_address, + hdev->cpu_pci_msb_addr); + hdev->asic_funcs->asic_dma_free_coherent(hdev, + HL_CPU_ACCESSIBLE_MEM_SIZE, + hdev->cpu_accessible_dma_mem, + hdev->cpu_accessible_dma_address); + + dma_pool_destroy(hdev->dma_pool); + + mutex_destroy(&gaudi->clk_gate_mutex); + + kfree(gaudi); + + return 0; +} + +static irqreturn_t gaudi_irq_handler_single(int irq, void *arg) +{ + struct hl_device *hdev = arg; + int i; + + if (hdev->disabled) + return IRQ_HANDLED; + + for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) + hl_irq_handler_cq(irq, &hdev->completion_queue[i]); + + hl_irq_handler_eq(irq, &hdev->event_queue); + + return IRQ_HANDLED; +} + +/* + * For backward compatibility, new MSI interrupts should be set after the + * existing CPU and NIC interrupts. + */ +static int gaudi_pci_irq_vector(struct hl_device *hdev, unsigned int nr, + bool cpu_eq) +{ + int msi_vec; + + if ((nr != GAUDI_EVENT_QUEUE_MSI_IDX) && (cpu_eq)) + dev_crit(hdev->dev, "CPU EQ must use IRQ %d\n", + GAUDI_EVENT_QUEUE_MSI_IDX); + + msi_vec = ((nr < GAUDI_EVENT_QUEUE_MSI_IDX) || (cpu_eq)) ? nr : + (nr + NIC_NUMBER_OF_ENGINES + 1); + + return pci_irq_vector(hdev->pdev, msi_vec); +} + +static int gaudi_enable_msi_single(struct hl_device *hdev) +{ + int rc, irq; + + dev_info(hdev->dev, "Working in single MSI IRQ mode\n"); + + irq = gaudi_pci_irq_vector(hdev, 0, false); + rc = request_irq(irq, gaudi_irq_handler_single, 0, + "gaudi single msi", hdev); + if (rc) + dev_err(hdev->dev, + "Failed to request single MSI IRQ\n"); + + return rc; +} + +static int gaudi_enable_msi_multi(struct hl_device *hdev) +{ + int cq_cnt = hdev->asic_prop.completion_queues_count; + int rc, i, irq_cnt_init, irq; + + for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) { + irq = gaudi_pci_irq_vector(hdev, i, false); + rc = request_irq(irq, hl_irq_handler_cq, 0, gaudi_irq_name[i], + &hdev->completion_queue[i]); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_irqs; + } + } + + irq = gaudi_pci_irq_vector(hdev, GAUDI_EVENT_QUEUE_MSI_IDX, true); + rc = request_irq(irq, hl_irq_handler_eq, 0, gaudi_irq_name[cq_cnt], + &hdev->event_queue); + if (rc) { + dev_err(hdev->dev, "Failed to request IRQ %d", irq); + goto free_irqs; + } + + return 0; + +free_irqs: + for (i = 0 ; i < irq_cnt_init ; i++) + free_irq(gaudi_pci_irq_vector(hdev, i, false), + &hdev->completion_queue[i]); + return rc; +} + +static int gaudi_enable_msi(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + + if (gaudi->hw_cap_initialized & HW_CAP_MSI) + return 0; + + rc = pci_alloc_irq_vectors(hdev->pdev, 1, GAUDI_MSI_ENTRIES, + PCI_IRQ_MSI); + if (rc < 0) { + dev_err(hdev->dev, "MSI: Failed to enable support %d\n", rc); + return rc; + } + + if (rc < NUMBER_OF_INTERRUPTS) { + gaudi->multi_msi_mode = false; + rc = gaudi_enable_msi_single(hdev); + } else { + gaudi->multi_msi_mode = true; + rc = gaudi_enable_msi_multi(hdev); + } + + if (rc) + goto free_pci_irq_vectors; + + gaudi->hw_cap_initialized |= HW_CAP_MSI; + + return 0; + +free_pci_irq_vectors: + pci_free_irq_vectors(hdev->pdev); + return rc; +} + +static void gaudi_sync_irqs(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int i, cq_cnt = hdev->asic_prop.completion_queues_count; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MSI)) + return; + + /* Wait for all pending IRQs to be finished */ + if (gaudi->multi_msi_mode) { + for (i = 0 ; i < cq_cnt ; i++) + synchronize_irq(gaudi_pci_irq_vector(hdev, i, false)); + + synchronize_irq(gaudi_pci_irq_vector(hdev, + GAUDI_EVENT_QUEUE_MSI_IDX, + true)); + } else { + synchronize_irq(gaudi_pci_irq_vector(hdev, 0, false)); + } +} + +static void gaudi_disable_msi(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int i, irq, cq_cnt = hdev->asic_prop.completion_queues_count; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MSI)) + return; + + gaudi_sync_irqs(hdev); + + if (gaudi->multi_msi_mode) { + irq = gaudi_pci_irq_vector(hdev, GAUDI_EVENT_QUEUE_MSI_IDX, + true); + free_irq(irq, &hdev->event_queue); + + for (i = 0 ; i < cq_cnt ; i++) { + irq = gaudi_pci_irq_vector(hdev, i, false); + free_irq(irq, &hdev->completion_queue[i]); + } + } else { + free_irq(gaudi_pci_irq_vector(hdev, 0, false), hdev); + } + + pci_free_irq_vectors(hdev->pdev); + + gaudi->hw_cap_initialized &= ~HW_CAP_MSI; +} + +static void gaudi_init_scrambler_sram(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (gaudi->hw_cap_initialized & HW_CAP_SRAM_SCRAMBLER) + return; + + if (!hdev->sram_scrambler_enable) + return; + + WREG32(mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN, + 1 << IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT); + + gaudi->hw_cap_initialized |= HW_CAP_SRAM_SCRAMBLER; +} + +static void gaudi_init_scrambler_hbm(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (gaudi->hw_cap_initialized & HW_CAP_HBM_SCRAMBLER) + return; + + if (!hdev->dram_scrambler_enable) + return; + + WREG32(mmNIF_RTR_CTRL_0_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_1_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_2_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_3_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_4_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_5_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_6_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_7_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_0_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_1_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_2_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_3_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_4_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_5_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_6_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_7_SCRAM_HBM_EN, + 1 << IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN, + 1 << DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT); + + gaudi->hw_cap_initialized |= HW_CAP_HBM_SCRAMBLER; +} + +static void gaudi_init_e2e(struct hl_device *hdev) +{ + WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 247 >> 3); + WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 785 >> 3); + WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 49); + WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 101); + + WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39); + + WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19); + WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19); + WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32); + + WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1); + WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39); + + WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 297 >> 3); + WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 908 >> 3); + WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 19); + WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 19); + + WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE, 318 >> 3); + WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE, 956 >> 3); + WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE, 79); + WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE, 163); + + WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE, 39); + + WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE, 19); + WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE, 176 >> 3); + WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE, 32 >> 3); + WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE, 19); + WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE, 32); + + WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE, 275 >> 3); + WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE, 614 >> 3); + WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE, 1); + WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE, 39); + + WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE, 318 >> 3); + WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE, 956 >> 3); + WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE, 79); + WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE, 79); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE, 338); + + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE, 344 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE, 1000 >> 3); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE, 162); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE, 338); + + if (!hdev->dram_scrambler_enable) { + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21); + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22); + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_0, 0x21); + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_SEL_1, 0x22); + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3, 0x20); + + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0, 0x21); + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1, 0x22); + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18, 0x1F); + WREG32(mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3, 0x20); + } + + WREG32(mmSIF_RTR_CTRL_0_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_0_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_1_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_1_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_2_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_2_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_3_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_3_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_4_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_4_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_5_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_5_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_6_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_6_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmSIF_RTR_CTRL_7_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmSIF_RTR_CTRL_7_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_0_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_0_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_1_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_1_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_2_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_2_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_3_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_3_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_4_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_4_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_5_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_5_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_6_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_6_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmNIF_RTR_CTRL_7_E2E_HBM_EN, + 1 << IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmNIF_RTR_CTRL_7_E2E_PCI_EN, + 1 << IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); + + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN, + 1 << DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT); + WREG32(mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN, + 1 << DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT); +} + +static void gaudi_init_hbm_cred(struct hl_device *hdev) +{ + uint32_t hbm0_wr, hbm1_wr, hbm0_rd, hbm1_rd; + + hbm0_wr = 0x33333333; + hbm1_wr = 0x33333333; + hbm0_rd = 0x77777777; + hbm1_rd = 0xDDDDDDDD; + + WREG32(mmDMA_IF_E_N_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_E_N_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_E_N_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_E_N_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_E_S_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_E_S_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_E_S_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_E_S_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_W_N_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_W_N_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_W_N_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_W_N_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_W_S_HBM0_WR_CRED_CNT, hbm0_wr); + WREG32(mmDMA_IF_W_S_HBM1_WR_CRED_CNT, hbm1_wr); + WREG32(mmDMA_IF_W_S_HBM0_RD_CRED_CNT, hbm0_rd); + WREG32(mmDMA_IF_W_S_HBM1_RD_CRED_CNT, hbm1_rd); + + WREG32(mmDMA_IF_E_N_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_E_S_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_N_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_S_HBM_CRED_EN_0, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + + WREG32(mmDMA_IF_E_N_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_E_S_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_N_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); + WREG32(mmDMA_IF_W_S_HBM_CRED_EN_1, + (1 << DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT) | + (1 << DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT)); +} + +static void gaudi_init_rate_limiter(struct hl_device *hdev) +{ + u32 nr, nf, od, sat, rst, timeout; + u64 freq; + + nr = RREG32(mmPSOC_HBM_PLL_NR); + nf = RREG32(mmPSOC_HBM_PLL_NF); + od = RREG32(mmPSOC_HBM_PLL_OD); + freq = (50 * (nf + 1)) / ((nr + 1) * (od + 1)); + + dev_dbg(hdev->dev, "HBM frequency is %lluMHz\n", freq); + + /* Configuration is for five (5) DDMA channels */ + if (freq == 800) { + sat = 4; + rst = 11; + timeout = 15; + } else if (freq == 900) { + sat = 4; + rst = 15; + timeout = 16; + } else if (freq == 950) { + sat = 4; + rst = 15; + timeout = 15; + } else { + dev_warn(hdev->dev, + "unsupported HBM frequency %lluMHz, no rate-limiters\n", + freq); + return; + } + + WREG32(mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1, 0x111); + WREG32(mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1, 0x111); + WREG32(mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1, 0x111); + WREG32(mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0, 0x111); + WREG32(mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1, 0x111); + + if (!hdev->rl_enable) { + dev_info(hdev->dev, "Rate limiters disabled\n"); + return; + } + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT, sat); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST, rst); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT, timeout); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_HBM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN, 1); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_SAT, sat); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT, sat); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RST, rst); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST, rst); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_TIMEOUT, timeout); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT, timeout); + + WREG32(mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_EN, 1); + WREG32(mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN, 1); +} + +static void gaudi_init_golden_registers(struct hl_device *hdev) +{ + u32 tpc_offset; + int tpc_id, i; + + gaudi_init_e2e(hdev); + + gaudi_init_hbm_cred(hdev); + + gaudi_init_rate_limiter(hdev); + + gaudi_disable_clock_gating(hdev); + + for (tpc_id = 0, tpc_offset = 0; + tpc_id < TPC_NUMBER_OF_ENGINES; + tpc_id++, tpc_offset += TPC_CFG_OFFSET) { + /* Mask all arithmetic interrupts from TPC */ + WREG32(mmTPC0_CFG_TPC_INTR_MASK + tpc_offset, 0x8FFF); + /* Set 16 cache lines */ + WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset, + ICACHE_FETCH_LINE_NUM, 2); + } + + /* Make sure 1st 128 bytes in SRAM are 0 for Tensor DMA */ + for (i = 0 ; i < 128 ; i += 8) + writeq(0, hdev->pcie_bar[SRAM_BAR_ID] + i); + + WREG32(mmMME0_CTRL_EUS_ROLLUP_CNT_ADD, 3); + WREG32(mmMME1_CTRL_EUS_ROLLUP_CNT_ADD, 3); + WREG32(mmMME2_CTRL_EUS_ROLLUP_CNT_ADD, 3); + WREG32(mmMME3_CTRL_EUS_ROLLUP_CNT_ADD, 3); + + /* WA for H3-2081 */ + WREG32(mmPCIE_WRAP_MAX_OUTSTAND, 0x10ff); +} + +static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id, + int qman_id, dma_addr_t qman_pq_addr) +{ + u32 mtr_base_en_lo, mtr_base_en_hi, mtr_base_ws_lo, mtr_base_ws_hi; + u32 so_base_en_lo, so_base_en_hi, so_base_ws_lo, so_base_ws_hi; + u32 q_off, dma_qm_offset; + u32 dma_qm_err_cfg; + + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + + mtr_base_en_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_en_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_en_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_en_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + mtr_base_ws_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_ws_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_ws_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_ws_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = dma_qm_offset + qman_id * 4; + + WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, lower_32_bits(qman_pq_addr)); + WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, upper_32_bits(qman_pq_addr)); + + WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HL_QUEUE_LENGTH)); + WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_en_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_en_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_en_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_en_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 + q_off, mtr_base_ws_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 + q_off, mtr_base_ws_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi); + + /* The following configuration is needed only once per QMAN */ + if (qman_id == 0) { + /* Configure RAZWI IRQ */ + dma_qm_err_cfg = PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + dma_qm_err_cfg |= + PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + + WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg); + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset, + gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id + + dma_id); + + WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset, + QMAN_EXTERNAL_MAKE_TRUSTED); + + WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0); + } +} + +static void gaudi_init_dma_core(struct hl_device *hdev, int dma_id) +{ + u32 dma_offset = dma_id * DMA_CORE_OFFSET; + u32 dma_err_cfg = 1 << DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT; + + /* Set to maximum possible according to physical size */ + WREG32(mmDMA0_CORE_RD_MAX_OUTSTAND + dma_offset, 0); + WREG32(mmDMA0_CORE_RD_MAX_SIZE + dma_offset, 0); + + /* STOP_ON bit implies no completion to operation in case of RAZWI */ + if (hdev->stop_on_err) + dma_err_cfg |= 1 << DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT; + + WREG32(mmDMA0_CORE_ERR_CFG + dma_offset, dma_err_cfg); + WREG32(mmDMA0_CORE_ERRMSG_ADDR_LO + dma_offset, + lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_CORE_ERRMSG_ADDR_HI + dma_offset, + upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_CORE_ERRMSG_WDATA + dma_offset, + gaudi_irq_map_table[GAUDI_EVENT_DMA0_CORE].cpu_id + dma_id); + WREG32(mmDMA0_CORE_PROT + dma_offset, + 1 << DMA0_CORE_PROT_ERR_VAL_SHIFT); + /* If the channel is secured, it should be in MMU bypass mode */ + WREG32(mmDMA0_CORE_SECURE_PROPS + dma_offset, + 1 << DMA0_CORE_SECURE_PROPS_MMBP_SHIFT); + WREG32(mmDMA0_CORE_CFG_0 + dma_offset, 1 << DMA0_CORE_CFG_0_EN_SHIFT); +} + +static void gaudi_enable_qman(struct hl_device *hdev, int dma_id, + u32 enable_mask) +{ + u32 dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + + WREG32(mmDMA0_QM_GLBL_CFG0 + dma_qm_offset, enable_mask); +} + +static void gaudi_init_pci_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct hl_hw_queue *q; + int i, j, dma_id, cpu_skip, nic_skip, cq_id = 0, q_idx, msi_vec = 0; + + if (gaudi->hw_cap_initialized & HW_CAP_PCI_DMA) + return; + + for (i = 0 ; i < PCI_DMA_NUMBER_OF_CHNLS ; i++) { + dma_id = gaudi_dma_assignment[i]; + /* + * For queues after the CPU Q need to add 1 to get the correct + * queue. In addition, need to add the CPU EQ and NIC IRQs in + * order to get the correct MSI register. + */ + if (dma_id > 1) { + cpu_skip = 1; + nic_skip = NIC_NUMBER_OF_ENGINES; + } else { + cpu_skip = 0; + nic_skip = 0; + } + + for (j = 0 ; j < QMAN_STREAMS ; j++) { + q_idx = 4 * dma_id + j + cpu_skip; + q = &hdev->kernel_queues[q_idx]; + q->cq_id = cq_id++; + q->msi_vec = nic_skip + cpu_skip + msi_vec++; + gaudi_init_pci_dma_qman(hdev, dma_id, j, + q->bus_address); + } + + gaudi_init_dma_core(hdev, dma_id); + + gaudi_enable_qman(hdev, dma_id, PCI_DMA_QMAN_ENABLE); + } + + gaudi->hw_cap_initialized |= HW_CAP_PCI_DMA; +} + +static void gaudi_init_hbm_dma_qman(struct hl_device *hdev, int dma_id, + int qman_id, u64 qman_base_addr) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 q_off, dma_qm_offset; + u32 dma_qm_err_cfg; + + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + + mtr_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = dma_qm_offset + qman_id * 4; + + if (qman_id < 4) { + WREG32(mmDMA0_QM_PQ_BASE_LO_0 + q_off, + lower_32_bits(qman_base_addr)); + WREG32(mmDMA0_QM_PQ_BASE_HI_0 + q_off, + upper_32_bits(qman_base_addr)); + + WREG32(mmDMA0_QM_PQ_SIZE_0 + q_off, ilog2(HBM_DMA_QMAN_LENGTH)); + WREG32(mmDMA0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmDMA0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC); + WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4); + WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + } else { + WREG32(mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + /* Configure RAZWI IRQ */ + dma_qm_err_cfg = HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + dma_qm_err_cfg |= + HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + WREG32(mmDMA0_QM_GLBL_ERR_CFG + dma_qm_offset, dma_qm_err_cfg); + + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_LO + dma_qm_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_ADDR_HI + dma_qm_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmDMA0_QM_GLBL_ERR_WDATA + dma_qm_offset, + gaudi_irq_map_table[GAUDI_EVENT_DMA0_QM].cpu_id + + dma_id); + + WREG32(mmDMA0_QM_ARB_ERR_MSG_EN + dma_qm_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmDMA0_QM_ARB_SLV_CHOISE_WDT + dma_qm_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmDMA0_QM_GLBL_CFG1 + dma_qm_offset, 0); + WREG32(mmDMA0_QM_GLBL_PROT + dma_qm_offset, + QMAN_INTERNAL_MAKE_TRUSTED); + } + + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo); + WREG32(mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi); +} + +static void gaudi_init_hbm_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u64 qman_base_addr; + int i, j, dma_id, internal_q_index; + + if (gaudi->hw_cap_initialized & HW_CAP_HBM_DMA) + return; + + for (i = 0 ; i < HBM_DMA_NUMBER_OF_CHNLS ; i++) { + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1 + i]; + + for (j = 0 ; j < QMAN_STREAMS ; j++) { + /* + * Add the CPU queue in order to get the correct queue + * number as all internal queue are placed after it + */ + internal_q_index = dma_id * QMAN_STREAMS + j + 1; + + q = &gaudi->internal_qmans[internal_q_index]; + qman_base_addr = (u64) q->pq_dma_addr; + gaudi_init_hbm_dma_qman(hdev, dma_id, j, + qman_base_addr); + } + + /* Initializing lower CP for HBM DMA QMAN */ + gaudi_init_hbm_dma_qman(hdev, dma_id, 4, 0); + + gaudi_init_dma_core(hdev, dma_id); + + gaudi_enable_qman(hdev, dma_id, HBM_DMA_QMAN_ENABLE); + } + + gaudi->hw_cap_initialized |= HW_CAP_HBM_DMA; +} + +static void gaudi_init_mme_qman(struct hl_device *hdev, u32 mme_offset, + int qman_id, u64 qman_base_addr) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 q_off, mme_id; + u32 mme_qm_err_cfg; + + mtr_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = mme_offset + qman_id * 4; + + if (qman_id < 4) { + WREG32(mmMME0_QM_PQ_BASE_LO_0 + q_off, + lower_32_bits(qman_base_addr)); + WREG32(mmMME0_QM_PQ_BASE_HI_0 + q_off, + upper_32_bits(qman_base_addr)); + + WREG32(mmMME0_QM_PQ_SIZE_0 + q_off, ilog2(MME_QMAN_LENGTH)); + WREG32(mmMME0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmMME0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC); + WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4); + WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + } else { + WREG32(mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + /* Configure RAZWI IRQ */ + mme_id = mme_offset / + (mmMME1_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0); + + mme_qm_err_cfg = MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + mme_qm_err_cfg |= + MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + WREG32(mmMME0_QM_GLBL_ERR_CFG + mme_offset, mme_qm_err_cfg); + WREG32(mmMME0_QM_GLBL_ERR_ADDR_LO + mme_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmMME0_QM_GLBL_ERR_ADDR_HI + mme_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmMME0_QM_GLBL_ERR_WDATA + mme_offset, + gaudi_irq_map_table[GAUDI_EVENT_MME0_QM].cpu_id + + mme_id); + + WREG32(mmMME0_QM_ARB_ERR_MSG_EN + mme_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmMME0_QM_ARB_SLV_CHOISE_WDT + mme_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmMME0_QM_GLBL_CFG1 + mme_offset, 0); + WREG32(mmMME0_QM_GLBL_PROT + mme_offset, + QMAN_INTERNAL_MAKE_TRUSTED); + } + + WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo); + WREG32(mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi); + WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo); + WREG32(mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi); +} + +static void gaudi_init_mme_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u64 qman_base_addr; + u32 mme_offset; + int i, internal_q_index; + + if (gaudi->hw_cap_initialized & HW_CAP_MME) + return; + + /* + * map GAUDI_QUEUE_ID_MME_0_X to the N_W_MME (mmMME2_QM_BASE) + * and GAUDI_QUEUE_ID_MME_1_X to the S_W_MME (mmMME0_QM_BASE) + */ + + mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0; + + for (i = 0 ; i < MME_NUMBER_OF_QMANS ; i++) { + internal_q_index = GAUDI_QUEUE_ID_MME_0_0 + i; + q = &gaudi->internal_qmans[internal_q_index]; + qman_base_addr = (u64) q->pq_dma_addr; + gaudi_init_mme_qman(hdev, mme_offset, (i & 0x3), + qman_base_addr); + if (i == 3) + mme_offset = 0; + } + + /* Initializing lower CP for MME QMANs */ + mme_offset = mmMME2_QM_GLBL_CFG0 - mmMME0_QM_GLBL_CFG0; + gaudi_init_mme_qman(hdev, mme_offset, 4, 0); + gaudi_init_mme_qman(hdev, 0, 4, 0); + + WREG32(mmMME2_QM_GLBL_CFG0, QMAN_MME_ENABLE); + WREG32(mmMME0_QM_GLBL_CFG0, QMAN_MME_ENABLE); + + gaudi->hw_cap_initialized |= HW_CAP_MME; +} + +static void gaudi_init_tpc_qman(struct hl_device *hdev, u32 tpc_offset, + int qman_id, u64 qman_base_addr) +{ + u32 mtr_base_lo, mtr_base_hi; + u32 so_base_lo, so_base_hi; + u32 q_off, tpc_id; + u32 tpc_qm_err_cfg; + + mtr_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + mtr_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0); + so_base_lo = lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + q_off = tpc_offset + qman_id * 4; + + if (qman_id < 4) { + WREG32(mmTPC0_QM_PQ_BASE_LO_0 + q_off, + lower_32_bits(qman_base_addr)); + WREG32(mmTPC0_QM_PQ_BASE_HI_0 + q_off, + upper_32_bits(qman_base_addr)); + + WREG32(mmTPC0_QM_PQ_SIZE_0 + q_off, ilog2(TPC_QMAN_LENGTH)); + WREG32(mmTPC0_QM_PQ_PI_0 + q_off, 0); + WREG32(mmTPC0_QM_PQ_CI_0 + q_off, 0); + + WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x81BC); + WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x81B4); + WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + } else { + WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 + q_off, 0x74); + WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 + q_off, 0x14); + WREG32(mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 + q_off, 0x1C); + + /* Configure RAZWI IRQ */ + tpc_id = tpc_offset / + (mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0); + + tpc_qm_err_cfg = TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK; + if (hdev->stop_on_err) { + tpc_qm_err_cfg |= + TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK; + } + + WREG32(mmTPC0_QM_GLBL_ERR_CFG + tpc_offset, tpc_qm_err_cfg); + WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + tpc_offset, + lower_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + tpc_offset, + upper_32_bits(CFG_BASE + + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); + WREG32(mmTPC0_QM_GLBL_ERR_WDATA + tpc_offset, + gaudi_irq_map_table[GAUDI_EVENT_TPC0_QM].cpu_id + + tpc_id); + + WREG32(mmTPC0_QM_ARB_ERR_MSG_EN + tpc_offset, + QM_ARB_ERR_MSG_EN_MASK); + + /* Increase ARB WDT to support streams architecture */ + WREG32(mmTPC0_QM_ARB_SLV_CHOISE_WDT + tpc_offset, + GAUDI_ARB_WDT_TIMEOUT); + + WREG32(mmTPC0_QM_GLBL_CFG1 + tpc_offset, 0); + WREG32(mmTPC0_QM_GLBL_PROT + tpc_offset, + QMAN_INTERNAL_MAKE_TRUSTED); + } + + WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 + q_off, mtr_base_lo); + WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 + q_off, mtr_base_hi); + WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 + q_off, so_base_lo); + WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 + q_off, so_base_hi); +} + +static void gaudi_init_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + u64 qman_base_addr; + u32 so_base_hi, tpc_offset = 0; + u32 tpc_delta = mmTPC1_CFG_SM_BASE_ADDRESS_HIGH - + mmTPC0_CFG_SM_BASE_ADDRESS_HIGH; + int i, tpc_id, internal_q_index; + + if (gaudi->hw_cap_initialized & HW_CAP_TPC_MASK) + return; + + so_base_hi = upper_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0); + + for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) { + for (i = 0 ; i < QMAN_STREAMS ; i++) { + internal_q_index = GAUDI_QUEUE_ID_TPC_0_0 + + tpc_id * QMAN_STREAMS + i; + q = &gaudi->internal_qmans[internal_q_index]; + qman_base_addr = (u64) q->pq_dma_addr; + gaudi_init_tpc_qman(hdev, tpc_offset, i, + qman_base_addr); + + if (i == 3) { + /* Initializing lower CP for TPC QMAN */ + gaudi_init_tpc_qman(hdev, tpc_offset, 4, 0); + + /* Enable the QMAN and TPC channel */ + WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, + QMAN_TPC_ENABLE); + } + } + + WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + tpc_id * tpc_delta, + so_base_hi); + + tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0; + + gaudi->hw_cap_initialized |= 1 << (HW_CAP_TPC_SHIFT + tpc_id); + } +} + +static void gaudi_disable_pci_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)) + return; + + WREG32(mmDMA0_QM_GLBL_CFG0, 0); + WREG32(mmDMA1_QM_GLBL_CFG0, 0); + WREG32(mmDMA5_QM_GLBL_CFG0, 0); +} + +static void gaudi_disable_hbm_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)) + return; + + WREG32(mmDMA2_QM_GLBL_CFG0, 0); + WREG32(mmDMA3_QM_GLBL_CFG0, 0); + WREG32(mmDMA4_QM_GLBL_CFG0, 0); + WREG32(mmDMA6_QM_GLBL_CFG0, 0); + WREG32(mmDMA7_QM_GLBL_CFG0, 0); +} + +static void gaudi_disable_mme_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MME)) + return; + + WREG32(mmMME2_QM_GLBL_CFG0, 0); + WREG32(mmMME0_QM_GLBL_CFG0, 0); +} + +static void gaudi_disable_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 tpc_offset = 0; + int tpc_id; + + if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + for (tpc_id = 0 ; tpc_id < TPC_NUMBER_OF_ENGINES ; tpc_id++) { + WREG32(mmTPC0_QM_GLBL_CFG0 + tpc_offset, 0); + tpc_offset += mmTPC1_QM_GLBL_CFG0 - mmTPC0_QM_GLBL_CFG0; + } +} + +static void gaudi_stop_pci_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)) + return; + + /* Stop upper CPs of QMANs 0.0 to 1.3 and 5.0 to 5.3 */ + WREG32(mmDMA0_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA1_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA5_QM_GLBL_CFG1, 0xF << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_stop_hbm_dma_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)) + return; + + /* Stop CPs of HBM DMA QMANs */ + + WREG32(mmDMA2_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA3_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA4_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA6_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmDMA7_QM_GLBL_CFG1, 0x1F << DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_stop_mme_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MME)) + return; + + /* Stop CPs of MME QMANs */ + WREG32(mmMME2_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmMME0_QM_GLBL_CFG1, 0x1F << MME0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_stop_tpc_qmans(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + WREG32(mmTPC0_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC1_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC2_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC3_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC4_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC5_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC6_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); + WREG32(mmTPC7_QM_GLBL_CFG1, 0x1F << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); +} + +static void gaudi_pci_dma_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_PCI_DMA)) + return; + + WREG32(mmDMA0_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA1_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA5_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); +} + +static void gaudi_hbm_dma_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_HBM_DMA)) + return; + + WREG32(mmDMA2_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA3_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA4_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA6_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); + WREG32(mmDMA7_CORE_CFG_1, 1 << DMA0_CORE_CFG_1_HALT_SHIFT); +} + +static void gaudi_mme_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MME)) + return; + + /* WA for H3-1800 bug: do ACC and SBAB writes twice */ + WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME0_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME0_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME1_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME1_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME2_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME2_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME3_ACC_ACC_STALL, 1 << MME_ACC_ACC_STALL_R_SHIFT); + WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); + WREG32(mmMME3_SBAB_SB_STALL, 1 << MME_SBAB_SB_STALL_R_SHIFT); +} + +static void gaudi_tpc_stall(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_TPC_MASK)) + return; + + WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); + WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT); +} + +static void gaudi_enable_clock_gating(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 qman_offset; + int i; + + if (!hdev->clock_gating) + return; + + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) + return; + + /* In case we are during debug session, don't enable the clock gate + * as it may interfere + */ + if (hdev->in_debug) + return; + + for (i = 0, qman_offset = 0 ; i < PCI_DMA_NUMBER_OF_CHNLS ; i++) { + qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET; + WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmDMA0_QM_CGM_CFG + qman_offset, + QMAN_UPPER_CP_CGM_PWR_GATE_EN); + } + + for (; i < HBM_DMA_NUMBER_OF_CHNLS ; i++) { + qman_offset = gaudi_dma_assignment[i] * DMA_QMAN_OFFSET; + WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmDMA0_QM_CGM_CFG + qman_offset, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + } + + WREG32(mmMME0_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmMME0_QM_CGM_CFG, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + WREG32(mmMME2_QM_CGM_CFG1, QMAN_CGM1_PWR_GATE_EN); + WREG32(mmMME2_QM_CGM_CFG, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + + for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, + QMAN_CGM1_PWR_GATE_EN); + WREG32(mmTPC0_QM_CGM_CFG + qman_offset, + QMAN_COMMON_CP_CGM_PWR_GATE_EN); + + qman_offset += TPC_QMAN_OFFSET; + } + + gaudi->hw_cap_initialized |= HW_CAP_CLK_GATE; +} + +static void gaudi_disable_clock_gating(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 qman_offset; + int i; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CLK_GATE)) + return; + + for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) { + WREG32(mmDMA0_QM_CGM_CFG + qman_offset, 0); + WREG32(mmDMA0_QM_CGM_CFG1 + qman_offset, 0); + + qman_offset += (mmDMA1_QM_CGM_CFG - mmDMA0_QM_CGM_CFG); + } + + WREG32(mmMME0_QM_CGM_CFG, 0); + WREG32(mmMME0_QM_CGM_CFG1, 0); + WREG32(mmMME2_QM_CGM_CFG, 0); + WREG32(mmMME2_QM_CGM_CFG1, 0); + + for (i = 0, qman_offset = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + WREG32(mmTPC0_QM_CGM_CFG + qman_offset, 0); + WREG32(mmTPC0_QM_CGM_CFG1 + qman_offset, 0); + + qman_offset += (mmTPC1_QM_CGM_CFG - mmTPC0_QM_CGM_CFG); + } + + gaudi->hw_cap_initialized &= ~(HW_CAP_CLK_GATE); +} + +static void gaudi_enable_timestamp(struct hl_device *hdev) +{ + /* Disable the timestamp counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); + + /* Zero the lower/upper parts of the 64-bit counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0); + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0); + + /* Enable the counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1); +} + +static void gaudi_disable_timestamp(struct hl_device *hdev) +{ + /* Disable the timestamp counter */ + WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0); +} + +static void gaudi_halt_engines(struct hl_device *hdev, bool hard_reset) +{ + u32 wait_timeout_ms, cpu_timeout_ms; + + dev_info(hdev->dev, + "Halting compute engines and disabling interrupts\n"); + + if (hdev->pldm) { + wait_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC; + cpu_timeout_ms = GAUDI_PLDM_RESET_WAIT_MSEC; + } else { + wait_timeout_ms = GAUDI_RESET_WAIT_MSEC; + cpu_timeout_ms = GAUDI_CPU_RESET_WAIT_MSEC; + } + + if (hard_reset) { + /* + * I don't know what is the state of the CPU so make sure it is + * stopped in any means necessary + */ + WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE); + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GAUDI_EVENT_HALT_MACHINE); + msleep(cpu_timeout_ms); + } + + gaudi_stop_mme_qmans(hdev); + gaudi_stop_tpc_qmans(hdev); + gaudi_stop_hbm_dma_qmans(hdev); + gaudi_stop_pci_dma_qmans(hdev); + + gaudi_disable_clock_gating(hdev); + + msleep(wait_timeout_ms); + + gaudi_pci_dma_stall(hdev); + gaudi_hbm_dma_stall(hdev); + gaudi_tpc_stall(hdev); + gaudi_mme_stall(hdev); + + msleep(wait_timeout_ms); + + gaudi_disable_mme_qmans(hdev); + gaudi_disable_tpc_qmans(hdev); + gaudi_disable_hbm_dma_qmans(hdev); + gaudi_disable_pci_dma_qmans(hdev); + + gaudi_disable_timestamp(hdev); + + if (hard_reset) + gaudi_disable_msi(hdev); + else + gaudi_sync_irqs(hdev); +} + +static int gaudi_mmu_init(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hop0_addr; + int rc, i; + + if (!hdev->mmu_enable) + return 0; + + if (gaudi->hw_cap_initialized & HW_CAP_MMU) + return 0; + + hdev->dram_supports_virtual_memory = false; + + for (i = 0 ; i < prop->max_asid ; i++) { + hop0_addr = prop->mmu_pgt_addr + + (i * prop->mmu_hop_table_size); + + rc = gaudi_mmu_update_asid_hop0_addr(hdev, i, hop0_addr); + if (rc) { + dev_err(hdev->dev, + "failed to set hop0 addr for asid %d\n", i); + goto err; + } + } + + /* init MMU cache manage page */ + WREG32(mmSTLB_CACHE_INV_BASE_39_8, MMU_CACHE_MNG_ADDR >> 8); + WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40); + + hdev->asic_funcs->mmu_invalidate_cache(hdev, true, + VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK); + + WREG32(mmMMU_UP_MMU_ENABLE, 1); + WREG32(mmMMU_UP_SPI_MASK, 0xF); + + WREG32(mmSTLB_HOP_CONFIGURATION, + hdev->mmu_huge_page_opt ? 0x30440 : 0x40440); + + gaudi->hw_cap_initialized |= HW_CAP_MMU; + + return 0; + +err: + return rc; +} + +static int gaudi_load_firmware_to_device(struct hl_device *hdev) +{ + void __iomem *dst; + + /* HBM scrambler must be initialized before pushing F/W to HBM */ + gaudi_init_scrambler_hbm(hdev); + + dst = hdev->pcie_bar[HBM_BAR_ID] + LINUX_FW_OFFSET; + + return hl_fw_load_fw_to_device(hdev, GAUDI_LINUX_FW_FILE, dst); +} + +static int gaudi_load_boot_fit_to_device(struct hl_device *hdev) +{ + void __iomem *dst; + + dst = hdev->pcie_bar[SRAM_BAR_ID] + BOOT_FIT_SRAM_OFFSET; + + return hl_fw_load_fw_to_device(hdev, GAUDI_BOOT_FIT_FILE, dst); +} + +static void gaudi_read_device_fw_version(struct hl_device *hdev, + enum hl_fw_component fwc) +{ + const char *name; + u32 ver_off; + char *dest; + + switch (fwc) { + case FW_COMP_UBOOT: + ver_off = RREG32(mmUBOOT_VER_OFFSET); + dest = hdev->asic_prop.uboot_ver; + name = "U-Boot"; + break; + case FW_COMP_PREBOOT: + ver_off = RREG32(mmPREBOOT_VER_OFFSET); + dest = hdev->asic_prop.preboot_ver; + name = "Preboot"; + break; + default: + dev_warn(hdev->dev, "Undefined FW component: %d\n", fwc); + return; + } + + ver_off &= ~((u32)SRAM_BASE_ADDR); + + if (ver_off < SRAM_SIZE - VERSION_MAX_LEN) { + memcpy_fromio(dest, hdev->pcie_bar[SRAM_BAR_ID] + ver_off, + VERSION_MAX_LEN); + } else { + dev_err(hdev->dev, "%s version offset (0x%x) is above SRAM\n", + name, ver_off); + strcpy(dest, "unavailable"); + } +} + +static int gaudi_init_cpu(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + + if (!hdev->cpu_enable) + return 0; + + if (gaudi->hw_cap_initialized & HW_CAP_CPU) + return 0; + + /* + * The device CPU works with 40 bits addresses. + * This register sets the extension to 50 bits. + */ + WREG32(mmCPU_IF_CPU_MSB_ADDR, hdev->cpu_pci_msb_addr); + + rc = hl_fw_init_cpu(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, + mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, + mmCPU_CMD_STATUS_TO_HOST, + mmCPU_BOOT_ERR0, + !hdev->bmc_enable, GAUDI_CPU_TIMEOUT_USEC, + GAUDI_BOOT_FIT_REQ_TIMEOUT_USEC); + + if (rc) + return rc; + + gaudi->hw_cap_initialized |= HW_CAP_CPU; + + return 0; +} + +static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct hl_eq *eq; + u32 status; + struct hl_hw_queue *cpu_pq = + &hdev->kernel_queues[GAUDI_QUEUE_ID_CPU_PQ]; + int err; + + if (!hdev->cpu_queues_enable) + return 0; + + if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q) + return 0; + + eq = &hdev->event_queue; + + WREG32(mmCPU_IF_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address)); + WREG32(mmCPU_IF_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address)); + + WREG32(mmCPU_IF_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address)); + WREG32(mmCPU_IF_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address)); + + WREG32(mmCPU_IF_CQ_BASE_ADDR_LOW, + lower_32_bits(hdev->cpu_accessible_dma_address)); + WREG32(mmCPU_IF_CQ_BASE_ADDR_HIGH, + upper_32_bits(hdev->cpu_accessible_dma_address)); + + WREG32(mmCPU_IF_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES); + WREG32(mmCPU_IF_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES); + WREG32(mmCPU_IF_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE); + + /* Used for EQ CI */ + WREG32(mmCPU_IF_EQ_RD_OFFS, 0); + + WREG32(mmCPU_IF_PF_PQ_PI, 0); + + if (gaudi->multi_msi_mode) + WREG32(mmCPU_IF_QUEUE_INIT, PQ_INIT_STATUS_READY_FOR_CP); + else + WREG32(mmCPU_IF_QUEUE_INIT, + PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI); + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_PI_UPDATE); + + err = hl_poll_timeout( + hdev, + mmCPU_IF_QUEUE_INIT, + status, + (status == PQ_INIT_STATUS_READY_FOR_HOST), + 1000, + cpu_timeout); + + if (err) { + dev_err(hdev->dev, + "Failed to communicate with ARM CPU (ArmCP timeout)\n"); + return -EIO; + } + + gaudi->hw_cap_initialized |= HW_CAP_CPU_Q; + return 0; +} + +static void gaudi_pre_hw_init(struct hl_device *hdev) +{ + /* Perform read from the device to make sure device is up */ + RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + /* + * Let's mark in the H/W that we have reached this point. We check + * this value in the reset_before_init function to understand whether + * we need to reset the chip before doing H/W init. This register is + * cleared by the H/W upon H/W reset + */ + WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); + + /* Set the access through PCI bars (Linux driver only) as secured */ + WREG32(mmPCIE_WRAP_LBW_PROT_OVR, (PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK | + PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK)); + + /* Perform read to flush the waiting writes to ensure configuration + * was set in the device + */ + RREG32(mmPCIE_WRAP_LBW_PROT_OVR); + + if (hdev->axi_drain) { + WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, + 1 << PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT); + WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, + 1 << PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT); + + /* Perform read to flush the DRAIN cfg */ + RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); + } else { + WREG32(mmPCIE_WRAP_LBW_DRAIN_CFG, 0); + WREG32(mmPCIE_WRAP_HBW_DRAIN_CFG, 0); + + /* Perform read to flush the DRAIN cfg */ + RREG32(mmPCIE_WRAP_HBW_DRAIN_CFG); + } + + /* Configure the reset registers. Must be done as early as possible + * in case we fail during H/W initialization + */ + WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H, + (CFG_RST_H_DMA_MASK | + CFG_RST_H_MME_MASK | + CFG_RST_H_SM_MASK | + CFG_RST_H_TPC_MASK)); + + WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L, CFG_RST_L_TPC_MASK); + + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H, + (CFG_RST_H_HBM_MASK | + CFG_RST_H_TPC_MASK | + CFG_RST_H_NIC_MASK | + CFG_RST_H_SM_MASK | + CFG_RST_H_DMA_MASK | + CFG_RST_H_MME_MASK | + CFG_RST_H_CPU_MASK | + CFG_RST_H_MMU_MASK)); + + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L, + (CFG_RST_L_IF_MASK | + CFG_RST_L_PSOC_MASK | + CFG_RST_L_TPC_MASK)); +} + +static int gaudi_hw_init(struct hl_device *hdev) +{ + int rc; + + dev_info(hdev->dev, "Starting initialization of H/W\n"); + + gaudi_pre_hw_init(hdev); + + gaudi_init_pci_dma_qmans(hdev); + + gaudi_init_hbm_dma_qmans(hdev); + + /* + * Before pushing u-boot/linux to device, need to set the hbm bar to + * base address of dram + */ + if (gaudi_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) { + dev_err(hdev->dev, + "failed to map HBM bar to DRAM base address\n"); + return -EIO; + } + + rc = gaudi_init_cpu(hdev); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU\n"); + return rc; + } + + /* SRAM scrambler must be initialized after CPU is running from HBM */ + gaudi_init_scrambler_sram(hdev); + + /* This is here just in case we are working without CPU */ + gaudi_init_scrambler_hbm(hdev); + + gaudi_init_golden_registers(hdev); + + rc = gaudi_mmu_init(hdev); + if (rc) + return rc; + + gaudi_init_security(hdev); + + gaudi_init_mme_qmans(hdev); + + gaudi_init_tpc_qmans(hdev); + + gaudi_enable_clock_gating(hdev); + + gaudi_enable_timestamp(hdev); + + /* MSI must be enabled before CPU queues are initialized */ + rc = gaudi_enable_msi(hdev); + if (rc) + goto disable_queues; + + /* must be called after MSI was enabled */ + rc = gaudi_init_cpu_queues(hdev, GAUDI_CPU_TIMEOUT_USEC); + if (rc) { + dev_err(hdev->dev, "failed to initialize CPU H/W queues %d\n", + rc); + goto disable_msi; + } + + /* Perform read from the device to flush all configuration */ + RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + return 0; + +disable_msi: + gaudi_disable_msi(hdev); +disable_queues: + gaudi_disable_mme_qmans(hdev); + gaudi_disable_pci_dma_qmans(hdev); + + return rc; +} + +static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 status, reset_timeout_ms, boot_strap = 0; + + if (hdev->pldm) { + if (hard_reset) + reset_timeout_ms = GAUDI_PLDM_HRESET_TIMEOUT_MSEC; + else + reset_timeout_ms = GAUDI_PLDM_SRESET_TIMEOUT_MSEC; + } else { + reset_timeout_ms = GAUDI_RESET_TIMEOUT_MSEC; + } + + if (hard_reset) { + /* Tell ASIC not to re-initialize PCIe */ + WREG32(mmPREBOOT_PCIE_EN, LKD_HARD_RESET_MAGIC); + + boot_strap = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS); + /* H/W bug WA: + * rdata[31:0] = strap_read_val; + * wdata[31:0] = rdata[30:21],1'b0,rdata[20:0] + */ + boot_strap = (((boot_strap & 0x7FE00000) << 1) | + (boot_strap & 0x001FFFFF)); + WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap & ~0x2); + + /* Restart BTL/BLR upon hard-reset */ + WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 1); + + WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST, + 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT); + dev_info(hdev->dev, + "Issued HARD reset command, going to wait %dms\n", + reset_timeout_ms); + } else { + /* Don't restart BTL/BLR upon soft-reset */ + WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START, 0); + + WREG32(mmPSOC_GLOBAL_CONF_SOFT_RST, + 1 << PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT); + dev_info(hdev->dev, + "Issued SOFT reset command, going to wait %dms\n", + reset_timeout_ms); + } + + /* + * After hard reset, we can't poll the BTM_FSM register because the PSOC + * itself is in reset. Need to wait until the reset is deasserted + */ + msleep(reset_timeout_ms); + + status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM); + if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK) + dev_err(hdev->dev, + "Timeout while waiting for device to reset 0x%x\n", + status); + + if (!hard_reset) { + gaudi->hw_cap_initialized &= ~(HW_CAP_PCI_DMA | HW_CAP_MME | + HW_CAP_TPC_MASK | + HW_CAP_HBM_DMA); + + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GAUDI_EVENT_SOFT_RESET); + return; + } + + /* We continue here only for hard-reset */ + + WREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS, boot_strap); + + gaudi->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q | + HW_CAP_HBM | HW_CAP_PCI_DMA | + HW_CAP_MME | HW_CAP_TPC_MASK | + HW_CAP_HBM_DMA | HW_CAP_PLL | + HW_CAP_MMU | + HW_CAP_SRAM_SCRAMBLER | + HW_CAP_HBM_SCRAMBLER); + memset(gaudi->events_stat, 0, sizeof(gaudi->events_stat)); +} + +static int gaudi_suspend(struct hl_device *hdev) +{ + int rc; + + rc = hl_fw_send_pci_access_msg(hdev, ARMCP_PACKET_DISABLE_PCI_ACCESS); + if (rc) + dev_err(hdev->dev, "Failed to disable PCI access from CPU\n"); + + return rc; +} + +static int gaudi_resume(struct hl_device *hdev) +{ + return gaudi_init_iatu(hdev); +} + +static int gaudi_cb_mmap(struct hl_device *hdev, struct vm_area_struct *vma, + u64 kaddress, phys_addr_t paddress, u32 size) +{ + int rc; + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | + VM_DONTCOPY | VM_NORESERVE; + + rc = remap_pfn_range(vma, vma->vm_start, paddress >> PAGE_SHIFT, + size, vma->vm_page_prot); + if (rc) + dev_err(hdev->dev, "remap_pfn_range error %d", rc); + + return rc; +} + +static void gaudi_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 db_reg_offset, db_value, dma_qm_offset, q_off; + int dma_id; + bool invalid_queue = false; + + switch (hw_queue_id) { + case GAUDI_QUEUE_ID_DMA_0_0...GAUDI_QUEUE_ID_DMA_0_3: + dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_1]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_1_0...GAUDI_QUEUE_ID_DMA_1_3: + dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_2]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + (hw_queue_id & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_2_0...GAUDI_QUEUE_ID_DMA_2_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_1]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_3_0...GAUDI_QUEUE_ID_DMA_3_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_2]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_4_0...GAUDI_QUEUE_ID_DMA_4_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_3]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_5_0...GAUDI_QUEUE_ID_DMA_5_3: + dma_id = gaudi_dma_assignment[GAUDI_PCI_DMA_3]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_6_0...GAUDI_QUEUE_ID_DMA_6_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_4]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_DMA_7_0...GAUDI_QUEUE_ID_DMA_7_3: + dma_id = gaudi_dma_assignment[GAUDI_HBM_DMA_5]; + dma_qm_offset = dma_id * DMA_QMAN_OFFSET; + q_off = dma_qm_offset + ((hw_queue_id - 1) & 0x3) * 4; + db_reg_offset = mmDMA0_QM_PQ_PI_0 + q_off; + break; + + case GAUDI_QUEUE_ID_CPU_PQ: + if (gaudi->hw_cap_initialized & HW_CAP_CPU_Q) + db_reg_offset = mmCPU_IF_PF_PQ_PI; + else + invalid_queue = true; + break; + + case GAUDI_QUEUE_ID_MME_0_0: + db_reg_offset = mmMME2_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_MME_0_1: + db_reg_offset = mmMME2_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_MME_0_2: + db_reg_offset = mmMME2_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_MME_0_3: + db_reg_offset = mmMME2_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_MME_1_0: + db_reg_offset = mmMME0_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_MME_1_1: + db_reg_offset = mmMME0_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_MME_1_2: + db_reg_offset = mmMME0_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_MME_1_3: + db_reg_offset = mmMME0_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_0_0: + db_reg_offset = mmTPC0_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_0_1: + db_reg_offset = mmTPC0_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_0_2: + db_reg_offset = mmTPC0_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_0_3: + db_reg_offset = mmTPC0_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_1_0: + db_reg_offset = mmTPC1_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_1_1: + db_reg_offset = mmTPC1_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_1_2: + db_reg_offset = mmTPC1_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_1_3: + db_reg_offset = mmTPC1_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_2_0: + db_reg_offset = mmTPC2_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_2_1: + db_reg_offset = mmTPC2_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_2_2: + db_reg_offset = mmTPC2_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_2_3: + db_reg_offset = mmTPC2_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_3_0: + db_reg_offset = mmTPC3_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_3_1: + db_reg_offset = mmTPC3_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_3_2: + db_reg_offset = mmTPC3_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_3_3: + db_reg_offset = mmTPC3_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_4_0: + db_reg_offset = mmTPC4_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_4_1: + db_reg_offset = mmTPC4_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_4_2: + db_reg_offset = mmTPC4_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_4_3: + db_reg_offset = mmTPC4_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_5_0: + db_reg_offset = mmTPC5_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_5_1: + db_reg_offset = mmTPC5_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_5_2: + db_reg_offset = mmTPC5_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_5_3: + db_reg_offset = mmTPC5_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_6_0: + db_reg_offset = mmTPC6_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_6_1: + db_reg_offset = mmTPC6_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_6_2: + db_reg_offset = mmTPC6_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_6_3: + db_reg_offset = mmTPC6_QM_PQ_PI_3; + break; + + case GAUDI_QUEUE_ID_TPC_7_0: + db_reg_offset = mmTPC7_QM_PQ_PI_0; + break; + + case GAUDI_QUEUE_ID_TPC_7_1: + db_reg_offset = mmTPC7_QM_PQ_PI_1; + break; + + case GAUDI_QUEUE_ID_TPC_7_2: + db_reg_offset = mmTPC7_QM_PQ_PI_2; + break; + + case GAUDI_QUEUE_ID_TPC_7_3: + db_reg_offset = mmTPC7_QM_PQ_PI_3; + break; + + default: + invalid_queue = true; + } + + if (invalid_queue) { + /* Should never get here */ + dev_err(hdev->dev, "h/w queue %d is invalid. Can't set pi\n", + hw_queue_id); + return; + } + + db_value = pi; + + /* ring the doorbell */ + WREG32(db_reg_offset, db_value); + + if (hw_queue_id == GAUDI_QUEUE_ID_CPU_PQ) + WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, + GAUDI_EVENT_PI_UPDATE); +} + +static void gaudi_pqe_write(struct hl_device *hdev, __le64 *pqe, + struct hl_bd *bd) +{ + __le64 *pbd = (__le64 *) bd; + + /* The QMANs are on the host memory so a simple copy suffice */ + pqe[0] = pbd[0]; + pqe[1] = pbd[1]; +} + +static void *gaudi_dma_alloc_coherent(struct hl_device *hdev, size_t size, + dma_addr_t *dma_handle, gfp_t flags) +{ + void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size, + dma_handle, flags); + + /* Shift to the device's base physical address of host memory */ + if (kernel_addr) + *dma_handle += HOST_PHYS_BASE; + + return kernel_addr; +} + +static void gaudi_dma_free_coherent(struct hl_device *hdev, size_t size, + void *cpu_addr, dma_addr_t dma_handle) +{ + /* Cancel the device's base physical address of host memory */ + dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE; + + dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle); +} + +static void *gaudi_get_int_queue_base(struct hl_device *hdev, + u32 queue_id, dma_addr_t *dma_handle, + u16 *queue_len) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct gaudi_internal_qman_info *q; + + if (queue_id >= GAUDI_QUEUE_ID_SIZE || + gaudi_queue_type[queue_id] != QUEUE_TYPE_INT) { + dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id); + return NULL; + } + + q = &gaudi->internal_qmans[queue_id]; + *dma_handle = q->pq_dma_addr; + *queue_len = q->pq_size / QMAN_PQ_ENTRY_SIZE; + + return q->pq_kernel_addr; +} + +static int gaudi_send_cpu_message(struct hl_device *hdev, u32 *msg, + u16 len, u32 timeout, long *result) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) { + if (result) + *result = 0; + return 0; + } + + return hl_fw_send_cpu_message(hdev, GAUDI_QUEUE_ID_CPU_PQ, msg, len, + timeout, result); +} + +static int gaudi_test_queue(struct hl_device *hdev, u32 hw_queue_id) +{ + struct packet_msg_prot *fence_pkt; + dma_addr_t pkt_dma_addr; + u32 fence_val, tmp, timeout_usec; + dma_addr_t fence_dma_addr; + u32 *fence_ptr; + int rc; + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_TEST_QUEUE_WAIT_USEC; + else + timeout_usec = GAUDI_TEST_QUEUE_WAIT_USEC; + + fence_val = GAUDI_QMAN0_FENCE_VAL; + + fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, + &fence_dma_addr); + if (!fence_ptr) { + dev_err(hdev->dev, + "Failed to allocate memory for queue testing\n"); + return -ENOMEM; + } + + *fence_ptr = 0; + + fence_pkt = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, + sizeof(struct packet_msg_prot), + GFP_KERNEL, &pkt_dma_addr); + if (!fence_pkt) { + dev_err(hdev->dev, + "Failed to allocate packet for queue testing\n"); + rc = -ENOMEM; + goto free_fence_ptr; + } + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_EB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + fence_pkt->ctl = cpu_to_le32(tmp); + fence_pkt->value = cpu_to_le32(fence_val); + fence_pkt->addr = cpu_to_le64(fence_dma_addr); + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, + sizeof(struct packet_msg_prot), + pkt_dma_addr); + if (rc) { + dev_err(hdev->dev, + "Failed to send fence packet\n"); + goto free_pkt; + } + + rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val), + 1000, timeout_usec, true); + + hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id); + + if (rc == -ETIMEDOUT) { + dev_err(hdev->dev, + "H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n", + hw_queue_id, (unsigned long long) fence_dma_addr, tmp); + rc = -EIO; + } + +free_pkt: + hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_pkt, + pkt_dma_addr); +free_fence_ptr: + hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, + fence_dma_addr); + return rc; +} + +static int gaudi_test_cpu_queue(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + /* + * check capability here as send_cpu_message() won't update the result + * value if no capability + */ + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_test_cpu_queue(hdev); +} + +static int gaudi_test_queues(struct hl_device *hdev) +{ + int i, rc, ret_val = 0; + + for (i = 0 ; i < HL_MAX_QUEUES ; i++) { + if (hdev->asic_prop.hw_queues_props[i].type == QUEUE_TYPE_EXT) { + rc = gaudi_test_queue(hdev, i); + if (rc) + ret_val = -EINVAL; + } + } + + rc = gaudi_test_cpu_queue(hdev); + if (rc) + ret_val = -EINVAL; + + return ret_val; +} + +static void *gaudi_dma_pool_zalloc(struct hl_device *hdev, size_t size, + gfp_t mem_flags, dma_addr_t *dma_handle) +{ + void *kernel_addr; + + if (size > GAUDI_DMA_POOL_BLK_SIZE) + return NULL; + + kernel_addr = dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle); + + /* Shift to the device's base physical address of host memory */ + if (kernel_addr) + *dma_handle += HOST_PHYS_BASE; + + return kernel_addr; +} + +static void gaudi_dma_pool_free(struct hl_device *hdev, void *vaddr, + dma_addr_t dma_addr) +{ + /* Cancel the device's base physical address of host memory */ + dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE; + + dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr); +} + +static void *gaudi_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, + size_t size, dma_addr_t *dma_handle) +{ + return hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle); +} + +static void gaudi_cpu_accessible_dma_pool_free(struct hl_device *hdev, + size_t size, void *vaddr) +{ + hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr); +} + +static int gaudi_dma_map_sg(struct hl_device *hdev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *sg; + int i; + + if (!dma_map_sg(&hdev->pdev->dev, sgl, nents, dir)) + return -ENOMEM; + + /* Shift to the device's base physical address of host memory */ + for_each_sg(sgl, sg, nents, i) + sg->dma_address += HOST_PHYS_BASE; + + return 0; +} + +static void gaudi_dma_unmap_sg(struct hl_device *hdev, struct scatterlist *sgl, + int nents, enum dma_data_direction dir) +{ + struct scatterlist *sg; + int i; + + /* Cancel the device's base physical address of host memory */ + for_each_sg(sgl, sg, nents, i) + sg->dma_address -= HOST_PHYS_BASE; + + dma_unmap_sg(&hdev->pdev->dev, sgl, nents, dir); +} + +static u32 gaudi_get_dma_desc_list_size(struct hl_device *hdev, + struct sg_table *sgt) +{ + struct scatterlist *sg, *sg_next_iter; + u32 count, dma_desc_cnt; + u64 len, len_next; + dma_addr_t addr, addr_next; + + dma_desc_cnt = 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, count) { + + len = sg_dma_len(sg); + addr = sg_dma_address(sg); + + if (len == 0) + break; + + while ((count + 1) < sgt->nents) { + sg_next_iter = sg_next(sg); + len_next = sg_dma_len(sg_next_iter); + addr_next = sg_dma_address(sg_next_iter); + + if (len_next == 0) + break; + + if ((addr + len == addr_next) && + (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { + len += len_next; + count++; + sg = sg_next_iter; + } else { + break; + } + } + + dma_desc_cnt++; + } + + return dma_desc_cnt * sizeof(struct packet_lin_dma); +} + +static int gaudi_pin_memory_before_cs(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + u64 addr, enum dma_data_direction dir) +{ + struct hl_userptr *userptr; + int rc; + + if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), + parser->job_userptr_list, &userptr)) + goto already_pinned; + + userptr = kzalloc(sizeof(*userptr), GFP_ATOMIC); + if (!userptr) + return -ENOMEM; + + rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize), + userptr); + if (rc) + goto free_userptr; + + list_add_tail(&userptr->job_node, parser->job_userptr_list); + + rc = hdev->asic_funcs->asic_dma_map_sg(hdev, userptr->sgt->sgl, + userptr->sgt->nents, dir); + if (rc) { + dev_err(hdev->dev, "failed to map sgt with DMA region\n"); + goto unpin_memory; + } + + userptr->dma_mapped = true; + userptr->dir = dir; + +already_pinned: + parser->patched_cb_size += + gaudi_get_dma_desc_list_size(hdev, userptr->sgt); + + return 0; + +unpin_memory: + hl_unpin_host_memory(hdev, userptr); +free_userptr: + kfree(userptr); + return rc; +} + +static int gaudi_validate_dma_pkt_host(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + bool src_in_host) +{ + enum dma_data_direction dir; + bool skip_host_mem_pin = false, user_memset; + u64 addr; + int rc = 0; + + user_memset = (le32_to_cpu(user_dma_pkt->ctl) & + GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >> + GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT; + + if (src_in_host) { + if (user_memset) + skip_host_mem_pin = true; + + dev_dbg(hdev->dev, "DMA direction is HOST --> DEVICE\n"); + dir = DMA_TO_DEVICE; + addr = le64_to_cpu(user_dma_pkt->src_addr); + } else { + dev_dbg(hdev->dev, "DMA direction is DEVICE --> HOST\n"); + dir = DMA_FROM_DEVICE; + addr = (le64_to_cpu(user_dma_pkt->dst_addr) & + GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >> + GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT; + } + + if (skip_host_mem_pin) + parser->patched_cb_size += sizeof(*user_dma_pkt); + else + rc = gaudi_pin_memory_before_cs(hdev, parser, user_dma_pkt, + addr, dir); + + return rc; +} + +static int gaudi_validate_dma_pkt_no_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt) +{ + bool src_in_host = false; + u64 dst_addr = (le64_to_cpu(user_dma_pkt->dst_addr) & + GAUDI_PKT_LIN_DMA_DST_ADDR_MASK) >> + GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT; + + dev_dbg(hdev->dev, "DMA packet details:\n"); + dev_dbg(hdev->dev, "source == 0x%llx\n", + le64_to_cpu(user_dma_pkt->src_addr)); + dev_dbg(hdev->dev, "destination == 0x%llx\n", dst_addr); + dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize)); + + /* + * Special handling for DMA with size 0. Bypass all validations + * because no transactions will be done except for WR_COMP, which + * is not a security issue + */ + if (!le32_to_cpu(user_dma_pkt->tsize)) { + parser->patched_cb_size += sizeof(*user_dma_pkt); + return 0; + } + + if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3) + src_in_host = true; + + return gaudi_validate_dma_pkt_host(hdev, parser, user_dma_pkt, + src_in_host); +} + +static int gaudi_validate_cb(struct hl_device *hdev, + struct hl_cs_parser *parser, bool is_mmu) +{ + u32 cb_parsed_length = 0; + int rc = 0; + + parser->patched_cb_size = 0; + + /* cb_user_size is more than 0 so loop will always be executed */ + while (cb_parsed_length < parser->user_cb_size) { + enum packet_id pkt_id; + u16 pkt_size; + struct gaudi_packet *user_pkt; + + user_pkt = (struct gaudi_packet *) (uintptr_t) + (parser->user_cb->kernel_address + cb_parsed_length); + + pkt_id = (enum packet_id) ( + (le64_to_cpu(user_pkt->header) & + PACKET_HEADER_PACKET_ID_MASK) >> + PACKET_HEADER_PACKET_ID_SHIFT); + + pkt_size = gaudi_packet_sizes[pkt_id]; + cb_parsed_length += pkt_size; + if (cb_parsed_length > parser->user_cb_size) { + dev_err(hdev->dev, + "packet 0x%x is out of CB boundary\n", pkt_id); + rc = -EINVAL; + break; + } + + switch (pkt_id) { + case PACKET_MSG_PROT: + dev_err(hdev->dev, + "User not allowed to use MSG_PROT\n"); + rc = -EPERM; + break; + + case PACKET_CP_DMA: + dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); + rc = -EPERM; + break; + + case PACKET_STOP: + dev_err(hdev->dev, "User not allowed to use STOP\n"); + rc = -EPERM; + break; + + case PACKET_LIN_DMA: + parser->contains_dma_pkt = true; + if (is_mmu) + parser->patched_cb_size += pkt_size; + else + rc = gaudi_validate_dma_pkt_no_mmu(hdev, parser, + (struct packet_lin_dma *) user_pkt); + break; + + case PACKET_WREG_32: + case PACKET_WREG_BULK: + case PACKET_MSG_LONG: + case PACKET_MSG_SHORT: + case PACKET_REPEAT: + case PACKET_FENCE: + case PACKET_NOP: + case PACKET_ARB_POINT: + case PACKET_LOAD_AND_EXE: + parser->patched_cb_size += pkt_size; + break; + + default: + dev_err(hdev->dev, "Invalid packet header 0x%x\n", + pkt_id); + rc = -EINVAL; + break; + } + + if (rc) + break; + } + + /* + * The new CB should have space at the end for two MSG_PROT packets: + * 1. A packet that will act as a completion packet + * 2. A packet that will generate MSI-X interrupt + */ + parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2; + + return rc; +} + +static int gaudi_patch_dma_packet(struct hl_device *hdev, + struct hl_cs_parser *parser, + struct packet_lin_dma *user_dma_pkt, + struct packet_lin_dma *new_dma_pkt, + u32 *new_dma_pkt_size) +{ + struct hl_userptr *userptr; + struct scatterlist *sg, *sg_next_iter; + u32 count, dma_desc_cnt, user_wrcomp_en_mask, ctl; + u64 len, len_next; + dma_addr_t dma_addr, dma_addr_next; + u64 device_memory_addr, addr; + enum dma_data_direction dir; + struct sg_table *sgt; + bool src_in_host = false; + bool skip_host_mem_pin = false; + bool user_memset; + + ctl = le32_to_cpu(user_dma_pkt->ctl); + + if (parser->hw_queue_id <= GAUDI_QUEUE_ID_DMA_0_3) + src_in_host = true; + + user_memset = (ctl & GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK) >> + GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT; + + if (src_in_host) { + addr = le64_to_cpu(user_dma_pkt->src_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr); + dir = DMA_TO_DEVICE; + if (user_memset) + skip_host_mem_pin = true; + } else { + addr = le64_to_cpu(user_dma_pkt->dst_addr); + device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr); + dir = DMA_FROM_DEVICE; + } + + if ((!skip_host_mem_pin) && + (!hl_userptr_is_pinned(hdev, addr, + le32_to_cpu(user_dma_pkt->tsize), + parser->job_userptr_list, &userptr))) { + dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n", + addr, user_dma_pkt->tsize); + return -EFAULT; + } + + if ((user_memset) && (dir == DMA_TO_DEVICE)) { + memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt)); + *new_dma_pkt_size = sizeof(*user_dma_pkt); + return 0; + } + + user_wrcomp_en_mask = ctl & GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK; + + sgt = userptr->sgt; + dma_desc_cnt = 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, count) { + len = sg_dma_len(sg); + dma_addr = sg_dma_address(sg); + + if (len == 0) + break; + + while ((count + 1) < sgt->nents) { + sg_next_iter = sg_next(sg); + len_next = sg_dma_len(sg_next_iter); + dma_addr_next = sg_dma_address(sg_next_iter); + + if (len_next == 0) + break; + + if ((dma_addr + len == dma_addr_next) && + (len + len_next <= DMA_MAX_TRANSFER_SIZE)) { + len += len_next; + count++; + sg = sg_next_iter; + } else { + break; + } + } + + new_dma_pkt->ctl = user_dma_pkt->ctl; + + ctl = le32_to_cpu(user_dma_pkt->ctl); + if (likely(dma_desc_cnt)) + ctl &= ~GAUDI_PKT_CTL_EB_MASK; + ctl &= ~GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK; + new_dma_pkt->ctl = cpu_to_le32(ctl); + new_dma_pkt->tsize = cpu_to_le32(len); + + if (dir == DMA_TO_DEVICE) { + new_dma_pkt->src_addr = cpu_to_le64(dma_addr); + new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr); + } else { + new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr); + new_dma_pkt->dst_addr = cpu_to_le64(dma_addr); + } + + if (!user_memset) + device_memory_addr += len; + dma_desc_cnt++; + new_dma_pkt++; + } + + if (!dma_desc_cnt) { + dev_err(hdev->dev, + "Error of 0 SG entries when patching DMA packet\n"); + return -EFAULT; + } + + /* Fix the last dma packet - wrcomp must be as user set it */ + new_dma_pkt--; + new_dma_pkt->ctl |= cpu_to_le32(user_wrcomp_en_mask); + + *new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma); + + return 0; +} + +static int gaudi_patch_cb(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u32 cb_parsed_length = 0; + u32 cb_patched_cur_length = 0; + int rc = 0; + + /* cb_user_size is more than 0 so loop will always be executed */ + while (cb_parsed_length < parser->user_cb_size) { + enum packet_id pkt_id; + u16 pkt_size; + u32 new_pkt_size = 0; + struct gaudi_packet *user_pkt, *kernel_pkt; + + user_pkt = (struct gaudi_packet *) (uintptr_t) + (parser->user_cb->kernel_address + cb_parsed_length); + kernel_pkt = (struct gaudi_packet *) (uintptr_t) + (parser->patched_cb->kernel_address + + cb_patched_cur_length); + + pkt_id = (enum packet_id) ( + (le64_to_cpu(user_pkt->header) & + PACKET_HEADER_PACKET_ID_MASK) >> + PACKET_HEADER_PACKET_ID_SHIFT); + + pkt_size = gaudi_packet_sizes[pkt_id]; + cb_parsed_length += pkt_size; + if (cb_parsed_length > parser->user_cb_size) { + dev_err(hdev->dev, + "packet 0x%x is out of CB boundary\n", pkt_id); + rc = -EINVAL; + break; + } + + switch (pkt_id) { + case PACKET_LIN_DMA: + rc = gaudi_patch_dma_packet(hdev, parser, + (struct packet_lin_dma *) user_pkt, + (struct packet_lin_dma *) kernel_pkt, + &new_pkt_size); + cb_patched_cur_length += new_pkt_size; + break; + + case PACKET_MSG_PROT: + dev_err(hdev->dev, + "User not allowed to use MSG_PROT\n"); + rc = -EPERM; + break; + + case PACKET_CP_DMA: + dev_err(hdev->dev, "User not allowed to use CP_DMA\n"); + rc = -EPERM; + break; + + case PACKET_STOP: + dev_err(hdev->dev, "User not allowed to use STOP\n"); + rc = -EPERM; + break; + + case PACKET_WREG_32: + case PACKET_WREG_BULK: + case PACKET_MSG_LONG: + case PACKET_MSG_SHORT: + case PACKET_REPEAT: + case PACKET_FENCE: + case PACKET_NOP: + case PACKET_ARB_POINT: + case PACKET_LOAD_AND_EXE: + memcpy(kernel_pkt, user_pkt, pkt_size); + cb_patched_cur_length += pkt_size; + break; + + default: + dev_err(hdev->dev, "Invalid packet header 0x%x\n", + pkt_id); + rc = -EINVAL; + break; + } + + if (rc) + break; + } + + return rc; +} + +static int gaudi_parse_cb_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u64 patched_cb_handle; + u32 patched_cb_size; + struct hl_cb *user_cb; + int rc; + + /* + * The new CB should have space at the end for two MSG_PROT pkt: + * 1. A packet that will act as a completion packet + * 2. A packet that will generate MSI interrupt + */ + parser->patched_cb_size = parser->user_cb_size + + sizeof(struct packet_msg_prot) * 2; + + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, + parser->patched_cb_size, + &patched_cb_handle, HL_KERNEL_ASID_ID); + + if (rc) { + dev_err(hdev->dev, + "Failed to allocate patched CB for DMA CS %d\n", + rc); + return rc; + } + + patched_cb_handle >>= PAGE_SHIFT; + parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr, + (u32) patched_cb_handle); + /* hl_cb_get should never fail here so use kernel WARN */ + WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n", + (u32) patched_cb_handle); + if (!parser->patched_cb) { + rc = -EFAULT; + goto out; + } + + /* + * The check that parser->user_cb_size <= parser->user_cb->size was done + * in validate_queue_index(). + */ + memcpy((void *) (uintptr_t) parser->patched_cb->kernel_address, + (void *) (uintptr_t) parser->user_cb->kernel_address, + parser->user_cb_size); + + patched_cb_size = parser->patched_cb_size; + + /* Validate patched CB instead of user CB */ + user_cb = parser->user_cb; + parser->user_cb = parser->patched_cb; + rc = gaudi_validate_cb(hdev, parser, true); + parser->user_cb = user_cb; + + if (rc) { + hl_cb_put(parser->patched_cb); + goto out; + } + + if (patched_cb_size != parser->patched_cb_size) { + dev_err(hdev->dev, "user CB size mismatch\n"); + hl_cb_put(parser->patched_cb); + rc = -EINVAL; + goto out; + } + +out: + /* + * Always call cb destroy here because we still have 1 reference + * to it by calling cb_get earlier. After the job will be completed, + * cb_put will release it, but here we want to remove it from the + * idr + */ + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, + patched_cb_handle << PAGE_SHIFT); + + return rc; +} + +static int gaudi_parse_cb_no_mmu(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + u64 patched_cb_handle; + int rc; + + rc = gaudi_validate_cb(hdev, parser, false); + + if (rc) + goto free_userptr; + + rc = hl_cb_create(hdev, &hdev->kernel_cb_mgr, + parser->patched_cb_size, + &patched_cb_handle, HL_KERNEL_ASID_ID); + if (rc) { + dev_err(hdev->dev, + "Failed to allocate patched CB for DMA CS %d\n", rc); + goto free_userptr; + } + + patched_cb_handle >>= PAGE_SHIFT; + parser->patched_cb = hl_cb_get(hdev, &hdev->kernel_cb_mgr, + (u32) patched_cb_handle); + /* hl_cb_get should never fail here so use kernel WARN */ + WARN(!parser->patched_cb, "DMA CB handle invalid 0x%x\n", + (u32) patched_cb_handle); + if (!parser->patched_cb) { + rc = -EFAULT; + goto out; + } + + rc = gaudi_patch_cb(hdev, parser); + + if (rc) + hl_cb_put(parser->patched_cb); + +out: + /* + * Always call cb destroy here because we still have 1 reference + * to it by calling cb_get earlier. After the job will be completed, + * cb_put will release it, but here we want to remove it from the + * idr + */ + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, + patched_cb_handle << PAGE_SHIFT); + +free_userptr: + if (rc) + hl_userptr_delete_list(hdev, parser->job_userptr_list); + return rc; +} + +static int gaudi_parse_cb_no_ext_queue(struct hl_device *hdev, + struct hl_cs_parser *parser) +{ + struct asic_fixed_properties *asic_prop = &hdev->asic_prop; + + /* For internal queue jobs just check if CB address is valid */ + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->sram_user_base_address, + asic_prop->sram_end_address)) + return 0; + + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->dram_user_base_address, + asic_prop->dram_end_address)) + return 0; + + /* PMMU and HPMMU addresses are equal, check only one of them */ + if (hl_mem_area_inside_range((u64) (uintptr_t) parser->user_cb, + parser->user_cb_size, + asic_prop->pmmu.start_addr, + asic_prop->pmmu.end_addr)) + return 0; + + dev_err(hdev->dev, + "CB address 0x%px + 0x%x for internal QMAN is not valid\n", + parser->user_cb, parser->user_cb_size); + + return -EFAULT; +} + +static int gaudi_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (parser->queue_type == QUEUE_TYPE_INT) + return gaudi_parse_cb_no_ext_queue(hdev, parser); + + if (gaudi->hw_cap_initialized & HW_CAP_MMU) + return gaudi_parse_cb_mmu(hdev, parser); + else + return gaudi_parse_cb_no_mmu(hdev, parser); +} + +static void gaudi_add_end_of_cb_packets(struct hl_device *hdev, + u64 kernel_address, u32 len, + u64 cq_addr, u32 cq_val, u32 msi_vec, + bool eb) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct packet_msg_prot *cq_pkt; + u32 tmp; + + cq_pkt = (struct packet_msg_prot *) (uintptr_t) + (kernel_address + len - (sizeof(struct packet_msg_prot) * 2)); + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + + if (eb) + tmp |= (1 << GAUDI_PKT_CTL_EB_SHIFT); + + cq_pkt->ctl = cpu_to_le32(tmp); + cq_pkt->value = cpu_to_le32(cq_val); + cq_pkt->addr = cpu_to_le64(cq_addr); + + cq_pkt++; + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + cq_pkt->ctl = cpu_to_le32(tmp); + cq_pkt->value = cpu_to_le32(1); + + if (!gaudi->multi_msi_mode) + msi_vec = 0; + + cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_MSI_INTR_0 + msi_vec * 4); +} + +static void gaudi_update_eq_ci(struct hl_device *hdev, u32 val) +{ + WREG32(mmCPU_IF_EQ_RD_OFFS, val); +} + +static int gaudi_memset_device_memory(struct hl_device *hdev, u64 addr, + u32 size, u64 val) +{ + struct packet_lin_dma *lin_dma_pkt; + struct hl_cs_job *job; + u32 cb_size, ctl; + struct hl_cb *cb; + int rc; + + cb = hl_cb_kernel_create(hdev, PAGE_SIZE); + if (!cb) + return -EFAULT; + + lin_dma_pkt = (struct packet_lin_dma *) (uintptr_t) cb->kernel_address; + memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt)); + cb_size = sizeof(*lin_dma_pkt); + + ctl = ((PACKET_LIN_DMA << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT) | + (1 << GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT) | + (1 << GAUDI_PKT_CTL_RB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT)); + lin_dma_pkt->ctl = cpu_to_le32(ctl); + lin_dma_pkt->src_addr = cpu_to_le64(val); + lin_dma_pkt->dst_addr |= cpu_to_le64(addr); + lin_dma_pkt->tsize = cpu_to_le32(size); + + job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true); + if (!job) { + dev_err(hdev->dev, "Failed to allocate a new job\n"); + rc = -ENOMEM; + goto release_cb; + } + + job->id = 0; + job->user_cb = cb; + job->user_cb->cs_cnt++; + job->user_cb_size = cb_size; + job->hw_queue_id = GAUDI_QUEUE_ID_DMA_0_0; + job->patched_cb = job->user_cb; + job->job_cb_size = job->user_cb_size + sizeof(struct packet_msg_prot); + + hl_debugfs_add_job(hdev, job); + + rc = gaudi_send_job_on_qman0(hdev, job); + + hl_debugfs_remove_job(hdev, job); + kfree(job); + cb->cs_cnt--; + +release_cb: + hl_cb_put(cb); + hl_cb_destroy(hdev, &hdev->kernel_cb_mgr, cb->id << PAGE_SHIFT); + + return rc; +} + +static void gaudi_restore_sm_registers(struct hl_device *hdev) +{ + int i; + + for (i = 0 ; i < NUM_OF_SOB_IN_BLOCK << 2 ; i += 4) { + WREG32(mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + WREG32(mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + WREG32(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + } + + for (i = 0 ; i < NUM_OF_MONITORS_IN_BLOCK << 2 ; i += 4) { + WREG32(mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); + WREG32(mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); + WREG32(mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); + } + + i = GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT * 4; + + for (; i < NUM_OF_SOB_IN_BLOCK << 2 ; i += 4) + WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + i, 0); + + i = GAUDI_FIRST_AVAILABLE_W_S_MONITOR * 4; + + for (; i < NUM_OF_MONITORS_IN_BLOCK << 2 ; i += 4) + WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 + i, 0); +} + +static void gaudi_restore_dma_registers(struct hl_device *hdev) +{ + u32 sob_delta = mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 - + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0; + int i; + + for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) { + u64 sob_addr = CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 + + (i * sob_delta); + u32 dma_offset = i * DMA_CORE_OFFSET; + + WREG32(mmDMA0_CORE_WR_COMP_ADDR_LO + dma_offset, + lower_32_bits(sob_addr)); + WREG32(mmDMA0_CORE_WR_COMP_ADDR_HI + dma_offset, + upper_32_bits(sob_addr)); + WREG32(mmDMA0_CORE_WR_COMP_WDATA + dma_offset, 0x80000001); + + /* For DMAs 2-7, need to restore WR_AWUSER_31_11 as it can be + * modified by the user for SRAM reduction + */ + if (i > 1) + WREG32(mmDMA0_CORE_WR_AWUSER_31_11 + dma_offset, + 0x00000001); + } +} + +static void gaudi_restore_qm_registers(struct hl_device *hdev) +{ + u32 qman_offset; + int i; + + for (i = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) { + qman_offset = i * DMA_QMAN_OFFSET; + WREG32(mmDMA0_QM_ARB_CFG_0 + qman_offset, 0); + } + + for (i = 0 ; i < MME_NUMBER_OF_MASTER_ENGINES ; i++) { + qman_offset = i * (mmMME2_QM_BASE - mmMME0_QM_BASE); + WREG32(mmMME0_QM_ARB_CFG_0 + qman_offset, 0); + } + + for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + qman_offset = i * TPC_QMAN_OFFSET; + WREG32(mmTPC0_QM_ARB_CFG_0 + qman_offset, 0); + } +} + +static void gaudi_restore_user_registers(struct hl_device *hdev) +{ + gaudi_restore_sm_registers(hdev); + gaudi_restore_dma_registers(hdev); + gaudi_restore_qm_registers(hdev); +} + +static int gaudi_context_switch(struct hl_device *hdev, u32 asid) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + u64 addr = prop->sram_user_base_address; + u32 size = hdev->pldm ? 0x10000 : + (prop->sram_size - SRAM_USER_BASE_OFFSET); + u64 val = 0x7777777777777777ull; + int rc; + + rc = gaudi_memset_device_memory(hdev, addr, size, val); + if (rc) { + dev_err(hdev->dev, "Failed to clear SRAM in context switch\n"); + return rc; + } + + gaudi_mmu_prepare(hdev, asid); + + gaudi_restore_user_registers(hdev); + + return 0; +} + +static int gaudi_mmu_clear_pgt_range(struct hl_device *hdev) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 addr = prop->mmu_pgt_addr; + u32 size = prop->mmu_pgt_size + MMU_CACHE_MNG_SIZE; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + return 0; + + return gaudi_memset_device_memory(hdev, addr, size, 0); +} + +static void gaudi_restore_phase_topology(struct hl_device *hdev) +{ + +} + +static int gaudi_debugfs_read32(struct hl_device *hdev, u64 addr, u32 *val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't read register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + *val = RREG32(addr - CFG_BASE); + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr < SRAM_BASE_ADDR + SRAM_BAR_SIZE)) { + *val = readl(hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + *val = readl(hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *val = *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE); + } else { + rc = -EFAULT; + } + + return rc; +} + +static int gaudi_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr < CFG_BASE + CFG_SIZE)) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't write register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + WREG32(addr - CFG_BASE, val); + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr < SRAM_BASE_ADDR + SRAM_BAR_SIZE)) { + writel(val, hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr < DRAM_PHYS_BASE + hdev->asic_prop.dram_size) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + writel(val, hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *(u32 *) phys_to_virt(addr - HOST_PHYS_BASE) = val; + } else { + rc = -EFAULT; + } + + return rc; +} + +static int gaudi_debugfs_read64(struct hl_device *hdev, u64 addr, u64 *val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't read register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + u32 val_l = RREG32(addr - CFG_BASE); + u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE); + + *val = (((u64) val_h) << 32) | val_l; + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr <= SRAM_BASE_ADDR + SRAM_BAR_SIZE - sizeof(u64))) { + *val = readq(hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr <= + DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + *val = readq(hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE); + } else { + rc = -EFAULT; + } + + return rc; +} + +static int gaudi_debugfs_write64(struct hl_device *hdev, u64 addr, u64 val) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + u64 hbm_bar_addr; + int rc = 0; + + if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) { + if (gaudi->hw_cap_initialized & HW_CAP_CLK_GATE) { + dev_err_ratelimited(hdev->dev, + "Can't write register - clock gating is enabled!\n"); + rc = -EFAULT; + } else { + WREG32(addr - CFG_BASE, lower_32_bits(val)); + WREG32(addr + sizeof(u32) - CFG_BASE, + upper_32_bits(val)); + } + } else if ((addr >= SRAM_BASE_ADDR) && + (addr <= SRAM_BASE_ADDR + SRAM_BAR_SIZE - sizeof(u64))) { + writeq(val, hdev->pcie_bar[SRAM_BAR_ID] + + (addr - SRAM_BASE_ADDR)); + } else if (addr <= + DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64)) { + u64 bar_base_addr = DRAM_PHYS_BASE + + (addr & ~(prop->dram_pci_bar_size - 0x1ull)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, bar_base_addr); + if (hbm_bar_addr != U64_MAX) { + writeq(val, hdev->pcie_bar[HBM_BAR_ID] + + (addr - bar_base_addr)); + + hbm_bar_addr = gaudi_set_hbm_bar_base(hdev, + hbm_bar_addr); + } + if (hbm_bar_addr == U64_MAX) + rc = -EIO; + } else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) { + *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val; + } else { + rc = -EFAULT; + } + + return rc; +} + +static u64 gaudi_read_pte(struct hl_device *hdev, u64 addr) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (hdev->hard_reset_pending) + return U64_MAX; + + return readq(hdev->pcie_bar[HBM_BAR_ID] + + (addr - gaudi->hbm_bar_cur_addr)); +} + +static void gaudi_write_pte(struct hl_device *hdev, u64 addr, u64 val) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (hdev->hard_reset_pending) + return; + + writeq(val, hdev->pcie_bar[HBM_BAR_ID] + + (addr - gaudi->hbm_bar_cur_addr)); +} + +static void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid) +{ + /* mask to zero the MMBP and ASID bits */ + WREG32_AND(reg, ~0x7FF); + WREG32_OR(reg, asid); +} + +static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + return; + + if (asid & ~DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK) { + WARN(1, "asid %u is too big\n", asid); + return; + } + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA0_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmDMA0_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA1_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA2_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA3_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA4_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA5_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA6_CORE_NON_SECURE_PROPS, asid); + gaudi_mmu_prepare_reg(hdev, mmDMA7_CORE_NON_SECURE_PROPS, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC0_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC1_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC2_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC3_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC4_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC5_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC6_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_ARUSER_LO, asid); + gaudi_mmu_prepare_reg(hdev, mmTPC7_CFG_AWUSER_LO, asid); + + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_QM_GLBL_NON_SECURE_PROPS_4, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_2, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_3, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_QM_GLBL_NON_SECURE_PROPS_4, asid); + + gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME1_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER0, asid); + gaudi_mmu_prepare_reg(hdev, mmMME3_SBAB_ARUSER1, asid); + gaudi_mmu_prepare_reg(hdev, mmMME0_ACC_WBC, asid); + gaudi_mmu_prepare_reg(hdev, mmMME1_ACC_WBC, asid); + gaudi_mmu_prepare_reg(hdev, mmMME2_ACC_WBC, asid); + gaudi_mmu_prepare_reg(hdev, mmMME3_ACC_WBC, asid); + + gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER, asid); + gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER, asid); + + hdev->asic_funcs->enable_clock_gating(hdev); + + mutex_unlock(&gaudi->clk_gate_mutex); +} + +static int gaudi_send_job_on_qman0(struct hl_device *hdev, + struct hl_cs_job *job) +{ + struct packet_msg_prot *fence_pkt; + u32 *fence_ptr; + dma_addr_t fence_dma_addr; + struct hl_cb *cb; + u32 tmp, timeout, dma_offset; + int rc; + + if (hdev->pldm) + timeout = GAUDI_PLDM_QMAN0_TIMEOUT_USEC; + else + timeout = HL_DEVICE_TIMEOUT_USEC; + + if (!hdev->asic_funcs->is_device_idle(hdev, NULL, NULL)) { + dev_err_ratelimited(hdev->dev, + "Can't send driver job on QMAN0 because the device is not idle\n"); + return -EBUSY; + } + + fence_ptr = hdev->asic_funcs->asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, + &fence_dma_addr); + if (!fence_ptr) { + dev_err(hdev->dev, + "Failed to allocate fence memory for QMAN0\n"); + return -ENOMEM; + } + + cb = job->patched_cb; + + fence_pkt = (struct packet_msg_prot *) (uintptr_t) (cb->kernel_address + + job->job_cb_size - sizeof(struct packet_msg_prot)); + + tmp = (PACKET_MSG_PROT << GAUDI_PKT_CTL_OPCODE_SHIFT) | + (1 << GAUDI_PKT_CTL_EB_SHIFT) | + (1 << GAUDI_PKT_CTL_MB_SHIFT); + fence_pkt->ctl = cpu_to_le32(tmp); + fence_pkt->value = cpu_to_le32(GAUDI_QMAN0_FENCE_VAL); + fence_pkt->addr = cpu_to_le64(fence_dma_addr); + + dma_offset = gaudi_dma_assignment[GAUDI_PCI_DMA_1] * DMA_CORE_OFFSET; + + WREG32_OR(mmDMA0_CORE_PROT + dma_offset, BIT(DMA0_CORE_PROT_VAL_SHIFT)); + + rc = hl_hw_queue_send_cb_no_cmpl(hdev, GAUDI_QUEUE_ID_DMA_0_0, + job->job_cb_size, cb->bus_address); + if (rc) { + dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc); + goto free_fence_ptr; + } + + rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, + (tmp == GAUDI_QMAN0_FENCE_VAL), 1000, + timeout, true); + + hl_hw_queue_inc_ci_kernel(hdev, GAUDI_QUEUE_ID_DMA_0_0); + + if (rc == -ETIMEDOUT) { + dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp); + goto free_fence_ptr; + } + +free_fence_ptr: + WREG32_AND(mmDMA0_CORE_PROT + dma_offset, + ~BIT(DMA0_CORE_PROT_VAL_SHIFT)); + + hdev->asic_funcs->asic_dma_pool_free(hdev, (void *) fence_ptr, + fence_dma_addr); + return rc; +} + +static void gaudi_get_event_desc(u16 event_type, char *desc, size_t size) +{ + if (event_type >= GAUDI_EVENT_SIZE) + goto event_not_supported; + + if (!gaudi_irq_map_table[event_type].valid) + goto event_not_supported; + + snprintf(desc, size, gaudi_irq_map_table[event_type].name); + + return; + +event_not_supported: + snprintf(desc, size, "N/A"); +} + +static const char *gaudi_get_razwi_initiator_dma_name(struct hl_device *hdev, + u32 x_y, bool is_write) +{ + u32 dma_id[2], dma_offset, err_cause[2], mask, i; + + mask = is_write ? DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK : + DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK; + + switch (x_y) { + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1: + dma_id[0] = 0; + dma_id[1] = 2; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1: + dma_id[0] = 1; + dma_id[1] = 3; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1: + dma_id[0] = 4; + dma_id[1] = 6; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1: + dma_id[0] = 5; + dma_id[1] = 7; + break; + default: + goto unknown_initiator; + } + + for (i = 0 ; i < 2 ; i++) { + dma_offset = dma_id[i] * DMA_CORE_OFFSET; + err_cause[i] = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset); + } + + switch (x_y) { + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA0"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA2"; + else + return "DMA0 or DMA2"; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA1"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA3"; + else + return "DMA1 or DMA3"; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA4"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA6"; + else + return "DMA4 or DMA6"; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1: + if ((err_cause[0] & mask) && !(err_cause[1] & mask)) + return "DMA5"; + else if (!(err_cause[0] & mask) && (err_cause[1] & mask)) + return "DMA7"; + else + return "DMA5 or DMA7"; + } + +unknown_initiator: + return "unknown initiator"; +} + +static const char *gaudi_get_razwi_initiator_name(struct hl_device *hdev, + bool is_write) +{ + u32 val, x_y, axi_id; + + val = is_write ? RREG32(mmMMU_UP_RAZWI_WRITE_ID) : + RREG32(mmMMU_UP_RAZWI_READ_ID); + x_y = val & ((RAZWI_INITIATOR_Y_MASK << RAZWI_INITIATOR_Y_SHIFT) | + (RAZWI_INITIATOR_X_MASK << RAZWI_INITIATOR_X_SHIFT)); + axi_id = val & (RAZWI_INITIATOR_AXI_ID_MASK << + RAZWI_INITIATOR_AXI_ID_SHIFT); + + switch (x_y) { + case RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC0"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) + return "NIC0"; + break; + case RAZWI_INITIATOR_ID_X_Y_TPC1: + return "TPC1"; + case RAZWI_INITIATOR_ID_X_Y_MME0_0: + case RAZWI_INITIATOR_ID_X_Y_MME0_1: + return "MME0"; + case RAZWI_INITIATOR_ID_X_Y_MME1_0: + case RAZWI_INITIATOR_ID_X_Y_MME1_1: + return "MME1"; + case RAZWI_INITIATOR_ID_X_Y_TPC2: + return "TPC2"; + case RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC3"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PCI)) + return "PCI"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_CPU)) + return "CPU"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_PSOC)) + return "PSOC"; + break; + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0: + case RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1: + return gaudi_get_razwi_initiator_dma_name(hdev, x_y, is_write); + case RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC4"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) + return "NIC1"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT)) + return "NIC2"; + break; + case RAZWI_INITIATOR_ID_X_Y_TPC5: + return "TPC5"; + case RAZWI_INITIATOR_ID_X_Y_MME2_0: + case RAZWI_INITIATOR_ID_X_Y_MME2_1: + return "MME2"; + case RAZWI_INITIATOR_ID_X_Y_MME3_0: + case RAZWI_INITIATOR_ID_X_Y_MME3_1: + return "MME3"; + case RAZWI_INITIATOR_ID_X_Y_TPC6: + return "TPC6"; + case RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5: + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_TPC)) + return "TPC7"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC)) + return "NIC4"; + if (axi_id == RAZWI_INITIATOR_ID_AXI_ID(AXI_ID_NIC_FT)) + return "NIC5"; + break; + default: + break; + } + + dev_err(hdev->dev, + "Unknown RAZWI initiator ID 0x%x [Y=%d, X=%d, AXI_ID=%d]\n", + val, + (val >> RAZWI_INITIATOR_Y_SHIFT) & RAZWI_INITIATOR_Y_MASK, + (val >> RAZWI_INITIATOR_X_SHIFT) & RAZWI_INITIATOR_X_MASK, + (val >> RAZWI_INITIATOR_AXI_ID_SHIFT) & + RAZWI_INITIATOR_AXI_ID_MASK); + + return "unknown initiator"; +} + +static void gaudi_print_razwi_info(struct hl_device *hdev) +{ + if (RREG32(mmMMU_UP_RAZWI_WRITE_VLD)) { + dev_err_ratelimited(hdev->dev, + "RAZWI event caused by illegal write of %s\n", + gaudi_get_razwi_initiator_name(hdev, true)); + WREG32(mmMMU_UP_RAZWI_WRITE_VLD, 0); + } + + if (RREG32(mmMMU_UP_RAZWI_READ_VLD)) { + dev_err_ratelimited(hdev->dev, + "RAZWI event caused by illegal read of %s\n", + gaudi_get_razwi_initiator_name(hdev, false)); + WREG32(mmMMU_UP_RAZWI_READ_VLD, 0); + } +} + +static void gaudi_print_mmu_error_info(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u64 addr; + u32 val; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + return; + + val = RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE); + if (val & MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) { + addr = val & MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK; + addr <<= 32; + addr |= RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE_VA); + + dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n", + addr); + + WREG32(mmMMU_UP_PAGE_ERROR_CAPTURE, 0); + } + + val = RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE); + if (val & MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK) { + addr = val & MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK; + addr <<= 32; + addr |= RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE_VA); + + dev_err_ratelimited(hdev->dev, + "MMU access error on va 0x%llx\n", addr); + + WREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE, 0); + } +} + +/* + * +-------------------+------------------------------------------------------+ + * | Configuration Reg | Description | + * | Address | | + * +-------------------+------------------------------------------------------+ + * | 0xF30 - 0xF3F |ECC single error indication (1 bit per memory wrapper)| + * | |0xF30 memory wrappers 31:0 (MSB to LSB) | + * | |0xF34 memory wrappers 63:32 | + * | |0xF38 memory wrappers 95:64 | + * | |0xF3C memory wrappers 127:96 | + * +-------------------+------------------------------------------------------+ + * | 0xF40 - 0xF4F |ECC double error indication (1 bit per memory wrapper)| + * | |0xF40 memory wrappers 31:0 (MSB to LSB) | + * | |0xF44 memory wrappers 63:32 | + * | |0xF48 memory wrappers 95:64 | + * | |0xF4C memory wrappers 127:96 | + * +-------------------+------------------------------------------------------+ + */ +static void gaudi_print_ecc_info_generic(struct hl_device *hdev, + const char *block_name, + u64 block_address, int num_memories, + bool derr, bool disable_clock_gating) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + int num_mem_regs = num_memories / 32 + ((num_memories % 32) ? 1 : 0); + + if (block_address >= CFG_BASE) + block_address -= CFG_BASE; + + if (derr) + block_address += GAUDI_ECC_DERR0_OFFSET; + else + block_address += GAUDI_ECC_SERR0_OFFSET; + + if (disable_clock_gating) { + mutex_lock(&gaudi->clk_gate_mutex); + hdev->asic_funcs->disable_clock_gating(hdev); + } + + switch (num_mem_regs) { + case 1: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x\n", + block_name, RREG32(block_address)); + break; + case 2: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x 0x%08x\n", + block_name, + RREG32(block_address), RREG32(block_address + 4)); + break; + case 3: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x 0x%08x 0x%08x\n", + block_name, + RREG32(block_address), RREG32(block_address + 4), + RREG32(block_address + 8)); + break; + case 4: + dev_err(hdev->dev, + "%s ECC indication: 0x%08x 0x%08x 0x%08x 0x%08x\n", + block_name, + RREG32(block_address), RREG32(block_address + 4), + RREG32(block_address + 8), RREG32(block_address + 0xc)); + break; + default: + break; + + } + + if (disable_clock_gating) { + hdev->asic_funcs->enable_clock_gating(hdev); + mutex_unlock(&gaudi->clk_gate_mutex); + } +} + +static void gaudi_handle_qman_err_generic(struct hl_device *hdev, + const char *qm_name, + u64 glbl_sts_addr, + u64 arb_err_addr) +{ + u32 i, j, glbl_sts_val, arb_err_val, glbl_sts_clr_val; + char reg_desc[32]; + + /* Iterate through all stream GLBL_STS1 registers + Lower CP */ + for (i = 0 ; i < QMAN_STREAMS + 1 ; i++) { + glbl_sts_clr_val = 0; + glbl_sts_val = RREG32(glbl_sts_addr + 4 * i); + + if (!glbl_sts_val) + continue; + + if (i == QMAN_STREAMS) + snprintf(reg_desc, ARRAY_SIZE(reg_desc), "LowerCP"); + else + snprintf(reg_desc, ARRAY_SIZE(reg_desc), "stream%u", i); + + for (j = 0 ; j < GAUDI_NUM_OF_QM_ERR_CAUSE ; j++) { + if (glbl_sts_val & BIT(j)) { + dev_err_ratelimited(hdev->dev, + "%s %s. err cause: %s\n", + qm_name, reg_desc, + gaudi_qman_error_cause[j]); + glbl_sts_clr_val |= BIT(j); + } + } + + /* Write 1 clear errors */ + WREG32(glbl_sts_addr + 4 * i, glbl_sts_clr_val); + } + + arb_err_val = RREG32(arb_err_addr); + + if (!arb_err_val) + return; + + for (j = 0 ; j < GAUDI_NUM_OF_QM_ARB_ERR_CAUSE ; j++) { + if (arb_err_val & BIT(j)) { + dev_err_ratelimited(hdev->dev, + "%s ARB_ERR. err cause: %s\n", + qm_name, + gaudi_qman_arb_error_cause[j]); + } + } +} + +static void gaudi_print_ecc_info(struct hl_device *hdev, u16 event_type) +{ + u64 block_address; + u8 index; + int num_memories; + char desc[32]; + bool derr; + bool disable_clock_gating; + + switch (event_type) { + case GAUDI_EVENT_PCIE_CORE_SERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_CORE"); + block_address = mmPCIE_CORE_BASE; + num_memories = 51; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_CORE_DERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_CORE"); + block_address = mmPCIE_CORE_BASE; + num_memories = 51; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_IF_SERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_WRAP"); + block_address = mmPCIE_WRAP_BASE; + num_memories = 11; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_IF_DERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_WRAP"); + block_address = mmPCIE_WRAP_BASE; + num_memories = 11; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_PHY_SERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_PHY"); + block_address = mmPCIE_PHY_BASE; + num_memories = 4; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PCIE_PHY_DERR: + snprintf(desc, ARRAY_SIZE(desc), "%s", "PCIE_PHY"); + block_address = mmPCIE_PHY_BASE; + num_memories = 4; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR: + index = event_type - GAUDI_EVENT_TPC0_SERR; + block_address = mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC", index); + num_memories = 90; + derr = false; + disable_clock_gating = true; + break; + case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR: + index = event_type - GAUDI_EVENT_TPC0_DERR; + block_address = + mmTPC0_CFG_BASE + index * TPC_CFG_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC", index); + num_memories = 90; + derr = true; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_ACC_SERR: + case GAUDI_EVENT_MME1_ACC_SERR: + case GAUDI_EVENT_MME2_ACC_SERR: + case GAUDI_EVENT_MME3_ACC_SERR: + index = (event_type - GAUDI_EVENT_MME0_ACC_SERR) / 4; + block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_ACC", index); + num_memories = 128; + derr = false; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_ACC_DERR: + case GAUDI_EVENT_MME1_ACC_DERR: + case GAUDI_EVENT_MME2_ACC_DERR: + case GAUDI_EVENT_MME3_ACC_DERR: + index = (event_type - GAUDI_EVENT_MME0_ACC_DERR) / 4; + block_address = mmMME0_ACC_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_ACC", index); + num_memories = 128; + derr = true; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_SBAB_SERR: + case GAUDI_EVENT_MME1_SBAB_SERR: + case GAUDI_EVENT_MME2_SBAB_SERR: + case GAUDI_EVENT_MME3_SBAB_SERR: + index = (event_type - GAUDI_EVENT_MME0_SBAB_SERR) / 4; + block_address = mmMME0_SBAB_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_SBAB", index); + num_memories = 33; + derr = false; + disable_clock_gating = true; + break; + case GAUDI_EVENT_MME0_SBAB_DERR: + case GAUDI_EVENT_MME1_SBAB_DERR: + case GAUDI_EVENT_MME2_SBAB_DERR: + case GAUDI_EVENT_MME3_SBAB_DERR: + index = (event_type - GAUDI_EVENT_MME0_SBAB_DERR) / 4; + block_address = mmMME0_SBAB_BASE + index * MME_ACC_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "MME%d_SBAB", index); + num_memories = 33; + derr = true; + disable_clock_gating = true; + break; + case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_DMA7_SERR_ECC: + index = event_type - GAUDI_EVENT_DMA0_SERR_ECC; + block_address = mmDMA0_CORE_BASE + index * DMA_CORE_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DMA%d_CORE", index); + num_memories = 16; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_DMA0_DERR_ECC ... GAUDI_EVENT_DMA7_DERR_ECC: + index = event_type - GAUDI_EVENT_DMA0_DERR_ECC; + block_address = mmDMA0_CORE_BASE + index * DMA_CORE_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "DMA%d_CORE", index); + num_memories = 16; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_CPU_IF_ECC_SERR: + block_address = mmCPU_IF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_CPU_IF_ECC_DERR: + block_address = mmCPU_IF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_MEM_SERR: + block_address = mmPSOC_GLOBAL_CONF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_MEM_DERR: + block_address = mmPSOC_GLOBAL_CONF_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 4; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_CORESIGHT_SERR: + block_address = mmPSOC_CS_TRACE_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 2; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_PSOC_CORESIGHT_DERR: + block_address = mmPSOC_CS_TRACE_BASE; + snprintf(desc, ARRAY_SIZE(desc), "%s", "CPU"); + num_memories = 2; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_SRAM0_SERR ... GAUDI_EVENT_SRAM28_SERR: + index = event_type - GAUDI_EVENT_SRAM0_SERR; + block_address = + mmSRAM_Y0_X0_BANK_BASE + index * SRAM_BANK_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "SRAM%d", index); + num_memories = 2; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_SRAM0_DERR ... GAUDI_EVENT_SRAM28_DERR: + index = event_type - GAUDI_EVENT_SRAM0_DERR; + block_address = + mmSRAM_Y0_X0_BANK_BASE + index * SRAM_BANK_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "SRAM%d", index); + num_memories = 2; + derr = true; + disable_clock_gating = false; + break; + case GAUDI_EVENT_DMA_IF0_SERR ... GAUDI_EVENT_DMA_IF3_SERR: + index = event_type - GAUDI_EVENT_DMA_IF0_SERR; + block_address = mmDMA_IF_W_S_BASE + + index * (mmDMA_IF_E_S_BASE - mmDMA_IF_W_S_BASE); + snprintf(desc, ARRAY_SIZE(desc), "DMA_IF%d", index); + num_memories = 60; + derr = false; + disable_clock_gating = false; + break; + case GAUDI_EVENT_DMA_IF0_DERR ... GAUDI_EVENT_DMA_IF3_DERR: + index = event_type - GAUDI_EVENT_DMA_IF0_DERR; + block_address = mmDMA_IF_W_S_BASE + + index * (mmDMA_IF_E_S_BASE - mmDMA_IF_W_S_BASE); + snprintf(desc, ARRAY_SIZE(desc), "DMA_IF%d", index); + derr = true; + num_memories = 60; + disable_clock_gating = false; + break; + case GAUDI_EVENT_HBM_0_SERR ... GAUDI_EVENT_HBM_3_SERR: + index = event_type - GAUDI_EVENT_HBM_0_SERR; + /* HBM Registers are at different offsets */ + block_address = mmHBM0_BASE + 0x8000 + + index * (mmHBM1_BASE - mmHBM0_BASE); + snprintf(desc, ARRAY_SIZE(desc), "HBM%d", index); + derr = false; + num_memories = 64; + disable_clock_gating = false; + break; + case GAUDI_EVENT_HBM_0_DERR ... GAUDI_EVENT_HBM_3_DERR: + index = event_type - GAUDI_EVENT_HBM_0_SERR; + /* HBM Registers are at different offsets */ + block_address = mmHBM0_BASE + 0x8000 + + index * (mmHBM1_BASE - mmHBM0_BASE); + snprintf(desc, ARRAY_SIZE(desc), "HBM%d", index); + derr = true; + num_memories = 64; + disable_clock_gating = false; + break; + default: + return; + } + + gaudi_print_ecc_info_generic(hdev, desc, block_address, num_memories, + derr, disable_clock_gating); +} + +static void gaudi_handle_qman_err(struct hl_device *hdev, u16 event_type) +{ + u64 glbl_sts_addr, arb_err_addr; + u8 index; + char desc[32]; + + switch (event_type) { + case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM: + index = event_type - GAUDI_EVENT_TPC0_QM; + glbl_sts_addr = + mmTPC0_QM_GLBL_STS1_0 + index * TPC_QMAN_OFFSET; + arb_err_addr = + mmTPC0_QM_ARB_ERR_CAUSE + index * TPC_QMAN_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "TPC_QM", index); + break; + case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM: + index = event_type - GAUDI_EVENT_MME0_QM; + glbl_sts_addr = + mmMME0_QM_GLBL_STS1_0 + index * MME_QMAN_OFFSET; + arb_err_addr = + mmMME0_QM_ARB_ERR_CAUSE + index * MME_QMAN_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "MME_QM", index); + break; + case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM: + index = event_type - GAUDI_EVENT_DMA0_QM; + glbl_sts_addr = + mmDMA0_QM_GLBL_STS1_0 + index * DMA_QMAN_OFFSET; + arb_err_addr = + mmDMA0_QM_ARB_ERR_CAUSE + index * DMA_QMAN_OFFSET; + snprintf(desc, ARRAY_SIZE(desc), "%s%d", "DMA_QM", index); + break; + default: + return; + } + + gaudi_handle_qman_err_generic(hdev, desc, glbl_sts_addr, arb_err_addr); +} + +static void gaudi_print_irq_info(struct hl_device *hdev, u16 event_type, + bool razwi) +{ + char desc[64] = ""; + + gaudi_get_event_desc(event_type, desc, sizeof(desc)); + dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n", + event_type, desc); + + gaudi_print_ecc_info(hdev, event_type); + + if (razwi) { + gaudi_print_razwi_info(hdev); + gaudi_print_mmu_error_info(hdev); + } +} + +static int gaudi_soft_reset_late_init(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + /* Unmask all IRQs since some could have been received + * during the soft reset + */ + return hl_fw_unmask_irq_arr(hdev, gaudi->events, sizeof(gaudi->events)); +} + +static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device) +{ + int ch, err = 0; + u32 base, val, val2; + + base = GAUDI_HBM_CFG_BASE + device * GAUDI_HBM_CFG_OFFSET; + for (ch = 0 ; ch < GAUDI_HBM_CHANNELS ; ch++) { + val = RREG32_MASK(base + ch * 0x1000 + 0x06C, 0x0000FFFF); + val = (val & 0xFF) | ((val >> 8) & 0xFF); + if (val) { + err = 1; + dev_err(hdev->dev, + "HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n", + device, ch * 2, val & 0x1, (val >> 1) & 0x1, + (val >> 2) & 0x1, (val >> 3) & 0x1, + (val >> 4) & 0x1); + + val2 = RREG32(base + ch * 0x1000 + 0x060); + dev_err(hdev->dev, + "HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DED_CNT=%d\n", + device, ch * 2, + RREG32(base + ch * 0x1000 + 0x064), + (val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10, + (val2 & 0xFF0000) >> 16, + (val2 & 0xFF000000) >> 24); + } + + val = RREG32_MASK(base + ch * 0x1000 + 0x07C, 0x0000FFFF); + val = (val & 0xFF) | ((val >> 8) & 0xFF); + if (val) { + err = 1; + dev_err(hdev->dev, + "HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n", + device, ch * 2 + 1, val & 0x1, (val >> 1) & 0x1, + (val >> 2) & 0x1, (val >> 3) & 0x1, + (val >> 4) & 0x1); + + val2 = RREG32(base + ch * 0x1000 + 0x070); + dev_err(hdev->dev, + "HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DED_CNT=%d\n", + device, ch * 2 + 1, + RREG32(base + ch * 0x1000 + 0x074), + (val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10, + (val2 & 0xFF0000) >> 16, + (val2 & 0xFF000000) >> 24); + } + + /* Clear interrupts */ + RMWREG32(base + (ch * 0x1000) + 0x060, 0x1C8, 0x1FF); + RMWREG32(base + (ch * 0x1000) + 0x070, 0x1C8, 0x1FF); + WREG32(base + (ch * 0x1000) + 0x06C, 0x1F1F); + WREG32(base + (ch * 0x1000) + 0x07C, 0x1F1F); + RMWREG32(base + (ch * 0x1000) + 0x060, 0x0, 0xF); + RMWREG32(base + (ch * 0x1000) + 0x070, 0x0, 0xF); + } + + val = RREG32(base + 0x8F30); + val2 = RREG32(base + 0x8F34); + if (val | val2) { + err = 1; + dev_err(hdev->dev, + "HBM %d MC SRAM SERR info: Reg 0x8F30=0x%x, Reg 0x8F34=0x%x\n", + device, val, val2); + } + val = RREG32(base + 0x8F40); + val2 = RREG32(base + 0x8F44); + if (val | val2) { + err = 1; + dev_err(hdev->dev, + "HBM %d MC SRAM DERR info: Reg 0x8F40=0x%x, Reg 0x8F44=0x%x\n", + device, val, val2); + } + + return err; +} + +static int gaudi_hbm_event_to_dev(u16 hbm_event_type) +{ + switch (hbm_event_type) { + case GAUDI_EVENT_HBM0_SPI_0: + case GAUDI_EVENT_HBM0_SPI_1: + return 0; + case GAUDI_EVENT_HBM1_SPI_0: + case GAUDI_EVENT_HBM1_SPI_1: + return 1; + case GAUDI_EVENT_HBM2_SPI_0: + case GAUDI_EVENT_HBM2_SPI_1: + return 2; + case GAUDI_EVENT_HBM3_SPI_0: + case GAUDI_EVENT_HBM3_SPI_1: + return 3; + default: + break; + } + + /* Should never happen */ + return 0; +} + +static bool gaudi_tpc_read_interrupts(struct hl_device *hdev, u8 tpc_id, + char *interrupt_name) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 tpc_offset = tpc_id * TPC_CFG_OFFSET, tpc_interrupts_cause, i; + bool soft_reset_required = false; + + /* Accessing the TPC_INTR_CAUSE registers requires disabling the clock + * gating, and thus cannot be done in ArmCP and should be done instead + * by the driver. + */ + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) & + TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK; + + for (i = 0 ; i < GAUDI_NUM_OF_TPC_INTR_CAUSE ; i++) + if (tpc_interrupts_cause & BIT(i)) { + dev_err_ratelimited(hdev->dev, + "TPC%d_%s interrupt cause: %s\n", + tpc_id, interrupt_name, + gaudi_tpc_interrupts_cause[i]); + /* If this is QM error, we need to soft-reset */ + if (i == 15) + soft_reset_required = true; + } + + /* Clear interrupts */ + WREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset, 0); + + hdev->asic_funcs->enable_clock_gating(hdev); + + mutex_unlock(&gaudi->clk_gate_mutex); + + return soft_reset_required; +} + +static int tpc_dec_event_to_tpc_id(u16 tpc_dec_event_type) +{ + return (tpc_dec_event_type - GAUDI_EVENT_TPC0_DEC) >> 1; +} + +static int tpc_krn_event_to_tpc_id(u16 tpc_dec_event_type) +{ + return (tpc_dec_event_type - GAUDI_EVENT_TPC0_KRN_ERR) / 6; +} + +static void gaudi_print_clk_change_info(struct hl_device *hdev, + u16 event_type) +{ + switch (event_type) { + case GAUDI_EVENT_FIX_POWER_ENV_S: + dev_info_ratelimited(hdev->dev, + "Clock throttling due to power consumption\n"); + break; + + case GAUDI_EVENT_FIX_POWER_ENV_E: + dev_info_ratelimited(hdev->dev, + "Power envelop is safe, back to optimal clock\n"); + break; + + case GAUDI_EVENT_FIX_THERMAL_ENV_S: + dev_info_ratelimited(hdev->dev, + "Clock throttling due to overheating\n"); + break; + + case GAUDI_EVENT_FIX_THERMAL_ENV_E: + dev_info_ratelimited(hdev->dev, + "Thermal envelop is safe, back to optimal clock\n"); + break; + + default: + dev_err(hdev->dev, "Received invalid clock change event %d\n", + event_type); + break; + } +} + +static void gaudi_handle_eqe(struct hl_device *hdev, + struct hl_eq_entry *eq_entry) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 ctl = le32_to_cpu(eq_entry->hdr.ctl); + u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK) + >> EQ_CTL_EVENT_TYPE_SHIFT); + u8 cause; + bool reset_required; + + gaudi->events_stat[event_type]++; + gaudi->events_stat_aggregate[event_type]++; + + switch (event_type) { + case GAUDI_EVENT_PCIE_CORE_DERR: + case GAUDI_EVENT_PCIE_IF_DERR: + case GAUDI_EVENT_PCIE_PHY_DERR: + case GAUDI_EVENT_TPC0_DERR ... GAUDI_EVENT_TPC7_DERR: + case GAUDI_EVENT_MME0_ACC_DERR: + case GAUDI_EVENT_MME0_SBAB_DERR: + case GAUDI_EVENT_MME1_ACC_DERR: + case GAUDI_EVENT_MME1_SBAB_DERR: + case GAUDI_EVENT_MME2_ACC_DERR: + case GAUDI_EVENT_MME2_SBAB_DERR: + case GAUDI_EVENT_MME3_ACC_DERR: + case GAUDI_EVENT_MME3_SBAB_DERR: + case GAUDI_EVENT_DMA0_DERR_ECC ... GAUDI_EVENT_DMA7_DERR_ECC: + fallthrough; + case GAUDI_EVENT_CPU_IF_ECC_DERR: + case GAUDI_EVENT_PSOC_MEM_DERR: + case GAUDI_EVENT_PSOC_CORESIGHT_DERR: + case GAUDI_EVENT_SRAM0_DERR ... GAUDI_EVENT_SRAM28_DERR: + case GAUDI_EVENT_DMA_IF0_DERR ... GAUDI_EVENT_DMA_IF3_DERR: + fallthrough; + case GAUDI_EVENT_GIC500: + case GAUDI_EVENT_HBM_0_DERR ... GAUDI_EVENT_HBM_3_DERR: + case GAUDI_EVENT_MMU_DERR: + case GAUDI_EVENT_AXI_ECC: + case GAUDI_EVENT_L2_RAM_ECC: + case GAUDI_EVENT_PLL0 ... GAUDI_EVENT_PLL17: + gaudi_print_irq_info(hdev, event_type, false); + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + break; + + case GAUDI_EVENT_HBM0_SPI_0: + case GAUDI_EVENT_HBM1_SPI_0: + case GAUDI_EVENT_HBM2_SPI_0: + case GAUDI_EVENT_HBM3_SPI_0: + gaudi_print_irq_info(hdev, event_type, false); + gaudi_hbm_read_interrupts(hdev, + gaudi_hbm_event_to_dev(event_type)); + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + break; + + case GAUDI_EVENT_HBM0_SPI_1: + case GAUDI_EVENT_HBM1_SPI_1: + case GAUDI_EVENT_HBM2_SPI_1: + case GAUDI_EVENT_HBM3_SPI_1: + gaudi_print_irq_info(hdev, event_type, false); + gaudi_hbm_read_interrupts(hdev, + gaudi_hbm_event_to_dev(event_type)); + break; + + case GAUDI_EVENT_TPC0_DEC: + case GAUDI_EVENT_TPC1_DEC: + case GAUDI_EVENT_TPC2_DEC: + case GAUDI_EVENT_TPC3_DEC: + case GAUDI_EVENT_TPC4_DEC: + case GAUDI_EVENT_TPC5_DEC: + case GAUDI_EVENT_TPC6_DEC: + case GAUDI_EVENT_TPC7_DEC: + gaudi_print_irq_info(hdev, event_type, true); + reset_required = gaudi_tpc_read_interrupts(hdev, + tpc_dec_event_to_tpc_id(event_type), + "AXI_SLV_DEC_Error"); + if (reset_required) { + dev_err(hdev->dev, "hard reset required due to %s\n", + gaudi_irq_map_table[event_type].name); + + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + } else { + hl_fw_unmask_irq(hdev, event_type); + } + break; + + case GAUDI_EVENT_TPC0_KRN_ERR: + case GAUDI_EVENT_TPC1_KRN_ERR: + case GAUDI_EVENT_TPC2_KRN_ERR: + case GAUDI_EVENT_TPC3_KRN_ERR: + case GAUDI_EVENT_TPC4_KRN_ERR: + case GAUDI_EVENT_TPC5_KRN_ERR: + case GAUDI_EVENT_TPC6_KRN_ERR: + case GAUDI_EVENT_TPC7_KRN_ERR: + gaudi_print_irq_info(hdev, event_type, true); + reset_required = gaudi_tpc_read_interrupts(hdev, + tpc_krn_event_to_tpc_id(event_type), + "KRN_ERR"); + if (reset_required) { + dev_err(hdev->dev, "hard reset required due to %s\n", + gaudi_irq_map_table[event_type].name); + + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + } else { + hl_fw_unmask_irq(hdev, event_type); + } + break; + + case GAUDI_EVENT_PCIE_CORE_SERR: + case GAUDI_EVENT_PCIE_IF_SERR: + case GAUDI_EVENT_PCIE_PHY_SERR: + case GAUDI_EVENT_TPC0_SERR ... GAUDI_EVENT_TPC7_SERR: + case GAUDI_EVENT_MME0_ACC_SERR: + case GAUDI_EVENT_MME0_SBAB_SERR: + case GAUDI_EVENT_MME1_ACC_SERR: + case GAUDI_EVENT_MME1_SBAB_SERR: + case GAUDI_EVENT_MME2_ACC_SERR: + case GAUDI_EVENT_MME2_SBAB_SERR: + case GAUDI_EVENT_MME3_ACC_SERR: + case GAUDI_EVENT_MME3_SBAB_SERR: + case GAUDI_EVENT_DMA0_SERR_ECC ... GAUDI_EVENT_DMA7_SERR_ECC: + case GAUDI_EVENT_CPU_IF_ECC_SERR: + case GAUDI_EVENT_PSOC_MEM_SERR: + case GAUDI_EVENT_PSOC_CORESIGHT_SERR: + case GAUDI_EVENT_SRAM0_SERR ... GAUDI_EVENT_SRAM28_SERR: + case GAUDI_EVENT_DMA_IF0_SERR ... GAUDI_EVENT_DMA_IF3_SERR: + case GAUDI_EVENT_HBM_0_SERR ... GAUDI_EVENT_HBM_3_SERR: + fallthrough; + case GAUDI_EVENT_MMU_SERR: + case GAUDI_EVENT_PCIE_DEC: + case GAUDI_EVENT_MME0_WBC_RSP: + case GAUDI_EVENT_MME0_SBAB0_RSP: + case GAUDI_EVENT_MME1_WBC_RSP: + case GAUDI_EVENT_MME1_SBAB0_RSP: + case GAUDI_EVENT_MME2_WBC_RSP: + case GAUDI_EVENT_MME2_SBAB0_RSP: + case GAUDI_EVENT_MME3_WBC_RSP: + case GAUDI_EVENT_MME3_SBAB0_RSP: + case GAUDI_EVENT_CPU_AXI_SPLITTER: + case GAUDI_EVENT_PSOC_AXI_DEC: + case GAUDI_EVENT_PSOC_PRSTN_FALL: + case GAUDI_EVENT_MMU_PAGE_FAULT: + case GAUDI_EVENT_MMU_WR_PERM: + case GAUDI_EVENT_RAZWI_OR_ADC: + case GAUDI_EVENT_TPC0_QM ... GAUDI_EVENT_TPC7_QM: + case GAUDI_EVENT_MME0_QM ... GAUDI_EVENT_MME2_QM: + case GAUDI_EVENT_DMA0_QM ... GAUDI_EVENT_DMA7_QM: + fallthrough; + case GAUDI_EVENT_DMA0_CORE ... GAUDI_EVENT_DMA7_CORE: + gaudi_print_irq_info(hdev, event_type, true); + gaudi_handle_qman_err(hdev, event_type); + hl_fw_unmask_irq(hdev, event_type); + break; + + case GAUDI_EVENT_RAZWI_OR_ADC_SW: + gaudi_print_irq_info(hdev, event_type, true); + if (hdev->hard_reset_on_fw_events) + hl_device_reset(hdev, true, false); + break; + + case GAUDI_EVENT_TPC0_BMON_SPMU: + case GAUDI_EVENT_TPC1_BMON_SPMU: + case GAUDI_EVENT_TPC2_BMON_SPMU: + case GAUDI_EVENT_TPC3_BMON_SPMU: + case GAUDI_EVENT_TPC4_BMON_SPMU: + case GAUDI_EVENT_TPC5_BMON_SPMU: + case GAUDI_EVENT_TPC6_BMON_SPMU: + case GAUDI_EVENT_TPC7_BMON_SPMU: + case GAUDI_EVENT_DMA_BM_CH0 ... GAUDI_EVENT_DMA_BM_CH7: + gaudi_print_irq_info(hdev, event_type, false); + hl_fw_unmask_irq(hdev, event_type); + break; + + case GAUDI_EVENT_FIX_POWER_ENV_S ... GAUDI_EVENT_FIX_THERMAL_ENV_E: + gaudi_print_clk_change_info(hdev, event_type); + hl_fw_unmask_irq(hdev, event_type); + break; + + case GAUDI_EVENT_PSOC_GPIO_U16_0: + cause = le64_to_cpu(eq_entry->data[0]) & 0xFF; + dev_err(hdev->dev, + "Received high temp H/W interrupt %d (cause %d)\n", + event_type, cause); + break; + + default: + dev_err(hdev->dev, "Received invalid H/W interrupt %d\n", + event_type); + break; + } +} + +static void *gaudi_get_events_stat(struct hl_device *hdev, bool aggregate, + u32 *size) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (aggregate) { + *size = (u32) sizeof(gaudi->events_stat_aggregate); + return gaudi->events_stat_aggregate; + } + + *size = (u32) sizeof(gaudi->events_stat); + return gaudi->events_stat; +} + +static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, + u32 flags) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 status, timeout_usec; + int rc; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU) || + hdev->hard_reset_pending) + return 0; + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + mutex_lock(&hdev->mmu_cache_lock); + + /* L0 & L1 invalidation */ + WREG32(mmSTLB_INV_PS, 2); + + rc = hl_poll_timeout( + hdev, + mmSTLB_INV_PS, + status, + !status, + 1000, + timeout_usec); + + WREG32(mmSTLB_INV_SET, 0); + + mutex_unlock(&hdev->mmu_cache_lock); + + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; +} + +static int gaudi_mmu_invalidate_cache_range(struct hl_device *hdev, + bool is_hard, u32 asid, u64 va, u64 size) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u32 status, timeout_usec; + u32 inv_data; + u32 pi; + int rc; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU) || + hdev->hard_reset_pending) + return 0; + + mutex_lock(&hdev->mmu_cache_lock); + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + /* + * TODO: currently invalidate entire L0 & L1 as in regular hard + * invalidation. Need to apply invalidation of specific cache + * lines with mask of ASID & VA & size. + * Note that L1 with be flushed entirely in any case. + */ + + /* L0 & L1 invalidation */ + inv_data = RREG32(mmSTLB_CACHE_INV); + /* PI is 8 bit */ + pi = ((inv_data & STLB_CACHE_INV_PRODUCER_INDEX_MASK) + 1) & 0xFF; + WREG32(mmSTLB_CACHE_INV, + (inv_data & STLB_CACHE_INV_INDEX_MASK_MASK) | pi); + + rc = hl_poll_timeout( + hdev, + mmSTLB_INV_CONSUMER_INDEX, + status, + status == pi, + 1000, + timeout_usec); + + mutex_unlock(&hdev->mmu_cache_lock); + + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; +} + +static int gaudi_mmu_update_asid_hop0_addr(struct hl_device *hdev, + u32 asid, u64 phys_addr) +{ + u32 status, timeout_usec; + int rc; + + if (hdev->pldm) + timeout_usec = GAUDI_PLDM_MMU_TIMEOUT_USEC; + else + timeout_usec = MMU_CONFIG_TIMEOUT_USEC; + + WREG32(MMU_ASID, asid); + WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT); + WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT); + WREG32(MMU_BUSY, 0x80000000); + + rc = hl_poll_timeout( + hdev, + MMU_BUSY, + status, + !(status & 0x80000000), + 1000, + timeout_usec); + + if (rc) { + dev_err(hdev->dev, + "Timeout during MMU hop0 config of asid %d\n", asid); + return rc; + } + + return 0; +} + +static int gaudi_send_heartbeat(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_send_heartbeat(hdev); +} + +static int gaudi_armcp_info_get(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct asic_fixed_properties *prop = &hdev->asic_prop; + int rc; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + rc = hl_fw_armcp_info_get(hdev); + if (rc) + return rc; + + if (!strlen(prop->armcp_info.card_name)) + strncpy(prop->armcp_info.card_name, GAUDI_DEFAULT_CARD_NAME, + CARD_NAME_MAX_LEN); + + return 0; +} + +static bool gaudi_is_device_idle(struct hl_device *hdev, u32 *mask, + struct seq_file *s) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + const char *fmt = "%-5d%-9s%#-14x%#-12x%#x\n"; + const char *mme_slave_fmt = "%-5d%-9s%-14s%-12s%#x\n"; + u32 qm_glbl_sts0, qm_cgm_sts, dma_core_sts0, tpc_cfg_sts, mme_arch_sts; + bool is_idle = true, is_eng_idle, is_slave; + u64 offset; + int i, dma_id; + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + if (s) + seq_puts(s, + "\nDMA is_idle QM_GLBL_STS0 QM_CGM_STS DMA_CORE_STS0\n" + "--- ------- ------------ ---------- -------------\n"); + + for (i = 0 ; i < DMA_NUMBER_OF_CHNLS ; i++) { + dma_id = gaudi_dma_assignment[i]; + offset = dma_id * DMA_QMAN_OFFSET; + + qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + offset); + qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + offset); + dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + offset); + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) && + IS_DMA_IDLE(dma_core_sts0); + is_idle &= is_eng_idle; + + if (mask) + *mask |= !is_eng_idle << + (GAUDI_ENGINE_ID_DMA_0 + dma_id); + if (s) + seq_printf(s, fmt, dma_id, + is_eng_idle ? "Y" : "N", qm_glbl_sts0, + qm_cgm_sts, dma_core_sts0); + } + + if (s) + seq_puts(s, + "\nTPC is_idle QM_GLBL_STS0 QM_CGM_STS CFG_STATUS\n" + "--- ------- ------------ ---------- ----------\n"); + + for (i = 0 ; i < TPC_NUMBER_OF_ENGINES ; i++) { + offset = i * TPC_QMAN_OFFSET; + qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + offset); + qm_cgm_sts = RREG32(mmTPC0_QM_CGM_STS + offset); + tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + offset); + is_eng_idle = IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) && + IS_TPC_IDLE(tpc_cfg_sts); + is_idle &= is_eng_idle; + + if (mask) + *mask |= !is_eng_idle << (GAUDI_ENGINE_ID_TPC_0 + i); + if (s) + seq_printf(s, fmt, i, + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, qm_cgm_sts, tpc_cfg_sts); + } + + if (s) + seq_puts(s, + "\nMME is_idle QM_GLBL_STS0 QM_CGM_STS ARCH_STATUS\n" + "--- ------- ------------ ---------- -----------\n"); + + for (i = 0 ; i < MME_NUMBER_OF_ENGINES ; i++) { + offset = i * MME_QMAN_OFFSET; + mme_arch_sts = RREG32(mmMME0_CTRL_ARCH_STATUS + offset); + is_eng_idle = IS_MME_IDLE(mme_arch_sts); + + /* MME 1 & 3 are slaves, no need to check their QMANs */ + is_slave = i % 2; + if (!is_slave) { + qm_glbl_sts0 = RREG32(mmMME0_QM_GLBL_STS0 + offset); + qm_cgm_sts = RREG32(mmMME0_QM_CGM_STS + offset); + is_eng_idle &= IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts); + } + + is_idle &= is_eng_idle; + + if (mask) + *mask |= !is_eng_idle << (GAUDI_ENGINE_ID_MME_0 + i); + if (s) { + if (!is_slave) + seq_printf(s, fmt, i, + is_eng_idle ? "Y" : "N", + qm_glbl_sts0, qm_cgm_sts, mme_arch_sts); + else + seq_printf(s, mme_slave_fmt, i, + is_eng_idle ? "Y" : "N", "-", + "-", mme_arch_sts); + } + } + + if (s) + seq_puts(s, "\n"); + + hdev->asic_funcs->enable_clock_gating(hdev); + + mutex_unlock(&gaudi->clk_gate_mutex); + + return is_idle; +} + +static void gaudi_hw_queues_lock(struct hl_device *hdev) + __acquires(&gaudi->hw_queues_lock) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + spin_lock(&gaudi->hw_queues_lock); +} + +static void gaudi_hw_queues_unlock(struct hl_device *hdev) + __releases(&gaudi->hw_queues_lock) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + spin_unlock(&gaudi->hw_queues_lock); +} + +static u32 gaudi_get_pci_id(struct hl_device *hdev) +{ + return hdev->pdev->device; +} + +static int gaudi_get_eeprom_data(struct hl_device *hdev, void *data, + size_t max_size) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q)) + return 0; + + return hl_fw_get_eeprom_data(hdev, data, max_size); +} + +/* + * this function should be used only during initialization and/or after reset, + * when there are no active users. + */ +static int gaudi_run_tpc_kernel(struct hl_device *hdev, u64 tpc_kernel, + u32 tpc_id) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + u64 kernel_timeout; + u32 status, offset; + int rc; + + offset = tpc_id * (mmTPC1_CFG_STATUS - mmTPC0_CFG_STATUS); + + if (hdev->pldm) + kernel_timeout = GAUDI_PLDM_TPC_KERNEL_WAIT_USEC; + else + kernel_timeout = HL_DEVICE_TIMEOUT_USEC; + + mutex_lock(&gaudi->clk_gate_mutex); + + hdev->asic_funcs->disable_clock_gating(hdev); + + WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW + offset, + lower_32_bits(tpc_kernel)); + WREG32(mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH + offset, + upper_32_bits(tpc_kernel)); + + WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW + offset, + lower_32_bits(tpc_kernel)); + WREG32(mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH + offset, + upper_32_bits(tpc_kernel)); + /* set a valid LUT pointer, content is of no significance */ + WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO + offset, + lower_32_bits(tpc_kernel)); + WREG32(mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI + offset, + upper_32_bits(tpc_kernel)); + + WREG32(mmTPC0_CFG_QM_SYNC_OBJECT_ADDR + offset, + lower_32_bits(CFG_BASE + + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0)); + + WREG32(mmTPC0_CFG_TPC_CMD + offset, + (1 << TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT | + 1 << TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT)); + /* wait a bit for the engine to start executing */ + usleep_range(1000, 1500); + + /* wait until engine has finished executing */ + rc = hl_poll_timeout( + hdev, + mmTPC0_CFG_STATUS + offset, + status, + (status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) == + TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK, + 1000, + kernel_timeout); + + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for TPC%d icache prefetch\n", + tpc_id); + hdev->asic_funcs->enable_clock_gating(hdev); + mutex_unlock(&gaudi->clk_gate_mutex); + return -EIO; + } + + WREG32(mmTPC0_CFG_TPC_EXECUTE + offset, + 1 << TPC0_CFG_TPC_EXECUTE_V_SHIFT); + + /* wait a bit for the engine to start executing */ + usleep_range(1000, 1500); + + /* wait until engine has finished executing */ + rc = hl_poll_timeout( + hdev, + mmTPC0_CFG_STATUS + offset, + status, + (status & TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK) == + TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK, + 1000, + kernel_timeout); + + rc = hl_poll_timeout( + hdev, + mmTPC0_CFG_WQ_INFLIGHT_CNTR + offset, + status, + (status == 0), + 1000, + kernel_timeout); + + hdev->asic_funcs->enable_clock_gating(hdev); + mutex_unlock(&gaudi->clk_gate_mutex); + + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for TPC%d kernel to execute\n", + tpc_id); + return -EIO; + } + + return 0; +} + +static enum hl_device_hw_state gaudi_get_hw_state(struct hl_device *hdev) +{ + return RREG32(mmHW_STATE); +} + +static u32 gaudi_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) +{ + return gaudi_cq_assignment[cq_idx]; +} + +static void gaudi_ext_queue_init(struct hl_device *hdev, u32 q_idx) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + struct hl_hw_queue *hw_queue = &hdev->kernel_queues[q_idx]; + struct hl_hw_sob *hw_sob; + int sob, ext_idx = gaudi->ext_queue_idx++; + + /* + * The external queues might not sit sequentially, hence use the + * real external queue index for the SOB/MON base id. + */ + hw_queue->base_sob_id = ext_idx * HL_RSVD_SOBS; + hw_queue->base_mon_id = ext_idx * HL_RSVD_MONS; + hw_queue->next_sob_val = 1; + hw_queue->curr_sob_offset = 0; + + for (sob = 0 ; sob < HL_RSVD_SOBS ; sob++) { + hw_sob = &hw_queue->hw_sob[sob]; + hw_sob->hdev = hdev; + hw_sob->sob_id = hw_queue->base_sob_id + sob; + hw_sob->q_idx = q_idx; + kref_init(&hw_sob->kref); + } +} + +static void gaudi_ext_queue_reset(struct hl_device *hdev, u32 q_idx) +{ + struct hl_hw_queue *hw_queue = &hdev->kernel_queues[q_idx]; + + /* + * In case we got here due to a stuck CS, the refcnt might be bigger + * than 1 and therefore we reset it. + */ + kref_init(&hw_queue->hw_sob[hw_queue->curr_sob_offset].kref); + hw_queue->curr_sob_offset = 0; + hw_queue->next_sob_val = 1; +} + +static u32 gaudi_get_signal_cb_size(struct hl_device *hdev) +{ + return sizeof(struct packet_msg_short) + + sizeof(struct packet_msg_prot) * 2; +} + +static u32 gaudi_get_wait_cb_size(struct hl_device *hdev) +{ + return sizeof(struct packet_msg_short) * 4 + + sizeof(struct packet_fence) + + sizeof(struct packet_msg_prot) * 2; +} + +static void gaudi_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id) +{ + struct hl_cb *cb = (struct hl_cb *) data; + struct packet_msg_short *pkt; + u32 value, ctl; + + pkt = (struct packet_msg_short *) (uintptr_t) cb->kernel_address; + memset(pkt, 0, sizeof(*pkt)); + + value = 1 << GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT; /* inc by 1 */ + value |= 1 << GAUDI_PKT_SHORT_VAL_SOB_MOD_SHIFT; /* add mode */ + + ctl = (sob_id * 4) << GAUDI_PKT_SHORT_CTL_ADDR_SHIFT; /* SOB id */ + ctl |= 0 << GAUDI_PKT_SHORT_CTL_OP_SHIFT; /* write the value */ + ctl |= 3 << GAUDI_PKT_SHORT_CTL_BASE_SHIFT; /* W_S SOB base */ + ctl |= PACKET_MSG_SHORT << GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_RB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_MB_SHIFT; + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); +} + +static u32 gaudi_add_mon_msg_short(struct packet_msg_short *pkt, u32 value, + u16 addr) +{ + u32 ctl, pkt_size = sizeof(*pkt); + + memset(pkt, 0, pkt_size); + + ctl = addr << GAUDI_PKT_SHORT_CTL_ADDR_SHIFT; + ctl |= 2 << GAUDI_PKT_SHORT_CTL_BASE_SHIFT; /* W_S MON base */ + ctl |= PACKET_MSG_SHORT << GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_RB_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_MB_SHIFT; /* only last pkt needs MB */ + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static u32 gaudi_add_arm_monitor_pkt(struct packet_msg_short *pkt, u16 sob_id, + u16 sob_val, u16 addr) +{ + u32 ctl, value, pkt_size = sizeof(*pkt); + u8 mask = ~(1 << (sob_id & 0x7)); + + memset(pkt, 0, pkt_size); + + value = (sob_id / 8) << GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT; + value |= sob_val << GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT; + value |= 0 << GAUDI_PKT_SHORT_VAL_MON_MODE_SHIFT; /* GREATER_OR_EQUAL */ + value |= mask << GAUDI_PKT_SHORT_VAL_MON_MASK_SHIFT; + + ctl = addr << GAUDI_PKT_SHORT_CTL_ADDR_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_OP_SHIFT; /* write the value */ + ctl |= 2 << GAUDI_PKT_SHORT_CTL_BASE_SHIFT; /* W_S MON base */ + ctl |= PACKET_MSG_SHORT << GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT; + ctl |= 0 << GAUDI_PKT_SHORT_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_RB_SHIFT; + ctl |= 1 << GAUDI_PKT_SHORT_CTL_MB_SHIFT; + + pkt->value = cpu_to_le32(value); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static u32 gaudi_add_fence_pkt(struct packet_fence *pkt) +{ + u32 ctl, cfg, pkt_size = sizeof(*pkt); + + memset(pkt, 0, pkt_size); + + cfg = 1 << GAUDI_PKT_FENCE_CFG_DEC_VAL_SHIFT; + cfg |= 1 << GAUDI_PKT_FENCE_CFG_TARGET_VAL_SHIFT; + cfg |= 2 << GAUDI_PKT_FENCE_CFG_ID_SHIFT; + + ctl = 0 << GAUDI_PKT_FENCE_CTL_PRED_SHIFT; + ctl |= PACKET_FENCE << GAUDI_PKT_FENCE_CTL_OPCODE_SHIFT; + ctl |= 0 << GAUDI_PKT_FENCE_CTL_EB_SHIFT; + ctl |= 1 << GAUDI_PKT_FENCE_CTL_RB_SHIFT; + ctl |= 1 << GAUDI_PKT_FENCE_CTL_MB_SHIFT; + + pkt->cfg = cpu_to_le32(cfg); + pkt->ctl = cpu_to_le32(ctl); + + return pkt_size; +} + +static void gaudi_gen_wait_cb(struct hl_device *hdev, void *data, u16 sob_id, + u16 sob_val, u16 mon_id, u32 q_idx) +{ + struct hl_cb *cb = (struct hl_cb *) data; + void *buf = (void *) (uintptr_t) cb->kernel_address; + u64 monitor_base, fence_addr = 0; + u32 size = 0; + u16 msg_addr_offset; + + switch (q_idx) { + case GAUDI_QUEUE_ID_DMA_0_0: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_0; + break; + case GAUDI_QUEUE_ID_DMA_0_1: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_1; + break; + case GAUDI_QUEUE_ID_DMA_0_2: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_2; + break; + case GAUDI_QUEUE_ID_DMA_0_3: + fence_addr = mmDMA0_QM_CP_FENCE2_RDATA_3; + break; + case GAUDI_QUEUE_ID_DMA_1_0: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_0; + break; + case GAUDI_QUEUE_ID_DMA_1_1: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_1; + break; + case GAUDI_QUEUE_ID_DMA_1_2: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_2; + break; + case GAUDI_QUEUE_ID_DMA_1_3: + fence_addr = mmDMA1_QM_CP_FENCE2_RDATA_3; + break; + case GAUDI_QUEUE_ID_DMA_5_0: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_0; + break; + case GAUDI_QUEUE_ID_DMA_5_1: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_1; + break; + case GAUDI_QUEUE_ID_DMA_5_2: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_2; + break; + case GAUDI_QUEUE_ID_DMA_5_3: + fence_addr = mmDMA5_QM_CP_FENCE2_RDATA_3; + break; + default: + /* queue index should be valid here */ + dev_crit(hdev->dev, "wrong queue id %d for wait packet\n", + q_idx); + return; + } + + fence_addr += CFG_BASE; + + /* + * monitor_base should be the content of the base0 address registers, + * so it will be added to the msg short offsets + */ + monitor_base = mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0; + + /* First monitor config packet: low address of the sync */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_id * 4) - + monitor_base; + + size += gaudi_add_mon_msg_short(buf + size, (u32) fence_addr, + msg_addr_offset); + + /* Second monitor config packet: high address of the sync */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_id * 4) - + monitor_base; + + size += gaudi_add_mon_msg_short(buf + size, (u32) (fence_addr >> 32), + msg_addr_offset); + + /* + * Third monitor config packet: the payload, i.e. what to write when the + * sync triggers + */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_id * 4) - + monitor_base; + + size += gaudi_add_mon_msg_short(buf + size, 1, msg_addr_offset); + + /* Fourth monitor config packet: bind the monitor to a sync object */ + msg_addr_offset = + (mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 + mon_id * 4) - + monitor_base; + size += gaudi_add_arm_monitor_pkt(buf + size, sob_id, sob_val, + msg_addr_offset); + + /* Fence packet */ + size += gaudi_add_fence_pkt(buf + size); +} + +static void gaudi_reset_sob(struct hl_device *hdev, void *data) +{ + struct hl_hw_sob *hw_sob = (struct hl_hw_sob *) data; + + dev_dbg(hdev->dev, "reset SOB, q_idx: %d, sob_id: %d\n", hw_sob->q_idx, + hw_sob->sob_id); + + WREG32(mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 + hw_sob->sob_id * 4, + 0); + + kref_init(&hw_sob->kref); +} + +static void gaudi_set_dma_mask_from_fw(struct hl_device *hdev) +{ + if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) == + HL_POWER9_HOST_MAGIC) { + hdev->power9_64bit_dma_enable = 1; + hdev->dma_mask = 64; + } else { + hdev->power9_64bit_dma_enable = 0; + hdev->dma_mask = 48; + } +} + +static u64 gaudi_get_device_time(struct hl_device *hdev) +{ + u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32; + + return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL); +} + +static const struct hl_asic_funcs gaudi_funcs = { + .early_init = gaudi_early_init, + .early_fini = gaudi_early_fini, + .late_init = gaudi_late_init, + .late_fini = gaudi_late_fini, + .sw_init = gaudi_sw_init, + .sw_fini = gaudi_sw_fini, + .hw_init = gaudi_hw_init, + .hw_fini = gaudi_hw_fini, + .halt_engines = gaudi_halt_engines, + .suspend = gaudi_suspend, + .resume = gaudi_resume, + .cb_mmap = gaudi_cb_mmap, + .ring_doorbell = gaudi_ring_doorbell, + .pqe_write = gaudi_pqe_write, + .asic_dma_alloc_coherent = gaudi_dma_alloc_coherent, + .asic_dma_free_coherent = gaudi_dma_free_coherent, + .get_int_queue_base = gaudi_get_int_queue_base, + .test_queues = gaudi_test_queues, + .asic_dma_pool_zalloc = gaudi_dma_pool_zalloc, + .asic_dma_pool_free = gaudi_dma_pool_free, + .cpu_accessible_dma_pool_alloc = gaudi_cpu_accessible_dma_pool_alloc, + .cpu_accessible_dma_pool_free = gaudi_cpu_accessible_dma_pool_free, + .hl_dma_unmap_sg = gaudi_dma_unmap_sg, + .cs_parser = gaudi_cs_parser, + .asic_dma_map_sg = gaudi_dma_map_sg, + .get_dma_desc_list_size = gaudi_get_dma_desc_list_size, + .add_end_of_cb_packets = gaudi_add_end_of_cb_packets, + .update_eq_ci = gaudi_update_eq_ci, + .context_switch = gaudi_context_switch, + .restore_phase_topology = gaudi_restore_phase_topology, + .debugfs_read32 = gaudi_debugfs_read32, + .debugfs_write32 = gaudi_debugfs_write32, + .debugfs_read64 = gaudi_debugfs_read64, + .debugfs_write64 = gaudi_debugfs_write64, + .add_device_attr = gaudi_add_device_attr, + .handle_eqe = gaudi_handle_eqe, + .set_pll_profile = gaudi_set_pll_profile, + .get_events_stat = gaudi_get_events_stat, + .read_pte = gaudi_read_pte, + .write_pte = gaudi_write_pte, + .mmu_invalidate_cache = gaudi_mmu_invalidate_cache, + .mmu_invalidate_cache_range = gaudi_mmu_invalidate_cache_range, + .send_heartbeat = gaudi_send_heartbeat, + .enable_clock_gating = gaudi_enable_clock_gating, + .disable_clock_gating = gaudi_disable_clock_gating, + .debug_coresight = gaudi_debug_coresight, + .is_device_idle = gaudi_is_device_idle, + .soft_reset_late_init = gaudi_soft_reset_late_init, + .hw_queues_lock = gaudi_hw_queues_lock, + .hw_queues_unlock = gaudi_hw_queues_unlock, + .get_pci_id = gaudi_get_pci_id, + .get_eeprom_data = gaudi_get_eeprom_data, + .send_cpu_message = gaudi_send_cpu_message, + .get_hw_state = gaudi_get_hw_state, + .pci_bars_map = gaudi_pci_bars_map, + .set_dram_bar_base = gaudi_set_hbm_bar_base, + .init_iatu = gaudi_init_iatu, + .rreg = hl_rreg, + .wreg = hl_wreg, + .halt_coresight = gaudi_halt_coresight, + .get_clk_rate = gaudi_get_clk_rate, + .get_queue_id_for_cq = gaudi_get_queue_id_for_cq, + .read_device_fw_version = gaudi_read_device_fw_version, + .load_firmware_to_device = gaudi_load_firmware_to_device, + .load_boot_fit_to_device = gaudi_load_boot_fit_to_device, + .ext_queue_init = gaudi_ext_queue_init, + .ext_queue_reset = gaudi_ext_queue_reset, + .get_signal_cb_size = gaudi_get_signal_cb_size, + .get_wait_cb_size = gaudi_get_wait_cb_size, + .gen_signal_cb = gaudi_gen_signal_cb, + .gen_wait_cb = gaudi_gen_wait_cb, + .reset_sob = gaudi_reset_sob, + .set_dma_mask_from_fw = gaudi_set_dma_mask_from_fw, + .get_device_time = gaudi_get_device_time +}; + +/** + * gaudi_set_asic_funcs - set GAUDI function pointers + * + * @*hdev: pointer to hl_device structure + * + */ +void gaudi_set_asic_funcs(struct hl_device *hdev) +{ + hdev->asic_funcs = &gaudi_funcs; +} diff --git a/drivers/misc/habanalabs/gaudi/gaudiP.h b/drivers/misc/habanalabs/gaudi/gaudiP.h new file mode 100644 index 000000000000..a46530d375fa --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudiP.h @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDIP_H_ +#define GAUDIP_H_ + +#include <uapi/misc/habanalabs.h> +#include "habanalabs.h" +#include "include/hl_boot_if.h" +#include "include/gaudi/gaudi_packets.h" +#include "include/gaudi/gaudi.h" +#include "include/gaudi/gaudi_async_events.h" + +#define NUMBER_OF_EXT_HW_QUEUES 12 +#define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES +#define NUMBER_OF_CPU_HW_QUEUES 1 +#define NUMBER_OF_INT_HW_QUEUES 100 +#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \ + NUMBER_OF_CPU_HW_QUEUES + \ + NUMBER_OF_INT_HW_QUEUES) + +/* + * Number of MSI interrupts IDS: + * Each completion queue has 1 ID + * The event queue has 1 ID + */ +#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \ + NUMBER_OF_CPU_HW_QUEUES) + +#if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES) +#error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES" +#endif + +#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */ + +#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ + +#define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */ + +#define MAX_POWER_DEFAULT 200000 /* 200W */ + +#define GAUDI_CPU_TIMEOUT_USEC 15000000 /* 15s */ + +#define TPC_ENABLED_MASK 0xFF + +#define GAUDI_HBM_SIZE_32GB 0x800000000ull +#define GAUDI_HBM_DEVICES 4 +#define GAUDI_HBM_CHANNELS 8 +#define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE) +#define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE) + +#define DMA_MAX_TRANSFER_SIZE U32_MAX + +#define GAUDI_DEFAULT_CARD_NAME "HL2000" + +#define PCI_DMA_NUMBER_OF_CHNLS 3 +#define HBM_DMA_NUMBER_OF_CHNLS 5 +#define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \ + HBM_DMA_NUMBER_OF_CHNLS) + +#define MME_NUMBER_OF_SLAVE_ENGINES 2 +#define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \ + MME_NUMBER_OF_SLAVE_ENGINES) +#define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \ + QMAN_STREAMS) + +#define QMAN_STREAMS 4 + +#define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE) +#define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE) +#define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE) +#define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE) + +#define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE) + +#define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE) + +#define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE) + +#define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE) + +#define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE) +#define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE) + +#define NUM_OF_SOB_IN_BLOCK \ + (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \ + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2) + +#define NUM_OF_MONITORS_IN_BLOCK \ + (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \ + mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2) + + +/* DRAM Memory Map */ + +#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */ +#define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */ +#define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */ +#define RESERVED 0x04000000 /* 64MB */ + +#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE +#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE) +#define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE) + +#define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\ + RESERVED) + +#define DRAM_BASE_ADDR_USER 0x20000000 + +#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER) +#error "Driver must reserve no more than 512MB" +#endif + +/* Internal QMANs PQ sizes */ + +#define MME_QMAN_LENGTH 64 +#define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) + +#define HBM_DMA_QMAN_LENGTH 64 +#define HBM_DMA_QMAN_SIZE_IN_BYTES \ + (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) + +#define TPC_QMAN_LENGTH 64 +#define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE) + +#define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START + +/* Virtual address space */ +#define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */ +#define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */ +#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \ + VA_HOST_SPACE_START) /* 767TB */ + +#define HW_CAP_PLL 0x00000001 +#define HW_CAP_HBM 0x00000002 +#define HW_CAP_MMU 0x00000004 +#define HW_CAP_MME 0x00000008 +#define HW_CAP_CPU 0x00000010 +#define HW_CAP_PCI_DMA 0x00000020 +#define HW_CAP_MSI 0x00000040 +#define HW_CAP_CPU_Q 0x00000080 +#define HW_CAP_HBM_DMA 0x00000100 +#define HW_CAP_CLK_GATE 0x00000200 +#define HW_CAP_SRAM_SCRAMBLER 0x00000400 +#define HW_CAP_HBM_SCRAMBLER 0x00000800 + +#define HW_CAP_TPC0 0x01000000 +#define HW_CAP_TPC1 0x02000000 +#define HW_CAP_TPC2 0x04000000 +#define HW_CAP_TPC3 0x08000000 +#define HW_CAP_TPC4 0x10000000 +#define HW_CAP_TPC5 0x20000000 +#define HW_CAP_TPC6 0x40000000 +#define HW_CAP_TPC7 0x80000000 +#define HW_CAP_TPC_MASK 0xFF000000 +#define HW_CAP_TPC_SHIFT 24 + +#define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39) +#define GAUDI_PCI_TO_CPU_ADDR(addr) \ + do { \ + (addr) &= ~GENMASK_ULL(49, 39); \ + (addr) |= BIT_ULL(39); \ + } while (0) +#define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \ + do { \ + (addr) &= ~GENMASK_ULL(49, 39); \ + (addr) |= (u64) (extension) << 39; \ + } while (0) + +enum gaudi_dma_channels { + GAUDI_PCI_DMA_1, + GAUDI_PCI_DMA_2, + GAUDI_PCI_DMA_3, + GAUDI_HBM_DMA_1, + GAUDI_HBM_DMA_2, + GAUDI_HBM_DMA_3, + GAUDI_HBM_DMA_4, + GAUDI_HBM_DMA_5, + GAUDI_DMA_MAX +}; + +enum gaudi_tpc_mask { + GAUDI_TPC_MASK_TPC0 = 0x01, + GAUDI_TPC_MASK_TPC1 = 0x02, + GAUDI_TPC_MASK_TPC2 = 0x04, + GAUDI_TPC_MASK_TPC3 = 0x08, + GAUDI_TPC_MASK_TPC4 = 0x10, + GAUDI_TPC_MASK_TPC5 = 0x20, + GAUDI_TPC_MASK_TPC6 = 0x40, + GAUDI_TPC_MASK_TPC7 = 0x80, + GAUDI_TPC_MASK_ALL = 0xFF +}; + +/** + * struct gaudi_internal_qman_info - Internal QMAN information. + * @pq_kernel_addr: Kernel address of the PQ memory area in the host. + * @pq_dma_addr: DMA address of the PQ memory area in the host. + * @pq_size: Size of allocated host memory for PQ. + */ +struct gaudi_internal_qman_info { + void *pq_kernel_addr; + dma_addr_t pq_dma_addr; + size_t pq_size; +}; + +/** + * struct gaudi_device - ASIC specific manage structure. + * @armcp_info_get: get information on device from ArmCP + * @hw_queues_lock: protects the H/W queues from concurrent access. + * @clk_gate_mutex: protects code areas that require clock gating to be disabled + * temporarily + * @internal_qmans: Internal QMANs information. The array size is larger than + * the actual number of internal queues because they are not in + * consecutive order. + * @hbm_bar_cur_addr: current address of HBM PCI bar. + * @max_freq_value: current max clk frequency. + * @events: array that holds all event id's + * @events_stat: array that holds histogram of all received events. + * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset + * @hw_cap_initialized: This field contains a bit per H/W engine. When that + * engine is initialized, that bit is set by the driver to + * signal we can use this engine in later code paths. + * Each bit is cleared upon reset of its corresponding H/W + * engine. + * @multi_msi_mode: whether we are working in multi MSI single MSI mode. + * Multi MSI is possible only with IOMMU enabled. + * @ext_queue_idx: helper index for external queues initialization. + */ +struct gaudi_device { + int (*armcp_info_get)(struct hl_device *hdev); + + /* TODO: remove hw_queues_lock after moving to scheduler code */ + spinlock_t hw_queues_lock; + struct mutex clk_gate_mutex; + + struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE]; + + u64 hbm_bar_cur_addr; + u64 max_freq_value; + + u32 events[GAUDI_EVENT_SIZE]; + u32 events_stat[GAUDI_EVENT_SIZE]; + u32 events_stat_aggregate[GAUDI_EVENT_SIZE]; + u32 hw_cap_initialized; + u8 multi_msi_mode; + u8 ext_queue_idx; +}; + +void gaudi_init_security(struct hl_device *hdev); +void gaudi_add_device_attr(struct hl_device *hdev, + struct attribute_group *dev_attr_grp); +void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq); +int gaudi_debug_coresight(struct hl_device *hdev, void *data); +void gaudi_halt_coresight(struct hl_device *hdev); +int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); + +#endif /* GAUDIP_H_ */ diff --git a/drivers/misc/habanalabs/gaudi/gaudi_coresight.c b/drivers/misc/habanalabs/gaudi/gaudi_coresight.c new file mode 100644 index 000000000000..bf0e062d7b87 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi_coresight.c @@ -0,0 +1,884 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/gaudi/gaudi_coresight.h" +#include "include/gaudi/asic_reg/gaudi_regs.h" +#include "include/gaudi/gaudi_masks.h" + +#include <uapi/misc/habanalabs.h> +#include <linux/coresight.h> + +#define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET +#define SPMU_EVENT_TYPES_OFFSET 0x400 +#define SPMU_MAX_COUNTERS 6 + +static u64 debug_stm_regs[GAUDI_STM_LAST + 1] = { + [GAUDI_STM_MME0_ACC] = mmMME0_ACC_STM_BASE, + [GAUDI_STM_MME0_SBAB] = mmMME0_SBAB_STM_BASE, + [GAUDI_STM_MME0_CTRL] = mmMME0_CTRL_STM_BASE, + [GAUDI_STM_MME1_ACC] = mmMME1_ACC_STM_BASE, + [GAUDI_STM_MME1_SBAB] = mmMME1_SBAB_STM_BASE, + [GAUDI_STM_MME1_CTRL] = mmMME1_CTRL_STM_BASE, + [GAUDI_STM_MME2_ACC] = mmMME2_ACC_STM_BASE, + [GAUDI_STM_MME2_SBAB] = mmMME2_SBAB_STM_BASE, + [GAUDI_STM_MME2_CTRL] = mmMME2_CTRL_STM_BASE, + [GAUDI_STM_MME3_ACC] = mmMME3_ACC_STM_BASE, + [GAUDI_STM_MME3_SBAB] = mmMME3_SBAB_STM_BASE, + [GAUDI_STM_MME3_CTRL] = mmMME3_CTRL_STM_BASE, + [GAUDI_STM_DMA_IF_W_S] = mmDMA_IF_W_S_STM_BASE, + [GAUDI_STM_DMA_IF_E_S] = mmDMA_IF_E_S_STM_BASE, + [GAUDI_STM_DMA_IF_W_N] = mmDMA_IF_W_N_STM_BASE, + [GAUDI_STM_DMA_IF_E_N] = mmDMA_IF_E_N_STM_BASE, + [GAUDI_STM_CPU] = mmCPU_STM_BASE, + [GAUDI_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE, + [GAUDI_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE, + [GAUDI_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE, + [GAUDI_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE, + [GAUDI_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE, + [GAUDI_STM_DMA_CH_5_CS] = mmDMA_CH_5_CS_STM_BASE, + [GAUDI_STM_DMA_CH_6_CS] = mmDMA_CH_6_CS_STM_BASE, + [GAUDI_STM_DMA_CH_7_CS] = mmDMA_CH_7_CS_STM_BASE, + [GAUDI_STM_PCIE] = mmPCIE_STM_BASE, + [GAUDI_STM_MMU_CS] = mmMMU_CS_STM_BASE, + [GAUDI_STM_PSOC] = mmPSOC_STM_BASE, + [GAUDI_STM_NIC0_0] = mmSTM_0_NIC0_DBG_BASE, + [GAUDI_STM_NIC0_1] = mmSTM_1_NIC0_DBG_BASE, + [GAUDI_STM_NIC1_0] = mmSTM_0_NIC1_DBG_BASE, + [GAUDI_STM_NIC1_1] = mmSTM_1_NIC1_DBG_BASE, + [GAUDI_STM_NIC2_0] = mmSTM_0_NIC2_DBG_BASE, + [GAUDI_STM_NIC2_1] = mmSTM_1_NIC2_DBG_BASE, + [GAUDI_STM_NIC3_0] = mmSTM_0_NIC3_DBG_BASE, + [GAUDI_STM_NIC3_1] = mmSTM_1_NIC3_DBG_BASE, + [GAUDI_STM_NIC4_0] = mmSTM_0_NIC4_DBG_BASE, + [GAUDI_STM_NIC4_1] = mmSTM_1_NIC4_DBG_BASE, + [GAUDI_STM_TPC0_EML] = mmTPC0_EML_STM_BASE, + [GAUDI_STM_TPC1_EML] = mmTPC1_EML_STM_BASE, + [GAUDI_STM_TPC2_EML] = mmTPC2_EML_STM_BASE, + [GAUDI_STM_TPC3_EML] = mmTPC3_EML_STM_BASE, + [GAUDI_STM_TPC4_EML] = mmTPC4_EML_STM_BASE, + [GAUDI_STM_TPC5_EML] = mmTPC5_EML_STM_BASE, + [GAUDI_STM_TPC6_EML] = mmTPC6_EML_STM_BASE, + [GAUDI_STM_TPC7_EML] = mmTPC7_EML_STM_BASE +}; + +static u64 debug_etf_regs[GAUDI_ETF_LAST + 1] = { + [GAUDI_ETF_MME0_ACC] = mmMME0_ACC_ETF_BASE, + [GAUDI_ETF_MME0_SBAB] = mmMME0_SBAB_ETF_BASE, + [GAUDI_ETF_MME0_CTRL] = mmMME0_CTRL_ETF_BASE, + [GAUDI_ETF_MME1_ACC] = mmMME1_ACC_ETF_BASE, + [GAUDI_ETF_MME1_SBAB] = mmMME1_SBAB_ETF_BASE, + [GAUDI_ETF_MME1_CTRL] = mmMME1_CTRL_ETF_BASE, + [GAUDI_ETF_MME2_ACC] = mmMME2_MME2_ACC_ETF_BASE, + [GAUDI_ETF_MME2_SBAB] = mmMME2_SBAB_ETF_BASE, + [GAUDI_ETF_MME2_CTRL] = mmMME2_CTRL_ETF_BASE, + [GAUDI_ETF_MME3_ACC] = mmMME3_ACC_ETF_BASE, + [GAUDI_ETF_MME3_SBAB] = mmMME3_SBAB_ETF_BASE, + [GAUDI_ETF_MME3_CTRL] = mmMME3_CTRL_ETF_BASE, + [GAUDI_ETF_DMA_IF_W_S] = mmDMA_IF_W_S_ETF_BASE, + [GAUDI_ETF_DMA_IF_E_S] = mmDMA_IF_E_S_ETF_BASE, + [GAUDI_ETF_DMA_IF_W_N] = mmDMA_IF_W_N_ETF_BASE, + [GAUDI_ETF_DMA_IF_E_N] = mmDMA_IF_E_N_ETF_BASE, + [GAUDI_ETF_CPU_0] = mmCPU_ETF_0_BASE, + [GAUDI_ETF_CPU_1] = mmCPU_ETF_1_BASE, + [GAUDI_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE, + [GAUDI_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_5_CS] = mmDMA_CH_5_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_6_CS] = mmDMA_CH_6_CS_ETF_BASE, + [GAUDI_ETF_DMA_CH_7_CS] = mmDMA_CH_7_CS_ETF_BASE, + [GAUDI_ETF_PCIE] = mmPCIE_ETF_BASE, + [GAUDI_ETF_MMU_CS] = mmMMU_CS_ETF_BASE, + [GAUDI_ETF_PSOC] = mmPSOC_ETF_BASE, + [GAUDI_ETF_NIC0_0] = mmETF_0_NIC0_DBG_BASE, + [GAUDI_ETF_NIC0_1] = mmETF_1_NIC0_DBG_BASE, + [GAUDI_ETF_NIC1_0] = mmETF_0_NIC1_DBG_BASE, + [GAUDI_ETF_NIC1_1] = mmETF_1_NIC1_DBG_BASE, + [GAUDI_ETF_NIC2_0] = mmETF_0_NIC2_DBG_BASE, + [GAUDI_ETF_NIC2_1] = mmETF_1_NIC2_DBG_BASE, + [GAUDI_ETF_NIC3_0] = mmETF_0_NIC3_DBG_BASE, + [GAUDI_ETF_NIC3_1] = mmETF_1_NIC3_DBG_BASE, + [GAUDI_ETF_NIC4_0] = mmETF_0_NIC4_DBG_BASE, + [GAUDI_ETF_NIC4_1] = mmETF_1_NIC4_DBG_BASE, + [GAUDI_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE, + [GAUDI_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE, + [GAUDI_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE, + [GAUDI_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE, + [GAUDI_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE, + [GAUDI_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE, + [GAUDI_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE, + [GAUDI_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE +}; + +static u64 debug_funnel_regs[GAUDI_FUNNEL_LAST + 1] = { + [GAUDI_FUNNEL_MME0_ACC] = mmMME0_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_MME1_ACC] = mmMME1_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_MME2_ACC] = mmMME2_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_MME3_ACC] = mmMME3_ACC_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X0] = mmSRAM_Y0_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X1] = mmSRAM_Y0_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X2] = mmSRAM_Y0_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X3] = mmSRAM_Y0_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X4] = mmSRAM_Y0_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X5] = mmSRAM_Y0_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X6] = mmSRAM_Y0_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y0_X7] = mmSRAM_Y0_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X0] = mmSRAM_Y1_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X1] = mmSRAM_Y1_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X2] = mmSRAM_Y1_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X3] = mmSRAM_Y1_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X4] = mmSRAM_Y1_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X5] = mmSRAM_Y1_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X6] = mmSRAM_Y1_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y1_X7] = mmSRAM_Y1_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X0] = mmSRAM_Y2_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X1] = mmSRAM_Y2_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X2] = mmSRAM_Y2_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X3] = mmSRAM_Y2_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X4] = mmSRAM_Y2_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X5] = mmSRAM_Y2_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X6] = mmSRAM_Y2_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y2_X7] = mmSRAM_Y2_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X0] = mmSRAM_Y3_X0_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X1] = mmSRAM_Y3_X1_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X2] = mmSRAM_Y3_X2_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X4] = mmSRAM_Y3_X4_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X3] = mmSRAM_Y3_X3_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X5] = mmSRAM_Y3_X5_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X6] = mmSRAM_Y3_X6_FUNNEL_BASE, + [GAUDI_FUNNEL_SRAM_Y3_X7] = mmSRAM_Y3_X7_FUNNEL_BASE, + [GAUDI_FUNNEL_SIF_0] = mmSIF_FUNNEL_0_BASE, + [GAUDI_FUNNEL_SIF_1] = mmSIF_FUNNEL_1_BASE, + [GAUDI_FUNNEL_SIF_2] = mmSIF_FUNNEL_2_BASE, + [GAUDI_FUNNEL_SIF_3] = mmSIF_FUNNEL_3_BASE, + [GAUDI_FUNNEL_SIF_4] = mmSIF_FUNNEL_4_BASE, + [GAUDI_FUNNEL_SIF_5] = mmSIF_FUNNEL_5_BASE, + [GAUDI_FUNNEL_SIF_6] = mmSIF_FUNNEL_6_BASE, + [GAUDI_FUNNEL_SIF_7] = mmSIF_FUNNEL_7_BASE, + [GAUDI_FUNNEL_NIF_0] = mmNIF_FUNNEL_0_BASE, + [GAUDI_FUNNEL_NIF_1] = mmNIF_FUNNEL_1_BASE, + [GAUDI_FUNNEL_NIF_2] = mmNIF_FUNNEL_2_BASE, + [GAUDI_FUNNEL_NIF_3] = mmNIF_FUNNEL_3_BASE, + [GAUDI_FUNNEL_NIF_4] = mmNIF_FUNNEL_4_BASE, + [GAUDI_FUNNEL_NIF_5] = mmNIF_FUNNEL_5_BASE, + [GAUDI_FUNNEL_NIF_6] = mmNIF_FUNNEL_6_BASE, + [GAUDI_FUNNEL_NIF_7] = mmNIF_FUNNEL_7_BASE, + [GAUDI_FUNNEL_DMA_IF_W_S] = mmDMA_IF_W_S_FUNNEL_BASE, + [GAUDI_FUNNEL_DMA_IF_E_S] = mmDMA_IF_E_S_FUNNEL_BASE, + [GAUDI_FUNNEL_DMA_IF_W_N] = mmDMA_IF_W_N_FUNNEL_BASE, + [GAUDI_FUNNEL_DMA_IF_E_N] = mmDMA_IF_E_N_FUNNEL_BASE, + [GAUDI_FUNNEL_CPU] = mmCPU_FUNNEL_BASE, + [GAUDI_FUNNEL_NIC_TPC_W_S] = mmNIC_TPC_FUNNEL_W_S_BASE, + [GAUDI_FUNNEL_NIC_TPC_E_S] = mmNIC_TPC_FUNNEL_E_S_BASE, + [GAUDI_FUNNEL_NIC_TPC_W_N] = mmNIC_TPC_FUNNEL_W_N_BASE, + [GAUDI_FUNNEL_NIC_TPC_E_N] = mmNIC_TPC_FUNNEL_E_N_BASE, + [GAUDI_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE, + [GAUDI_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE, + [GAUDI_FUNNEL_NIC0] = mmFUNNEL_NIC0_DBG_BASE, + [GAUDI_FUNNEL_NIC1] = mmFUNNEL_NIC1_DBG_BASE, + [GAUDI_FUNNEL_NIC2] = mmFUNNEL_NIC2_DBG_BASE, + [GAUDI_FUNNEL_NIC3] = mmFUNNEL_NIC3_DBG_BASE, + [GAUDI_FUNNEL_NIC4] = mmFUNNEL_NIC4_DBG_BASE, + [GAUDI_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE, + [GAUDI_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE +}; + +static u64 debug_bmon_regs[GAUDI_BMON_LAST + 1] = { + [GAUDI_BMON_MME0_ACC_0] = mmMME0_ACC_BMON0_BASE, + [GAUDI_BMON_MME0_SBAB_0] = mmMME0_SBAB_BMON0_BASE, + [GAUDI_BMON_MME0_SBAB_1] = mmMME0_SBAB_BMON1_BASE, + [GAUDI_BMON_MME0_CTRL_0] = mmMME0_CTRL_BMON0_BASE, + [GAUDI_BMON_MME0_CTRL_1] = mmMME0_CTRL_BMON1_BASE, + [GAUDI_BMON_MME1_ACC_0] = mmMME1_ACC_BMON0_BASE, + [GAUDI_BMON_MME1_SBAB_0] = mmMME1_SBAB_BMON0_BASE, + [GAUDI_BMON_MME1_SBAB_1] = mmMME1_SBAB_BMON1_BASE, + [GAUDI_BMON_MME1_CTRL_0] = mmMME1_CTRL_BMON0_BASE, + [GAUDI_BMON_MME1_CTRL_1] = mmMME1_CTRL_BMON1_BASE, + [GAUDI_BMON_MME2_ACC_0] = mmMME2_ACC_BMON0_BASE, + [GAUDI_BMON_MME2_SBAB_0] = mmMME2_SBAB_BMON0_BASE, + [GAUDI_BMON_MME2_SBAB_1] = mmMME2_SBAB_BMON1_BASE, + [GAUDI_BMON_MME2_CTRL_0] = mmMME2_CTRL_BMON0_BASE, + [GAUDI_BMON_MME2_CTRL_1] = mmMME2_CTRL_BMON1_BASE, + [GAUDI_BMON_MME3_ACC_0] = mmMME3_ACC_BMON0_BASE, + [GAUDI_BMON_MME3_SBAB_0] = mmMME3_SBAB_BMON0_BASE, + [GAUDI_BMON_MME3_SBAB_1] = mmMME3_SBAB_BMON1_BASE, + [GAUDI_BMON_MME3_CTRL_0] = mmMME3_CTRL_BMON0_BASE, + [GAUDI_BMON_MME3_CTRL_1] = mmMME3_CTRL_BMON1_BASE, + [GAUDI_BMON_DMA_IF_W_S_SOB_WR] = mmDMA_IF_W_S_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_0_WR] = mmDMA_IF_W_S_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_0_RD] = mmDMA_IF_W_S_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_1_WR] = mmDMA_IF_W_S_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_S_1_RD] = mmDMA_IF_W_S_HBM1_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_SOB_WR] = mmDMA_IF_E_S_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_0_WR] = mmDMA_IF_E_S_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_0_RD] = mmDMA_IF_E_S_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_1_WR] = mmDMA_IF_E_S_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_S_1_RD] = mmDMA_IF_E_S_HBM1_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_SOB_WR] = mmDMA_IF_W_N_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM0_WR] = mmDMA_IF_W_N_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM0_RD] = mmDMA_IF_W_N_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM1_WR] = mmDMA_IF_W_N_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_W_N_HBM1_RD] = mmDMA_IF_W_N_HBM1_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_SOB_WR] = mmDMA_IF_E_N_SOB_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM0_WR] = mmDMA_IF_E_N_HBM0_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM0_RD] = mmDMA_IF_E_N_HBM0_RD_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM1_WR] = mmDMA_IF_E_N_HBM1_WR_BMON_BASE, + [GAUDI_BMON_DMA_IF_E_N_HBM1_RD] = mmDMA_IF_E_N_HBM1_RD_BMON_BASE, + [GAUDI_BMON_CPU_WR] = mmCPU_WR_BMON_BASE, + [GAUDI_BMON_CPU_RD] = mmCPU_RD_BMON_BASE, + [GAUDI_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_5_0] = mmDMA_CH_5_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_5_1] = mmDMA_CH_5_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_6_0] = mmDMA_CH_6_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_6_1] = mmDMA_CH_6_BMON_1_BASE, + [GAUDI_BMON_DMA_CH_7_0] = mmDMA_CH_7_BMON_0_BASE, + [GAUDI_BMON_DMA_CH_7_1] = mmDMA_CH_7_BMON_1_BASE, + [GAUDI_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE, + [GAUDI_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE, + [GAUDI_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE, + [GAUDI_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE, + [GAUDI_BMON_MMU_0] = mmMMU_BMON_0_BASE, + [GAUDI_BMON_MMU_1] = mmMMU_BMON_1_BASE, + [GAUDI_BMON_NIC0_0] = mmBMON0_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_1] = mmBMON1_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_2] = mmBMON2_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_3] = mmBMON3_NIC0_DBG_BASE, + [GAUDI_BMON_NIC0_4] = mmBMON4_NIC0_DBG_BASE, + [GAUDI_BMON_NIC1_0] = mmBMON0_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_1] = mmBMON1_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_2] = mmBMON2_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_3] = mmBMON3_NIC1_DBG_BASE, + [GAUDI_BMON_NIC1_4] = mmBMON4_NIC1_DBG_BASE, + [GAUDI_BMON_NIC2_0] = mmBMON0_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_1] = mmBMON1_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_2] = mmBMON2_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_3] = mmBMON3_NIC2_DBG_BASE, + [GAUDI_BMON_NIC2_4] = mmBMON4_NIC2_DBG_BASE, + [GAUDI_BMON_NIC3_0] = mmBMON0_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_1] = mmBMON1_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_2] = mmBMON2_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_3] = mmBMON3_NIC3_DBG_BASE, + [GAUDI_BMON_NIC3_4] = mmBMON4_NIC3_DBG_BASE, + [GAUDI_BMON_NIC4_0] = mmBMON0_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_1] = mmBMON1_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_2] = mmBMON2_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_3] = mmBMON3_NIC4_DBG_BASE, + [GAUDI_BMON_NIC4_4] = mmBMON4_NIC4_DBG_BASE, + [GAUDI_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE, + [GAUDI_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE, + [GAUDI_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE, + [GAUDI_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE, + [GAUDI_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE +}; + +static u64 debug_spmu_regs[GAUDI_SPMU_LAST + 1] = { + [GAUDI_SPMU_MME0_ACC] = mmMME0_ACC_SPMU_BASE, + [GAUDI_SPMU_MME0_SBAB] = mmMME0_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME0_CTRL] = mmMME0_CTRL_SPMU_BASE, + [GAUDI_SPMU_MME1_ACC] = mmMME1_ACC_SPMU_BASE, + [GAUDI_SPMU_MME1_SBAB] = mmMME1_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME1_CTRL] = mmMME1_CTRL_SPMU_BASE, + [GAUDI_SPMU_MME2_MME2_ACC] = mmMME2_ACC_SPMU_BASE, + [GAUDI_SPMU_MME2_SBAB] = mmMME2_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME2_CTRL] = mmMME2_CTRL_SPMU_BASE, + [GAUDI_SPMU_MME3_ACC] = mmMME3_ACC_SPMU_BASE, + [GAUDI_SPMU_MME3_SBAB] = mmMME3_SBAB_SPMU_BASE, + [GAUDI_SPMU_MME3_CTRL] = mmMME3_CTRL_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_5_CS] = mmDMA_CH_5_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_6_CS] = mmDMA_CH_6_CS_SPMU_BASE, + [GAUDI_SPMU_DMA_CH_7_CS] = mmDMA_CH_7_CS_SPMU_BASE, + [GAUDI_SPMU_PCIE] = mmPCIE_SPMU_BASE, + [GAUDI_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE, + [GAUDI_SPMU_NIC0_0] = mmSPMU_0_NIC0_DBG_BASE, + [GAUDI_SPMU_NIC0_1] = mmSPMU_1_NIC0_DBG_BASE, + [GAUDI_SPMU_NIC1_0] = mmSPMU_0_NIC1_DBG_BASE, + [GAUDI_SPMU_NIC1_1] = mmSPMU_1_NIC1_DBG_BASE, + [GAUDI_SPMU_NIC2_0] = mmSPMU_0_NIC2_DBG_BASE, + [GAUDI_SPMU_NIC2_1] = mmSPMU_1_NIC2_DBG_BASE, + [GAUDI_SPMU_NIC3_0] = mmSPMU_0_NIC3_DBG_BASE, + [GAUDI_SPMU_NIC3_1] = mmSPMU_1_NIC3_DBG_BASE, + [GAUDI_SPMU_NIC4_0] = mmSPMU_0_NIC4_DBG_BASE, + [GAUDI_SPMU_NIC4_1] = mmSPMU_1_NIC4_DBG_BASE, + [GAUDI_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE, + [GAUDI_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE, + [GAUDI_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE, + [GAUDI_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE, + [GAUDI_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE, + [GAUDI_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE, + [GAUDI_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE, + [GAUDI_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE +}; + +static int gaudi_coresight_timeout(struct hl_device *hdev, u64 addr, + int position, bool up) +{ + int rc; + u32 val; + + rc = hl_poll_timeout( + hdev, + addr, + val, + up ? val & BIT(position) : !(val & BIT(position)), + 1000, + CORESIGHT_TIMEOUT_USEC); + + if (rc) { + dev_err(hdev->dev, + "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n", + addr, position, up); + return -EFAULT; + } + + return 0; +} + +static int gaudi_config_stm(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_stm *input; + u64 base_reg; + int rc; + + if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { + dev_err(hdev->dev, "Invalid register index in STM\n"); + return -EINVAL; + } + + base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + 0xE80, 0x80004); + WREG32(base_reg + 0xD64, 7); + WREG32(base_reg + 0xD60, 0); + WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask)); + WREG32(base_reg + 0xD60, 1); + WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask)); + WREG32(base_reg + 0xE70, 0x10); + WREG32(base_reg + 0xE60, 0); + WREG32(base_reg + 0xE00, lower_32_bits(input->sp_mask)); + WREG32(base_reg + 0xEF4, input->id); + WREG32(base_reg + 0xDF4, 0x80); + WREG32(base_reg + 0xE8C, input->frequency); + WREG32(base_reg + 0xE90, 0x7FF); + + /* SW-2176 - SW WA for HW bug */ + if ((CFG_BASE + base_reg) >= mmDMA_CH_0_CS_STM_BASE && + (CFG_BASE + base_reg) <= mmDMA_CH_7_CS_STM_BASE) { + + WREG32(base_reg + 0xE68, 0xffff8005); + WREG32(base_reg + 0xE6C, 0x0); + } + + WREG32(base_reg + 0xE80, 0x27 | (input->id << 16)); + } else { + WREG32(base_reg + 0xE80, 4); + WREG32(base_reg + 0xD64, 0); + WREG32(base_reg + 0xD60, 1); + WREG32(base_reg + 0xD00, 0); + WREG32(base_reg + 0xD20, 0); + WREG32(base_reg + 0xD60, 0); + WREG32(base_reg + 0xE20, 0); + WREG32(base_reg + 0xE00, 0); + WREG32(base_reg + 0xDF4, 0x80); + WREG32(base_reg + 0xE70, 0); + WREG32(base_reg + 0xE60, 0); + WREG32(base_reg + 0xE64, 0); + WREG32(base_reg + 0xE8C, 0); + + rc = gaudi_coresight_timeout(hdev, base_reg + 0xE80, 23, false); + if (rc) { + dev_err(hdev->dev, + "Failed to disable STM on timeout, error %d\n", + rc); + return rc; + } + + WREG32(base_reg + 0xE80, 4); + } + + return 0; +} + +static int gaudi_config_etf(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_etf *input; + u64 base_reg; + u32 val; + int rc; + + if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { + dev_err(hdev->dev, "Invalid register index in ETF\n"); + return -EINVAL; + } + + base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); + + val = RREG32(base_reg + 0x304); + val |= 0x1000; + WREG32(base_reg + 0x304, val); + val |= 0x40; + WREG32(base_reg + 0x304, val); + + rc = gaudi_coresight_timeout(hdev, base_reg + 0x304, 6, false); + if (rc) { + dev_err(hdev->dev, + "Failed to %s ETF on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + rc = gaudi_coresight_timeout(hdev, base_reg + 0xC, 2, true); + if (rc) { + dev_err(hdev->dev, + "Failed to %s ETF on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + WREG32(base_reg + 0x20, 0); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + 0x34, 0x3FFC); + WREG32(base_reg + 0x28, input->sink_mode); + WREG32(base_reg + 0x304, 0x4001); + WREG32(base_reg + 0x308, 0xA); + WREG32(base_reg + 0x20, 1); + } else { + WREG32(base_reg + 0x34, 0); + WREG32(base_reg + 0x28, 0); + WREG32(base_reg + 0x304, 0); + } + + return 0; +} + +static bool gaudi_etr_validate_address(struct hl_device *hdev, u64 addr, + u32 size, bool *is_host) +{ + struct asic_fixed_properties *prop = &hdev->asic_prop; + struct gaudi_device *gaudi = hdev->asic_specific; + + /* maximum address length is 50 bits */ + if (addr >> 50) { + dev_err(hdev->dev, + "ETR buffer address shouldn't exceed 50 bits\n"); + return false; + } + + /* PMMU and HPMMU addresses are equal, check only one of them */ + if ((gaudi->hw_cap_initialized & HW_CAP_MMU) && + hl_mem_area_inside_range(addr, size, + prop->pmmu.start_addr, + prop->pmmu.end_addr)) { + *is_host = true; + return true; + } + + if (hl_mem_area_inside_range(addr, size, + prop->dram_user_base_address, + prop->dram_end_address)) + return true; + + if (hl_mem_area_inside_range(addr, size, + prop->sram_user_base_address, + prop->sram_end_address)) + return true; + + if (!(gaudi->hw_cap_initialized & HW_CAP_MMU)) + dev_err(hdev->dev, "ETR buffer should be in SRAM/DRAM\n"); + + return false; +} + +static int gaudi_config_etr(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_etr *input; + u64 msb; + u32 val; + int rc; + + WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK); + + val = RREG32(mmPSOC_ETR_FFCR); + val |= 0x1000; + WREG32(mmPSOC_ETR_FFCR, val); + val |= 0x40; + WREG32(mmPSOC_ETR_FFCR, val); + + rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + rc = gaudi_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true); + if (rc) { + dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", + params->enable ? "enable" : "disable", rc); + return rc; + } + + WREG32(mmPSOC_ETR_CTL, 0); + + if (params->enable) { + bool is_host = false; + + input = params->input; + + if (!input) + return -EINVAL; + + if (input->buffer_size == 0) { + dev_err(hdev->dev, + "ETR buffer size should be bigger than 0\n"); + return -EINVAL; + } + + if (!gaudi_etr_validate_address(hdev, + input->buffer_address, input->buffer_size, + &is_host)) { + dev_err(hdev->dev, "ETR buffer address is invalid\n"); + return -EINVAL; + } + + msb = upper_32_bits(input->buffer_address) >> 8; + msb &= PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK; + WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb); + + WREG32(mmPSOC_ETR_BUFWM, 0x3FFC); + WREG32(mmPSOC_ETR_RSZ, input->buffer_size); + WREG32(mmPSOC_ETR_MODE, input->sink_mode); + /* Workaround for H3 #HW-2075 bug: use small data chunks */ + WREG32(mmPSOC_ETR_AXICTL, (is_host ? 0 : 0x700) | + PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT); + WREG32(mmPSOC_ETR_DBALO, + lower_32_bits(input->buffer_address)); + WREG32(mmPSOC_ETR_DBAHI, + upper_32_bits(input->buffer_address)); + WREG32(mmPSOC_ETR_FFCR, 3); + WREG32(mmPSOC_ETR_PSCR, 0xA); + WREG32(mmPSOC_ETR_CTL, 1); + } else { + WREG32(mmPSOC_ETR_BUFWM, 0); + WREG32(mmPSOC_ETR_RSZ, 0x400); + WREG32(mmPSOC_ETR_DBALO, 0); + WREG32(mmPSOC_ETR_DBAHI, 0); + WREG32(mmPSOC_ETR_PSCR, 0); + WREG32(mmPSOC_ETR_MODE, 0); + WREG32(mmPSOC_ETR_FFCR, 0); + + if (params->output_size >= sizeof(u64)) { + u32 rwp, rwphi; + + /* + * The trace buffer address is 50 bits wide. The end of + * the buffer is set in the RWP register (lower 32 + * bits), and in the RWPHI register (upper 8 bits). + * The 10 msb of the 50-bit address are stored in a + * global configuration register. + */ + rwp = RREG32(mmPSOC_ETR_RWP); + rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff; + msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR) & + PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK; + *(u64 *) params->output = ((u64) msb << 40) | + ((u64) rwphi << 32) | rwp; + } + } + + return 0; +} + +static int gaudi_config_funnel(struct hl_device *hdev, + struct hl_debug_params *params) +{ + u64 base_reg; + + if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { + dev_err(hdev->dev, "Invalid register index in FUNNEL\n"); + return -EINVAL; + } + + base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK); + + WREG32(base_reg, params->enable ? 0x33F : 0); + + return 0; +} + +static int gaudi_config_bmon(struct hl_device *hdev, + struct hl_debug_params *params) +{ + struct hl_debug_params_bmon *input; + u64 base_reg; + + if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { + dev_err(hdev->dev, "Invalid register index in BMON\n"); + return -EINVAL; + } + + base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; + + WREG32(base_reg + 0x104, 1); + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0)); + WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0)); + WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0)); + WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0)); + WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1)); + WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1)); + WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1)); + WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1)); + WREG32(base_reg + 0x224, 0); + WREG32(base_reg + 0x234, 0); + WREG32(base_reg + 0x30C, input->bw_win); + WREG32(base_reg + 0x308, input->win_capture); + WREG32(base_reg + 0x700, 0xA000B00 | (input->id << 12)); + WREG32(base_reg + 0x708, 0xA000A00 | (input->id << 12)); + WREG32(base_reg + 0x70C, 0xA000C00 | (input->id << 12)); + WREG32(base_reg + 0x100, 0x11); + WREG32(base_reg + 0x304, 0x1); + } else { + WREG32(base_reg + 0x200, 0); + WREG32(base_reg + 0x204, 0); + WREG32(base_reg + 0x208, 0xFFFFFFFF); + WREG32(base_reg + 0x20C, 0xFFFFFFFF); + WREG32(base_reg + 0x240, 0); + WREG32(base_reg + 0x244, 0); + WREG32(base_reg + 0x248, 0xFFFFFFFF); + WREG32(base_reg + 0x24C, 0xFFFFFFFF); + WREG32(base_reg + 0x224, 0xFFFFFFFF); + WREG32(base_reg + 0x234, 0x1070F); + WREG32(base_reg + 0x30C, 0); + WREG32(base_reg + 0x308, 0xFFFF); + WREG32(base_reg + 0x700, 0xA000B00); + WREG32(base_reg + 0x708, 0xA000A00); + WREG32(base_reg + 0x70C, 0xA000C00); + WREG32(base_reg + 0x100, 1); + WREG32(base_reg + 0x304, 0); + WREG32(base_reg + 0x104, 0); + } + + return 0; +} + +static int gaudi_config_spmu(struct hl_device *hdev, + struct hl_debug_params *params) +{ + u64 base_reg; + struct hl_debug_params_spmu *input = params->input; + u64 *output; + u32 output_arr_len; + u32 events_num; + u32 overflow_idx; + u32 cycle_cnt_idx; + int i; + + if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) { + dev_err(hdev->dev, "Invalid register index in SPMU\n"); + return -EINVAL; + } + + base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE; + + if (params->enable) { + input = params->input; + + if (!input) + return -EINVAL; + + if (input->event_types_num < 3) { + dev_err(hdev->dev, + "not enough event types values for SPMU enable\n"); + return -EINVAL; + } + + if (input->event_types_num > SPMU_MAX_COUNTERS) { + dev_err(hdev->dev, + "too many event types values for SPMU enable\n"); + return -EINVAL; + } + + WREG32(base_reg + 0xE04, 0x41013046); + WREG32(base_reg + 0xE04, 0x41013040); + + for (i = 0 ; i < input->event_types_num ; i++) + WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4, + input->event_types[i]); + + WREG32(base_reg + 0xE04, 0x41013041); + WREG32(base_reg + 0xC00, 0x8000003F); + } else { + output = params->output; + output_arr_len = params->output_size / 8; + events_num = output_arr_len - 2; + overflow_idx = output_arr_len - 2; + cycle_cnt_idx = output_arr_len - 1; + + if (!output) + return -EINVAL; + + if (output_arr_len < 3) { + dev_err(hdev->dev, + "not enough values for SPMU disable\n"); + return -EINVAL; + } + + if (events_num > SPMU_MAX_COUNTERS) { + dev_err(hdev->dev, + "too many events values for SPMU disable\n"); + return -EINVAL; + } + + WREG32(base_reg + 0xE04, 0x41013040); + + for (i = 0 ; i < events_num ; i++) + output[i] = RREG32(base_reg + i * 8); + + output[overflow_idx] = RREG32(base_reg + 0xCC0); + + output[cycle_cnt_idx] = RREG32(base_reg + 0xFC); + output[cycle_cnt_idx] <<= 32; + output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8); + + WREG32(base_reg + 0xCC0, 0); + } + + return 0; +} + +int gaudi_debug_coresight(struct hl_device *hdev, void *data) +{ + struct hl_debug_params *params = data; + int rc = 0; + + switch (params->op) { + case HL_DEBUG_OP_STM: + rc = gaudi_config_stm(hdev, params); + break; + case HL_DEBUG_OP_ETF: + rc = gaudi_config_etf(hdev, params); + break; + case HL_DEBUG_OP_ETR: + rc = gaudi_config_etr(hdev, params); + break; + case HL_DEBUG_OP_FUNNEL: + rc = gaudi_config_funnel(hdev, params); + break; + case HL_DEBUG_OP_BMON: + rc = gaudi_config_bmon(hdev, params); + break; + case HL_DEBUG_OP_SPMU: + rc = gaudi_config_spmu(hdev, params); + break; + case HL_DEBUG_OP_TIMESTAMP: + /* Do nothing as this opcode is deprecated */ + break; + + default: + dev_err(hdev->dev, "Unknown coresight id %d\n", params->op); + return -EINVAL; + } + + /* Perform read from the device to flush all configuration */ + RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG); + + return rc; +} + +void gaudi_halt_coresight(struct hl_device *hdev) +{ + struct hl_debug_params params = {}; + int i, rc; + + for (i = GAUDI_ETF_FIRST ; i <= GAUDI_ETF_LAST ; i++) { + params.reg_idx = i; + rc = gaudi_config_etf(hdev, ¶ms); + if (rc) + dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i); + } + + rc = gaudi_config_etr(hdev, ¶ms); + if (rc) + dev_err(hdev->dev, "halt ETR failed, %d\n", rc); +} diff --git a/drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c b/drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c new file mode 100644 index 000000000000..6dd2c2a1cd70 --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi_hwmgr.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/gaudi/gaudi_fw_if.h" + +void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + if (freq == PLL_LAST) + hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value); +} + +int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) +{ + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, false); + + if (value < 0) { + dev_err(hdev->dev, "Failed to retrieve device max clock %ld\n", + value); + return value; + } + + *max_clk = (value / 1000 / 1000); + + value = hl_get_frequency(hdev, MME_PLL, true); + + if (value < 0) { + dev_err(hdev->dev, + "Failed to retrieve device current clock %ld\n", + value); + return value; + } + + *cur_clk = (value / 1000 / 1000); + + return 0; +} + +static ssize_t clk_max_freq_mhz_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + struct gaudi_device *gaudi = hdev->asic_specific; + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, false); + + gaudi->max_freq_value = value; + + return sprintf(buf, "%lu\n", (value / 1000 / 1000)); +} + +static ssize_t clk_max_freq_mhz_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + struct gaudi_device *gaudi = hdev->asic_specific; + int rc; + u64 value; + + if (hl_device_disabled_or_in_reset(hdev)) { + count = -ENODEV; + goto fail; + } + + rc = kstrtoull(buf, 0, &value); + if (rc) { + count = -EINVAL; + goto fail; + } + + gaudi->max_freq_value = value * 1000 * 1000; + + hl_set_frequency(hdev, MME_PLL, gaudi->max_freq_value); + +fail: + return count; +} + +static ssize_t clk_cur_freq_mhz_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hl_device *hdev = dev_get_drvdata(dev); + long value; + + if (hl_device_disabled_or_in_reset(hdev)) + return -ENODEV; + + value = hl_get_frequency(hdev, MME_PLL, true); + + return sprintf(buf, "%lu\n", (value / 1000 / 1000)); +} + +static DEVICE_ATTR_RW(clk_max_freq_mhz); +static DEVICE_ATTR_RO(clk_cur_freq_mhz); + +static struct attribute *gaudi_dev_attrs[] = { + &dev_attr_clk_max_freq_mhz.attr, + &dev_attr_clk_cur_freq_mhz.attr, + NULL, +}; + +void gaudi_add_device_attr(struct hl_device *hdev, + struct attribute_group *dev_attr_grp) +{ + dev_attr_grp->attrs = gaudi_dev_attrs; +} diff --git a/drivers/misc/habanalabs/gaudi/gaudi_security.c b/drivers/misc/habanalabs/gaudi/gaudi_security.c new file mode 100644 index 000000000000..6a351e31fa6a --- /dev/null +++ b/drivers/misc/habanalabs/gaudi/gaudi_security.c @@ -0,0 +1,9090 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + */ + +#include "gaudiP.h" +#include "include/gaudi/asic_reg/gaudi_regs.h" + +#define GAUDI_NUMBER_OF_RR_REGS 24 +#define GAUDI_NUMBER_OF_LBW_RANGES 12 + +static u64 gaudi_rr_lbw_hit_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_HIT_WPROT, + mmDMA_IF_W_S_DMA1_HIT_WPROT, + mmDMA_IF_E_S_DMA0_HIT_WPROT, + mmDMA_IF_E_S_DMA1_HIT_WPROT, + mmDMA_IF_W_N_DMA0_HIT_WPROT, + mmDMA_IF_W_N_DMA1_HIT_WPROT, + mmDMA_IF_E_N_DMA0_HIT_WPROT, + mmDMA_IF_E_N_DMA1_HIT_WPROT, + mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW, + mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW, + mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW, +}; + +static u64 gaudi_rr_lbw_hit_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_HIT_RPROT, + mmDMA_IF_W_S_DMA1_HIT_RPROT, + mmDMA_IF_E_S_DMA0_HIT_RPROT, + mmDMA_IF_E_S_DMA1_HIT_RPROT, + mmDMA_IF_W_N_DMA0_HIT_RPROT, + mmDMA_IF_W_N_DMA1_HIT_RPROT, + mmDMA_IF_E_N_DMA0_HIT_RPROT, + mmDMA_IF_E_N_DMA1_HIT_RPROT, + mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR, + mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR, + mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR, +}; + +static u64 gaudi_rr_lbw_min_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MIN_WPROT_0, + mmDMA_IF_W_S_DMA1_MIN_WPROT_0, + mmDMA_IF_E_S_DMA0_MIN_WPROT_0, + mmDMA_IF_E_S_DMA1_MIN_WPROT_0, + mmDMA_IF_W_N_DMA0_MIN_WPROT_0, + mmDMA_IF_W_N_DMA1_MIN_WPROT_0, + mmDMA_IF_E_N_DMA0_MIN_WPROT_0, + mmDMA_IF_E_N_DMA1_MIN_WPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0, +}; + +static u64 gaudi_rr_lbw_max_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MAX_WPROT_0, + mmDMA_IF_W_S_DMA1_MAX_WPROT_0, + mmDMA_IF_E_S_DMA0_MAX_WPROT_0, + mmDMA_IF_E_S_DMA1_MAX_WPROT_0, + mmDMA_IF_W_N_DMA0_MAX_WPROT_0, + mmDMA_IF_W_N_DMA1_MAX_WPROT_0, + mmDMA_IF_E_N_DMA0_MAX_WPROT_0, + mmDMA_IF_E_N_DMA1_MAX_WPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0, +}; + +static u64 gaudi_rr_lbw_min_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MIN_RPROT_0, + mmDMA_IF_W_S_DMA1_MIN_RPROT_0, + mmDMA_IF_E_S_DMA0_MIN_RPROT_0, + mmDMA_IF_E_S_DMA1_MIN_RPROT_0, + mmDMA_IF_W_N_DMA0_MIN_RPROT_0, + mmDMA_IF_W_N_DMA1_MIN_RPROT_0, + mmDMA_IF_E_N_DMA0_MIN_RPROT_0, + mmDMA_IF_E_N_DMA1_MIN_RPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0, +}; + +static u64 gaudi_rr_lbw_max_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DMA0_MAX_RPROT_0, + mmDMA_IF_W_S_DMA1_MAX_RPROT_0, + mmDMA_IF_E_S_DMA0_MAX_RPROT_0, + mmDMA_IF_E_S_DMA1_MAX_RPROT_0, + mmDMA_IF_W_N_DMA0_MAX_RPROT_0, + mmDMA_IF_W_N_DMA1_MAX_RPROT_0, + mmDMA_IF_E_N_DMA0_MAX_RPROT_0, + mmDMA_IF_E_N_DMA1_MAX_RPROT_0, + mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0, + mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0, + mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0, +}; + +static u64 gaudi_rr_hbw_hit_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW, + mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW, + mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW +}; + +static u64 gaudi_rr_hbw_hit_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR, + mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR, + mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR +}; + +static u64 gaudi_rr_hbw_base_low_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 +}; + +static u64 gaudi_rr_hbw_base_high_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 +}; + +static u64 gaudi_rr_hbw_mask_low_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 +}; + +static u64 gaudi_rr_hbw_mask_high_aw_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 +}; + +static u64 gaudi_rr_hbw_base_low_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 +}; + +static u64 gaudi_rr_hbw_base_high_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 +}; + +static u64 gaudi_rr_hbw_mask_low_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 +}; + +static u64 gaudi_rr_hbw_mask_high_ar_regs[GAUDI_NUMBER_OF_RR_REGS] = { + mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0, + mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0, + mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0, + mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 +}; + +/** + * gaudi_set_block_as_protected - set the given block as protected + * + * @hdev: pointer to hl_device structure + * @block: block base address + * + */ +static void gaudi_pb_set_block(struct hl_device *hdev, u64 base) +{ + u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; + + while (pb_addr & 0xFFF) { + WREG32(pb_addr, 0); + pb_addr += 4; + } +} + +static void gaudi_init_mme_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + gaudi_pb_set_block(hdev, mmMME0_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME0_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME0_PRTN_BASE); + gaudi_pb_set_block(hdev, mmMME1_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME1_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME1_PRTN_BASE); + gaudi_pb_set_block(hdev, mmMME2_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME2_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME2_PRTN_BASE); + gaudi_pb_set_block(hdev, mmMME3_ACC_BASE); + gaudi_pb_set_block(hdev, mmMME3_SBAB_BASE); + gaudi_pb_set_block(hdev, mmMME3_PRTN_BASE); + + WREG32(mmMME0_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME1_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME2_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME3_CTRL_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + WREG32(mmMME0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmMME2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmMME0_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME0_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME1_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME1_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME1_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME1_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME1_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME1_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME1_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + /* MME 1 is slave, hence its whole QM block is protected (with RR) */ + + pb_addr = (mmMME2_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME2_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & + PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmMME2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME3_CTRL_RESET & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME3_CTRL_RESET & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmMME3_CTRL_RESET & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_QM_STALL & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_LOG_SHADOW & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_TH & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_MIN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_CTRL_EN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_BF16 & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_EU_POWER_SAVE_DISABLE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_CS_DBG_BLOCK_ID & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_TE_CLOSE_CGATE & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_AGU_SM_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_EZSYNC_OUT_CREDIT & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_PCU_RL_SAT_SEC & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER & 0x7F) >> 2); + mask |= 1 << ((mmMME3_CTRL_QM_SLV_LBW_CLK_EN & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmMME3_CTRL_SHADOW_0_STATUS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmMME3_CTRL_SHADOW_0_STATUS & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmMME3_CTRL_SHADOW_0_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + /* MME 3 is slave, hence its whole QM block is protected (with RR) */ +} + +static void gaudi_init_dma_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH0_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH1_BASE); + gaudi_pb_set_block(hdev, mmDMA_E_PLL_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_BASE); + + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH0_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH1_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_BASE); + + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH0_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH1_BASE); + gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_BASE); + + WREG32(mmDMA0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + WREG32(mmDMA0_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA1_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA2_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA3_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA4_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA5_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA6_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmDMA7_CORE_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmDMA0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = + ((mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA0_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA0_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA0_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA0_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA0_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA1_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA1_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA1_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA1_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA1_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA2_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA2_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA2_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA2_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA2_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA3_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA3_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA3_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA3_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA3_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA4_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA4_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA4_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA4_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA4_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA5_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA5_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA5_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA5_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA5_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA6_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA6_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA6_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA6_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA6_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_LBW_MAX_OUTSTAND & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_PROT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_SECURE_PROPS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_NON_SECURE_PROPS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_RD_MAX_OUTSTAND & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_RD_MAX_OUTSTAND & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmDMA7_CORE_RD_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_ARCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_ARUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_MAX_OUTSTAND & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_MAX_AWID & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_AWCACHE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_INFLIGHTS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERRMSG_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERRMSG_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_ERRMSG_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_STS0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_STS0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_STS1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmDMA7_CORE_RD_DBGMEM_ADD & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmDMA7_CORE_RD_DBGMEM_ADD & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmDMA7_CORE_RD_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_RD_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_HBW_AXI_AR_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_HBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_LBW_AXI_AW_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_DESC_CNT & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_STS & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_RD_DESC_ID & 0x7F) >> 2); + mask |= 1 << ((mmDMA7_CORE_DBG_WR_DESC_ID & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); +} + +static void gaudi_init_tpc_protection_bits(struct hl_device *hdev) +{ + u32 pb_addr, mask; + u8 word_offset; + + gaudi_pb_set_block(hdev, mmTPC0_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC1_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC2_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC3_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC4_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC5_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC6_E2E_CRED_BASE); + gaudi_pb_set_block(hdev, mmTPC7_E2E_CRED_BASE); + + WREG32(mmTPC0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC0_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC0_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + + mask = 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC0_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC0_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC0_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC0_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC1_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC1_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC1_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC1_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC1_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC1_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC2_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC2_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC2_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC2_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC2_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC2_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC2_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC3_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC3_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC3_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC3_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC3_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC3_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC4_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC4_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC4_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC4_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC4_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC4_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC4_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC5_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC5_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC5_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC5_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC5_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC5_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC5_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC6_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC6_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC6_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC6_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + + mask = 1 << ((mmTPC6_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC6_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC6_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC6_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + WREG32(mmTPC7_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + WREG32(mmTPC7_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0); + + pb_addr = (mmTPC7_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_STS1_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_MSG_EN_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_PQ_BASE_HI_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_PQ_BASE_HI_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_PQ_BASE_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_SIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_PI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_CFG1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS0_3 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_PQ_STS1_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_PQ_STS1_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_PQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_PQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_STS1_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_0 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CQ_CTL_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CQ_CTL_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CQ_CTL_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CQ_CTL_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CQ_CTL_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CQ_CTL_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CQ_IFIFO_CNT_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & ~0xFFF) + + PROT_BITS_OFFS; + + word_offset = ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & PROT_BITS_OFFS) + >> 7) << 2; + + mask = 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_STS_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_STS_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CP_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_LO_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_CURRENT_INST_HI_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_2 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_BARRIER_CFG_3 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_BARRIER_CFG_3 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CP_BARRIER_CFG_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_BARRIER_CFG_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_CP_DBG_0_2 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_CP_DBG_0_2 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_CP_DBG_0_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_DBG_0_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_ARUSER_31_11_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CP_AWUSER_31_11_4 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_CFG_0 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_CFG_0 & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_ARB_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_19 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_23 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_AVAIL_CRED_31 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & ~0xFFF) + + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 & PROT_BITS_OFFS) + >> 7) << 2; + mask = 1 << ((mmTPC7_QM_ARB_MST_QUIET_PER & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_WDT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_MAX_INFLIGHT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_31_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_STATE_STS & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_STATE_STS & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_ARB_STATE_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_CHOISE_FULLNESS_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MSG_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_ERR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_ERR_MSG_EN & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_ERR_STS_DRP & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_9 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_10 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_11 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_12 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_13 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_14 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_15 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_16 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_17 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_18 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_19 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_ARB_MST_CRED_STS_20 & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_ARB_MST_CRED_STS_20 & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_20 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_21 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_22 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_23 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_24 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_25 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_26 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_27 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_28 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_29 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_30 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_ARB_MST_CRED_STS_31 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CGM_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CGM_STS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CGM_CFG1 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_LOCAL_RANGE_BASE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_LOCAL_RANGE_BASE & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_QM_LOCAL_RANGE_BASE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_LOCAL_RANGE_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_CSMR_STRICT_PRIO_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_AXCACHE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_CFG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_WDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_RDATA & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_IND_GW_APB_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_QM_GLBL_MEM_INIT_BUSY & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_QM_GLBL_MEM_INIT_BUSY & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_ROUND_CSR & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_ROUND_CSR & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CFG_ROUND_CSR & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_PROT & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_PROT & PROT_BITS_OFFS) >> 7) << 2; + mask = 1 << ((mmTPC7_CFG_PROT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_RD_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WR_RATE_LIMIT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_CREDITS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_ARUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_ARUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_AWUSER_LO & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_AWUSER_HI & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_OPCODE_EXEC & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + + pb_addr = (mmTPC7_CFG_TSB_CFG_MAX_SIZE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & PROT_BITS_OFFS) >> 7) + << 2; + mask = 1 << ((mmTPC7_CFG_TSB_CFG_MAX_SIZE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_ADD & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_DATA_WR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_DATA_RD & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_CTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_DBGMEM_RC & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TSB_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_INFLIGHT_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_LBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_WQ_HBW_TOTAL_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_IRQ_OCCOUPY_CNTR & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); +} + +/** + * gaudi_init_protection_bits - Initialize protection bits of specific registers + * + * @hdev: pointer to hl_device structure + * + * All protection bits are 1 by default, means not protected. Need to set to 0 + * each bit that belongs to a protected register. + * + */ +static void gaudi_init_protection_bits(struct hl_device *hdev) +{ + /* + * In each 4K block of registers, the last 128 bytes are protection + * bits - total of 1024 bits, one for each register. Each bit is related + * to a specific register, by the order of the registers. + * So in order to calculate the bit that is related to a given register, + * we need to calculate its word offset and then the exact bit inside + * the word (which is 4 bytes). + * + * Register address: + * + * 31 12 11 7 6 2 1 0 + * ----------------------------------------------------------------- + * | Don't | word | bit location | 0 | + * | care | offset | inside word | | + * ----------------------------------------------------------------- + * + * Bits 7-11 represents the word offset inside the 128 bytes. + * Bits 2-6 represents the bit location inside the word. + * + * When a bit is cleared, it means the register it represents can only + * be accessed by a secured entity. When the bit is set, any entity can + * access the register. + * + * The last 4 bytes in the block of the PBs control the security of + * the PBs themselves, so they always need to be configured to be + * secured + */ + + gaudi_pb_set_block(hdev, mmIF_E_PLL_BASE); + gaudi_pb_set_block(hdev, mmMESH_W_PLL_BASE); + gaudi_pb_set_block(hdev, mmSRAM_W_PLL_BASE); + gaudi_pb_set_block(hdev, mmMESH_E_PLL_BASE); + gaudi_pb_set_block(hdev, mmSRAM_E_PLL_BASE); + + gaudi_init_dma_protection_bits(hdev); + + gaudi_init_mme_protection_bits(hdev); + + gaudi_init_tpc_protection_bits(hdev); +} + +static void gaudi_init_range_registers_lbw(struct hl_device *hdev) +{ + u32 lbw_rng_start[GAUDI_NUMBER_OF_LBW_RANGES]; + u32 lbw_rng_end[GAUDI_NUMBER_OF_LBW_RANGES]; + int i, j; + + lbw_rng_start[0] = (0xFBFE0000 & 0x3FFFFFF) - 1; + lbw_rng_end[0] = (0xFBFFF000 & 0x3FFFFFF) + 1; + + lbw_rng_start[1] = (0xFC0E8000 & 0x3FFFFFF) - 1; + lbw_rng_end[1] = (0xFC120000 & 0x3FFFFFF) + 1; + + lbw_rng_start[2] = (0xFC1E8000 & 0x3FFFFFF) - 1; + lbw_rng_end[2] = (0xFC48FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[3] = (0xFC600000 & 0x3FFFFFF) - 1; + lbw_rng_end[3] = (0xFCC48FFF & 0x3FFFFFF) + 1; + + lbw_rng_start[4] = (0xFCC4A000 & 0x3FFFFFF) - 1; + lbw_rng_end[4] = (0xFCCDFFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[5] = (0xFCCE4000 & 0x3FFFFFF) - 1; + lbw_rng_end[5] = (0xFCD1FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[6] = (0xFCD24000 & 0x3FFFFFF) - 1; + lbw_rng_end[6] = (0xFCD5FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[7] = (0xFCD64000 & 0x3FFFFFF) - 1; + lbw_rng_end[7] = (0xFCD9FFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[8] = (0xFCDA4000 & 0x3FFFFFF) - 1; + lbw_rng_end[8] = (0xFCDDFFFF & 0x3FFFFFF) + 1; + + lbw_rng_start[9] = (0xFCDE4000 & 0x3FFFFFF) - 1; + lbw_rng_end[9] = (0xFCE05FFF & 0x3FFFFFF) + 1; + + lbw_rng_start[10] = (0xFEC43000 & 0x3FFFFFF) - 1; + lbw_rng_end[10] = (0xFEC43FFF & 0x3FFFFFF) + 1; + + lbw_rng_start[11] = (0xFE484000 & 0x3FFFFFF) - 1; + lbw_rng_end[11] = (0xFE484FFF & 0x3FFFFFF) + 1; + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) { + WREG32(gaudi_rr_lbw_hit_aw_regs[i], + (1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1); + WREG32(gaudi_rr_lbw_hit_ar_regs[i], + (1 << GAUDI_NUMBER_OF_LBW_RANGES) - 1); + } + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) + for (j = 0 ; j < GAUDI_NUMBER_OF_LBW_RANGES ; j++) { + WREG32(gaudi_rr_lbw_min_aw_regs[i] + (j << 2), + lbw_rng_start[j]); + + WREG32(gaudi_rr_lbw_min_ar_regs[i] + (j << 2), + lbw_rng_start[j]); + + WREG32(gaudi_rr_lbw_max_aw_regs[i] + (j << 2), + lbw_rng_end[j]); + + WREG32(gaudi_rr_lbw_max_ar_regs[i] + (j << 2), + lbw_rng_end[j]); + } +} + +static void gaudi_init_range_registers_hbw(struct hl_device *hdev) +{ + struct gaudi_device *gaudi = hdev->asic_specific; + + u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE); + u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE); + + u32 sram_addr_lo = lower_32_bits(SRAM_BASE_ADDR); + u32 sram_addr_hi = upper_32_bits(SRAM_BASE_ADDR); + + u32 scratch_addr_lo = lower_32_bits(PSOC_SCRATCHPAD_ADDR); + u32 scratch_addr_hi = upper_32_bits(PSOC_SCRATCHPAD_ADDR); + + u32 pcie_fw_addr_lo = lower_32_bits(PCIE_FW_SRAM_ADDR); + u32 pcie_fw_addr_hi = upper_32_bits(PCIE_FW_SRAM_ADDR); + + u32 spi_addr_lo = lower_32_bits(SPI_FLASH_BASE_ADDR); + u32 spi_addr_hi = upper_32_bits(SPI_FLASH_BASE_ADDR); + + int i; + + /* Configure HBW RR: + * 1st range is the DRAM (first 512MB) + * 2nd range is the 1st 128 bytes in SRAM (for tensor DMA). This area + * is defined as read-only for user + * 3rd range is the PSOC scratch-pad + * 4th range is the PCIe F/W SRAM area + * 5th range is the SPI FLASH area + * 6th range is the host + */ + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) { + WREG32(gaudi_rr_hbw_hit_aw_regs[i], 0x1F); + WREG32(gaudi_rr_hbw_hit_ar_regs[i], 0x1D); + } + + for (i = 0 ; i < GAUDI_NUMBER_OF_RR_REGS ; i++) { + WREG32(gaudi_rr_hbw_base_low_aw_regs[i], dram_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i], dram_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i], dram_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i], dram_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i], 0xE0000000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i], 0xE0000000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i], 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i], 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 4, sram_addr_lo); + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 4, sram_addr_hi); + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 4, 0xFFFFFF80); + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 4, 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 8, scratch_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 8, scratch_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 8, scratch_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 8, scratch_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 8, 0xFFFF0000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 8, 0xFFFF0000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 8, 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 8, 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 12, pcie_fw_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 12, pcie_fw_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 12, pcie_fw_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 12, pcie_fw_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 12, 0xFFFF8000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 12, 0xFFFF8000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 12, 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 12, 0x3FFFF); + + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 16, spi_addr_lo); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 16, spi_addr_lo); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 16, spi_addr_hi); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 16, spi_addr_hi); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 16, 0xFE000000); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 16, 0xFE000000); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 16, 0x3FFFF); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 16, 0x3FFFF); + + if (gaudi->hw_cap_initialized & HW_CAP_MMU) + continue; + + /* Protect HOST */ + WREG32(gaudi_rr_hbw_base_low_aw_regs[i] + 20, 0); + WREG32(gaudi_rr_hbw_base_low_ar_regs[i] + 20, 0); + + WREG32(gaudi_rr_hbw_base_high_aw_regs[i] + 20, 0); + WREG32(gaudi_rr_hbw_base_high_ar_regs[i] + 20, 0); + + WREG32(gaudi_rr_hbw_mask_low_aw_regs[i] + 20, 0); + WREG32(gaudi_rr_hbw_mask_low_ar_regs[i] + 20, 0); + + WREG32(gaudi_rr_hbw_mask_high_aw_regs[i] + 20, 0xFFF80); + WREG32(gaudi_rr_hbw_mask_high_ar_regs[i] + 20, 0xFFF80); + } +} + +/** + * gaudi_init_security - Initialize security model + * + * @hdev: pointer to hl_device structure + * + * Initialize the security model of the device + * That includes range registers and protection bit per register + * + */ +void gaudi_init_security(struct hl_device *hdev) +{ + /* Due to H/W errata GAUDI0500, need to override default security + * property configuration of MME SBAB and ACC to be non-privileged and + * non-secured + */ + WREG32(mmMME0_SBAB_PROT, 0x2); + WREG32(mmMME0_ACC_PROT, 0x2); + WREG32(mmMME1_SBAB_PROT, 0x2); + WREG32(mmMME1_ACC_PROT, 0x2); + WREG32(mmMME2_SBAB_PROT, 0x2); + WREG32(mmMME2_ACC_PROT, 0x2); + WREG32(mmMME3_SBAB_PROT, 0x2); + WREG32(mmMME3_ACC_PROT, 0x2); + + /* On RAZWI, 0 will be returned from RR and 0xBABA0BAD from PB */ + WREG32(0xC01B28, 0x1); + + gaudi_init_range_registers_lbw(hdev); + + gaudi_init_range_registers_hbw(hdev); + + gaudi_init_protection_bits(hdev); +} diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c index 68f065607544..0d2952bb58df 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -72,7 +72,7 @@ * */ -#define GOYA_UBOOT_FW_FILE "habanalabs/goya/goya-u-boot.bin" +#define GOYA_BOOT_FIT_FILE "habanalabs/goya/goya-boot-fit.itb" #define GOYA_LINUX_FW_FILE "habanalabs/goya/goya-fit.itb" #define GOYA_MMU_REGS_NUM 63 @@ -87,6 +87,7 @@ #define GOYA_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ #define GOYA_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 100) #define GOYA_PLDM_QMAN0_TIMEOUT_USEC (HL_DEVICE_TIMEOUT_USEC * 30) +#define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC 1000000 /* 1s */ #define GOYA_QMAN0_FENCE_VAL 0xD169B243 @@ -531,7 +532,7 @@ static int goya_early_init(struct hl_device *hdev) prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID); - rc = hl_pci_init(hdev, 48); + rc = hl_pci_init(hdev); if (rc) return rc; @@ -750,6 +751,8 @@ static int goya_sw_init(struct hl_device *hdev) } spin_lock_init(&goya->hw_queues_lock); + hdev->supports_coresight = true; + hdev->supports_soft_reset = true; return 0; @@ -800,6 +803,7 @@ static void goya_init_dma_qman(struct hl_device *hdev, int dma_id, u32 so_base_lo, so_base_hi; u32 gic_base_lo, gic_base_hi; u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI); + u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN; mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0); @@ -836,7 +840,10 @@ static void goya_init_dma_qman(struct hl_device *hdev, int dma_id, else WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED); - WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, QMAN_DMA_ERR_MSG_EN); + if (hdev->stop_on_err) + dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT; + + WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg); WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE); } @@ -886,6 +893,7 @@ void goya_init_dma_qmans(struct hl_device *hdev) q = &hdev->kernel_queues[0]; for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) { + q->cq_id = q->msi_vec = i; goya_init_dma_qman(hdev, i, q->bus_address); goya_init_dma_ch(hdev, i); } @@ -2205,80 +2213,37 @@ static void goya_halt_engines(struct hl_device *hdev, bool hard_reset) } /* - * goya_push_uboot_to_device() - Push u-boot FW code to device. + * goya_load_firmware_to_device() - Load LINUX FW code to device. * @hdev: Pointer to hl_device structure. * - * Copy u-boot fw code from firmware file to SRAM BAR. + * Copy LINUX fw code from firmware file to HBM BAR. * * Return: 0 on success, non-zero for failure. */ -static int goya_push_uboot_to_device(struct hl_device *hdev) +static int goya_load_firmware_to_device(struct hl_device *hdev) { void __iomem *dst; - dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + UBOOT_FW_OFFSET; + dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; - return hl_fw_push_fw_to_device(hdev, GOYA_UBOOT_FW_FILE, dst); + return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst); } /* - * goya_push_linux_to_device() - Push LINUX FW code to device. + * goya_load_boot_fit_to_device() - Load boot fit to device. * @hdev: Pointer to hl_device structure. * - * Copy LINUX fw code from firmware file to HBM BAR. + * Copy boot fit file to SRAM BAR. * * Return: 0 on success, non-zero for failure. */ -static int goya_push_linux_to_device(struct hl_device *hdev) +static int goya_load_boot_fit_to_device(struct hl_device *hdev) { void __iomem *dst; - dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET; + dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET; - return hl_fw_push_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst); -} - -static int goya_pldm_init_cpu(struct hl_device *hdev) -{ - u32 unit_rst_val; - int rc; - - /* Must initialize SRAM scrambler before pushing u-boot to SRAM */ - goya_init_golden_registers(hdev); - - /* Put ARM cores into reset */ - WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, CPU_RESET_ASSERT); - RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); - - /* Reset the CA53 MACRO */ - unit_rst_val = RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); - WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, CA53_RESET); - RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); - WREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N, unit_rst_val); - RREG32(mmPSOC_GLOBAL_CONF_UNIT_RST_N); - - rc = goya_push_uboot_to_device(hdev); - if (rc) - return rc; - - rc = goya_push_linux_to_device(hdev); - if (rc) - return rc; - - WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); - WREG32(mmPSOC_GLOBAL_CONF_WARM_REBOOT, CPU_BOOT_STATUS_NA); - - WREG32(mmCPU_CA53_CFG_RST_ADDR_LSB_0, - lower_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET)); - WREG32(mmCPU_CA53_CFG_RST_ADDR_MSB_0, - upper_32_bits(SRAM_BASE_ADDR + UBOOT_FW_OFFSET)); - - /* Release ARM core 0 from reset */ - WREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL, - CPU_RESET_CORE0_DEASSERT); - RREG32(mmCPU_CA53_CFG_ARM_RST_CONTROL); - - return 0; + return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst); } /* @@ -2286,7 +2251,7 @@ static int goya_pldm_init_cpu(struct hl_device *hdev) * The version string should be located by that offset. */ static void goya_read_device_fw_version(struct hl_device *hdev, - enum goya_fw_component fwc) + enum hl_fw_component fwc) { const char *name; u32 ver_off; @@ -2320,10 +2285,9 @@ static void goya_read_device_fw_version(struct hl_device *hdev, } } -static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout) +static int goya_init_cpu(struct hl_device *hdev) { struct goya_device *goya = hdev->asic_specific; - u32 status; int rc; if (!hdev->cpu_enable) @@ -2342,115 +2306,15 @@ static int goya_init_cpu(struct hl_device *hdev, u32 cpu_timeout) return -EIO; } - if (hdev->pldm) { - rc = goya_pldm_init_cpu(hdev); - if (rc) - return rc; - - goto out; - } - - /* Make sure CPU boot-loader is running */ - rc = hl_poll_timeout( - hdev, - mmPSOC_GLOBAL_CONF_WARM_REBOOT, - status, - (status == CPU_BOOT_STATUS_DRAM_RDY) || - (status == CPU_BOOT_STATUS_SRAM_AVAIL), - 10000, - cpu_timeout); + rc = hl_fw_init_cpu(hdev, mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS, + mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, + mmCPU_CMD_STATUS_TO_HOST, mmCPU_BOOT_ERR0, + false, GOYA_CPU_TIMEOUT_USEC, + GOYA_BOOT_FIT_REQ_TIMEOUT_USEC); - /* Read U-Boot version now in case we will later fail */ - goya_read_device_fw_version(hdev, FW_COMP_UBOOT); - goya_read_device_fw_version(hdev, FW_COMP_PREBOOT); - - if (rc) { - dev_err(hdev->dev, "Error in ARM u-boot!"); - switch (status) { - case CPU_BOOT_STATUS_NA: - dev_err(hdev->dev, - "ARM status %d - BTL did NOT run\n", status); - break; - case CPU_BOOT_STATUS_IN_WFE: - dev_err(hdev->dev, - "ARM status %d - Inside WFE loop\n", status); - break; - case CPU_BOOT_STATUS_IN_BTL: - dev_err(hdev->dev, - "ARM status %d - Stuck in BTL\n", status); - break; - case CPU_BOOT_STATUS_IN_PREBOOT: - dev_err(hdev->dev, - "ARM status %d - Stuck in Preboot\n", status); - break; - case CPU_BOOT_STATUS_IN_SPL: - dev_err(hdev->dev, - "ARM status %d - Stuck in SPL\n", status); - break; - case CPU_BOOT_STATUS_IN_UBOOT: - dev_err(hdev->dev, - "ARM status %d - Stuck in u-boot\n", status); - break; - case CPU_BOOT_STATUS_DRAM_INIT_FAIL: - dev_err(hdev->dev, - "ARM status %d - DDR initialization failed\n", - status); - break; - case CPU_BOOT_STATUS_UBOOT_NOT_READY: - dev_err(hdev->dev, - "ARM status %d - u-boot stopped by user\n", - status); - break; - case CPU_BOOT_STATUS_TS_INIT_FAIL: - dev_err(hdev->dev, - "ARM status %d - Thermal Sensor initialization failed\n", - status); - break; - default: - dev_err(hdev->dev, - "ARM status %d - Invalid status code\n", - status); - break; - } - return -EIO; - } - - if (!hdev->fw_loading) { - dev_info(hdev->dev, "Skip loading FW\n"); - goto out; - } - - if (status == CPU_BOOT_STATUS_SRAM_AVAIL) - goto out; - - rc = goya_push_linux_to_device(hdev); if (rc) return rc; - WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_FIT_RDY); - - rc = hl_poll_timeout( - hdev, - mmPSOC_GLOBAL_CONF_WARM_REBOOT, - status, - (status == CPU_BOOT_STATUS_SRAM_AVAIL), - 10000, - cpu_timeout); - - if (rc) { - if (status == CPU_BOOT_STATUS_FIT_CORRUPTED) - dev_err(hdev->dev, - "ARM u-boot reports FIT image is corrupted\n"); - else - dev_err(hdev->dev, - "ARM Linux failed to load, %d\n", status); - WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_NA); - return -EIO; - } - - dev_info(hdev->dev, "Successfully loaded firmware to device\n"); - -out: goya->hw_cap_initialized |= HW_CAP_CPU; return 0; @@ -2565,7 +2429,7 @@ static int goya_hw_init(struct hl_device *hdev) */ WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY); - rc = goya_init_cpu(hdev, GOYA_CPU_TIMEOUT_USEC); + rc = goya_init_cpu(hdev); if (rc) { dev_err(hdev->dev, "failed to initialize CPU\n"); return rc; @@ -2684,30 +2548,6 @@ static void goya_hw_fini(struct hl_device *hdev, bool hard_reset) HW_CAP_MMU | HW_CAP_TPC_MBIST | HW_CAP_GOLDEN | HW_CAP_TPC); memset(goya->events_stat, 0, sizeof(goya->events_stat)); - - if (!hdev->pldm) { - int rc; - /* In case we are running inside VM and the VM is - * shutting down, we need to make sure CPU boot-loader - * is running before we can continue the VM shutdown. - * That is because the VM will send an FLR signal that - * we must answer - */ - dev_info(hdev->dev, - "Going to wait up to %ds for CPU boot loader\n", - GOYA_CPU_TIMEOUT_USEC / 1000 / 1000); - - rc = hl_poll_timeout( - hdev, - mmPSOC_GLOBAL_CONF_WARM_REBOOT, - status, - (status == CPU_BOOT_STATUS_DRAM_RDY), - 10000, - GOYA_CPU_TIMEOUT_USEC); - if (rc) - dev_err(hdev->dev, - "failed to wait for CPU boot loader\n"); - } } int goya_suspend(struct hl_device *hdev) @@ -3555,6 +3395,7 @@ static int goya_validate_cb(struct hl_device *hdev, */ rc = goya_validate_wreg32(hdev, parser, (struct packet_wreg32 *) user_pkt); + parser->patched_cb_size += pkt_size; break; case PACKET_WREG_BULK: @@ -4016,7 +3857,8 @@ int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser) } void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address, - u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec) + u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec, + bool eb) { struct packet_msg_prot *cq_pkt; u32 tmp; @@ -5042,7 +4884,7 @@ static void goya_mmu_prepare(struct hl_device *hdev, u32 asid) goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid); } -static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, +static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, u32 flags) { struct goya_device *goya = hdev->asic_specific; @@ -5051,11 +4893,11 @@ static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, if (!(goya->hw_cap_initialized & HW_CAP_MMU) || hdev->hard_reset_pending) - return; + return 0; /* no need in L1 only invalidation in Goya */ if (!is_hard) - return; + return 0; if (hdev->pldm) timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; @@ -5077,13 +4919,17 @@ static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, mutex_unlock(&hdev->mmu_cache_lock); - if (rc) - dev_notice_ratelimited(hdev->dev, - "Timeout when waiting for MMU cache invalidation\n"); + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; } -static void goya_mmu_invalidate_cache_range(struct hl_device *hdev, - bool is_hard, u32 asid, u64 va, u64 size) +static int goya_mmu_invalidate_cache_range(struct hl_device *hdev, + bool is_hard, u32 asid, u64 va, u64 size) { struct goya_device *goya = hdev->asic_specific; u32 status, timeout_usec, inv_data, pi; @@ -5091,11 +4937,11 @@ static void goya_mmu_invalidate_cache_range(struct hl_device *hdev, if (!(goya->hw_cap_initialized & HW_CAP_MMU) || hdev->hard_reset_pending) - return; + return 0; /* no need in L1 only invalidation in Goya */ if (!is_hard) - return; + return 0; if (hdev->pldm) timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC; @@ -5128,9 +4974,13 @@ static void goya_mmu_invalidate_cache_range(struct hl_device *hdev, mutex_unlock(&hdev->mmu_cache_lock); - if (rc) - dev_notice_ratelimited(hdev->dev, - "Timeout when waiting for MMU cache invalidation\n"); + if (rc) { + dev_err_ratelimited(hdev->dev, + "MMU cache invalidation timeout\n"); + hl_device_reset(hdev, true, false); + } + + return rc; } int goya_send_heartbeat(struct hl_device *hdev) @@ -5178,6 +5028,16 @@ int goya_armcp_info_get(struct hl_device *hdev) return 0; } +static void goya_enable_clock_gating(struct hl_device *hdev) +{ + +} + +static void goya_disable_clock_gating(struct hl_device *hdev) +{ + +} + static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask, struct seq_file *s) { @@ -5293,6 +5153,68 @@ static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev) return RREG32(mmHW_STATE); } +u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx) +{ + return cq_idx; +} + +static void goya_ext_queue_init(struct hl_device *hdev, u32 q_idx) +{ + +} + +static void goya_ext_queue_reset(struct hl_device *hdev, u32 q_idx) +{ + +} + +static u32 goya_get_signal_cb_size(struct hl_device *hdev) +{ + return 0; +} + +static u32 goya_get_wait_cb_size(struct hl_device *hdev) +{ + return 0; +} + +static void goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id) +{ + +} + +static void goya_gen_wait_cb(struct hl_device *hdev, void *data, u16 sob_id, + u16 sob_val, u16 mon_id, u32 q_idx) +{ + +} + +static void goya_reset_sob(struct hl_device *hdev, void *data) +{ + +} + +static void goya_set_dma_mask_from_fw(struct hl_device *hdev) +{ + if (RREG32(mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0) == + HL_POWER9_HOST_MAGIC) { + dev_dbg(hdev->dev, "Working in 64-bit DMA mode\n"); + hdev->power9_64bit_dma_enable = 1; + hdev->dma_mask = 64; + } else { + dev_dbg(hdev->dev, "Working in 48-bit DMA mode\n"); + hdev->power9_64bit_dma_enable = 0; + hdev->dma_mask = 48; + } +} + +u64 goya_get_device_time(struct hl_device *hdev) +{ + u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32; + + return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL); +} + static const struct hl_asic_funcs goya_funcs = { .early_init = goya_early_init, .early_fini = goya_early_fini, @@ -5337,6 +5259,8 @@ static const struct hl_asic_funcs goya_funcs = { .mmu_invalidate_cache = goya_mmu_invalidate_cache, .mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range, .send_heartbeat = goya_send_heartbeat, + .enable_clock_gating = goya_enable_clock_gating, + .disable_clock_gating = goya_disable_clock_gating, .debug_coresight = goya_debug_coresight, .is_device_idle = goya_is_device_idle, .soft_reset_late_init = goya_soft_reset_late_init, @@ -5352,7 +5276,20 @@ static const struct hl_asic_funcs goya_funcs = { .rreg = hl_rreg, .wreg = hl_wreg, .halt_coresight = goya_halt_coresight, - .get_clk_rate = goya_get_clk_rate + .get_clk_rate = goya_get_clk_rate, + .get_queue_id_for_cq = goya_get_queue_id_for_cq, + .read_device_fw_version = goya_read_device_fw_version, + .load_firmware_to_device = goya_load_firmware_to_device, + .load_boot_fit_to_device = goya_load_boot_fit_to_device, + .ext_queue_init = goya_ext_queue_init, + .ext_queue_reset = goya_ext_queue_reset, + .get_signal_cb_size = goya_get_signal_cb_size, + .get_wait_cb_size = goya_get_wait_cb_size, + .gen_signal_cb = goya_gen_signal_cb, + .gen_wait_cb = goya_gen_wait_cb, + .reset_sob = goya_reset_sob, + .set_dma_mask_from_fw = goya_set_dma_mask_from_fw, + .get_device_time = goya_get_device_time }; /* diff --git a/drivers/misc/habanalabs/goya/goyaP.h b/drivers/misc/habanalabs/goya/goyaP.h index c3230cb6e25c..d36f8d90c9c9 100644 --- a/drivers/misc/habanalabs/goya/goyaP.h +++ b/drivers/misc/habanalabs/goya/goyaP.h @@ -45,7 +45,7 @@ #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */ -#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */ +#define GOYA_CPU_TIMEOUT_USEC 15000000 /* 15s */ #define TPC_ENABLED_MASK 0xFF @@ -149,11 +149,6 @@ #define HW_CAP_GOLDEN 0x00000400 #define HW_CAP_TPC 0x00000800 -enum goya_fw_component { - FW_COMP_UBOOT, - FW_COMP_PREBOOT -}; - struct goya_device { /* TODO: remove hw_queues_lock after moving to scheduler code */ spinlock_t hw_queues_lock; @@ -221,7 +216,8 @@ void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry); void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size); void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address, - u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec); + u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec, + bool eb); int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser); void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id, dma_addr_t *dma_handle, u16 *queue_len); @@ -234,5 +230,7 @@ void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev); int goya_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); +u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx); +u64 goya_get_device_time(struct hl_device *hdev); #endif /* GOYAP_H_ */ diff --git a/drivers/misc/habanalabs/goya/goya_coresight.c b/drivers/misc/habanalabs/goya/goya_coresight.c index a1bc930d904f..1258724ea510 100644 --- a/drivers/misc/habanalabs/goya/goya_coresight.c +++ b/drivers/misc/habanalabs/goya/goya_coresight.c @@ -266,7 +266,7 @@ static int goya_config_stm(struct hl_device *hdev, WREG32(base_reg + 0xDF4, 0x80); WREG32(base_reg + 0xE8C, input->frequency); WREG32(base_reg + 0xE90, 0x7FF); - WREG32(base_reg + 0xE80, 0x7 | (input->id << 16)); + WREG32(base_reg + 0xE80, 0x27 | (input->id << 16)); } else { WREG32(base_reg + 0xE80, 4); WREG32(base_reg + 0xD64, 0); diff --git a/drivers/misc/habanalabs/goya/goya_security.c b/drivers/misc/habanalabs/goya/goya_security.c index d6ec12b3e692..de8297001fea 100644 --- a/drivers/misc/habanalabs/goya/goya_security.c +++ b/drivers/misc/habanalabs/goya/goya_security.c @@ -683,7 +683,6 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask = 1 << ((mmTPC0_CFG_SEMAPHORE & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_LFSR_POLYNOM & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -695,7 +694,6 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); - mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); @@ -875,6 +873,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC1_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC1_WR_REGULATOR_BASE); + pb_addr = (mmTPC1_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC1_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC1_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -882,6 +890,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC1_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1057,6 +1069,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC2_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC2_WR_REGULATOR_BASE); + pb_addr = (mmTPC2_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC2_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC2_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1064,6 +1086,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC2_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1239,6 +1265,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC3_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC3_WR_REGULATOR_BASE); + pb_addr = (mmTPC3_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC3_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC3_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1246,6 +1282,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC3_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1421,6 +1461,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC4_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC4_WR_REGULATOR_BASE); + pb_addr = (mmTPC4_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC4_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC4_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1428,6 +1478,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC4_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1603,6 +1657,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC5_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC5_WR_REGULATOR_BASE); + pb_addr = (mmTPC5_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC5_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC5_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1610,6 +1674,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC5_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1785,6 +1853,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC6_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC6_WR_REGULATOR_BASE); + pb_addr = (mmTPC6_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC6_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC6_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1792,6 +1870,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC6_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); @@ -1967,6 +2049,16 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) goya_pb_set_block(hdev, mmTPC7_RD_REGULATOR_BASE); goya_pb_set_block(hdev, mmTPC7_WR_REGULATOR_BASE); + pb_addr = (mmTPC7_CFG_SEMAPHORE & ~0xFFF) + PROT_BITS_OFFS; + word_offset = ((mmTPC7_CFG_SEMAPHORE & PROT_BITS_OFFS) >> 7) << 2; + + mask = 1 << ((mmTPC7_CFG_SEMAPHORE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_VFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_SFLAGS & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_STATUS & 0x7F) >> 2); + + WREG32(pb_addr + word_offset, ~mask); + pb_addr = (mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & ~0xFFF) + PROT_BITS_OFFS; word_offset = ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & PROT_BITS_OFFS) >> 7) << 2; @@ -1974,6 +2066,10 @@ static void goya_init_tpc_protection_bits(struct hl_device *hdev) mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_STALL & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_MSS_CONFIG & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); + mask |= 1 << ((mmTPC7_CFG_TPC_INTR_MASK & 0x7F) >> 2); WREG32(pb_addr + word_offset, ~mask); diff --git a/drivers/misc/habanalabs/habanalabs.h b/drivers/misc/habanalabs/habanalabs.h index 31ebcf9458fe..1ecdcf8b763a 100644 --- a/drivers/misc/habanalabs/habanalabs.h +++ b/drivers/misc/habanalabs/habanalabs.h @@ -23,7 +23,9 @@ #define HL_MMAP_CB_MASK (0x8000000000000000ull >> PAGE_SHIFT) -#define HL_PENDING_RESET_PER_SEC 5 +#define HL_PENDING_RESET_PER_SEC 30 + +#define HL_HARD_RESET_MAX_TIMEOUT 120 #define HL_DEVICE_TIMEOUT_USEC 1000000 /* 1 s */ @@ -51,6 +53,14 @@ /* MMU */ #define MMU_HASH_TABLE_BITS 7 /* 1 << 7 buckets */ +#define HL_RSVD_SOBS 4 +#define HL_RSVD_MONS 2 + +#define HL_RSVD_SOBS_IN_USE 2 +#define HL_RSVD_MONS_IN_USE 1 + +#define HL_MAX_SOB_VAL (1 << 15) + /** * struct pgt_info - MMU hop page info. * @node: hash linked-list node for the pgts shadow hash of pgts. @@ -76,6 +86,16 @@ struct hl_device; struct hl_fpriv; /** + * enum hl_fw_component - F/W components to read version through registers. + * @FW_COMP_UBOOT: u-boot. + * @FW_COMP_PREBOOT: preboot. + */ +enum hl_fw_component { + FW_COMP_UBOOT, + FW_COMP_PREBOOT +}; + +/** * enum hl_queue_type - Supported QUEUE types. * @QUEUE_TYPE_NA: queue is not available. * @QUEUE_TYPE_EXT: external queue which is a DMA channel that may access the @@ -94,6 +114,26 @@ enum hl_queue_type { QUEUE_TYPE_HW }; +enum hl_cs_type { + CS_TYPE_DEFAULT, + CS_TYPE_SIGNAL, + CS_TYPE_WAIT +}; + +/* + * struct hl_hw_sob - H/W SOB info. + * @hdev: habanalabs device structure. + * @kref: refcount of this SOB. The SOB will reset once the refcount is zero. + * @sob_id: id of this SOB. + * @q_idx: the H/W queue that uses this SOB. + */ +struct hl_hw_sob { + struct hl_device *hdev; + struct kref kref; + u32 sob_id; + u32 q_idx; +}; + /** * struct hw_queue_properties - queue information. * @type: queue type. @@ -250,17 +290,23 @@ struct asic_fixed_properties { }; /** - * struct hl_dma_fence - wrapper for fence object used by command submissions. + * struct hl_cs_compl - command submission completion object. * @base_fence: kernel fence object. * @lock: spinlock to protect fence. * @hdev: habanalabs device structure. + * @hw_sob: the H/W SOB used in this signal/wait CS. * @cs_seq: command submission sequence number. + * @type: type of the CS - signal/wait. + * @sob_val: the SOB value that is used in this signal/wait CS. */ -struct hl_dma_fence { +struct hl_cs_compl { struct dma_fence base_fence; spinlock_t lock; struct hl_device *hdev; + struct hl_hw_sob *hw_sob; u64 cs_seq; + enum hl_cs_type type; + u16 sob_val; }; /* @@ -358,6 +404,7 @@ struct hl_cs_job; /** * struct hl_hw_queue - describes a H/W transport queue. + * @hw_sob: array of the used H/W SOBs by this H/W queue. * @shadow_queue: pointer to a shadow queue that holds pointers to jobs. * @queue_type: type of queue. * @kernel_address: holds the queue's kernel virtual address. @@ -365,11 +412,19 @@ struct hl_cs_job; * @pi: holds the queue's pi value. * @ci: holds the queue's ci value, AS CALCULATED BY THE DRIVER (not real ci). * @hw_queue_id: the id of the H/W queue. + * @cq_id: the id for the corresponding CQ for this H/W queue. + * @msi_vec: the IRQ number of the H/W queue. * @int_queue_len: length of internal queue (number of entries). + * @next_sob_val: the next value to use for the currently used SOB. + * @base_sob_id: the base SOB id of the SOBs used by this queue. + * @base_mon_id: the base MON id of the MONs used by this queue. * @valid: is the queue valid (we have array of 32 queues, not all of them - * exists). + * exist). + * @curr_sob_offset: the id offset to the currently used SOB from the + * HL_RSVD_SOBS that are being used by this queue. */ struct hl_hw_queue { + struct hl_hw_sob hw_sob[HL_RSVD_SOBS]; struct hl_cs_job **shadow_queue; enum hl_queue_type queue_type; u64 kernel_address; @@ -377,8 +432,14 @@ struct hl_hw_queue { u32 pi; u32 ci; u32 hw_queue_id; + u32 cq_id; + u32 msi_vec; u16 int_queue_len; + u16 next_sob_val; + u16 base_sob_id; + u16 base_mon_id; u8 valid; + u8 curr_sob_offset; }; /** @@ -517,6 +578,8 @@ enum hl_pll_frequency { * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with * ASID-VA-size mask. * @send_heartbeat: send is-alive packet to ArmCP and verify response. + * @enable_clock_gating: enable clock gating for reducing power consumption. + * @disable_clock_gating: disable clock for accessing registers on HBW. * @debug_coresight: perform certain actions on Coresight for debugging. * @is_device_idle: return true if device is idle, false otherwise. * @soft_reset_late_init: perform certain actions needed after soft reset. @@ -534,6 +597,21 @@ enum hl_pll_frequency { * @wreg: Write a register. Needed for simulator support. * @halt_coresight: stop the ETF and ETR traces. * @get_clk_rate: Retrieve the ASIC current and maximum clock rate in MHz + * @get_queue_id_for_cq: Get the H/W queue id related to the given CQ index. + * @read_device_fw_version: read the device's firmware versions that are + * contained in registers + * @load_firmware_to_device: load the firmware to the device's memory + * @load_boot_fit_to_device: load boot fit to device's memory + * @ext_queue_init: Initialize the given external queue. + * @ext_queue_reset: Reset the given external queue. + * @get_signal_cb_size: Get signal CB size. + * @get_wait_cb_size: Get wait CB size. + * @gen_signal_cb: Generate a signal CB. + * @gen_wait_cb: Generate a wait CB. + * @reset_sob: Reset a SOB. + * @set_dma_mask_from_fw: set the DMA mask in the driver according to the + * firmware configuration + * @get_device_time: Get the device time. */ struct hl_asic_funcs { int (*early_init)(struct hl_device *hdev); @@ -578,7 +656,8 @@ struct hl_asic_funcs { struct sg_table *sgt); void (*add_end_of_cb_packets)(struct hl_device *hdev, u64 kernel_address, u32 len, - u64 cq_addr, u32 cq_val, u32 msix_num); + u64 cq_addr, u32 cq_val, u32 msix_num, + bool eb); void (*update_eq_ci)(struct hl_device *hdev, u32 val); int (*context_switch)(struct hl_device *hdev, u32 asid); void (*restore_phase_topology)(struct hl_device *hdev); @@ -596,11 +675,13 @@ struct hl_asic_funcs { u32 *size); u64 (*read_pte)(struct hl_device *hdev, u64 addr); void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val); - void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard, + int (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard, u32 flags); - void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard, + int (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard, u32 asid, u64 va, u64 size); int (*send_heartbeat)(struct hl_device *hdev); + void (*enable_clock_gating)(struct hl_device *hdev); + void (*disable_clock_gating)(struct hl_device *hdev); int (*debug_coresight)(struct hl_device *hdev, void *data); bool (*is_device_idle)(struct hl_device *hdev, u32 *mask, struct seq_file *s); @@ -620,6 +701,21 @@ struct hl_asic_funcs { void (*wreg)(struct hl_device *hdev, u32 reg, u32 val); void (*halt_coresight)(struct hl_device *hdev); int (*get_clk_rate)(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk); + u32 (*get_queue_id_for_cq)(struct hl_device *hdev, u32 cq_idx); + void (*read_device_fw_version)(struct hl_device *hdev, + enum hl_fw_component fwc); + int (*load_firmware_to_device)(struct hl_device *hdev); + int (*load_boot_fit_to_device)(struct hl_device *hdev); + void (*ext_queue_init)(struct hl_device *hdev, u32 hw_queue_id); + void (*ext_queue_reset)(struct hl_device *hdev, u32 hw_queue_id); + u32 (*get_signal_cb_size)(struct hl_device *hdev); + u32 (*get_wait_cb_size)(struct hl_device *hdev); + void (*gen_signal_cb)(struct hl_device *hdev, void *data, u16 sob_id); + void (*gen_wait_cb)(struct hl_device *hdev, void *data, u16 sob_id, + u16 sob_val, u16 mon_id, u32 q_idx); + void (*reset_sob)(struct hl_device *hdev, void *data); + void (*set_dma_mask_from_fw)(struct hl_device *hdev); + u64 (*get_device_time)(struct hl_device *hdev); }; @@ -659,8 +755,8 @@ struct hl_va_range { * with huge pages. * @dram_va_range: holds available virtual addresses for DRAM mappings. * @mem_hash_lock: protects the mem_hash. - * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifing the - * MMU hash or walking the PGT requires talking this lock + * @mmu_lock: protects the MMU page tables. Any change to the PGT, modifying the + * MMU hash or walking the PGT requires talking this lock. * @debugfs_list: node in debugfs list of contexts. * @cs_sequence: sequence number for CS. Value is assigned to a CS and passed * to user so user could inquire about CS. It is used as @@ -751,10 +847,14 @@ struct hl_userptr { * @job_lock: spinlock for the CS's jobs list. Needed for free_job. * @refcount: reference counter for usage of the CS. * @fence: pointer to the fence object of this CS. + * @signal_fence: pointer to the fence object of the signal CS (used by wait + * CS only). + * @finish_work: workqueue object to run when CS is completed by H/W. * @work_tdr: delayed work node for TDR. * @mirror_node : node in device mirror list of command submissions. * @debugfs_list: node in debugfs list of command submissions. * @sequence: the sequence number of this CS. + * @type: CS_TYPE_*. * @submitted: true if CS was submitted to H/W. * @completed: true if CS was completed by device. * @timedout : true if CS was timedout. @@ -769,10 +869,13 @@ struct hl_cs { spinlock_t job_lock; struct kref refcount; struct dma_fence *fence; + struct dma_fence *signal_fence; + struct work_struct finish_work; struct delayed_work work_tdr; struct list_head mirror_node; struct list_head debugfs_list; u64 sequence; + enum hl_cs_type type; u8 submitted; u8 completed; u8 timedout; @@ -799,6 +902,12 @@ struct hl_cs { * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a * handle to a kernel-allocated CB object, false * otherwise (SRAM/DRAM/host address). + * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This + * info is needed later, when adding the 2xMSG_PROT at the + * end of the JOB, to know which barriers to put in the + * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't + * have streams so the engine can't be busy by another + * stream. */ struct hl_cs_job { struct list_head cs_node; @@ -814,6 +923,7 @@ struct hl_cs_job { u32 user_cb_size; u32 job_cb_size; u8 is_kernel_allocated_cb; + u8 contains_dma_pkt; }; /** @@ -833,6 +943,12 @@ struct hl_cs_job { * @is_kernel_allocated_cb: true if the CB handle we got from the user holds a * handle to a kernel-allocated CB object, false * otherwise (SRAM/DRAM/host address). + * @contains_dma_pkt: whether the JOB contains at least one DMA packet. This + * info is needed later, when adding the 2xMSG_PROT at the + * end of the JOB, to know which barriers to put in the + * MSG_PROT packets. Relevant only for GAUDI as GOYA doesn't + * have streams so the engine can't be busy by another + * stream. */ struct hl_cs_parser { struct hl_cb *user_cb; @@ -846,6 +962,7 @@ struct hl_cs_parser { u32 patched_cb_size; u8 job_id; u8 is_kernel_allocated_cb; + u8 contains_dma_pkt; }; @@ -1093,6 +1210,16 @@ void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) +#define RMWREG32(reg, val, mask) \ + do { \ + u32 tmp_ = RREG32(reg); \ + tmp_ &= ~(mask); \ + tmp_ |= ((val) << __ffs(mask)); \ + WREG32(reg, tmp_); \ + } while (0) + +#define RREG32_MASK(reg, mask) ((RREG32(reg) & mask) >> __ffs(mask)) + #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK #define WREG32_FIELD(reg, offset, field, val) \ @@ -1282,6 +1409,8 @@ struct hl_device_idle_busy_ts { * @idle_busy_ts_idx: index of current entry in idle_busy_ts_arr * @id: device minor. * @id_control: minor of the control device + * @cpu_pci_msb_addr: 50-bit extension bits for the device CPU's 40-bit + * addresses. * @disabled: is device disabled. * @late_init_done: is late init stage was done during initialization. * @hwmon_initialized: is H/W monitor sensors was initialized. @@ -1295,11 +1424,19 @@ struct hl_device_idle_busy_ts { * huge pages. * @init_done: is the initialization of the device done. * @mmu_enable: is MMU enabled. + * @mmu_huge_page_opt: is MMU huge pages optimization enabled. + * @clock_gating: is clock gating enabled. * @device_cpu_disabled: is the device CPU disabled (due to timeouts) * @dma_mask: the dma mask that was set for this device * @in_debug: is device under debug. This, together with fpriv_list, enforces * that only a single user is configuring the debug infrastructure. + * @power9_64bit_dma_enable: true to enable 64-bit DMA mask support. Relevant + * only to POWER9 machines. * @cdev_sysfs_created: were char devices and sysfs nodes created. + * @stop_on_err: true if engines should stop on error. + * @supports_sync_stream: is sync stream supported. + * @supports_coresight: is CoreSight supported. + * @supports_soft_reset: is soft reset supported. */ struct hl_device { struct pci_dev *pdev; @@ -1366,6 +1503,7 @@ struct hl_device { u32 idle_busy_ts_idx; u16 id; u16 id_control; + u16 cpu_pci_msb_addr; u8 disabled; u8 late_init_done; u8 hwmon_initialized; @@ -1376,18 +1514,31 @@ struct hl_device { u8 dram_default_page_mapping; u8 pmmu_huge_range; u8 init_done; + u8 clock_gating; u8 device_cpu_disabled; u8 dma_mask; u8 in_debug; + u8 power9_64bit_dma_enable; u8 cdev_sysfs_created; + u8 stop_on_err; + u8 supports_sync_stream; + u8 supports_coresight; + u8 supports_soft_reset; /* Parameters for bring-up */ u8 mmu_enable; + u8 mmu_huge_page_opt; u8 cpu_enable; u8 reset_pcilink; u8 cpu_queues_enable; u8 fw_loading; u8 pldm; + u8 axi_drain; + u8 sram_scrambler_enable; + u8 dram_scrambler_enable; + u8 hard_reset_on_fw_events; + u8 bmc_enable; + u8 rl_enable; }; @@ -1554,8 +1705,10 @@ int hl_cb_pool_fini(struct hl_device *hdev); void hl_cs_rollback_all(struct hl_device *hdev); struct hl_cs_job *hl_cs_allocate_job(struct hl_device *hdev, enum hl_queue_type queue_type, bool is_kernel_allocated_cb); +void hl_sob_reset_error(struct kref *ref); void goya_set_asic_funcs(struct hl_device *hdev); +void gaudi_set_asic_funcs(struct hl_device *hdev); int hl_vm_ctx_init(struct hl_ctx *ctx); void hl_vm_ctx_fini(struct hl_ctx *ctx); @@ -1583,11 +1736,14 @@ int hl_mmu_unmap(struct hl_ctx *ctx, u64 virt_addr, u32 page_size, void hl_mmu_swap_out(struct hl_ctx *ctx); void hl_mmu_swap_in(struct hl_ctx *ctx); -int hl_fw_push_fw_to_device(struct hl_device *hdev, const char *fw_name, +int hl_fw_load_fw_to_device(struct hl_device *hdev, const char *fw_name, void __iomem *dst); int hl_fw_send_pci_access_msg(struct hl_device *hdev, u32 opcode); int hl_fw_send_cpu_message(struct hl_device *hdev, u32 hw_queue_id, u32 *msg, u16 len, u32 timeout, long *result); +int hl_fw_unmask_irq(struct hl_device *hdev, u16 event_type); +int hl_fw_unmask_irq_arr(struct hl_device *hdev, const u32 *irq_arr, + size_t irq_arr_size); int hl_fw_test_cpu_queue(struct hl_device *hdev); void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, dma_addr_t *dma_handle); @@ -1596,6 +1752,10 @@ void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size, int hl_fw_send_heartbeat(struct hl_device *hdev); int hl_fw_armcp_info_get(struct hl_device *hdev); int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size); +int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, + u32 msg_to_cpu_reg, u32 cpu_msg_status_reg, + u32 boot_err0_reg, bool skip_bmc, + u32 cpu_timeout, u32 boot_fit_timeout); int hl_pci_bars_map(struct hl_device *hdev, const char * const name[3], bool is_wc[3]); @@ -1605,9 +1765,8 @@ int hl_pci_set_dram_bar_base(struct hl_device *hdev, u8 inbound_region, u8 bar, int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, u64 dram_base_address, u64 host_phys_base_address, u64 host_phys_size); -int hl_pci_init(struct hl_device *hdev, u8 dma_mask); +int hl_pci_init(struct hl_device *hdev); void hl_pci_fini(struct hl_device *hdev); -int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask); long hl_get_frequency(struct hl_device *hdev, u32 pll_index, bool curr); void hl_set_frequency(struct hl_device *hdev, u32 pll_index, u64 freq); @@ -1627,6 +1786,10 @@ void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, long value); u64 hl_get_max_power(struct hl_device *hdev); void hl_set_max_power(struct hl_device *hdev, u64 value); +int hl_set_voltage(struct hl_device *hdev, + int sensor_index, u32 attr, long value); +int hl_set_current(struct hl_device *hdev, + int sensor_index, u32 attr, long value); #ifdef CONFIG_DEBUG_FS diff --git a/drivers/misc/habanalabs/habanalabs_drv.c b/drivers/misc/habanalabs/habanalabs_drv.c index b670859c677a..8652c7e5d7f1 100644 --- a/drivers/misc/habanalabs/habanalabs_drv.c +++ b/drivers/misc/habanalabs/habanalabs_drv.c @@ -47,6 +47,7 @@ static const struct pci_device_id ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_HABANALABS, PCI_IDS_GAUDI), }, { 0, } }; +MODULE_DEVICE_TABLE(pci, ids); /* * get_asic_type - translate device id to asic type @@ -171,6 +172,7 @@ out_err: put_pid(hpriv->taskpid); kfree(hpriv); + return rc; } @@ -230,8 +232,15 @@ static void set_driver_behavior_per_device(struct hl_device *hdev) hdev->fw_loading = 1; hdev->cpu_queues_enable = 1; hdev->heartbeat = 1; + hdev->clock_gating = 1; hdev->reset_pcilink = 0; + hdev->axi_drain = 0; + hdev->sram_scrambler_enable = 1; + hdev->dram_scrambler_enable = 1; + hdev->rl_enable = 1; + hdev->bmc_enable = 1; + hdev->hard_reset_on_fw_events = 1; } /* @@ -267,11 +276,6 @@ int create_hdev(struct hl_device **dev, struct pci_dev *pdev, dev_err(&pdev->dev, "Unsupported ASIC\n"); rc = -ENODEV; goto free_hdev; - } else if (hdev->asic_type == ASIC_GAUDI) { - dev_err(&pdev->dev, - "GAUDI is not supported by the current kernel\n"); - rc = -ENODEV; - goto free_hdev; } } else { hdev->asic_type = asic_type; diff --git a/drivers/misc/habanalabs/habanalabs_ioctl.c b/drivers/misc/habanalabs/habanalabs_ioctl.c index 6474b868ef27..52eedd3a6c3a 100644 --- a/drivers/misc/habanalabs/habanalabs_ioctl.c +++ b/drivers/misc/habanalabs/habanalabs_ioctl.c @@ -71,6 +71,8 @@ static int hw_ip_info(struct hl_device *hdev, struct hl_info_args *args) min(CARD_NAME_MAX_LEN, HL_INFO_CARD_NAME_MAX_LEN)); hw_ip.armcp_cpld_version = le32_to_cpu(prop->armcp_info.cpld_version); + hw_ip.module_id = le32_to_cpu(prop->armcp_info.card_location); + hw_ip.psoc_pci_pll_nr = prop->psoc_pci_pll_nr; hw_ip.psoc_pci_pll_nf = prop->psoc_pci_pll_nf; hw_ip.psoc_pci_pll_od = prop->psoc_pci_pll_od; @@ -258,6 +260,22 @@ static int get_reset_count(struct hl_device *hdev, struct hl_info_args *args) min((size_t) max_size, sizeof(reset_count))) ? -EFAULT : 0; } +static int time_sync_info(struct hl_device *hdev, struct hl_info_args *args) +{ + struct hl_info_time_sync time_sync = {0}; + u32 max_size = args->return_size; + void __user *out = (void __user *) (uintptr_t) args->return_pointer; + + if ((!max_size) || (!out)) + return -EINVAL; + + time_sync.device_time = hdev->asic_funcs->get_device_time(hdev); + time_sync.host_time = ktime_get_raw_ns(); + + return copy_to_user(out, &time_sync, + min((size_t) max_size, sizeof(time_sync))) ? -EFAULT : 0; +} + static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, struct device *dev) { @@ -315,6 +333,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, rc = get_clk_rate(hdev, args); break; + case HL_INFO_TIME_SYNC: + return time_sync_info(hdev, args); + default: dev_err(dev, "Invalid request %d\n", args->op); rc = -ENOTTY; diff --git a/drivers/misc/habanalabs/hw_queue.c b/drivers/misc/habanalabs/hw_queue.c index 91579dde9262..f4434b39ef1b 100644 --- a/drivers/misc/habanalabs/hw_queue.c +++ b/drivers/misc/habanalabs/hw_queue.c @@ -111,7 +111,7 @@ static int ext_queue_sanity_checks(struct hl_device *hdev, bool reserve_cq_entry) { atomic_t *free_slots = - &hdev->completion_queue[q->hw_queue_id].free_slots_cnt; + &hdev->completion_queue[q->cq_id].free_slots_cnt; int free_slots_cnt; /* Check we have enough space in the queue */ @@ -194,7 +194,7 @@ static int hw_queue_sanity_checks(struct hl_device *hdev, struct hl_hw_queue *q, int num_of_entries) { atomic_t *free_slots = - &hdev->completion_queue[q->hw_queue_id].free_slots_cnt; + &hdev->completion_queue[q->cq_id].free_slots_cnt; /* * Check we have enough space in the completion queue. @@ -308,13 +308,14 @@ static void ext_queue_schedule_job(struct hl_cs_job *job) * No need to check if CQ is full because it was already * checked in ext_queue_sanity_checks */ - cq = &hdev->completion_queue[q->hw_queue_id]; + cq = &hdev->completion_queue[q->cq_id]; cq_addr = cq->bus_address + cq->pi * sizeof(struct hl_cq_entry); hdev->asic_funcs->add_end_of_cb_packets(hdev, cb->kernel_address, len, cq_addr, le32_to_cpu(cq_pkt.data), - q->hw_queue_id); + q->msi_vec, + job->contains_dma_pkt); q->shadow_queue[hl_pi_2_offset(q->pi)] = job; @@ -401,21 +402,111 @@ static void hw_queue_schedule_job(struct hl_cs_job *job) * No need to check if CQ is full because it was already * checked in hw_queue_sanity_checks */ - cq = &hdev->completion_queue[q->hw_queue_id]; + cq = &hdev->completion_queue[q->cq_id]; + cq->pi = hl_cq_inc_ptr(cq->pi); ext_and_hw_queue_submit_bd(hdev, q, ctl, len, ptr); } /* - * hl_hw_queue_schedule_cs - schedule a command submission - * - * @job : pointer to the CS + * init_signal_wait_cs - initialize a signal/wait CS + * @cs: pointer to the signal/wait CS * + * H/W queues spinlock should be taken before calling this function + */ +static void init_signal_wait_cs(struct hl_cs *cs) +{ + struct hl_ctx *ctx = cs->ctx; + struct hl_device *hdev = ctx->hdev; + struct hl_hw_queue *hw_queue; + struct hl_cs_compl *cs_cmpl = + container_of(cs->fence, struct hl_cs_compl, base_fence); + + struct hl_hw_sob *hw_sob; + struct hl_cs_job *job; + u32 q_idx; + + /* There is only one job in a signal/wait CS */ + job = list_first_entry(&cs->job_list, struct hl_cs_job, + cs_node); + q_idx = job->hw_queue_id; + hw_queue = &hdev->kernel_queues[q_idx]; + + if (cs->type & CS_TYPE_SIGNAL) { + hw_sob = &hw_queue->hw_sob[hw_queue->curr_sob_offset]; + + cs_cmpl->hw_sob = hw_sob; + cs_cmpl->sob_val = hw_queue->next_sob_val++; + + dev_dbg(hdev->dev, + "generate signal CB, sob_id: %d, sob val: 0x%x, q_idx: %d\n", + cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, q_idx); + + hdev->asic_funcs->gen_signal_cb(hdev, job->patched_cb, + cs_cmpl->hw_sob->sob_id); + + kref_get(&hw_sob->kref); + + /* check for wraparound */ + if (hw_queue->next_sob_val == HL_MAX_SOB_VAL) { + /* + * Decrement as we reached the max value. + * The release function won't be called here as we've + * just incremented the refcount. + */ + kref_put(&hw_sob->kref, hl_sob_reset_error); + hw_queue->next_sob_val = 1; + /* only two SOBs are currently in use */ + hw_queue->curr_sob_offset = + (hw_queue->curr_sob_offset + 1) % + HL_RSVD_SOBS_IN_USE; + + dev_dbg(hdev->dev, "switched to SOB %d, q_idx: %d\n", + hw_queue->curr_sob_offset, q_idx); + } + } else if (cs->type & CS_TYPE_WAIT) { + struct hl_cs_compl *signal_cs_cmpl; + + signal_cs_cmpl = container_of(cs->signal_fence, + struct hl_cs_compl, + base_fence); + + /* copy the the SOB id and value of the signal CS */ + cs_cmpl->hw_sob = signal_cs_cmpl->hw_sob; + cs_cmpl->sob_val = signal_cs_cmpl->sob_val; + + dev_dbg(hdev->dev, + "generate wait CB, sob_id: %d, sob_val: 0x%x, mon_id: %d, q_idx: %d\n", + cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, + hw_queue->base_mon_id, q_idx); + + hdev->asic_funcs->gen_wait_cb(hdev, job->patched_cb, + cs_cmpl->hw_sob->sob_id, + cs_cmpl->sob_val, + hw_queue->base_mon_id, + q_idx); + + kref_get(&cs_cmpl->hw_sob->kref); + /* + * Must put the signal fence after the SOB refcnt increment so + * the SOB refcnt won't turn 0 and reset the SOB before the + * wait CS was submitted. + */ + mb(); + dma_fence_put(cs->signal_fence); + cs->signal_fence = NULL; + } +} + +/* + * hl_hw_queue_schedule_cs - schedule a command submission + * @cs: pointer to the CS */ int hl_hw_queue_schedule_cs(struct hl_cs *cs) { - struct hl_device *hdev = cs->ctx->hdev; + struct hl_ctx *ctx = cs->ctx; + struct hl_device *hdev = ctx->hdev; struct hl_cs_job *job, *tmp; struct hl_hw_queue *q; int rc = 0, i, cq_cnt; @@ -461,6 +552,9 @@ int hl_hw_queue_schedule_cs(struct hl_cs *cs) } } + if ((cs->type == CS_TYPE_SIGNAL) || (cs->type == CS_TYPE_WAIT)) + init_signal_wait_cs(cs); + spin_lock(&hdev->hw_queues_mirror_lock); list_add_tail(&cs->mirror_node, &hdev->hw_queues_mirror_list); @@ -569,6 +663,9 @@ static int ext_and_cpu_queue_init(struct hl_device *hdev, struct hl_hw_queue *q, q->ci = 0; q->pi = 0; + if (!is_cpu_queue) + hdev->asic_funcs->ext_queue_init(hdev, q->hw_queue_id); + return 0; free_queue: @@ -791,5 +888,8 @@ void hl_hw_queue_reset(struct hl_device *hdev, bool hard_reset) ((!hard_reset) && (q->queue_type == QUEUE_TYPE_CPU))) continue; q->pi = q->ci = 0; + + if (q->queue_type == QUEUE_TYPE_EXT) + hdev->asic_funcs->ext_queue_reset(hdev, q->hw_queue_id); } } diff --git a/drivers/misc/habanalabs/hwmon.c b/drivers/misc/habanalabs/hwmon.c index a21a26e07c3b..8c6cd77e6af6 100644 --- a/drivers/misc/habanalabs/hwmon.c +++ b/drivers/misc/habanalabs/hwmon.c @@ -200,6 +200,7 @@ static int hl_write(struct device *dev, enum hwmon_sensor_types type, case hwmon_temp: switch (attr) { case hwmon_temp_offset: + case hwmon_temp_reset_history: break; default: return -EINVAL; @@ -216,6 +217,24 @@ static int hl_write(struct device *dev, enum hwmon_sensor_types type, } hl_set_pwm_info(hdev, channel, attr, val); break; + case hwmon_in: + switch (attr) { + case hwmon_in_reset_history: + break; + default: + return -EINVAL; + } + hl_set_voltage(hdev, channel, attr, val); + break; + case hwmon_curr: + switch (attr) { + case hwmon_curr_reset_history: + break; + default: + return -EINVAL; + } + hl_set_current(hdev, channel, attr, val); + break; default: return -EINVAL; } @@ -237,6 +256,8 @@ static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type, return 0444; case hwmon_temp_offset: return 0644; + case hwmon_temp_reset_history: + return 0200; } break; case hwmon_in: @@ -246,6 +267,8 @@ static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type, case hwmon_in_max: case hwmon_in_highest: return 0444; + case hwmon_in_reset_history: + return 0200; } break; case hwmon_curr: @@ -255,6 +278,8 @@ static umode_t hl_is_visible(const void *data, enum hwmon_sensor_types type, case hwmon_curr_max: case hwmon_curr_highest: return 0444; + case hwmon_curr_reset_history: + return 0200; } break; case hwmon_fan: @@ -462,6 +487,56 @@ void hl_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr, sensor_index, rc); } +int hl_set_voltage(struct hl_device *hdev, + int sensor_index, u32 attr, long value) +{ + struct armcp_packet pkt; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_VOLTAGE_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + pkt.value = __cpu_to_le64(value); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, NULL); + + if (rc) + dev_err(hdev->dev, + "Failed to set voltage of sensor %d, error %d\n", + sensor_index, rc); + + return rc; +} + +int hl_set_current(struct hl_device *hdev, + int sensor_index, u32 attr, long value) +{ + struct armcp_packet pkt; + int rc; + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ctl = cpu_to_le32(ARMCP_PACKET_CURRENT_SET << + ARMCP_PKT_CTL_OPCODE_SHIFT); + pkt.sensor_index = __cpu_to_le16(sensor_index); + pkt.type = __cpu_to_le16(attr); + pkt.value = __cpu_to_le64(value); + + rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt), + SENSORS_PKT_TIMEOUT, NULL); + + if (rc) + dev_err(hdev->dev, + "Failed to set current of sensor %d, error %d\n", + sensor_index, rc); + + return rc; +} + int hl_hwmon_init(struct hl_device *hdev) { struct device *dev = hdev->pdev ? &hdev->pdev->dev : hdev->dev; diff --git a/drivers/misc/habanalabs/include/armcp_if.h b/drivers/misc/habanalabs/include/armcp_if.h index bdd0a4c3a9cf..a34fc39ad87e 100644 --- a/drivers/misc/habanalabs/include/armcp_if.h +++ b/drivers/misc/habanalabs/include/armcp_if.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2016-2019 HabanaLabs, Ltd. + * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -35,7 +35,8 @@ struct hl_eq_entry { enum pq_init_status { PQ_INIT_STATUS_NA = 0, PQ_INIT_STATUS_READY_FOR_CP, - PQ_INIT_STATUS_READY_FOR_HOST + PQ_INIT_STATUS_READY_FOR_HOST, + PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI }; /* @@ -193,6 +194,16 @@ enum pq_init_status { * Set the value of the offset property of a specified thermal sensor. * The packet's arguments specify the desired sensor and the field to * set. + * + * ARMCP_PACKET_VOLTAGE_SET - + * Trigger the reset_history property of a specified voltage sensor. + * The packet's arguments specify the desired sensor and the field to + * set. + * + * ARMCP_PACKET_CURRENT_SET - + * Trigger the reset_history property of a specified current sensor. + * The packet's arguments specify the desired sensor and the field to + * set. */ enum armcp_packet_id { @@ -220,6 +231,8 @@ enum armcp_packet_id { ARMCP_PACKET_EEPROM_DATA_GET, /* sysfs */ ARMCP_RESERVED, ARMCP_PACKET_TEMPERATURE_SET, /* sysfs */ + ARMCP_PACKET_VOLTAGE_SET, /* sysfs */ + ARMCP_PACKET_CURRENT_SET, /* sysfs */ }; #define ARMCP_PACKET_FENCE_VAL 0xFE8CE7A5 @@ -288,21 +301,24 @@ enum armcp_temp_type { armcp_temp_crit, armcp_temp_crit_hyst, armcp_temp_offset = 19, - armcp_temp_highest = 22 + armcp_temp_highest = 22, + armcp_temp_reset_history = 23 }; enum armcp_in_attributes { armcp_in_input, armcp_in_min, armcp_in_max, - armcp_in_highest = 7 + armcp_in_highest = 7, + armcp_in_reset_history }; enum armcp_curr_attributes { armcp_curr_input, armcp_curr_min, armcp_curr_max, - armcp_curr_highest = 7 + armcp_curr_highest = 7, + armcp_curr_reset_history }; enum armcp_fan_attributes { @@ -336,10 +352,23 @@ struct armcp_sensor { }; /** + * struct armcp_card_types - ASIC card type. + * @armcp_card_type_pci: PCI card. + * @armcp_card_type_pmc: PCI Mezzanine Card. + */ +enum armcp_card_types { + armcp_card_type_pci, + armcp_card_type_pmc +}; + +/** * struct armcp_info - Info from ArmCP that is necessary to the host's driver * @sensors: available sensors description. * @kernel_version: ArmCP linux kernel version. * @reserved: reserved field. + * @card_type: card configuration type. + * @card_location: in a server, each card has different connections topology + * depending on its location (relevant for PMC card type) * @cpld_version: CPLD programmed F/W version. * @infineon_version: Infineon main DC-DC version. * @fuse_version: silicon production FUSE information. @@ -351,7 +380,9 @@ struct armcp_sensor { struct armcp_info { struct armcp_sensor sensors[ARMCP_MAX_SENSORS]; __u8 kernel_version[VERSION_MAX_LEN]; - __le32 reserved[3]; + __le32 reserved; + __le32 card_type; + __le32 card_location; __le32 cpld_version; __le32 infineon_version; __u8 fuse_version[VERSION_MAX_LEN]; diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000000..cf80e31317ad --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/cpu_if_regs.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_ARUSER_OVR 0x442104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x442108 + +#define mmCPU_IF_AWUSER_OVR 0x44210C + +#define mmCPU_IF_AWUSER_OVR_EN 0x442110 + +#define mmCPU_IF_AXCACHE_OVR 0x442114 + +#define mmCPU_IF_LOCK_OVR 0x442118 + +#define mmCPU_IF_PROT_OVR 0x44211C + +#define mmCPU_IF_MAX_OUTSTANDING 0x442120 + +#define mmCPU_IF_EARLY_BRESP_EN 0x442124 + +#define mmCPU_IF_FORCE_RSP_OK 0x442128 + +#define mmCPU_IF_CPU_MSB_ADDR 0x44212C + +#define mmCPU_IF_AXI_SPLIT_INTR 0x442130 + +#define mmCPU_IF_TOTAL_WR_CNT 0x442140 + +#define mmCPU_IF_INFLIGHT_WR_CNT 0x442144 + +#define mmCPU_IF_TOTAL_RD_CNT 0x442150 + +#define mmCPU_IF_INFLIGHT_RD_CNT 0x442154 + +#define mmCPU_IF_PF_PQ_PI 0x442200 + +#define mmCPU_IF_PQ_BASE_ADDR_LOW 0x442204 + +#define mmCPU_IF_PQ_BASE_ADDR_HIGH 0x442208 + +#define mmCPU_IF_PQ_LENGTH 0x44220C + +#define mmCPU_IF_CQ_BASE_ADDR_LOW 0x442210 + +#define mmCPU_IF_CQ_BASE_ADDR_HIGH 0x442214 + +#define mmCPU_IF_CQ_LENGTH 0x442218 + +#define mmCPU_IF_EQ_BASE_ADDR_LOW 0x442220 + +#define mmCPU_IF_EQ_BASE_ADDR_HIGH 0x442224 + +#define mmCPU_IF_EQ_LENGTH 0x442228 + +#define mmCPU_IF_EQ_RD_OFFS 0x44222C + +#define mmCPU_IF_QUEUE_INIT 0x442230 + +#define mmCPU_IF_TPC_SERR_INTR_STS 0x442300 + +#define mmCPU_IF_TPC_SERR_INTR_CLR 0x442304 + +#define mmCPU_IF_TPC_SERR_INTR_MASK 0x442308 + +#define mmCPU_IF_TPC_DERR_INTR_STS 0x442310 + +#define mmCPU_IF_TPC_DERR_INTR_CLR 0x442314 + +#define mmCPU_IF_TPC_DERR_INTR_MASK 0x442318 + +#define mmCPU_IF_DMA_SERR_INTR_STS 0x442320 + +#define mmCPU_IF_DMA_SERR_INTR_CLR 0x442324 + +#define mmCPU_IF_DMA_SERR_INTR_MASK 0x442328 + +#define mmCPU_IF_DMA_DERR_INTR_STS 0x442330 + +#define mmCPU_IF_DMA_DERR_INTR_CLR 0x442334 + +#define mmCPU_IF_DMA_DERR_INTR_MASK 0x442338 + +#define mmCPU_IF_SRAM_SERR_INTR_STS 0x442340 + +#define mmCPU_IF_SRAM_SERR_INTR_CLR 0x442344 + +#define mmCPU_IF_SRAM_SERR_INTR_MASK 0x442348 + +#define mmCPU_IF_SRAM_DERR_INTR_STS 0x442350 + +#define mmCPU_IF_SRAM_DERR_INTR_CLR 0x442354 + +#define mmCPU_IF_SRAM_DERR_INTR_MASK 0x442358 + +#define mmCPU_IF_NIC_SERR_INTR_STS 0x442360 + +#define mmCPU_IF_NIC_SERR_INTR_CLR 0x442364 + +#define mmCPU_IF_NIC_SERR_INTR_MASK 0x442368 + +#define mmCPU_IF_NIC_DERR_INTR_STS 0x442370 + +#define mmCPU_IF_NIC_DERR_INTR_CLR 0x442374 + +#define mmCPU_IF_NIC_DERR_INTR_MASK 0x442378 + +#define mmCPU_IF_DMA_IF_SERR_INTR_STS 0x442380 + +#define mmCPU_IF_DMA_IF_SERR_INTR_CLR 0x442384 + +#define mmCPU_IF_DMA_IF_SERR_INTR_MASK 0x442388 + +#define mmCPU_IF_DMA_IF_DERR_INTR_STS 0x442390 + +#define mmCPU_IF_DMA_IF_DERR_INTR_CLR 0x442394 + +#define mmCPU_IF_DMA_IF_DERR_INTR_MASK 0x442398 + +#define mmCPU_IF_HBM_SERR_INTR_STS 0x4423A0 + +#define mmCPU_IF_HBM_SERR_INTR_CLR 0x4423A4 + +#define mmCPU_IF_HBM_SERR_INTR_MASK 0x4423A8 + +#define mmCPU_IF_HBM_DERR_INTR_STS 0x4423B0 + +#define mmCPU_IF_HBM_DERR_INTR_CLR 0x4423B4 + +#define mmCPU_IF_HBM_DERR_INTR_MASK 0x4423B8 + +#define mmCPU_IF_PLL_SEI_INTR_STS 0x442400 + +#define mmCPU_IF_PLL_SEI_INTR_CLR 0x442404 + +#define mmCPU_IF_PLL_SEI_INTR_MASK 0x442408 + +#define mmCPU_IF_NIC_SEI_INTR_STS 0x442410 + +#define mmCPU_IF_NIC_SEI_INTR_CLR 0x442414 + +#define mmCPU_IF_NIC_SEI_INTR_MASK 0x442418 + +#define mmCPU_IF_DMA_SEI_INTR_STS 0x442420 + +#define mmCPU_IF_DMA_SEI_INTR_CLR 0x442424 + +#define mmCPU_IF_DMA_SEI_INTR_MASK 0x442428 + +#define mmCPU_IF_DMA_IF_SEI_INTR_STS 0x442430 + +#define mmCPU_IF_DMA_IF_SEI_INTR_CLR 0x442434 + +#define mmCPU_IF_DMA_IF_SEI_INTR_MASK 0x442438 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h new file mode 100644 index 000000000000..d079a37acab8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_masks.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_CORE_MASKS_H_ +#define ASIC_REG_DMA0_CORE_MASKS_H_ + +/* + ***************************************** + * DMA0_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +/* DMA0_CORE_CFG_0 */ +#define DMA0_CORE_CFG_0_EN_SHIFT 0 +#define DMA0_CORE_CFG_0_EN_MASK 0x1 + +/* DMA0_CORE_CFG_1 */ +#define DMA0_CORE_CFG_1_HALT_SHIFT 0 +#define DMA0_CORE_CFG_1_HALT_MASK 0x1 +#define DMA0_CORE_CFG_1_FLUSH_SHIFT 1 +#define DMA0_CORE_CFG_1_FLUSH_MASK 0x2 +#define DMA0_CORE_CFG_1_SB_FORCE_MISS_SHIFT 2 +#define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4 + +/* DMA0_CORE_LBW_MAX_OUTSTAND */ +#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F + +/* DMA0_CORE_SRC_BASE_LO */ +#define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0 +#define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_BASE_HI */ +#define DMA0_CORE_SRC_BASE_HI_VAL_SHIFT 0 +#define DMA0_CORE_SRC_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_BASE_LO */ +#define DMA0_CORE_DST_BASE_LO_VAL_SHIFT 0 +#define DMA0_CORE_DST_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_BASE_HI */ +#define DMA0_CORE_DST_BASE_HI_VAL_SHIFT 0 +#define DMA0_CORE_DST_BASE_HI_VAL_MASK 0xFFFFFF +#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_SHIFT 24 +#define DMA0_CORE_DST_BASE_HI_CTX_ID_HI_MASK 0xFF000000 + +/* DMA0_CORE_SRC_TSIZE_1 */ +#define DMA0_CORE_SRC_TSIZE_1_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_1 */ +#define DMA0_CORE_SRC_STRIDE_1_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_2 */ +#define DMA0_CORE_SRC_TSIZE_2_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_2 */ +#define DMA0_CORE_SRC_STRIDE_2_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_3 */ +#define DMA0_CORE_SRC_TSIZE_3_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_3 */ +#define DMA0_CORE_SRC_STRIDE_3_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_4 */ +#define DMA0_CORE_SRC_TSIZE_4_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_STRIDE_4 */ +#define DMA0_CORE_SRC_STRIDE_4_VAL_SHIFT 0 +#define DMA0_CORE_SRC_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_SRC_TSIZE_0 */ +#define DMA0_CORE_SRC_TSIZE_0_VAL_SHIFT 0 +#define DMA0_CORE_SRC_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_1 */ +#define DMA0_CORE_DST_TSIZE_1_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_1 */ +#define DMA0_CORE_DST_STRIDE_1_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_2 */ +#define DMA0_CORE_DST_TSIZE_2_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_2 */ +#define DMA0_CORE_DST_STRIDE_2_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_3 */ +#define DMA0_CORE_DST_TSIZE_3_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_3 */ +#define DMA0_CORE_DST_STRIDE_3_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_4 */ +#define DMA0_CORE_DST_TSIZE_4_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_STRIDE_4 */ +#define DMA0_CORE_DST_STRIDE_4_VAL_SHIFT 0 +#define DMA0_CORE_DST_STRIDE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_DST_TSIZE_0 */ +#define DMA0_CORE_DST_TSIZE_0_VAL_SHIFT 0 +#define DMA0_CORE_DST_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_COMMIT */ +#define DMA0_CORE_COMMIT_WR_COMP_EN_SHIFT 0 +#define DMA0_CORE_COMMIT_WR_COMP_EN_MASK 0x1 +#define DMA0_CORE_COMMIT_TRANSPOSE_SHIFT 1 +#define DMA0_CORE_COMMIT_TRANSPOSE_MASK 0x2 +#define DMA0_CORE_COMMIT_DTYPE_SHIFT 2 +#define DMA0_CORE_COMMIT_DTYPE_MASK 0x4 +#define DMA0_CORE_COMMIT_LIN_SHIFT 3 +#define DMA0_CORE_COMMIT_LIN_MASK 0x8 +#define DMA0_CORE_COMMIT_MEM_SET_SHIFT 4 +#define DMA0_CORE_COMMIT_MEM_SET_MASK 0x10 +#define DMA0_CORE_COMMIT_COMPRESS_SHIFT 5 +#define DMA0_CORE_COMMIT_COMPRESS_MASK 0x20 +#define DMA0_CORE_COMMIT_DECOMPRESS_SHIFT 6 +#define DMA0_CORE_COMMIT_DECOMPRESS_MASK 0x40 +#define DMA0_CORE_COMMIT_CTX_ID_SHIFT 16 +#define DMA0_CORE_COMMIT_CTX_ID_MASK 0xFF0000 + +/* DMA0_CORE_WR_COMP_WDATA */ +#define DMA0_CORE_WR_COMP_WDATA_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_ADDR_LO */ +#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_ADDR_HI */ +#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_COMP_AWUSER_31_11 */ +#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_WR_COMP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_TE_NUMROWS */ +#define DMA0_CORE_TE_NUMROWS_VAL_SHIFT 0 +#define DMA0_CORE_TE_NUMROWS_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_PROT */ +#define DMA0_CORE_PROT_VAL_SHIFT 0 +#define DMA0_CORE_PROT_VAL_MASK 0x1 +#define DMA0_CORE_PROT_ERR_VAL_SHIFT 1 +#define DMA0_CORE_PROT_ERR_VAL_MASK 0x2 + +/* DMA0_CORE_SECURE_PROPS */ +#define DMA0_CORE_SECURE_PROPS_ASID_SHIFT 0 +#define DMA0_CORE_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA0_CORE_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA0_CORE_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA0_CORE_NON_SECURE_PROPS */ +#define DMA0_CORE_NON_SECURE_PROPS_ASID_SHIFT 0 +#define DMA0_CORE_NON_SECURE_PROPS_ASID_MASK 0x3FF +#define DMA0_CORE_NON_SECURE_PROPS_MMBP_SHIFT 10 +#define DMA0_CORE_NON_SECURE_PROPS_MMBP_MASK 0x400 + +/* DMA0_CORE_RD_MAX_OUTSTAND */ +#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_RD_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DMA0_CORE_RD_MAX_SIZE */ +#define DMA0_CORE_RD_MAX_SIZE_DATA_SHIFT 0 +#define DMA0_CORE_RD_MAX_SIZE_DATA_MASK 0x7FF +#define DMA0_CORE_RD_MAX_SIZE_MD_SHIFT 16 +#define DMA0_CORE_RD_MAX_SIZE_MD_MASK 0x7FF0000 + +/* DMA0_CORE_RD_ARCACHE */ +#define DMA0_CORE_RD_ARCACHE_VAL_SHIFT 0 +#define DMA0_CORE_RD_ARCACHE_VAL_MASK 0xF + +/* DMA0_CORE_RD_ARUSER_31_11 */ +#define DMA0_CORE_RD_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_RD_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_RD_INFLIGHTS */ +#define DMA0_CORE_RD_INFLIGHTS_VAL_SHIFT 0 +#define DMA0_CORE_RD_INFLIGHTS_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_WR_MAX_OUTSTAND */ +#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_SHIFT 0 +#define DMA0_CORE_WR_MAX_OUTSTAND_VAL_MASK 0xFFF + +/* DMA0_CORE_WR_MAX_AWID */ +#define DMA0_CORE_WR_MAX_AWID_VAL_SHIFT 0 +#define DMA0_CORE_WR_MAX_AWID_VAL_MASK 0xFFFF + +/* DMA0_CORE_WR_AWCACHE */ +#define DMA0_CORE_WR_AWCACHE_VAL_SHIFT 0 +#define DMA0_CORE_WR_AWCACHE_VAL_MASK 0xF + +/* DMA0_CORE_WR_AWUSER_31_11 */ +#define DMA0_CORE_WR_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_CORE_WR_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_CORE_WR_INFLIGHTS */ +#define DMA0_CORE_WR_INFLIGHTS_VAL_SHIFT 0 +#define DMA0_CORE_WR_INFLIGHTS_VAL_MASK 0xFFFF + +/* DMA0_CORE_RD_RATE_LIM_CFG_0 */ +#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_CORE_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_CORE_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_CORE_RD_RATE_LIM_CFG_1 */ +#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_CORE_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_CORE_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_CORE_WR_RATE_LIM_CFG_0 */ +#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_CORE_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_CORE_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_CORE_WR_RATE_LIM_CFG_1 */ +#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_CORE_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_CORE_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_CORE_ERR_CFG */ +#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 +#define DMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 +#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 +#define DMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 + +/* DMA0_CORE_ERR_CAUSE */ +#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 +#define DMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 +#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 +#define DMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 +#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 2 +#define DMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x4 +#define DMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 +#define DMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 + +/* DMA0_CORE_ERRMSG_ADDR_LO */ +#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_ERRMSG_ADDR_HI */ +#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_ERRMSG_WDATA */ +#define DMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 +#define DMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_STS0 */ +#define DMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 +#define DMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF +#define DMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 +#define DMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 +#define DMA0_CORE_STS0_BUSY_SHIFT 31 +#define DMA0_CORE_STS0_BUSY_MASK 0x80000000 + +/* DMA0_CORE_STS1 */ +#define DMA0_CORE_STS1_IS_HALT_SHIFT 0 +#define DMA0_CORE_STS1_IS_HALT_MASK 0x1 + +/* DMA0_CORE_RD_DBGMEM_ADD */ +#define DMA0_CORE_RD_DBGMEM_ADD_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_ADD_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_DATA_WR */ +#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_DATA_WR_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_DATA_RD */ +#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_DATA_RD_VAL_MASK 0xFFFFFFFF + +/* DMA0_CORE_RD_DBGMEM_CTRL */ +#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* DMA0_CORE_RD_DBGMEM_RC */ +#define DMA0_CORE_RD_DBGMEM_RC_VALID_SHIFT 0 +#define DMA0_CORE_RD_DBGMEM_RC_VALID_MASK 0x1 + +/* DMA0_CORE_DBG_HBW_AXI_AR_CNT */ + +/* DMA0_CORE_DBG_HBW_AXI_AW_CNT */ + +/* DMA0_CORE_DBG_LBW_AXI_AW_CNT */ + +/* DMA0_CORE_DBG_DESC_CNT */ +#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_SHIFT 0 +#define DMA0_CORE_DBG_DESC_CNT_RD_STS_CTX_CNT_MASK 0xFFFFFFFF + +/* DMA0_CORE_DBG_STS */ +#define DMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 +#define DMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 +#define DMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 +#define DMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 +#define DMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 +#define DMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 +#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 +#define DMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 +#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 +#define DMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 +#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 +#define DMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 +#define DMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 +#define DMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 +#define DMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 +#define DMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 +#define DMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 +#define DMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 +#define DMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 +#define DMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 +#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_SHIFT 20 +#define DMA0_CORE_DBG_STS_RDBUF_FULLNESS_MASK 0x7FF00000 + +/* DMA0_CORE_DBG_RD_DESC_ID */ + +/* DMA0_CORE_DBG_WR_DESC_ID */ + +#endif /* ASIC_REG_DMA0_CORE_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h new file mode 100644 index 000000000000..1fdd5d5fc6d2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_CORE_REGS_H_ +#define ASIC_REG_DMA0_CORE_REGS_H_ + +/* + ***************************************** + * DMA0_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA0_CORE_CFG_0 0x500000 + +#define mmDMA0_CORE_CFG_1 0x500004 + +#define mmDMA0_CORE_LBW_MAX_OUTSTAND 0x500008 + +#define mmDMA0_CORE_SRC_BASE_LO 0x500014 + +#define mmDMA0_CORE_SRC_BASE_HI 0x500018 + +#define mmDMA0_CORE_DST_BASE_LO 0x50001C + +#define mmDMA0_CORE_DST_BASE_HI 0x500020 + +#define mmDMA0_CORE_SRC_TSIZE_1 0x50002C + +#define mmDMA0_CORE_SRC_STRIDE_1 0x500030 + +#define mmDMA0_CORE_SRC_TSIZE_2 0x500034 + +#define mmDMA0_CORE_SRC_STRIDE_2 0x500038 + +#define mmDMA0_CORE_SRC_TSIZE_3 0x50003C + +#define mmDMA0_CORE_SRC_STRIDE_3 0x500040 + +#define mmDMA0_CORE_SRC_TSIZE_4 0x500044 + +#define mmDMA0_CORE_SRC_STRIDE_4 0x500048 + +#define mmDMA0_CORE_SRC_TSIZE_0 0x50004C + +#define mmDMA0_CORE_DST_TSIZE_1 0x500054 + +#define mmDMA0_CORE_DST_STRIDE_1 0x500058 + +#define mmDMA0_CORE_DST_TSIZE_2 0x50005C + +#define mmDMA0_CORE_DST_STRIDE_2 0x500060 + +#define mmDMA0_CORE_DST_TSIZE_3 0x500064 + +#define mmDMA0_CORE_DST_STRIDE_3 0x500068 + +#define mmDMA0_CORE_DST_TSIZE_4 0x50006C + +#define mmDMA0_CORE_DST_STRIDE_4 0x500070 + +#define mmDMA0_CORE_DST_TSIZE_0 0x500074 + +#define mmDMA0_CORE_COMMIT 0x500078 + +#define mmDMA0_CORE_WR_COMP_WDATA 0x50007C + +#define mmDMA0_CORE_WR_COMP_ADDR_LO 0x500080 + +#define mmDMA0_CORE_WR_COMP_ADDR_HI 0x500084 + +#define mmDMA0_CORE_WR_COMP_AWUSER_31_11 0x500088 + +#define mmDMA0_CORE_TE_NUMROWS 0x500094 + +#define mmDMA0_CORE_PROT 0x5000B8 + +#define mmDMA0_CORE_SECURE_PROPS 0x5000F0 + +#define mmDMA0_CORE_NON_SECURE_PROPS 0x5000F4 + +#define mmDMA0_CORE_RD_MAX_OUTSTAND 0x500100 + +#define mmDMA0_CORE_RD_MAX_SIZE 0x500104 + +#define mmDMA0_CORE_RD_ARCACHE 0x500108 + +#define mmDMA0_CORE_RD_ARUSER_31_11 0x500110 + +#define mmDMA0_CORE_RD_INFLIGHTS 0x500114 + +#define mmDMA0_CORE_WR_MAX_OUTSTAND 0x500120 + +#define mmDMA0_CORE_WR_MAX_AWID 0x500124 + +#define mmDMA0_CORE_WR_AWCACHE 0x500128 + +#define mmDMA0_CORE_WR_AWUSER_31_11 0x500130 + +#define mmDMA0_CORE_WR_INFLIGHTS 0x500134 + +#define mmDMA0_CORE_RD_RATE_LIM_CFG_0 0x500150 + +#define mmDMA0_CORE_RD_RATE_LIM_CFG_1 0x500154 + +#define mmDMA0_CORE_WR_RATE_LIM_CFG_0 0x500158 + +#define mmDMA0_CORE_WR_RATE_LIM_CFG_1 0x50015C + +#define mmDMA0_CORE_ERR_CFG 0x500160 + +#define mmDMA0_CORE_ERR_CAUSE 0x500164 + +#define mmDMA0_CORE_ERRMSG_ADDR_LO 0x500170 + +#define mmDMA0_CORE_ERRMSG_ADDR_HI 0x500174 + +#define mmDMA0_CORE_ERRMSG_WDATA 0x500178 + +#define mmDMA0_CORE_STS0 0x500190 + +#define mmDMA0_CORE_STS1 0x500194 + +#define mmDMA0_CORE_RD_DBGMEM_ADD 0x500200 + +#define mmDMA0_CORE_RD_DBGMEM_DATA_WR 0x500204 + +#define mmDMA0_CORE_RD_DBGMEM_DATA_RD 0x500208 + +#define mmDMA0_CORE_RD_DBGMEM_CTRL 0x50020C + +#define mmDMA0_CORE_RD_DBGMEM_RC 0x500210 + +#define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT 0x500220 + +#define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT 0x500224 + +#define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT 0x500228 + +#define mmDMA0_CORE_DBG_DESC_CNT 0x50022C + +#define mmDMA0_CORE_DBG_STS 0x500230 + +#define mmDMA0_CORE_DBG_RD_DESC_ID 0x500234 + +#define mmDMA0_CORE_DBG_WR_DESC_ID 0x500238 + +#endif /* ASIC_REG_DMA0_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h new file mode 100644 index 000000000000..48376aabc3ba --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_QM_MASKS_H_ +#define ASIC_REG_DMA0_QM_MASKS_H_ + +/* + ***************************************** + * DMA0_QM (Prototype: QMAN) + ***************************************** + */ + +/* DMA0_QM_GLBL_CFG0 */ +#define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define DMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* DMA0_QM_GLBL_CFG1 */ +#define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define DMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define DMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define DMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define DMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* DMA0_QM_GLBL_PROT */ +#define DMA0_QM_GLBL_PROT_PQF_SHIFT 0 +#define DMA0_QM_GLBL_PROT_PQF_MASK 0xF +#define DMA0_QM_GLBL_PROT_CQF_SHIFT 4 +#define DMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define DMA0_QM_GLBL_PROT_CP_SHIFT 9 +#define DMA0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define DMA0_QM_GLBL_PROT_ERR_SHIFT 14 +#define DMA0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_PROT_ARB_SHIFT 15 +#define DMA0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* DMA0_QM_GLBL_ERR_CFG */ +#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define DMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* DMA0_QM_GLBL_SECURE_PROPS */ +#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define DMA0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* DMA0_QM_GLBL_NON_SECURE_PROPS */ +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define DMA0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* DMA0_QM_GLBL_STS0 */ +#define DMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define DMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define DMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define DMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define DMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define DMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define DMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define DMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define DMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define DMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define DMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* DMA0_QM_GLBL_STS1 */ +#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define DMA0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_STS1_4 */ +#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_MSG_EN */ +#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define DMA0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_GLBL_MSG_EN_4 */ +#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define DMA0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define DMA0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define DMA0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define DMA0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define DMA0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define DMA0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* DMA0_QM_PQ_BASE_LO */ +#define DMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define DMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_BASE_HI */ +#define DMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define DMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_SIZE */ +#define DMA0_QM_PQ_SIZE_VAL_SHIFT 0 +#define DMA0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_PI */ +#define DMA0_QM_PQ_PI_VAL_SHIFT 0 +#define DMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_CI */ +#define DMA0_QM_PQ_CI_VAL_SHIFT 0 +#define DMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_PQ_CFG0 */ +#define DMA0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define DMA0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* DMA0_QM_PQ_CFG1 */ +#define DMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA0_QM_PQ_ARUSER_31_11 */ +#define DMA0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_PQ_STS0 */ +#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define DMA0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define DMA0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA0_QM_PQ_STS1 */ +#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define DMA0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define DMA0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define DMA0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* DMA0_QM_CQ_CFG0 */ +#define DMA0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define DMA0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* DMA0_QM_CQ_CFG1 */ +#define DMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define DMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define DMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_ARUSER_31_11 */ +#define DMA0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_CQ_STS0 */ +#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define DMA0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define DMA0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_STS1 */ +#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define DMA0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define DMA0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define DMA0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* DMA0_QM_CQ_PTR_LO_0 */ +#define DMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_0 */ +#define DMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_0 */ +#define DMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_0 */ +#define DMA0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_1 */ +#define DMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_1 */ +#define DMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_1 */ +#define DMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_1 */ +#define DMA0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_2 */ +#define DMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_2 */ +#define DMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_2 */ +#define DMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_2 */ +#define DMA0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_3 */ +#define DMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_3 */ +#define DMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_3 */ +#define DMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_3 */ +#define DMA0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_4 */ +#define DMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_4 */ +#define DMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_4 */ +#define DMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_4 */ +#define DMA0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_PTR_LO_STS */ +#define DMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_PTR_HI_STS */ +#define DMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_TSIZE_STS */ +#define DMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define DMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CQ_CTL_STS */ +#define DMA0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define DMA0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define DMA0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define DMA0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* DMA0_QM_CQ_IFIFO_CNT */ +#define DMA0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define DMA0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* DMA0_QM_CP_MSG_BASE0_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE0_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE1_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE1_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE2_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE2_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE3_ADDR_LO */ +#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_MSG_BASE3_ADDR_HI */ +#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_TSIZE_OFFSET */ +#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define DMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_FENCE0_RDATA */ +#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE1_RDATA */ +#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE2_RDATA */ +#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE3_RDATA */ +#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* DMA0_QM_CP_FENCE0_CNT */ +#define DMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE1_CNT */ +#define DMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE2_CNT */ +#define DMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_FENCE3_CNT */ +#define DMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define DMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* DMA0_QM_CP_STS */ +#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define DMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define DMA0_QM_CP_STS_ERDY_SHIFT 16 +#define DMA0_QM_CP_STS_ERDY_MASK 0x10000 +#define DMA0_QM_CP_STS_RRDY_SHIFT 17 +#define DMA0_QM_CP_STS_RRDY_MASK 0x20000 +#define DMA0_QM_CP_STS_MRDY_SHIFT 18 +#define DMA0_QM_CP_STS_MRDY_MASK 0x40000 +#define DMA0_QM_CP_STS_SW_STOP_SHIFT 19 +#define DMA0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define DMA0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define DMA0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define DMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* DMA0_QM_CP_CURRENT_INST_LO */ +#define DMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define DMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_CURRENT_INST_HI */ +#define DMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define DMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_CP_BARRIER_CFG */ +#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define DMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define DMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* DMA0_QM_CP_DBG_0 */ +#define DMA0_QM_CP_DBG_0_CS_SHIFT 0 +#define DMA0_QM_CP_DBG_0_CS_MASK 0xF +#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define DMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define DMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define DMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define DMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define DMA0_QM_CP_DBG_0_STALL_SHIFT 7 +#define DMA0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* DMA0_QM_CP_ARUSER_31_11 */ +#define DMA0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_CP_AWUSER_31_11 */ +#define DMA0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_ARB_CFG_0 */ +#define DMA0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define DMA0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define DMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define DMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define DMA0_QM_ARB_CFG_0_EN_SHIFT 8 +#define DMA0_QM_ARB_CFG_0_EN_MASK 0x100 +#define DMA0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define DMA0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define DMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* DMA0_QM_ARB_CHOISE_Q_PUSH */ +#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define DMA0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* DMA0_QM_ARB_WRR_WEIGHT */ +#define DMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define DMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_CFG_1 */ +#define DMA0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define DMA0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* DMA0_QM_ARB_MST_AVAIL_CRED */ +#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* DMA0_QM_ARB_MST_CRED_INC */ +#define DMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_SLAVE_EN */ +#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_MST_QUIET_PER */ +#define DMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_CHOISE_WDT */ +#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_SLV_ID */ +#define DMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* DMA0_QM_ARB_MSG_MAX_INFLIGHT */ +#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define DMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* DMA0_QM_ARB_MSG_AWUSER_31_11 */ +#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* DMA0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define DMA0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define DMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* DMA0_QM_ARB_BASE_LO */ +#define DMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define DMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_BASE_HI */ +#define DMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define DMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_STATE_STS */ +#define DMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_ARB_CHOISE_FULLNESS_STS */ +#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* DMA0_QM_ARB_MSG_STS */ +#define DMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define DMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define DMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* DMA0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define DMA0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* DMA0_QM_ARB_ERR_CAUSE */ +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define DMA0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define DMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* DMA0_QM_ARB_ERR_MSG_EN */ +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define DMA0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define DMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* DMA0_QM_ARB_ERR_STS_DRP */ +#define DMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define DMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* DMA0_QM_ARB_MST_CRED_STS */ +#define DMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define DMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* DMA0_QM_CGM_CFG */ +#define DMA0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define DMA0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define DMA0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define DMA0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define DMA0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define DMA0_QM_CGM_CFG_EN_SHIFT 31 +#define DMA0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* DMA0_QM_CGM_STS */ +#define DMA0_QM_CGM_STS_ST_SHIFT 0 +#define DMA0_QM_CGM_STS_ST_MASK 0x3 +#define DMA0_QM_CGM_STS_CG_SHIFT 4 +#define DMA0_QM_CGM_STS_CG_MASK 0x10 +#define DMA0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define DMA0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define DMA0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define DMA0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define DMA0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define DMA0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* DMA0_QM_CGM_CFG1 */ +#define DMA0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define DMA0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* DMA0_QM_LOCAL_RANGE_BASE */ +#define DMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define DMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* DMA0_QM_LOCAL_RANGE_SIZE */ +#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define DMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* DMA0_QM_CSMR_STRICT_PRIO_CFG */ +#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define DMA0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* DMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define DMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* DMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define DMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* DMA0_QM_GLBL_AXCACHE */ +#define DMA0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define DMA0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define DMA0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define DMA0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* DMA0_QM_IND_GW_APB_CFG */ +#define DMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define DMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define DMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define DMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* DMA0_QM_IND_GW_APB_WDATA */ +#define DMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define DMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_IND_GW_APB_RDATA */ +#define DMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define DMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_IND_GW_APB_STATUS */ +#define DMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define DMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define DMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define DMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* DMA0_QM_GLBL_ERR_ADDR_LO */ +#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_ERR_ADDR_HI */ +#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_ERR_WDATA */ +#define DMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define DMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* DMA0_QM_GLBL_MEM_INIT_BUSY */ +#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define DMA0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_DMA0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h new file mode 100644 index 000000000000..8e56a93d88a1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA0_QM_REGS_H_ +#define ASIC_REG_DMA0_QM_REGS_H_ + +/* + ***************************************** + * DMA0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA0_QM_GLBL_CFG0 0x508000 + +#define mmDMA0_QM_GLBL_CFG1 0x508004 + +#define mmDMA0_QM_GLBL_PROT 0x508008 + +#define mmDMA0_QM_GLBL_ERR_CFG 0x50800C + +#define mmDMA0_QM_GLBL_SECURE_PROPS_0 0x508010 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_1 0x508014 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_2 0x508018 + +#define mmDMA0_QM_GLBL_SECURE_PROPS_3 0x50801C + +#define mmDMA0_QM_GLBL_SECURE_PROPS_4 0x508020 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_0 0x508024 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_1 0x508028 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_2 0x50802C + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_3 0x508030 + +#define mmDMA0_QM_GLBL_NON_SECURE_PROPS_4 0x508034 + +#define mmDMA0_QM_GLBL_STS0 0x508038 + +#define mmDMA0_QM_GLBL_STS1_0 0x508040 + +#define mmDMA0_QM_GLBL_STS1_1 0x508044 + +#define mmDMA0_QM_GLBL_STS1_2 0x508048 + +#define mmDMA0_QM_GLBL_STS1_3 0x50804C + +#define mmDMA0_QM_GLBL_STS1_4 0x508050 + +#define mmDMA0_QM_GLBL_MSG_EN_0 0x508054 + +#define mmDMA0_QM_GLBL_MSG_EN_1 0x508058 + +#define mmDMA0_QM_GLBL_MSG_EN_2 0x50805C + +#define mmDMA0_QM_GLBL_MSG_EN_3 0x508060 + +#define mmDMA0_QM_GLBL_MSG_EN_4 0x508068 + +#define mmDMA0_QM_PQ_BASE_LO_0 0x508070 + +#define mmDMA0_QM_PQ_BASE_LO_1 0x508074 + +#define mmDMA0_QM_PQ_BASE_LO_2 0x508078 + +#define mmDMA0_QM_PQ_BASE_LO_3 0x50807C + +#define mmDMA0_QM_PQ_BASE_HI_0 0x508080 + +#define mmDMA0_QM_PQ_BASE_HI_1 0x508084 + +#define mmDMA0_QM_PQ_BASE_HI_2 0x508088 + +#define mmDMA0_QM_PQ_BASE_HI_3 0x50808C + +#define mmDMA0_QM_PQ_SIZE_0 0x508090 + +#define mmDMA0_QM_PQ_SIZE_1 0x508094 + +#define mmDMA0_QM_PQ_SIZE_2 0x508098 + +#define mmDMA0_QM_PQ_SIZE_3 0x50809C + +#define mmDMA0_QM_PQ_PI_0 0x5080A0 + +#define mmDMA0_QM_PQ_PI_1 0x5080A4 + +#define mmDMA0_QM_PQ_PI_2 0x5080A8 + +#define mmDMA0_QM_PQ_PI_3 0x5080AC + +#define mmDMA0_QM_PQ_CI_0 0x5080B0 + +#define mmDMA0_QM_PQ_CI_1 0x5080B4 + +#define mmDMA0_QM_PQ_CI_2 0x5080B8 + +#define mmDMA0_QM_PQ_CI_3 0x5080BC + +#define mmDMA0_QM_PQ_CFG0_0 0x5080C0 + +#define mmDMA0_QM_PQ_CFG0_1 0x5080C4 + +#define mmDMA0_QM_PQ_CFG0_2 0x5080C8 + +#define mmDMA0_QM_PQ_CFG0_3 0x5080CC + +#define mmDMA0_QM_PQ_CFG1_0 0x5080D0 + +#define mmDMA0_QM_PQ_CFG1_1 0x5080D4 + +#define mmDMA0_QM_PQ_CFG1_2 0x5080D8 + +#define mmDMA0_QM_PQ_CFG1_3 0x5080DC + +#define mmDMA0_QM_PQ_ARUSER_31_11_0 0x5080E0 + +#define mmDMA0_QM_PQ_ARUSER_31_11_1 0x5080E4 + +#define mmDMA0_QM_PQ_ARUSER_31_11_2 0x5080E8 + +#define mmDMA0_QM_PQ_ARUSER_31_11_3 0x5080EC + +#define mmDMA0_QM_PQ_STS0_0 0x5080F0 + +#define mmDMA0_QM_PQ_STS0_1 0x5080F4 + +#define mmDMA0_QM_PQ_STS0_2 0x5080F8 + +#define mmDMA0_QM_PQ_STS0_3 0x5080FC + +#define mmDMA0_QM_PQ_STS1_0 0x508100 + +#define mmDMA0_QM_PQ_STS1_1 0x508104 + +#define mmDMA0_QM_PQ_STS1_2 0x508108 + +#define mmDMA0_QM_PQ_STS1_3 0x50810C + +#define mmDMA0_QM_CQ_CFG0_0 0x508110 + +#define mmDMA0_QM_CQ_CFG0_1 0x508114 + +#define mmDMA0_QM_CQ_CFG0_2 0x508118 + +#define mmDMA0_QM_CQ_CFG0_3 0x50811C + +#define mmDMA0_QM_CQ_CFG0_4 0x508120 + +#define mmDMA0_QM_CQ_CFG1_0 0x508124 + +#define mmDMA0_QM_CQ_CFG1_1 0x508128 + +#define mmDMA0_QM_CQ_CFG1_2 0x50812C + +#define mmDMA0_QM_CQ_CFG1_3 0x508130 + +#define mmDMA0_QM_CQ_CFG1_4 0x508134 + +#define mmDMA0_QM_CQ_ARUSER_31_11_0 0x508138 + +#define mmDMA0_QM_CQ_ARUSER_31_11_1 0x50813C + +#define mmDMA0_QM_CQ_ARUSER_31_11_2 0x508140 + +#define mmDMA0_QM_CQ_ARUSER_31_11_3 0x508144 + +#define mmDMA0_QM_CQ_ARUSER_31_11_4 0x508148 + +#define mmDMA0_QM_CQ_STS0_0 0x50814C + +#define mmDMA0_QM_CQ_STS0_1 0x508150 + +#define mmDMA0_QM_CQ_STS0_2 0x508154 + +#define mmDMA0_QM_CQ_STS0_3 0x508158 + +#define mmDMA0_QM_CQ_STS0_4 0x50815C + +#define mmDMA0_QM_CQ_STS1_0 0x508160 + +#define mmDMA0_QM_CQ_STS1_1 0x508164 + +#define mmDMA0_QM_CQ_STS1_2 0x508168 + +#define mmDMA0_QM_CQ_STS1_3 0x50816C + +#define mmDMA0_QM_CQ_STS1_4 0x508170 + +#define mmDMA0_QM_CQ_PTR_LO_0 0x508174 + +#define mmDMA0_QM_CQ_PTR_HI_0 0x508178 + +#define mmDMA0_QM_CQ_TSIZE_0 0x50817C + +#define mmDMA0_QM_CQ_CTL_0 0x508180 + +#define mmDMA0_QM_CQ_PTR_LO_1 0x508184 + +#define mmDMA0_QM_CQ_PTR_HI_1 0x508188 + +#define mmDMA0_QM_CQ_TSIZE_1 0x50818C + +#define mmDMA0_QM_CQ_CTL_1 0x508190 + +#define mmDMA0_QM_CQ_PTR_LO_2 0x508194 + +#define mmDMA0_QM_CQ_PTR_HI_2 0x508198 + +#define mmDMA0_QM_CQ_TSIZE_2 0x50819C + +#define mmDMA0_QM_CQ_CTL_2 0x5081A0 + +#define mmDMA0_QM_CQ_PTR_LO_3 0x5081A4 + +#define mmDMA0_QM_CQ_PTR_HI_3 0x5081A8 + +#define mmDMA0_QM_CQ_TSIZE_3 0x5081AC + +#define mmDMA0_QM_CQ_CTL_3 0x5081B0 + +#define mmDMA0_QM_CQ_PTR_LO_4 0x5081B4 + +#define mmDMA0_QM_CQ_PTR_HI_4 0x5081B8 + +#define mmDMA0_QM_CQ_TSIZE_4 0x5081BC + +#define mmDMA0_QM_CQ_CTL_4 0x5081C0 + +#define mmDMA0_QM_CQ_PTR_LO_STS_0 0x5081C4 + +#define mmDMA0_QM_CQ_PTR_LO_STS_1 0x5081C8 + +#define mmDMA0_QM_CQ_PTR_LO_STS_2 0x5081CC + +#define mmDMA0_QM_CQ_PTR_LO_STS_3 0x5081D0 + +#define mmDMA0_QM_CQ_PTR_LO_STS_4 0x5081D4 + +#define mmDMA0_QM_CQ_PTR_HI_STS_0 0x5081D8 + +#define mmDMA0_QM_CQ_PTR_HI_STS_1 0x5081DC + +#define mmDMA0_QM_CQ_PTR_HI_STS_2 0x5081E0 + +#define mmDMA0_QM_CQ_PTR_HI_STS_3 0x5081E4 + +#define mmDMA0_QM_CQ_PTR_HI_STS_4 0x5081E8 + +#define mmDMA0_QM_CQ_TSIZE_STS_0 0x5081EC + +#define mmDMA0_QM_CQ_TSIZE_STS_1 0x5081F0 + +#define mmDMA0_QM_CQ_TSIZE_STS_2 0x5081F4 + +#define mmDMA0_QM_CQ_TSIZE_STS_3 0x5081F8 + +#define mmDMA0_QM_CQ_TSIZE_STS_4 0x5081FC + +#define mmDMA0_QM_CQ_CTL_STS_0 0x508200 + +#define mmDMA0_QM_CQ_CTL_STS_1 0x508204 + +#define mmDMA0_QM_CQ_CTL_STS_2 0x508208 + +#define mmDMA0_QM_CQ_CTL_STS_3 0x50820C + +#define mmDMA0_QM_CQ_CTL_STS_4 0x508210 + +#define mmDMA0_QM_CQ_IFIFO_CNT_0 0x508214 + +#define mmDMA0_QM_CQ_IFIFO_CNT_1 0x508218 + +#define mmDMA0_QM_CQ_IFIFO_CNT_2 0x50821C + +#define mmDMA0_QM_CQ_IFIFO_CNT_3 0x508220 + +#define mmDMA0_QM_CQ_IFIFO_CNT_4 0x508224 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x508228 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x50822C + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x508230 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x508234 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x508238 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x50823C + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x508240 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x508244 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x508248 + +#define mmDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x50824C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x508250 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x508254 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x508258 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x50825C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x508260 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x508264 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x508268 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x50826C + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x508270 + +#define mmDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x508274 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x508278 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x50827C + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x508280 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x508284 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x508288 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x50828C + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x508290 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x508294 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x508298 + +#define mmDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x50829C + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x5082A0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x5082A4 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x5082A8 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x5082AC + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x5082B0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x5082B4 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x5082B8 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x5082BC + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x5082C0 + +#define mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x5082C4 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_0 0x5082C8 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_1 0x5082CC + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_2 0x5082D0 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_3 0x5082D4 + +#define mmDMA0_QM_CP_LDMA_TSIZE_OFFSET_4 0x5082D8 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5082E0 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5082E4 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5082E8 + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5082EC + +#define mmDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5082F0 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5082F4 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5082F8 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5082FC + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x508300 + +#define mmDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x508304 + +#define mmDMA0_QM_CP_FENCE0_RDATA_0 0x508308 + +#define mmDMA0_QM_CP_FENCE0_RDATA_1 0x50830C + +#define mmDMA0_QM_CP_FENCE0_RDATA_2 0x508310 + +#define mmDMA0_QM_CP_FENCE0_RDATA_3 0x508314 + +#define mmDMA0_QM_CP_FENCE0_RDATA_4 0x508318 + +#define mmDMA0_QM_CP_FENCE1_RDATA_0 0x50831C + +#define mmDMA0_QM_CP_FENCE1_RDATA_1 0x508320 + +#define mmDMA0_QM_CP_FENCE1_RDATA_2 0x508324 + +#define mmDMA0_QM_CP_FENCE1_RDATA_3 0x508328 + +#define mmDMA0_QM_CP_FENCE1_RDATA_4 0x50832C + +#define mmDMA0_QM_CP_FENCE2_RDATA_0 0x508330 + +#define mmDMA0_QM_CP_FENCE2_RDATA_1 0x508334 + +#define mmDMA0_QM_CP_FENCE2_RDATA_2 0x508338 + +#define mmDMA0_QM_CP_FENCE2_RDATA_3 0x50833C + +#define mmDMA0_QM_CP_FENCE2_RDATA_4 0x508340 + +#define mmDMA0_QM_CP_FENCE3_RDATA_0 0x508344 + +#define mmDMA0_QM_CP_FENCE3_RDATA_1 0x508348 + +#define mmDMA0_QM_CP_FENCE3_RDATA_2 0x50834C + +#define mmDMA0_QM_CP_FENCE3_RDATA_3 0x508350 + +#define mmDMA0_QM_CP_FENCE3_RDATA_4 0x508354 + +#define mmDMA0_QM_CP_FENCE0_CNT_0 0x508358 + +#define mmDMA0_QM_CP_FENCE0_CNT_1 0x50835C + +#define mmDMA0_QM_CP_FENCE0_CNT_2 0x508360 + +#define mmDMA0_QM_CP_FENCE0_CNT_3 0x508364 + +#define mmDMA0_QM_CP_FENCE0_CNT_4 0x508368 + +#define mmDMA0_QM_CP_FENCE1_CNT_0 0x50836C + +#define mmDMA0_QM_CP_FENCE1_CNT_1 0x508370 + +#define mmDMA0_QM_CP_FENCE1_CNT_2 0x508374 + +#define mmDMA0_QM_CP_FENCE1_CNT_3 0x508378 + +#define mmDMA0_QM_CP_FENCE1_CNT_4 0x50837C + +#define mmDMA0_QM_CP_FENCE2_CNT_0 0x508380 + +#define mmDMA0_QM_CP_FENCE2_CNT_1 0x508384 + +#define mmDMA0_QM_CP_FENCE2_CNT_2 0x508388 + +#define mmDMA0_QM_CP_FENCE2_CNT_3 0x50838C + +#define mmDMA0_QM_CP_FENCE2_CNT_4 0x508390 + +#define mmDMA0_QM_CP_FENCE3_CNT_0 0x508394 + +#define mmDMA0_QM_CP_FENCE3_CNT_1 0x508398 + +#define mmDMA0_QM_CP_FENCE3_CNT_2 0x50839C + +#define mmDMA0_QM_CP_FENCE3_CNT_3 0x5083A0 + +#define mmDMA0_QM_CP_FENCE3_CNT_4 0x5083A4 + +#define mmDMA0_QM_CP_STS_0 0x5083A8 + +#define mmDMA0_QM_CP_STS_1 0x5083AC + +#define mmDMA0_QM_CP_STS_2 0x5083B0 + +#define mmDMA0_QM_CP_STS_3 0x5083B4 + +#define mmDMA0_QM_CP_STS_4 0x5083B8 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_0 0x5083BC + +#define mmDMA0_QM_CP_CURRENT_INST_LO_1 0x5083C0 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_2 0x5083C4 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_3 0x5083C8 + +#define mmDMA0_QM_CP_CURRENT_INST_LO_4 0x5083CC + +#define mmDMA0_QM_CP_CURRENT_INST_HI_0 0x5083D0 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_1 0x5083D4 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_2 0x5083D8 + +#define mmDMA0_QM_CP_CURRENT_INST_HI_3 0x5083DC + +#define mmDMA0_QM_CP_CURRENT_INST_HI_4 0x5083E0 + +#define mmDMA0_QM_CP_BARRIER_CFG_0 0x5083F4 + +#define mmDMA0_QM_CP_BARRIER_CFG_1 0x5083F8 + +#define mmDMA0_QM_CP_BARRIER_CFG_2 0x5083FC + +#define mmDMA0_QM_CP_BARRIER_CFG_3 0x508400 + +#define mmDMA0_QM_CP_BARRIER_CFG_4 0x508404 + +#define mmDMA0_QM_CP_DBG_0_0 0x508408 + +#define mmDMA0_QM_CP_DBG_0_1 0x50840C + +#define mmDMA0_QM_CP_DBG_0_2 0x508410 + +#define mmDMA0_QM_CP_DBG_0_3 0x508414 + +#define mmDMA0_QM_CP_DBG_0_4 0x508418 + +#define mmDMA0_QM_CP_ARUSER_31_11_0 0x50841C + +#define mmDMA0_QM_CP_ARUSER_31_11_1 0x508420 + +#define mmDMA0_QM_CP_ARUSER_31_11_2 0x508424 + +#define mmDMA0_QM_CP_ARUSER_31_11_3 0x508428 + +#define mmDMA0_QM_CP_ARUSER_31_11_4 0x50842C + +#define mmDMA0_QM_CP_AWUSER_31_11_0 0x508430 + +#define mmDMA0_QM_CP_AWUSER_31_11_1 0x508434 + +#define mmDMA0_QM_CP_AWUSER_31_11_2 0x508438 + +#define mmDMA0_QM_CP_AWUSER_31_11_3 0x50843C + +#define mmDMA0_QM_CP_AWUSER_31_11_4 0x508440 + +#define mmDMA0_QM_ARB_CFG_0 0x508A00 + +#define mmDMA0_QM_ARB_CHOISE_Q_PUSH 0x508A04 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_0 0x508A08 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_1 0x508A0C + +#define mmDMA0_QM_ARB_WRR_WEIGHT_2 0x508A10 + +#define mmDMA0_QM_ARB_WRR_WEIGHT_3 0x508A14 + +#define mmDMA0_QM_ARB_CFG_1 0x508A18 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_0 0x508A20 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_1 0x508A24 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_2 0x508A28 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_3 0x508A2C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_4 0x508A30 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_5 0x508A34 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_6 0x508A38 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_7 0x508A3C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_8 0x508A40 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_9 0x508A44 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_10 0x508A48 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_11 0x508A4C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_12 0x508A50 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_13 0x508A54 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_14 0x508A58 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_15 0x508A5C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_16 0x508A60 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_17 0x508A64 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_18 0x508A68 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_19 0x508A6C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_20 0x508A70 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_21 0x508A74 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_22 0x508A78 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_23 0x508A7C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_24 0x508A80 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_25 0x508A84 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_26 0x508A88 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_27 0x508A8C + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_28 0x508A90 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_29 0x508A94 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_30 0x508A98 + +#define mmDMA0_QM_ARB_MST_AVAIL_CRED_31 0x508A9C + +#define mmDMA0_QM_ARB_MST_CRED_INC 0x508AA0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x508AA4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x508AA8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x508AAC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x508AB0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x508AB4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x508AB8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x508ABC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x508AC0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x508AC4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x508AC8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x508ACC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x508AD0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x508AD4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x508AD8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x508ADC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x508AE0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x508AE4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x508AE8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x508AEC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x508AF0 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x508AF4 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x508AF8 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x508AFC + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x508B00 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x508B04 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x508B08 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x508B0C + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x508B10 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x508B14 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x508B18 + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x508B1C + +#define mmDMA0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x508B20 + +#define mmDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x508B28 + +#define mmDMA0_QM_ARB_MST_SLAVE_EN 0x508B2C + +#define mmDMA0_QM_ARB_MST_QUIET_PER 0x508B34 + +#define mmDMA0_QM_ARB_SLV_CHOISE_WDT 0x508B38 + +#define mmDMA0_QM_ARB_SLV_ID 0x508B3C + +#define mmDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x508B44 + +#define mmDMA0_QM_ARB_MSG_AWUSER_31_11 0x508B48 + +#define mmDMA0_QM_ARB_MSG_AWUSER_SEC_PROP 0x508B4C + +#define mmDMA0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x508B50 + +#define mmDMA0_QM_ARB_BASE_LO 0x508B54 + +#define mmDMA0_QM_ARB_BASE_HI 0x508B58 + +#define mmDMA0_QM_ARB_STATE_STS 0x508B80 + +#define mmDMA0_QM_ARB_CHOISE_FULLNESS_STS 0x508B84 + +#define mmDMA0_QM_ARB_MSG_STS 0x508B88 + +#define mmDMA0_QM_ARB_SLV_CHOISE_Q_HEAD 0x508B8C + +#define mmDMA0_QM_ARB_ERR_CAUSE 0x508B9C + +#define mmDMA0_QM_ARB_ERR_MSG_EN 0x508BA0 + +#define mmDMA0_QM_ARB_ERR_STS_DRP 0x508BA8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_0 0x508BB0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_1 0x508BB4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_2 0x508BB8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_3 0x508BBC + +#define mmDMA0_QM_ARB_MST_CRED_STS_4 0x508BC0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_5 0x508BC4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_6 0x508BC8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_7 0x508BCC + +#define mmDMA0_QM_ARB_MST_CRED_STS_8 0x508BD0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_9 0x508BD4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_10 0x508BD8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_11 0x508BDC + +#define mmDMA0_QM_ARB_MST_CRED_STS_12 0x508BE0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_13 0x508BE4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_14 0x508BE8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_15 0x508BEC + +#define mmDMA0_QM_ARB_MST_CRED_STS_16 0x508BF0 + +#define mmDMA0_QM_ARB_MST_CRED_STS_17 0x508BF4 + +#define mmDMA0_QM_ARB_MST_CRED_STS_18 0x508BF8 + +#define mmDMA0_QM_ARB_MST_CRED_STS_19 0x508BFC + +#define mmDMA0_QM_ARB_MST_CRED_STS_20 0x508C00 + +#define mmDMA0_QM_ARB_MST_CRED_STS_21 0x508C04 + +#define mmDMA0_QM_ARB_MST_CRED_STS_22 0x508C08 + +#define mmDMA0_QM_ARB_MST_CRED_STS_23 0x508C0C + +#define mmDMA0_QM_ARB_MST_CRED_STS_24 0x508C10 + +#define mmDMA0_QM_ARB_MST_CRED_STS_25 0x508C14 + +#define mmDMA0_QM_ARB_MST_CRED_STS_26 0x508C18 + +#define mmDMA0_QM_ARB_MST_CRED_STS_27 0x508C1C + +#define mmDMA0_QM_ARB_MST_CRED_STS_28 0x508C20 + +#define mmDMA0_QM_ARB_MST_CRED_STS_29 0x508C24 + +#define mmDMA0_QM_ARB_MST_CRED_STS_30 0x508C28 + +#define mmDMA0_QM_ARB_MST_CRED_STS_31 0x508C2C + +#define mmDMA0_QM_CGM_CFG 0x508C70 + +#define mmDMA0_QM_CGM_STS 0x508C74 + +#define mmDMA0_QM_CGM_CFG1 0x508C78 + +#define mmDMA0_QM_LOCAL_RANGE_BASE 0x508C80 + +#define mmDMA0_QM_LOCAL_RANGE_SIZE 0x508C84 + +#define mmDMA0_QM_CSMR_STRICT_PRIO_CFG 0x508C90 + +#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x508C94 + +#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x508C98 + +#define mmDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x508C9C + +#define mmDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x508CA0 + +#define mmDMA0_QM_GLBL_AXCACHE 0x508CA4 + +#define mmDMA0_QM_IND_GW_APB_CFG 0x508CB0 + +#define mmDMA0_QM_IND_GW_APB_WDATA 0x508CB4 + +#define mmDMA0_QM_IND_GW_APB_RDATA 0x508CB8 + +#define mmDMA0_QM_IND_GW_APB_STATUS 0x508CBC + +#define mmDMA0_QM_GLBL_ERR_ADDR_LO 0x508CD0 + +#define mmDMA0_QM_GLBL_ERR_ADDR_HI 0x508CD4 + +#define mmDMA0_QM_GLBL_ERR_WDATA 0x508CD8 + +#define mmDMA0_QM_GLBL_MEM_INIT_BUSY 0x508D00 + +#endif /* ASIC_REG_DMA0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h new file mode 100644 index 000000000000..4d8d8f26c5d4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA1_CORE_REGS_H_ +#define ASIC_REG_DMA1_CORE_REGS_H_ + +/* + ***************************************** + * DMA1_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA1_CORE_CFG_0 0x520000 + +#define mmDMA1_CORE_CFG_1 0x520004 + +#define mmDMA1_CORE_LBW_MAX_OUTSTAND 0x520008 + +#define mmDMA1_CORE_SRC_BASE_LO 0x520014 + +#define mmDMA1_CORE_SRC_BASE_HI 0x520018 + +#define mmDMA1_CORE_DST_BASE_LO 0x52001C + +#define mmDMA1_CORE_DST_BASE_HI 0x520020 + +#define mmDMA1_CORE_SRC_TSIZE_1 0x52002C + +#define mmDMA1_CORE_SRC_STRIDE_1 0x520030 + +#define mmDMA1_CORE_SRC_TSIZE_2 0x520034 + +#define mmDMA1_CORE_SRC_STRIDE_2 0x520038 + +#define mmDMA1_CORE_SRC_TSIZE_3 0x52003C + +#define mmDMA1_CORE_SRC_STRIDE_3 0x520040 + +#define mmDMA1_CORE_SRC_TSIZE_4 0x520044 + +#define mmDMA1_CORE_SRC_STRIDE_4 0x520048 + +#define mmDMA1_CORE_SRC_TSIZE_0 0x52004C + +#define mmDMA1_CORE_DST_TSIZE_1 0x520054 + +#define mmDMA1_CORE_DST_STRIDE_1 0x520058 + +#define mmDMA1_CORE_DST_TSIZE_2 0x52005C + +#define mmDMA1_CORE_DST_STRIDE_2 0x520060 + +#define mmDMA1_CORE_DST_TSIZE_3 0x520064 + +#define mmDMA1_CORE_DST_STRIDE_3 0x520068 + +#define mmDMA1_CORE_DST_TSIZE_4 0x52006C + +#define mmDMA1_CORE_DST_STRIDE_4 0x520070 + +#define mmDMA1_CORE_DST_TSIZE_0 0x520074 + +#define mmDMA1_CORE_COMMIT 0x520078 + +#define mmDMA1_CORE_WR_COMP_WDATA 0x52007C + +#define mmDMA1_CORE_WR_COMP_ADDR_LO 0x520080 + +#define mmDMA1_CORE_WR_COMP_ADDR_HI 0x520084 + +#define mmDMA1_CORE_WR_COMP_AWUSER_31_11 0x520088 + +#define mmDMA1_CORE_TE_NUMROWS 0x520094 + +#define mmDMA1_CORE_PROT 0x5200B8 + +#define mmDMA1_CORE_SECURE_PROPS 0x5200F0 + +#define mmDMA1_CORE_NON_SECURE_PROPS 0x5200F4 + +#define mmDMA1_CORE_RD_MAX_OUTSTAND 0x520100 + +#define mmDMA1_CORE_RD_MAX_SIZE 0x520104 + +#define mmDMA1_CORE_RD_ARCACHE 0x520108 + +#define mmDMA1_CORE_RD_ARUSER_31_11 0x520110 + +#define mmDMA1_CORE_RD_INFLIGHTS 0x520114 + +#define mmDMA1_CORE_WR_MAX_OUTSTAND 0x520120 + +#define mmDMA1_CORE_WR_MAX_AWID 0x520124 + +#define mmDMA1_CORE_WR_AWCACHE 0x520128 + +#define mmDMA1_CORE_WR_AWUSER_31_11 0x520130 + +#define mmDMA1_CORE_WR_INFLIGHTS 0x520134 + +#define mmDMA1_CORE_RD_RATE_LIM_CFG_0 0x520150 + +#define mmDMA1_CORE_RD_RATE_LIM_CFG_1 0x520154 + +#define mmDMA1_CORE_WR_RATE_LIM_CFG_0 0x520158 + +#define mmDMA1_CORE_WR_RATE_LIM_CFG_1 0x52015C + +#define mmDMA1_CORE_ERR_CFG 0x520160 + +#define mmDMA1_CORE_ERR_CAUSE 0x520164 + +#define mmDMA1_CORE_ERRMSG_ADDR_LO 0x520170 + +#define mmDMA1_CORE_ERRMSG_ADDR_HI 0x520174 + +#define mmDMA1_CORE_ERRMSG_WDATA 0x520178 + +#define mmDMA1_CORE_STS0 0x520190 + +#define mmDMA1_CORE_STS1 0x520194 + +#define mmDMA1_CORE_RD_DBGMEM_ADD 0x520200 + +#define mmDMA1_CORE_RD_DBGMEM_DATA_WR 0x520204 + +#define mmDMA1_CORE_RD_DBGMEM_DATA_RD 0x520208 + +#define mmDMA1_CORE_RD_DBGMEM_CTRL 0x52020C + +#define mmDMA1_CORE_RD_DBGMEM_RC 0x520210 + +#define mmDMA1_CORE_DBG_HBW_AXI_AR_CNT 0x520220 + +#define mmDMA1_CORE_DBG_HBW_AXI_AW_CNT 0x520224 + +#define mmDMA1_CORE_DBG_LBW_AXI_AW_CNT 0x520228 + +#define mmDMA1_CORE_DBG_DESC_CNT 0x52022C + +#define mmDMA1_CORE_DBG_STS 0x520230 + +#define mmDMA1_CORE_DBG_RD_DESC_ID 0x520234 + +#define mmDMA1_CORE_DBG_WR_DESC_ID 0x520238 + +#endif /* ASIC_REG_DMA1_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h new file mode 100644 index 000000000000..c3ef300849be --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma1_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA1_QM_REGS_H_ +#define ASIC_REG_DMA1_QM_REGS_H_ + +/* + ***************************************** + * DMA1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA1_QM_GLBL_CFG0 0x528000 + +#define mmDMA1_QM_GLBL_CFG1 0x528004 + +#define mmDMA1_QM_GLBL_PROT 0x528008 + +#define mmDMA1_QM_GLBL_ERR_CFG 0x52800C + +#define mmDMA1_QM_GLBL_SECURE_PROPS_0 0x528010 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_1 0x528014 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_2 0x528018 + +#define mmDMA1_QM_GLBL_SECURE_PROPS_3 0x52801C + +#define mmDMA1_QM_GLBL_SECURE_PROPS_4 0x528020 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_0 0x528024 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_1 0x528028 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_2 0x52802C + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_3 0x528030 + +#define mmDMA1_QM_GLBL_NON_SECURE_PROPS_4 0x528034 + +#define mmDMA1_QM_GLBL_STS0 0x528038 + +#define mmDMA1_QM_GLBL_STS1_0 0x528040 + +#define mmDMA1_QM_GLBL_STS1_1 0x528044 + +#define mmDMA1_QM_GLBL_STS1_2 0x528048 + +#define mmDMA1_QM_GLBL_STS1_3 0x52804C + +#define mmDMA1_QM_GLBL_STS1_4 0x528050 + +#define mmDMA1_QM_GLBL_MSG_EN_0 0x528054 + +#define mmDMA1_QM_GLBL_MSG_EN_1 0x528058 + +#define mmDMA1_QM_GLBL_MSG_EN_2 0x52805C + +#define mmDMA1_QM_GLBL_MSG_EN_3 0x528060 + +#define mmDMA1_QM_GLBL_MSG_EN_4 0x528068 + +#define mmDMA1_QM_PQ_BASE_LO_0 0x528070 + +#define mmDMA1_QM_PQ_BASE_LO_1 0x528074 + +#define mmDMA1_QM_PQ_BASE_LO_2 0x528078 + +#define mmDMA1_QM_PQ_BASE_LO_3 0x52807C + +#define mmDMA1_QM_PQ_BASE_HI_0 0x528080 + +#define mmDMA1_QM_PQ_BASE_HI_1 0x528084 + +#define mmDMA1_QM_PQ_BASE_HI_2 0x528088 + +#define mmDMA1_QM_PQ_BASE_HI_3 0x52808C + +#define mmDMA1_QM_PQ_SIZE_0 0x528090 + +#define mmDMA1_QM_PQ_SIZE_1 0x528094 + +#define mmDMA1_QM_PQ_SIZE_2 0x528098 + +#define mmDMA1_QM_PQ_SIZE_3 0x52809C + +#define mmDMA1_QM_PQ_PI_0 0x5280A0 + +#define mmDMA1_QM_PQ_PI_1 0x5280A4 + +#define mmDMA1_QM_PQ_PI_2 0x5280A8 + +#define mmDMA1_QM_PQ_PI_3 0x5280AC + +#define mmDMA1_QM_PQ_CI_0 0x5280B0 + +#define mmDMA1_QM_PQ_CI_1 0x5280B4 + +#define mmDMA1_QM_PQ_CI_2 0x5280B8 + +#define mmDMA1_QM_PQ_CI_3 0x5280BC + +#define mmDMA1_QM_PQ_CFG0_0 0x5280C0 + +#define mmDMA1_QM_PQ_CFG0_1 0x5280C4 + +#define mmDMA1_QM_PQ_CFG0_2 0x5280C8 + +#define mmDMA1_QM_PQ_CFG0_3 0x5280CC + +#define mmDMA1_QM_PQ_CFG1_0 0x5280D0 + +#define mmDMA1_QM_PQ_CFG1_1 0x5280D4 + +#define mmDMA1_QM_PQ_CFG1_2 0x5280D8 + +#define mmDMA1_QM_PQ_CFG1_3 0x5280DC + +#define mmDMA1_QM_PQ_ARUSER_31_11_0 0x5280E0 + +#define mmDMA1_QM_PQ_ARUSER_31_11_1 0x5280E4 + +#define mmDMA1_QM_PQ_ARUSER_31_11_2 0x5280E8 + +#define mmDMA1_QM_PQ_ARUSER_31_11_3 0x5280EC + +#define mmDMA1_QM_PQ_STS0_0 0x5280F0 + +#define mmDMA1_QM_PQ_STS0_1 0x5280F4 + +#define mmDMA1_QM_PQ_STS0_2 0x5280F8 + +#define mmDMA1_QM_PQ_STS0_3 0x5280FC + +#define mmDMA1_QM_PQ_STS1_0 0x528100 + +#define mmDMA1_QM_PQ_STS1_1 0x528104 + +#define mmDMA1_QM_PQ_STS1_2 0x528108 + +#define mmDMA1_QM_PQ_STS1_3 0x52810C + +#define mmDMA1_QM_CQ_CFG0_0 0x528110 + +#define mmDMA1_QM_CQ_CFG0_1 0x528114 + +#define mmDMA1_QM_CQ_CFG0_2 0x528118 + +#define mmDMA1_QM_CQ_CFG0_3 0x52811C + +#define mmDMA1_QM_CQ_CFG0_4 0x528120 + +#define mmDMA1_QM_CQ_CFG1_0 0x528124 + +#define mmDMA1_QM_CQ_CFG1_1 0x528128 + +#define mmDMA1_QM_CQ_CFG1_2 0x52812C + +#define mmDMA1_QM_CQ_CFG1_3 0x528130 + +#define mmDMA1_QM_CQ_CFG1_4 0x528134 + +#define mmDMA1_QM_CQ_ARUSER_31_11_0 0x528138 + +#define mmDMA1_QM_CQ_ARUSER_31_11_1 0x52813C + +#define mmDMA1_QM_CQ_ARUSER_31_11_2 0x528140 + +#define mmDMA1_QM_CQ_ARUSER_31_11_3 0x528144 + +#define mmDMA1_QM_CQ_ARUSER_31_11_4 0x528148 + +#define mmDMA1_QM_CQ_STS0_0 0x52814C + +#define mmDMA1_QM_CQ_STS0_1 0x528150 + +#define mmDMA1_QM_CQ_STS0_2 0x528154 + +#define mmDMA1_QM_CQ_STS0_3 0x528158 + +#define mmDMA1_QM_CQ_STS0_4 0x52815C + +#define mmDMA1_QM_CQ_STS1_0 0x528160 + +#define mmDMA1_QM_CQ_STS1_1 0x528164 + +#define mmDMA1_QM_CQ_STS1_2 0x528168 + +#define mmDMA1_QM_CQ_STS1_3 0x52816C + +#define mmDMA1_QM_CQ_STS1_4 0x528170 + +#define mmDMA1_QM_CQ_PTR_LO_0 0x528174 + +#define mmDMA1_QM_CQ_PTR_HI_0 0x528178 + +#define mmDMA1_QM_CQ_TSIZE_0 0x52817C + +#define mmDMA1_QM_CQ_CTL_0 0x528180 + +#define mmDMA1_QM_CQ_PTR_LO_1 0x528184 + +#define mmDMA1_QM_CQ_PTR_HI_1 0x528188 + +#define mmDMA1_QM_CQ_TSIZE_1 0x52818C + +#define mmDMA1_QM_CQ_CTL_1 0x528190 + +#define mmDMA1_QM_CQ_PTR_LO_2 0x528194 + +#define mmDMA1_QM_CQ_PTR_HI_2 0x528198 + +#define mmDMA1_QM_CQ_TSIZE_2 0x52819C + +#define mmDMA1_QM_CQ_CTL_2 0x5281A0 + +#define mmDMA1_QM_CQ_PTR_LO_3 0x5281A4 + +#define mmDMA1_QM_CQ_PTR_HI_3 0x5281A8 + +#define mmDMA1_QM_CQ_TSIZE_3 0x5281AC + +#define mmDMA1_QM_CQ_CTL_3 0x5281B0 + +#define mmDMA1_QM_CQ_PTR_LO_4 0x5281B4 + +#define mmDMA1_QM_CQ_PTR_HI_4 0x5281B8 + +#define mmDMA1_QM_CQ_TSIZE_4 0x5281BC + +#define mmDMA1_QM_CQ_CTL_4 0x5281C0 + +#define mmDMA1_QM_CQ_PTR_LO_STS_0 0x5281C4 + +#define mmDMA1_QM_CQ_PTR_LO_STS_1 0x5281C8 + +#define mmDMA1_QM_CQ_PTR_LO_STS_2 0x5281CC + +#define mmDMA1_QM_CQ_PTR_LO_STS_3 0x5281D0 + +#define mmDMA1_QM_CQ_PTR_LO_STS_4 0x5281D4 + +#define mmDMA1_QM_CQ_PTR_HI_STS_0 0x5281D8 + +#define mmDMA1_QM_CQ_PTR_HI_STS_1 0x5281DC + +#define mmDMA1_QM_CQ_PTR_HI_STS_2 0x5281E0 + +#define mmDMA1_QM_CQ_PTR_HI_STS_3 0x5281E4 + +#define mmDMA1_QM_CQ_PTR_HI_STS_4 0x5281E8 + +#define mmDMA1_QM_CQ_TSIZE_STS_0 0x5281EC + +#define mmDMA1_QM_CQ_TSIZE_STS_1 0x5281F0 + +#define mmDMA1_QM_CQ_TSIZE_STS_2 0x5281F4 + +#define mmDMA1_QM_CQ_TSIZE_STS_3 0x5281F8 + +#define mmDMA1_QM_CQ_TSIZE_STS_4 0x5281FC + +#define mmDMA1_QM_CQ_CTL_STS_0 0x528200 + +#define mmDMA1_QM_CQ_CTL_STS_1 0x528204 + +#define mmDMA1_QM_CQ_CTL_STS_2 0x528208 + +#define mmDMA1_QM_CQ_CTL_STS_3 0x52820C + +#define mmDMA1_QM_CQ_CTL_STS_4 0x528210 + +#define mmDMA1_QM_CQ_IFIFO_CNT_0 0x528214 + +#define mmDMA1_QM_CQ_IFIFO_CNT_1 0x528218 + +#define mmDMA1_QM_CQ_IFIFO_CNT_2 0x52821C + +#define mmDMA1_QM_CQ_IFIFO_CNT_3 0x528220 + +#define mmDMA1_QM_CQ_IFIFO_CNT_4 0x528224 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_0 0x528228 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_1 0x52822C + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_2 0x528230 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_3 0x528234 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_LO_4 0x528238 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_0 0x52823C + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_1 0x528240 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_2 0x528244 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_3 0x528248 + +#define mmDMA1_QM_CP_MSG_BASE0_ADDR_HI_4 0x52824C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_0 0x528250 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_1 0x528254 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_2 0x528258 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_3 0x52825C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_LO_4 0x528260 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_0 0x528264 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_1 0x528268 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_2 0x52826C + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_3 0x528270 + +#define mmDMA1_QM_CP_MSG_BASE1_ADDR_HI_4 0x528274 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_0 0x528278 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_1 0x52827C + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_2 0x528280 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_3 0x528284 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_LO_4 0x528288 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_0 0x52828C + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_1 0x528290 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_2 0x528294 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_3 0x528298 + +#define mmDMA1_QM_CP_MSG_BASE2_ADDR_HI_4 0x52829C + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_0 0x5282A0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_1 0x5282A4 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_2 0x5282A8 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_3 0x5282AC + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_LO_4 0x5282B0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_0 0x5282B4 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_1 0x5282B8 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_2 0x5282BC + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_3 0x5282C0 + +#define mmDMA1_QM_CP_MSG_BASE3_ADDR_HI_4 0x5282C4 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_0 0x5282C8 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_1 0x5282CC + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_2 0x5282D0 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_3 0x5282D4 + +#define mmDMA1_QM_CP_LDMA_TSIZE_OFFSET_4 0x5282D8 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5282E0 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5282E4 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5282E8 + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5282EC + +#define mmDMA1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5282F0 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5282F4 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5282F8 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5282FC + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x528300 + +#define mmDMA1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x528304 + +#define mmDMA1_QM_CP_FENCE0_RDATA_0 0x528308 + +#define mmDMA1_QM_CP_FENCE0_RDATA_1 0x52830C + +#define mmDMA1_QM_CP_FENCE0_RDATA_2 0x528310 + +#define mmDMA1_QM_CP_FENCE0_RDATA_3 0x528314 + +#define mmDMA1_QM_CP_FENCE0_RDATA_4 0x528318 + +#define mmDMA1_QM_CP_FENCE1_RDATA_0 0x52831C + +#define mmDMA1_QM_CP_FENCE1_RDATA_1 0x528320 + +#define mmDMA1_QM_CP_FENCE1_RDATA_2 0x528324 + +#define mmDMA1_QM_CP_FENCE1_RDATA_3 0x528328 + +#define mmDMA1_QM_CP_FENCE1_RDATA_4 0x52832C + +#define mmDMA1_QM_CP_FENCE2_RDATA_0 0x528330 + +#define mmDMA1_QM_CP_FENCE2_RDATA_1 0x528334 + +#define mmDMA1_QM_CP_FENCE2_RDATA_2 0x528338 + +#define mmDMA1_QM_CP_FENCE2_RDATA_3 0x52833C + +#define mmDMA1_QM_CP_FENCE2_RDATA_4 0x528340 + +#define mmDMA1_QM_CP_FENCE3_RDATA_0 0x528344 + +#define mmDMA1_QM_CP_FENCE3_RDATA_1 0x528348 + +#define mmDMA1_QM_CP_FENCE3_RDATA_2 0x52834C + +#define mmDMA1_QM_CP_FENCE3_RDATA_3 0x528350 + +#define mmDMA1_QM_CP_FENCE3_RDATA_4 0x528354 + +#define mmDMA1_QM_CP_FENCE0_CNT_0 0x528358 + +#define mmDMA1_QM_CP_FENCE0_CNT_1 0x52835C + +#define mmDMA1_QM_CP_FENCE0_CNT_2 0x528360 + +#define mmDMA1_QM_CP_FENCE0_CNT_3 0x528364 + +#define mmDMA1_QM_CP_FENCE0_CNT_4 0x528368 + +#define mmDMA1_QM_CP_FENCE1_CNT_0 0x52836C + +#define mmDMA1_QM_CP_FENCE1_CNT_1 0x528370 + +#define mmDMA1_QM_CP_FENCE1_CNT_2 0x528374 + +#define mmDMA1_QM_CP_FENCE1_CNT_3 0x528378 + +#define mmDMA1_QM_CP_FENCE1_CNT_4 0x52837C + +#define mmDMA1_QM_CP_FENCE2_CNT_0 0x528380 + +#define mmDMA1_QM_CP_FENCE2_CNT_1 0x528384 + +#define mmDMA1_QM_CP_FENCE2_CNT_2 0x528388 + +#define mmDMA1_QM_CP_FENCE2_CNT_3 0x52838C + +#define mmDMA1_QM_CP_FENCE2_CNT_4 0x528390 + +#define mmDMA1_QM_CP_FENCE3_CNT_0 0x528394 + +#define mmDMA1_QM_CP_FENCE3_CNT_1 0x528398 + +#define mmDMA1_QM_CP_FENCE3_CNT_2 0x52839C + +#define mmDMA1_QM_CP_FENCE3_CNT_3 0x5283A0 + +#define mmDMA1_QM_CP_FENCE3_CNT_4 0x5283A4 + +#define mmDMA1_QM_CP_STS_0 0x5283A8 + +#define mmDMA1_QM_CP_STS_1 0x5283AC + +#define mmDMA1_QM_CP_STS_2 0x5283B0 + +#define mmDMA1_QM_CP_STS_3 0x5283B4 + +#define mmDMA1_QM_CP_STS_4 0x5283B8 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_0 0x5283BC + +#define mmDMA1_QM_CP_CURRENT_INST_LO_1 0x5283C0 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_2 0x5283C4 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_3 0x5283C8 + +#define mmDMA1_QM_CP_CURRENT_INST_LO_4 0x5283CC + +#define mmDMA1_QM_CP_CURRENT_INST_HI_0 0x5283D0 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_1 0x5283D4 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_2 0x5283D8 + +#define mmDMA1_QM_CP_CURRENT_INST_HI_3 0x5283DC + +#define mmDMA1_QM_CP_CURRENT_INST_HI_4 0x5283E0 + +#define mmDMA1_QM_CP_BARRIER_CFG_0 0x5283F4 + +#define mmDMA1_QM_CP_BARRIER_CFG_1 0x5283F8 + +#define mmDMA1_QM_CP_BARRIER_CFG_2 0x5283FC + +#define mmDMA1_QM_CP_BARRIER_CFG_3 0x528400 + +#define mmDMA1_QM_CP_BARRIER_CFG_4 0x528404 + +#define mmDMA1_QM_CP_DBG_0_0 0x528408 + +#define mmDMA1_QM_CP_DBG_0_1 0x52840C + +#define mmDMA1_QM_CP_DBG_0_2 0x528410 + +#define mmDMA1_QM_CP_DBG_0_3 0x528414 + +#define mmDMA1_QM_CP_DBG_0_4 0x528418 + +#define mmDMA1_QM_CP_ARUSER_31_11_0 0x52841C + +#define mmDMA1_QM_CP_ARUSER_31_11_1 0x528420 + +#define mmDMA1_QM_CP_ARUSER_31_11_2 0x528424 + +#define mmDMA1_QM_CP_ARUSER_31_11_3 0x528428 + +#define mmDMA1_QM_CP_ARUSER_31_11_4 0x52842C + +#define mmDMA1_QM_CP_AWUSER_31_11_0 0x528430 + +#define mmDMA1_QM_CP_AWUSER_31_11_1 0x528434 + +#define mmDMA1_QM_CP_AWUSER_31_11_2 0x528438 + +#define mmDMA1_QM_CP_AWUSER_31_11_3 0x52843C + +#define mmDMA1_QM_CP_AWUSER_31_11_4 0x528440 + +#define mmDMA1_QM_ARB_CFG_0 0x528A00 + +#define mmDMA1_QM_ARB_CHOISE_Q_PUSH 0x528A04 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_0 0x528A08 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_1 0x528A0C + +#define mmDMA1_QM_ARB_WRR_WEIGHT_2 0x528A10 + +#define mmDMA1_QM_ARB_WRR_WEIGHT_3 0x528A14 + +#define mmDMA1_QM_ARB_CFG_1 0x528A18 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_0 0x528A20 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_1 0x528A24 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_2 0x528A28 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_3 0x528A2C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_4 0x528A30 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_5 0x528A34 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_6 0x528A38 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_7 0x528A3C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_8 0x528A40 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_9 0x528A44 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_10 0x528A48 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_11 0x528A4C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_12 0x528A50 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_13 0x528A54 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_14 0x528A58 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_15 0x528A5C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_16 0x528A60 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_17 0x528A64 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_18 0x528A68 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_19 0x528A6C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_20 0x528A70 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_21 0x528A74 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_22 0x528A78 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_23 0x528A7C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_24 0x528A80 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_25 0x528A84 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_26 0x528A88 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_27 0x528A8C + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_28 0x528A90 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_29 0x528A94 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_30 0x528A98 + +#define mmDMA1_QM_ARB_MST_AVAIL_CRED_31 0x528A9C + +#define mmDMA1_QM_ARB_MST_CRED_INC 0x528AA0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x528AA4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x528AA8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x528AAC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x528AB0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x528AB4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x528AB8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x528ABC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x528AC0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x528AC4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x528AC8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x528ACC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x528AD0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x528AD4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x528AD8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x528ADC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x528AE0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x528AE4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x528AE8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x528AEC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x528AF0 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x528AF4 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x528AF8 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x528AFC + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x528B00 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x528B04 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x528B08 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x528B0C + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x528B10 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x528B14 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x528B18 + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x528B1C + +#define mmDMA1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x528B20 + +#define mmDMA1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x528B28 + +#define mmDMA1_QM_ARB_MST_SLAVE_EN 0x528B2C + +#define mmDMA1_QM_ARB_MST_QUIET_PER 0x528B34 + +#define mmDMA1_QM_ARB_SLV_CHOISE_WDT 0x528B38 + +#define mmDMA1_QM_ARB_SLV_ID 0x528B3C + +#define mmDMA1_QM_ARB_MSG_MAX_INFLIGHT 0x528B44 + +#define mmDMA1_QM_ARB_MSG_AWUSER_31_11 0x528B48 + +#define mmDMA1_QM_ARB_MSG_AWUSER_SEC_PROP 0x528B4C + +#define mmDMA1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x528B50 + +#define mmDMA1_QM_ARB_BASE_LO 0x528B54 + +#define mmDMA1_QM_ARB_BASE_HI 0x528B58 + +#define mmDMA1_QM_ARB_STATE_STS 0x528B80 + +#define mmDMA1_QM_ARB_CHOISE_FULLNESS_STS 0x528B84 + +#define mmDMA1_QM_ARB_MSG_STS 0x528B88 + +#define mmDMA1_QM_ARB_SLV_CHOISE_Q_HEAD 0x528B8C + +#define mmDMA1_QM_ARB_ERR_CAUSE 0x528B9C + +#define mmDMA1_QM_ARB_ERR_MSG_EN 0x528BA0 + +#define mmDMA1_QM_ARB_ERR_STS_DRP 0x528BA8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_0 0x528BB0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_1 0x528BB4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_2 0x528BB8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_3 0x528BBC + +#define mmDMA1_QM_ARB_MST_CRED_STS_4 0x528BC0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_5 0x528BC4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_6 0x528BC8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_7 0x528BCC + +#define mmDMA1_QM_ARB_MST_CRED_STS_8 0x528BD0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_9 0x528BD4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_10 0x528BD8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_11 0x528BDC + +#define mmDMA1_QM_ARB_MST_CRED_STS_12 0x528BE0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_13 0x528BE4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_14 0x528BE8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_15 0x528BEC + +#define mmDMA1_QM_ARB_MST_CRED_STS_16 0x528BF0 + +#define mmDMA1_QM_ARB_MST_CRED_STS_17 0x528BF4 + +#define mmDMA1_QM_ARB_MST_CRED_STS_18 0x528BF8 + +#define mmDMA1_QM_ARB_MST_CRED_STS_19 0x528BFC + +#define mmDMA1_QM_ARB_MST_CRED_STS_20 0x528C00 + +#define mmDMA1_QM_ARB_MST_CRED_STS_21 0x528C04 + +#define mmDMA1_QM_ARB_MST_CRED_STS_22 0x528C08 + +#define mmDMA1_QM_ARB_MST_CRED_STS_23 0x528C0C + +#define mmDMA1_QM_ARB_MST_CRED_STS_24 0x528C10 + +#define mmDMA1_QM_ARB_MST_CRED_STS_25 0x528C14 + +#define mmDMA1_QM_ARB_MST_CRED_STS_26 0x528C18 + +#define mmDMA1_QM_ARB_MST_CRED_STS_27 0x528C1C + +#define mmDMA1_QM_ARB_MST_CRED_STS_28 0x528C20 + +#define mmDMA1_QM_ARB_MST_CRED_STS_29 0x528C24 + +#define mmDMA1_QM_ARB_MST_CRED_STS_30 0x528C28 + +#define mmDMA1_QM_ARB_MST_CRED_STS_31 0x528C2C + +#define mmDMA1_QM_CGM_CFG 0x528C70 + +#define mmDMA1_QM_CGM_STS 0x528C74 + +#define mmDMA1_QM_CGM_CFG1 0x528C78 + +#define mmDMA1_QM_LOCAL_RANGE_BASE 0x528C80 + +#define mmDMA1_QM_LOCAL_RANGE_SIZE 0x528C84 + +#define mmDMA1_QM_CSMR_STRICT_PRIO_CFG 0x528C90 + +#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_1 0x528C94 + +#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_0 0x528C98 + +#define mmDMA1_QM_LBW_WR_RATE_LIM_CFG_1 0x528C9C + +#define mmDMA1_QM_HBW_RD_RATE_LIM_CFG_0 0x528CA0 + +#define mmDMA1_QM_GLBL_AXCACHE 0x528CA4 + +#define mmDMA1_QM_IND_GW_APB_CFG 0x528CB0 + +#define mmDMA1_QM_IND_GW_APB_WDATA 0x528CB4 + +#define mmDMA1_QM_IND_GW_APB_RDATA 0x528CB8 + +#define mmDMA1_QM_IND_GW_APB_STATUS 0x528CBC + +#define mmDMA1_QM_GLBL_ERR_ADDR_LO 0x528CD0 + +#define mmDMA1_QM_GLBL_ERR_ADDR_HI 0x528CD4 + +#define mmDMA1_QM_GLBL_ERR_WDATA 0x528CD8 + +#define mmDMA1_QM_GLBL_MEM_INIT_BUSY 0x528D00 + +#endif /* ASIC_REG_DMA1_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h new file mode 100644 index 000000000000..a42862cd5ae0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA2_CORE_REGS_H_ +#define ASIC_REG_DMA2_CORE_REGS_H_ + +/* + ***************************************** + * DMA2_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA2_CORE_CFG_0 0x540000 + +#define mmDMA2_CORE_CFG_1 0x540004 + +#define mmDMA2_CORE_LBW_MAX_OUTSTAND 0x540008 + +#define mmDMA2_CORE_SRC_BASE_LO 0x540014 + +#define mmDMA2_CORE_SRC_BASE_HI 0x540018 + +#define mmDMA2_CORE_DST_BASE_LO 0x54001C + +#define mmDMA2_CORE_DST_BASE_HI 0x540020 + +#define mmDMA2_CORE_SRC_TSIZE_1 0x54002C + +#define mmDMA2_CORE_SRC_STRIDE_1 0x540030 + +#define mmDMA2_CORE_SRC_TSIZE_2 0x540034 + +#define mmDMA2_CORE_SRC_STRIDE_2 0x540038 + +#define mmDMA2_CORE_SRC_TSIZE_3 0x54003C + +#define mmDMA2_CORE_SRC_STRIDE_3 0x540040 + +#define mmDMA2_CORE_SRC_TSIZE_4 0x540044 + +#define mmDMA2_CORE_SRC_STRIDE_4 0x540048 + +#define mmDMA2_CORE_SRC_TSIZE_0 0x54004C + +#define mmDMA2_CORE_DST_TSIZE_1 0x540054 + +#define mmDMA2_CORE_DST_STRIDE_1 0x540058 + +#define mmDMA2_CORE_DST_TSIZE_2 0x54005C + +#define mmDMA2_CORE_DST_STRIDE_2 0x540060 + +#define mmDMA2_CORE_DST_TSIZE_3 0x540064 + +#define mmDMA2_CORE_DST_STRIDE_3 0x540068 + +#define mmDMA2_CORE_DST_TSIZE_4 0x54006C + +#define mmDMA2_CORE_DST_STRIDE_4 0x540070 + +#define mmDMA2_CORE_DST_TSIZE_0 0x540074 + +#define mmDMA2_CORE_COMMIT 0x540078 + +#define mmDMA2_CORE_WR_COMP_WDATA 0x54007C + +#define mmDMA2_CORE_WR_COMP_ADDR_LO 0x540080 + +#define mmDMA2_CORE_WR_COMP_ADDR_HI 0x540084 + +#define mmDMA2_CORE_WR_COMP_AWUSER_31_11 0x540088 + +#define mmDMA2_CORE_TE_NUMROWS 0x540094 + +#define mmDMA2_CORE_PROT 0x5400B8 + +#define mmDMA2_CORE_SECURE_PROPS 0x5400F0 + +#define mmDMA2_CORE_NON_SECURE_PROPS 0x5400F4 + +#define mmDMA2_CORE_RD_MAX_OUTSTAND 0x540100 + +#define mmDMA2_CORE_RD_MAX_SIZE 0x540104 + +#define mmDMA2_CORE_RD_ARCACHE 0x540108 + +#define mmDMA2_CORE_RD_ARUSER_31_11 0x540110 + +#define mmDMA2_CORE_RD_INFLIGHTS 0x540114 + +#define mmDMA2_CORE_WR_MAX_OUTSTAND 0x540120 + +#define mmDMA2_CORE_WR_MAX_AWID 0x540124 + +#define mmDMA2_CORE_WR_AWCACHE 0x540128 + +#define mmDMA2_CORE_WR_AWUSER_31_11 0x540130 + +#define mmDMA2_CORE_WR_INFLIGHTS 0x540134 + +#define mmDMA2_CORE_RD_RATE_LIM_CFG_0 0x540150 + +#define mmDMA2_CORE_RD_RATE_LIM_CFG_1 0x540154 + +#define mmDMA2_CORE_WR_RATE_LIM_CFG_0 0x540158 + +#define mmDMA2_CORE_WR_RATE_LIM_CFG_1 0x54015C + +#define mmDMA2_CORE_ERR_CFG 0x540160 + +#define mmDMA2_CORE_ERR_CAUSE 0x540164 + +#define mmDMA2_CORE_ERRMSG_ADDR_LO 0x540170 + +#define mmDMA2_CORE_ERRMSG_ADDR_HI 0x540174 + +#define mmDMA2_CORE_ERRMSG_WDATA 0x540178 + +#define mmDMA2_CORE_STS0 0x540190 + +#define mmDMA2_CORE_STS1 0x540194 + +#define mmDMA2_CORE_RD_DBGMEM_ADD 0x540200 + +#define mmDMA2_CORE_RD_DBGMEM_DATA_WR 0x540204 + +#define mmDMA2_CORE_RD_DBGMEM_DATA_RD 0x540208 + +#define mmDMA2_CORE_RD_DBGMEM_CTRL 0x54020C + +#define mmDMA2_CORE_RD_DBGMEM_RC 0x540210 + +#define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT 0x540220 + +#define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT 0x540224 + +#define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT 0x540228 + +#define mmDMA2_CORE_DBG_DESC_CNT 0x54022C + +#define mmDMA2_CORE_DBG_STS 0x540230 + +#define mmDMA2_CORE_DBG_RD_DESC_ID 0x540234 + +#define mmDMA2_CORE_DBG_WR_DESC_ID 0x540238 + +#endif /* ASIC_REG_DMA2_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h new file mode 100644 index 000000000000..8c4d4e016852 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA2_QM_REGS_H_ +#define ASIC_REG_DMA2_QM_REGS_H_ + +/* + ***************************************** + * DMA2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA2_QM_GLBL_CFG0 0x548000 + +#define mmDMA2_QM_GLBL_CFG1 0x548004 + +#define mmDMA2_QM_GLBL_PROT 0x548008 + +#define mmDMA2_QM_GLBL_ERR_CFG 0x54800C + +#define mmDMA2_QM_GLBL_SECURE_PROPS_0 0x548010 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_1 0x548014 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_2 0x548018 + +#define mmDMA2_QM_GLBL_SECURE_PROPS_3 0x54801C + +#define mmDMA2_QM_GLBL_SECURE_PROPS_4 0x548020 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_0 0x548024 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_1 0x548028 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_2 0x54802C + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_3 0x548030 + +#define mmDMA2_QM_GLBL_NON_SECURE_PROPS_4 0x548034 + +#define mmDMA2_QM_GLBL_STS0 0x548038 + +#define mmDMA2_QM_GLBL_STS1_0 0x548040 + +#define mmDMA2_QM_GLBL_STS1_1 0x548044 + +#define mmDMA2_QM_GLBL_STS1_2 0x548048 + +#define mmDMA2_QM_GLBL_STS1_3 0x54804C + +#define mmDMA2_QM_GLBL_STS1_4 0x548050 + +#define mmDMA2_QM_GLBL_MSG_EN_0 0x548054 + +#define mmDMA2_QM_GLBL_MSG_EN_1 0x548058 + +#define mmDMA2_QM_GLBL_MSG_EN_2 0x54805C + +#define mmDMA2_QM_GLBL_MSG_EN_3 0x548060 + +#define mmDMA2_QM_GLBL_MSG_EN_4 0x548068 + +#define mmDMA2_QM_PQ_BASE_LO_0 0x548070 + +#define mmDMA2_QM_PQ_BASE_LO_1 0x548074 + +#define mmDMA2_QM_PQ_BASE_LO_2 0x548078 + +#define mmDMA2_QM_PQ_BASE_LO_3 0x54807C + +#define mmDMA2_QM_PQ_BASE_HI_0 0x548080 + +#define mmDMA2_QM_PQ_BASE_HI_1 0x548084 + +#define mmDMA2_QM_PQ_BASE_HI_2 0x548088 + +#define mmDMA2_QM_PQ_BASE_HI_3 0x54808C + +#define mmDMA2_QM_PQ_SIZE_0 0x548090 + +#define mmDMA2_QM_PQ_SIZE_1 0x548094 + +#define mmDMA2_QM_PQ_SIZE_2 0x548098 + +#define mmDMA2_QM_PQ_SIZE_3 0x54809C + +#define mmDMA2_QM_PQ_PI_0 0x5480A0 + +#define mmDMA2_QM_PQ_PI_1 0x5480A4 + +#define mmDMA2_QM_PQ_PI_2 0x5480A8 + +#define mmDMA2_QM_PQ_PI_3 0x5480AC + +#define mmDMA2_QM_PQ_CI_0 0x5480B0 + +#define mmDMA2_QM_PQ_CI_1 0x5480B4 + +#define mmDMA2_QM_PQ_CI_2 0x5480B8 + +#define mmDMA2_QM_PQ_CI_3 0x5480BC + +#define mmDMA2_QM_PQ_CFG0_0 0x5480C0 + +#define mmDMA2_QM_PQ_CFG0_1 0x5480C4 + +#define mmDMA2_QM_PQ_CFG0_2 0x5480C8 + +#define mmDMA2_QM_PQ_CFG0_3 0x5480CC + +#define mmDMA2_QM_PQ_CFG1_0 0x5480D0 + +#define mmDMA2_QM_PQ_CFG1_1 0x5480D4 + +#define mmDMA2_QM_PQ_CFG1_2 0x5480D8 + +#define mmDMA2_QM_PQ_CFG1_3 0x5480DC + +#define mmDMA2_QM_PQ_ARUSER_31_11_0 0x5480E0 + +#define mmDMA2_QM_PQ_ARUSER_31_11_1 0x5480E4 + +#define mmDMA2_QM_PQ_ARUSER_31_11_2 0x5480E8 + +#define mmDMA2_QM_PQ_ARUSER_31_11_3 0x5480EC + +#define mmDMA2_QM_PQ_STS0_0 0x5480F0 + +#define mmDMA2_QM_PQ_STS0_1 0x5480F4 + +#define mmDMA2_QM_PQ_STS0_2 0x5480F8 + +#define mmDMA2_QM_PQ_STS0_3 0x5480FC + +#define mmDMA2_QM_PQ_STS1_0 0x548100 + +#define mmDMA2_QM_PQ_STS1_1 0x548104 + +#define mmDMA2_QM_PQ_STS1_2 0x548108 + +#define mmDMA2_QM_PQ_STS1_3 0x54810C + +#define mmDMA2_QM_CQ_CFG0_0 0x548110 + +#define mmDMA2_QM_CQ_CFG0_1 0x548114 + +#define mmDMA2_QM_CQ_CFG0_2 0x548118 + +#define mmDMA2_QM_CQ_CFG0_3 0x54811C + +#define mmDMA2_QM_CQ_CFG0_4 0x548120 + +#define mmDMA2_QM_CQ_CFG1_0 0x548124 + +#define mmDMA2_QM_CQ_CFG1_1 0x548128 + +#define mmDMA2_QM_CQ_CFG1_2 0x54812C + +#define mmDMA2_QM_CQ_CFG1_3 0x548130 + +#define mmDMA2_QM_CQ_CFG1_4 0x548134 + +#define mmDMA2_QM_CQ_ARUSER_31_11_0 0x548138 + +#define mmDMA2_QM_CQ_ARUSER_31_11_1 0x54813C + +#define mmDMA2_QM_CQ_ARUSER_31_11_2 0x548140 + +#define mmDMA2_QM_CQ_ARUSER_31_11_3 0x548144 + +#define mmDMA2_QM_CQ_ARUSER_31_11_4 0x548148 + +#define mmDMA2_QM_CQ_STS0_0 0x54814C + +#define mmDMA2_QM_CQ_STS0_1 0x548150 + +#define mmDMA2_QM_CQ_STS0_2 0x548154 + +#define mmDMA2_QM_CQ_STS0_3 0x548158 + +#define mmDMA2_QM_CQ_STS0_4 0x54815C + +#define mmDMA2_QM_CQ_STS1_0 0x548160 + +#define mmDMA2_QM_CQ_STS1_1 0x548164 + +#define mmDMA2_QM_CQ_STS1_2 0x548168 + +#define mmDMA2_QM_CQ_STS1_3 0x54816C + +#define mmDMA2_QM_CQ_STS1_4 0x548170 + +#define mmDMA2_QM_CQ_PTR_LO_0 0x548174 + +#define mmDMA2_QM_CQ_PTR_HI_0 0x548178 + +#define mmDMA2_QM_CQ_TSIZE_0 0x54817C + +#define mmDMA2_QM_CQ_CTL_0 0x548180 + +#define mmDMA2_QM_CQ_PTR_LO_1 0x548184 + +#define mmDMA2_QM_CQ_PTR_HI_1 0x548188 + +#define mmDMA2_QM_CQ_TSIZE_1 0x54818C + +#define mmDMA2_QM_CQ_CTL_1 0x548190 + +#define mmDMA2_QM_CQ_PTR_LO_2 0x548194 + +#define mmDMA2_QM_CQ_PTR_HI_2 0x548198 + +#define mmDMA2_QM_CQ_TSIZE_2 0x54819C + +#define mmDMA2_QM_CQ_CTL_2 0x5481A0 + +#define mmDMA2_QM_CQ_PTR_LO_3 0x5481A4 + +#define mmDMA2_QM_CQ_PTR_HI_3 0x5481A8 + +#define mmDMA2_QM_CQ_TSIZE_3 0x5481AC + +#define mmDMA2_QM_CQ_CTL_3 0x5481B0 + +#define mmDMA2_QM_CQ_PTR_LO_4 0x5481B4 + +#define mmDMA2_QM_CQ_PTR_HI_4 0x5481B8 + +#define mmDMA2_QM_CQ_TSIZE_4 0x5481BC + +#define mmDMA2_QM_CQ_CTL_4 0x5481C0 + +#define mmDMA2_QM_CQ_PTR_LO_STS_0 0x5481C4 + +#define mmDMA2_QM_CQ_PTR_LO_STS_1 0x5481C8 + +#define mmDMA2_QM_CQ_PTR_LO_STS_2 0x5481CC + +#define mmDMA2_QM_CQ_PTR_LO_STS_3 0x5481D0 + +#define mmDMA2_QM_CQ_PTR_LO_STS_4 0x5481D4 + +#define mmDMA2_QM_CQ_PTR_HI_STS_0 0x5481D8 + +#define mmDMA2_QM_CQ_PTR_HI_STS_1 0x5481DC + +#define mmDMA2_QM_CQ_PTR_HI_STS_2 0x5481E0 + +#define mmDMA2_QM_CQ_PTR_HI_STS_3 0x5481E4 + +#define mmDMA2_QM_CQ_PTR_HI_STS_4 0x5481E8 + +#define mmDMA2_QM_CQ_TSIZE_STS_0 0x5481EC + +#define mmDMA2_QM_CQ_TSIZE_STS_1 0x5481F0 + +#define mmDMA2_QM_CQ_TSIZE_STS_2 0x5481F4 + +#define mmDMA2_QM_CQ_TSIZE_STS_3 0x5481F8 + +#define mmDMA2_QM_CQ_TSIZE_STS_4 0x5481FC + +#define mmDMA2_QM_CQ_CTL_STS_0 0x548200 + +#define mmDMA2_QM_CQ_CTL_STS_1 0x548204 + +#define mmDMA2_QM_CQ_CTL_STS_2 0x548208 + +#define mmDMA2_QM_CQ_CTL_STS_3 0x54820C + +#define mmDMA2_QM_CQ_CTL_STS_4 0x548210 + +#define mmDMA2_QM_CQ_IFIFO_CNT_0 0x548214 + +#define mmDMA2_QM_CQ_IFIFO_CNT_1 0x548218 + +#define mmDMA2_QM_CQ_IFIFO_CNT_2 0x54821C + +#define mmDMA2_QM_CQ_IFIFO_CNT_3 0x548220 + +#define mmDMA2_QM_CQ_IFIFO_CNT_4 0x548224 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_0 0x548228 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_1 0x54822C + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_2 0x548230 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_3 0x548234 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_LO_4 0x548238 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_0 0x54823C + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_1 0x548240 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_2 0x548244 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_3 0x548248 + +#define mmDMA2_QM_CP_MSG_BASE0_ADDR_HI_4 0x54824C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_0 0x548250 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_1 0x548254 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_2 0x548258 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_3 0x54825C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_LO_4 0x548260 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_0 0x548264 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_1 0x548268 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_2 0x54826C + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_3 0x548270 + +#define mmDMA2_QM_CP_MSG_BASE1_ADDR_HI_4 0x548274 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_0 0x548278 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_1 0x54827C + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_2 0x548280 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_3 0x548284 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_LO_4 0x548288 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_0 0x54828C + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_1 0x548290 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_2 0x548294 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_3 0x548298 + +#define mmDMA2_QM_CP_MSG_BASE2_ADDR_HI_4 0x54829C + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_0 0x5482A0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_1 0x5482A4 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_2 0x5482A8 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_3 0x5482AC + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_LO_4 0x5482B0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_0 0x5482B4 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_1 0x5482B8 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_2 0x5482BC + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_3 0x5482C0 + +#define mmDMA2_QM_CP_MSG_BASE3_ADDR_HI_4 0x5482C4 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_0 0x5482C8 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_1 0x5482CC + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_2 0x5482D0 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_3 0x5482D4 + +#define mmDMA2_QM_CP_LDMA_TSIZE_OFFSET_4 0x5482D8 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5482E0 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5482E4 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5482E8 + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5482EC + +#define mmDMA2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5482F0 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5482F4 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5482F8 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5482FC + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x548300 + +#define mmDMA2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x548304 + +#define mmDMA2_QM_CP_FENCE0_RDATA_0 0x548308 + +#define mmDMA2_QM_CP_FENCE0_RDATA_1 0x54830C + +#define mmDMA2_QM_CP_FENCE0_RDATA_2 0x548310 + +#define mmDMA2_QM_CP_FENCE0_RDATA_3 0x548314 + +#define mmDMA2_QM_CP_FENCE0_RDATA_4 0x548318 + +#define mmDMA2_QM_CP_FENCE1_RDATA_0 0x54831C + +#define mmDMA2_QM_CP_FENCE1_RDATA_1 0x548320 + +#define mmDMA2_QM_CP_FENCE1_RDATA_2 0x548324 + +#define mmDMA2_QM_CP_FENCE1_RDATA_3 0x548328 + +#define mmDMA2_QM_CP_FENCE1_RDATA_4 0x54832C + +#define mmDMA2_QM_CP_FENCE2_RDATA_0 0x548330 + +#define mmDMA2_QM_CP_FENCE2_RDATA_1 0x548334 + +#define mmDMA2_QM_CP_FENCE2_RDATA_2 0x548338 + +#define mmDMA2_QM_CP_FENCE2_RDATA_3 0x54833C + +#define mmDMA2_QM_CP_FENCE2_RDATA_4 0x548340 + +#define mmDMA2_QM_CP_FENCE3_RDATA_0 0x548344 + +#define mmDMA2_QM_CP_FENCE3_RDATA_1 0x548348 + +#define mmDMA2_QM_CP_FENCE3_RDATA_2 0x54834C + +#define mmDMA2_QM_CP_FENCE3_RDATA_3 0x548350 + +#define mmDMA2_QM_CP_FENCE3_RDATA_4 0x548354 + +#define mmDMA2_QM_CP_FENCE0_CNT_0 0x548358 + +#define mmDMA2_QM_CP_FENCE0_CNT_1 0x54835C + +#define mmDMA2_QM_CP_FENCE0_CNT_2 0x548360 + +#define mmDMA2_QM_CP_FENCE0_CNT_3 0x548364 + +#define mmDMA2_QM_CP_FENCE0_CNT_4 0x548368 + +#define mmDMA2_QM_CP_FENCE1_CNT_0 0x54836C + +#define mmDMA2_QM_CP_FENCE1_CNT_1 0x548370 + +#define mmDMA2_QM_CP_FENCE1_CNT_2 0x548374 + +#define mmDMA2_QM_CP_FENCE1_CNT_3 0x548378 + +#define mmDMA2_QM_CP_FENCE1_CNT_4 0x54837C + +#define mmDMA2_QM_CP_FENCE2_CNT_0 0x548380 + +#define mmDMA2_QM_CP_FENCE2_CNT_1 0x548384 + +#define mmDMA2_QM_CP_FENCE2_CNT_2 0x548388 + +#define mmDMA2_QM_CP_FENCE2_CNT_3 0x54838C + +#define mmDMA2_QM_CP_FENCE2_CNT_4 0x548390 + +#define mmDMA2_QM_CP_FENCE3_CNT_0 0x548394 + +#define mmDMA2_QM_CP_FENCE3_CNT_1 0x548398 + +#define mmDMA2_QM_CP_FENCE3_CNT_2 0x54839C + +#define mmDMA2_QM_CP_FENCE3_CNT_3 0x5483A0 + +#define mmDMA2_QM_CP_FENCE3_CNT_4 0x5483A4 + +#define mmDMA2_QM_CP_STS_0 0x5483A8 + +#define mmDMA2_QM_CP_STS_1 0x5483AC + +#define mmDMA2_QM_CP_STS_2 0x5483B0 + +#define mmDMA2_QM_CP_STS_3 0x5483B4 + +#define mmDMA2_QM_CP_STS_4 0x5483B8 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_0 0x5483BC + +#define mmDMA2_QM_CP_CURRENT_INST_LO_1 0x5483C0 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_2 0x5483C4 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_3 0x5483C8 + +#define mmDMA2_QM_CP_CURRENT_INST_LO_4 0x5483CC + +#define mmDMA2_QM_CP_CURRENT_INST_HI_0 0x5483D0 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_1 0x5483D4 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_2 0x5483D8 + +#define mmDMA2_QM_CP_CURRENT_INST_HI_3 0x5483DC + +#define mmDMA2_QM_CP_CURRENT_INST_HI_4 0x5483E0 + +#define mmDMA2_QM_CP_BARRIER_CFG_0 0x5483F4 + +#define mmDMA2_QM_CP_BARRIER_CFG_1 0x5483F8 + +#define mmDMA2_QM_CP_BARRIER_CFG_2 0x5483FC + +#define mmDMA2_QM_CP_BARRIER_CFG_3 0x548400 + +#define mmDMA2_QM_CP_BARRIER_CFG_4 0x548404 + +#define mmDMA2_QM_CP_DBG_0_0 0x548408 + +#define mmDMA2_QM_CP_DBG_0_1 0x54840C + +#define mmDMA2_QM_CP_DBG_0_2 0x548410 + +#define mmDMA2_QM_CP_DBG_0_3 0x548414 + +#define mmDMA2_QM_CP_DBG_0_4 0x548418 + +#define mmDMA2_QM_CP_ARUSER_31_11_0 0x54841C + +#define mmDMA2_QM_CP_ARUSER_31_11_1 0x548420 + +#define mmDMA2_QM_CP_ARUSER_31_11_2 0x548424 + +#define mmDMA2_QM_CP_ARUSER_31_11_3 0x548428 + +#define mmDMA2_QM_CP_ARUSER_31_11_4 0x54842C + +#define mmDMA2_QM_CP_AWUSER_31_11_0 0x548430 + +#define mmDMA2_QM_CP_AWUSER_31_11_1 0x548434 + +#define mmDMA2_QM_CP_AWUSER_31_11_2 0x548438 + +#define mmDMA2_QM_CP_AWUSER_31_11_3 0x54843C + +#define mmDMA2_QM_CP_AWUSER_31_11_4 0x548440 + +#define mmDMA2_QM_ARB_CFG_0 0x548A00 + +#define mmDMA2_QM_ARB_CHOISE_Q_PUSH 0x548A04 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_0 0x548A08 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_1 0x548A0C + +#define mmDMA2_QM_ARB_WRR_WEIGHT_2 0x548A10 + +#define mmDMA2_QM_ARB_WRR_WEIGHT_3 0x548A14 + +#define mmDMA2_QM_ARB_CFG_1 0x548A18 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_0 0x548A20 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_1 0x548A24 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_2 0x548A28 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_3 0x548A2C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_4 0x548A30 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_5 0x548A34 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_6 0x548A38 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_7 0x548A3C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_8 0x548A40 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_9 0x548A44 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_10 0x548A48 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_11 0x548A4C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_12 0x548A50 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_13 0x548A54 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_14 0x548A58 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_15 0x548A5C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_16 0x548A60 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_17 0x548A64 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_18 0x548A68 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_19 0x548A6C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_20 0x548A70 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_21 0x548A74 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_22 0x548A78 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_23 0x548A7C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_24 0x548A80 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_25 0x548A84 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_26 0x548A88 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_27 0x548A8C + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_28 0x548A90 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_29 0x548A94 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_30 0x548A98 + +#define mmDMA2_QM_ARB_MST_AVAIL_CRED_31 0x548A9C + +#define mmDMA2_QM_ARB_MST_CRED_INC 0x548AA0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x548AA4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x548AA8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x548AAC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x548AB0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x548AB4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x548AB8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x548ABC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x548AC0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x548AC4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x548AC8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x548ACC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x548AD0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x548AD4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x548AD8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x548ADC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x548AE0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x548AE4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x548AE8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x548AEC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x548AF0 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x548AF4 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x548AF8 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x548AFC + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x548B00 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x548B04 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x548B08 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x548B0C + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x548B10 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x548B14 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x548B18 + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x548B1C + +#define mmDMA2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x548B20 + +#define mmDMA2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x548B28 + +#define mmDMA2_QM_ARB_MST_SLAVE_EN 0x548B2C + +#define mmDMA2_QM_ARB_MST_QUIET_PER 0x548B34 + +#define mmDMA2_QM_ARB_SLV_CHOISE_WDT 0x548B38 + +#define mmDMA2_QM_ARB_SLV_ID 0x548B3C + +#define mmDMA2_QM_ARB_MSG_MAX_INFLIGHT 0x548B44 + +#define mmDMA2_QM_ARB_MSG_AWUSER_31_11 0x548B48 + +#define mmDMA2_QM_ARB_MSG_AWUSER_SEC_PROP 0x548B4C + +#define mmDMA2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x548B50 + +#define mmDMA2_QM_ARB_BASE_LO 0x548B54 + +#define mmDMA2_QM_ARB_BASE_HI 0x548B58 + +#define mmDMA2_QM_ARB_STATE_STS 0x548B80 + +#define mmDMA2_QM_ARB_CHOISE_FULLNESS_STS 0x548B84 + +#define mmDMA2_QM_ARB_MSG_STS 0x548B88 + +#define mmDMA2_QM_ARB_SLV_CHOISE_Q_HEAD 0x548B8C + +#define mmDMA2_QM_ARB_ERR_CAUSE 0x548B9C + +#define mmDMA2_QM_ARB_ERR_MSG_EN 0x548BA0 + +#define mmDMA2_QM_ARB_ERR_STS_DRP 0x548BA8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_0 0x548BB0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_1 0x548BB4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_2 0x548BB8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_3 0x548BBC + +#define mmDMA2_QM_ARB_MST_CRED_STS_4 0x548BC0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_5 0x548BC4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_6 0x548BC8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_7 0x548BCC + +#define mmDMA2_QM_ARB_MST_CRED_STS_8 0x548BD0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_9 0x548BD4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_10 0x548BD8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_11 0x548BDC + +#define mmDMA2_QM_ARB_MST_CRED_STS_12 0x548BE0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_13 0x548BE4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_14 0x548BE8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_15 0x548BEC + +#define mmDMA2_QM_ARB_MST_CRED_STS_16 0x548BF0 + +#define mmDMA2_QM_ARB_MST_CRED_STS_17 0x548BF4 + +#define mmDMA2_QM_ARB_MST_CRED_STS_18 0x548BF8 + +#define mmDMA2_QM_ARB_MST_CRED_STS_19 0x548BFC + +#define mmDMA2_QM_ARB_MST_CRED_STS_20 0x548C00 + +#define mmDMA2_QM_ARB_MST_CRED_STS_21 0x548C04 + +#define mmDMA2_QM_ARB_MST_CRED_STS_22 0x548C08 + +#define mmDMA2_QM_ARB_MST_CRED_STS_23 0x548C0C + +#define mmDMA2_QM_ARB_MST_CRED_STS_24 0x548C10 + +#define mmDMA2_QM_ARB_MST_CRED_STS_25 0x548C14 + +#define mmDMA2_QM_ARB_MST_CRED_STS_26 0x548C18 + +#define mmDMA2_QM_ARB_MST_CRED_STS_27 0x548C1C + +#define mmDMA2_QM_ARB_MST_CRED_STS_28 0x548C20 + +#define mmDMA2_QM_ARB_MST_CRED_STS_29 0x548C24 + +#define mmDMA2_QM_ARB_MST_CRED_STS_30 0x548C28 + +#define mmDMA2_QM_ARB_MST_CRED_STS_31 0x548C2C + +#define mmDMA2_QM_CGM_CFG 0x548C70 + +#define mmDMA2_QM_CGM_STS 0x548C74 + +#define mmDMA2_QM_CGM_CFG1 0x548C78 + +#define mmDMA2_QM_LOCAL_RANGE_BASE 0x548C80 + +#define mmDMA2_QM_LOCAL_RANGE_SIZE 0x548C84 + +#define mmDMA2_QM_CSMR_STRICT_PRIO_CFG 0x548C90 + +#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_1 0x548C94 + +#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_0 0x548C98 + +#define mmDMA2_QM_LBW_WR_RATE_LIM_CFG_1 0x548C9C + +#define mmDMA2_QM_HBW_RD_RATE_LIM_CFG_0 0x548CA0 + +#define mmDMA2_QM_GLBL_AXCACHE 0x548CA4 + +#define mmDMA2_QM_IND_GW_APB_CFG 0x548CB0 + +#define mmDMA2_QM_IND_GW_APB_WDATA 0x548CB4 + +#define mmDMA2_QM_IND_GW_APB_RDATA 0x548CB8 + +#define mmDMA2_QM_IND_GW_APB_STATUS 0x548CBC + +#define mmDMA2_QM_GLBL_ERR_ADDR_LO 0x548CD0 + +#define mmDMA2_QM_GLBL_ERR_ADDR_HI 0x548CD4 + +#define mmDMA2_QM_GLBL_ERR_WDATA 0x548CD8 + +#define mmDMA2_QM_GLBL_MEM_INIT_BUSY 0x548D00 + +#endif /* ASIC_REG_DMA2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h new file mode 100644 index 000000000000..fb145f416fe6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA3_CORE_REGS_H_ +#define ASIC_REG_DMA3_CORE_REGS_H_ + +/* + ***************************************** + * DMA3_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA3_CORE_CFG_0 0x560000 + +#define mmDMA3_CORE_CFG_1 0x560004 + +#define mmDMA3_CORE_LBW_MAX_OUTSTAND 0x560008 + +#define mmDMA3_CORE_SRC_BASE_LO 0x560014 + +#define mmDMA3_CORE_SRC_BASE_HI 0x560018 + +#define mmDMA3_CORE_DST_BASE_LO 0x56001C + +#define mmDMA3_CORE_DST_BASE_HI 0x560020 + +#define mmDMA3_CORE_SRC_TSIZE_1 0x56002C + +#define mmDMA3_CORE_SRC_STRIDE_1 0x560030 + +#define mmDMA3_CORE_SRC_TSIZE_2 0x560034 + +#define mmDMA3_CORE_SRC_STRIDE_2 0x560038 + +#define mmDMA3_CORE_SRC_TSIZE_3 0x56003C + +#define mmDMA3_CORE_SRC_STRIDE_3 0x560040 + +#define mmDMA3_CORE_SRC_TSIZE_4 0x560044 + +#define mmDMA3_CORE_SRC_STRIDE_4 0x560048 + +#define mmDMA3_CORE_SRC_TSIZE_0 0x56004C + +#define mmDMA3_CORE_DST_TSIZE_1 0x560054 + +#define mmDMA3_CORE_DST_STRIDE_1 0x560058 + +#define mmDMA3_CORE_DST_TSIZE_2 0x56005C + +#define mmDMA3_CORE_DST_STRIDE_2 0x560060 + +#define mmDMA3_CORE_DST_TSIZE_3 0x560064 + +#define mmDMA3_CORE_DST_STRIDE_3 0x560068 + +#define mmDMA3_CORE_DST_TSIZE_4 0x56006C + +#define mmDMA3_CORE_DST_STRIDE_4 0x560070 + +#define mmDMA3_CORE_DST_TSIZE_0 0x560074 + +#define mmDMA3_CORE_COMMIT 0x560078 + +#define mmDMA3_CORE_WR_COMP_WDATA 0x56007C + +#define mmDMA3_CORE_WR_COMP_ADDR_LO 0x560080 + +#define mmDMA3_CORE_WR_COMP_ADDR_HI 0x560084 + +#define mmDMA3_CORE_WR_COMP_AWUSER_31_11 0x560088 + +#define mmDMA3_CORE_TE_NUMROWS 0x560094 + +#define mmDMA3_CORE_PROT 0x5600B8 + +#define mmDMA3_CORE_SECURE_PROPS 0x5600F0 + +#define mmDMA3_CORE_NON_SECURE_PROPS 0x5600F4 + +#define mmDMA3_CORE_RD_MAX_OUTSTAND 0x560100 + +#define mmDMA3_CORE_RD_MAX_SIZE 0x560104 + +#define mmDMA3_CORE_RD_ARCACHE 0x560108 + +#define mmDMA3_CORE_RD_ARUSER_31_11 0x560110 + +#define mmDMA3_CORE_RD_INFLIGHTS 0x560114 + +#define mmDMA3_CORE_WR_MAX_OUTSTAND 0x560120 + +#define mmDMA3_CORE_WR_MAX_AWID 0x560124 + +#define mmDMA3_CORE_WR_AWCACHE 0x560128 + +#define mmDMA3_CORE_WR_AWUSER_31_11 0x560130 + +#define mmDMA3_CORE_WR_INFLIGHTS 0x560134 + +#define mmDMA3_CORE_RD_RATE_LIM_CFG_0 0x560150 + +#define mmDMA3_CORE_RD_RATE_LIM_CFG_1 0x560154 + +#define mmDMA3_CORE_WR_RATE_LIM_CFG_0 0x560158 + +#define mmDMA3_CORE_WR_RATE_LIM_CFG_1 0x56015C + +#define mmDMA3_CORE_ERR_CFG 0x560160 + +#define mmDMA3_CORE_ERR_CAUSE 0x560164 + +#define mmDMA3_CORE_ERRMSG_ADDR_LO 0x560170 + +#define mmDMA3_CORE_ERRMSG_ADDR_HI 0x560174 + +#define mmDMA3_CORE_ERRMSG_WDATA 0x560178 + +#define mmDMA3_CORE_STS0 0x560190 + +#define mmDMA3_CORE_STS1 0x560194 + +#define mmDMA3_CORE_RD_DBGMEM_ADD 0x560200 + +#define mmDMA3_CORE_RD_DBGMEM_DATA_WR 0x560204 + +#define mmDMA3_CORE_RD_DBGMEM_DATA_RD 0x560208 + +#define mmDMA3_CORE_RD_DBGMEM_CTRL 0x56020C + +#define mmDMA3_CORE_RD_DBGMEM_RC 0x560210 + +#define mmDMA3_CORE_DBG_HBW_AXI_AR_CNT 0x560220 + +#define mmDMA3_CORE_DBG_HBW_AXI_AW_CNT 0x560224 + +#define mmDMA3_CORE_DBG_LBW_AXI_AW_CNT 0x560228 + +#define mmDMA3_CORE_DBG_DESC_CNT 0x56022C + +#define mmDMA3_CORE_DBG_STS 0x560230 + +#define mmDMA3_CORE_DBG_RD_DESC_ID 0x560234 + +#define mmDMA3_CORE_DBG_WR_DESC_ID 0x560238 + +#endif /* ASIC_REG_DMA3_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h new file mode 100644 index 000000000000..a4b461ca3d94 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma3_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA3_QM_REGS_H_ +#define ASIC_REG_DMA3_QM_REGS_H_ + +/* + ***************************************** + * DMA3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA3_QM_GLBL_CFG0 0x568000 + +#define mmDMA3_QM_GLBL_CFG1 0x568004 + +#define mmDMA3_QM_GLBL_PROT 0x568008 + +#define mmDMA3_QM_GLBL_ERR_CFG 0x56800C + +#define mmDMA3_QM_GLBL_SECURE_PROPS_0 0x568010 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_1 0x568014 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_2 0x568018 + +#define mmDMA3_QM_GLBL_SECURE_PROPS_3 0x56801C + +#define mmDMA3_QM_GLBL_SECURE_PROPS_4 0x568020 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_0 0x568024 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_1 0x568028 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_2 0x56802C + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_3 0x568030 + +#define mmDMA3_QM_GLBL_NON_SECURE_PROPS_4 0x568034 + +#define mmDMA3_QM_GLBL_STS0 0x568038 + +#define mmDMA3_QM_GLBL_STS1_0 0x568040 + +#define mmDMA3_QM_GLBL_STS1_1 0x568044 + +#define mmDMA3_QM_GLBL_STS1_2 0x568048 + +#define mmDMA3_QM_GLBL_STS1_3 0x56804C + +#define mmDMA3_QM_GLBL_STS1_4 0x568050 + +#define mmDMA3_QM_GLBL_MSG_EN_0 0x568054 + +#define mmDMA3_QM_GLBL_MSG_EN_1 0x568058 + +#define mmDMA3_QM_GLBL_MSG_EN_2 0x56805C + +#define mmDMA3_QM_GLBL_MSG_EN_3 0x568060 + +#define mmDMA3_QM_GLBL_MSG_EN_4 0x568068 + +#define mmDMA3_QM_PQ_BASE_LO_0 0x568070 + +#define mmDMA3_QM_PQ_BASE_LO_1 0x568074 + +#define mmDMA3_QM_PQ_BASE_LO_2 0x568078 + +#define mmDMA3_QM_PQ_BASE_LO_3 0x56807C + +#define mmDMA3_QM_PQ_BASE_HI_0 0x568080 + +#define mmDMA3_QM_PQ_BASE_HI_1 0x568084 + +#define mmDMA3_QM_PQ_BASE_HI_2 0x568088 + +#define mmDMA3_QM_PQ_BASE_HI_3 0x56808C + +#define mmDMA3_QM_PQ_SIZE_0 0x568090 + +#define mmDMA3_QM_PQ_SIZE_1 0x568094 + +#define mmDMA3_QM_PQ_SIZE_2 0x568098 + +#define mmDMA3_QM_PQ_SIZE_3 0x56809C + +#define mmDMA3_QM_PQ_PI_0 0x5680A0 + +#define mmDMA3_QM_PQ_PI_1 0x5680A4 + +#define mmDMA3_QM_PQ_PI_2 0x5680A8 + +#define mmDMA3_QM_PQ_PI_3 0x5680AC + +#define mmDMA3_QM_PQ_CI_0 0x5680B0 + +#define mmDMA3_QM_PQ_CI_1 0x5680B4 + +#define mmDMA3_QM_PQ_CI_2 0x5680B8 + +#define mmDMA3_QM_PQ_CI_3 0x5680BC + +#define mmDMA3_QM_PQ_CFG0_0 0x5680C0 + +#define mmDMA3_QM_PQ_CFG0_1 0x5680C4 + +#define mmDMA3_QM_PQ_CFG0_2 0x5680C8 + +#define mmDMA3_QM_PQ_CFG0_3 0x5680CC + +#define mmDMA3_QM_PQ_CFG1_0 0x5680D0 + +#define mmDMA3_QM_PQ_CFG1_1 0x5680D4 + +#define mmDMA3_QM_PQ_CFG1_2 0x5680D8 + +#define mmDMA3_QM_PQ_CFG1_3 0x5680DC + +#define mmDMA3_QM_PQ_ARUSER_31_11_0 0x5680E0 + +#define mmDMA3_QM_PQ_ARUSER_31_11_1 0x5680E4 + +#define mmDMA3_QM_PQ_ARUSER_31_11_2 0x5680E8 + +#define mmDMA3_QM_PQ_ARUSER_31_11_3 0x5680EC + +#define mmDMA3_QM_PQ_STS0_0 0x5680F0 + +#define mmDMA3_QM_PQ_STS0_1 0x5680F4 + +#define mmDMA3_QM_PQ_STS0_2 0x5680F8 + +#define mmDMA3_QM_PQ_STS0_3 0x5680FC + +#define mmDMA3_QM_PQ_STS1_0 0x568100 + +#define mmDMA3_QM_PQ_STS1_1 0x568104 + +#define mmDMA3_QM_PQ_STS1_2 0x568108 + +#define mmDMA3_QM_PQ_STS1_3 0x56810C + +#define mmDMA3_QM_CQ_CFG0_0 0x568110 + +#define mmDMA3_QM_CQ_CFG0_1 0x568114 + +#define mmDMA3_QM_CQ_CFG0_2 0x568118 + +#define mmDMA3_QM_CQ_CFG0_3 0x56811C + +#define mmDMA3_QM_CQ_CFG0_4 0x568120 + +#define mmDMA3_QM_CQ_CFG1_0 0x568124 + +#define mmDMA3_QM_CQ_CFG1_1 0x568128 + +#define mmDMA3_QM_CQ_CFG1_2 0x56812C + +#define mmDMA3_QM_CQ_CFG1_3 0x568130 + +#define mmDMA3_QM_CQ_CFG1_4 0x568134 + +#define mmDMA3_QM_CQ_ARUSER_31_11_0 0x568138 + +#define mmDMA3_QM_CQ_ARUSER_31_11_1 0x56813C + +#define mmDMA3_QM_CQ_ARUSER_31_11_2 0x568140 + +#define mmDMA3_QM_CQ_ARUSER_31_11_3 0x568144 + +#define mmDMA3_QM_CQ_ARUSER_31_11_4 0x568148 + +#define mmDMA3_QM_CQ_STS0_0 0x56814C + +#define mmDMA3_QM_CQ_STS0_1 0x568150 + +#define mmDMA3_QM_CQ_STS0_2 0x568154 + +#define mmDMA3_QM_CQ_STS0_3 0x568158 + +#define mmDMA3_QM_CQ_STS0_4 0x56815C + +#define mmDMA3_QM_CQ_STS1_0 0x568160 + +#define mmDMA3_QM_CQ_STS1_1 0x568164 + +#define mmDMA3_QM_CQ_STS1_2 0x568168 + +#define mmDMA3_QM_CQ_STS1_3 0x56816C + +#define mmDMA3_QM_CQ_STS1_4 0x568170 + +#define mmDMA3_QM_CQ_PTR_LO_0 0x568174 + +#define mmDMA3_QM_CQ_PTR_HI_0 0x568178 + +#define mmDMA3_QM_CQ_TSIZE_0 0x56817C + +#define mmDMA3_QM_CQ_CTL_0 0x568180 + +#define mmDMA3_QM_CQ_PTR_LO_1 0x568184 + +#define mmDMA3_QM_CQ_PTR_HI_1 0x568188 + +#define mmDMA3_QM_CQ_TSIZE_1 0x56818C + +#define mmDMA3_QM_CQ_CTL_1 0x568190 + +#define mmDMA3_QM_CQ_PTR_LO_2 0x568194 + +#define mmDMA3_QM_CQ_PTR_HI_2 0x568198 + +#define mmDMA3_QM_CQ_TSIZE_2 0x56819C + +#define mmDMA3_QM_CQ_CTL_2 0x5681A0 + +#define mmDMA3_QM_CQ_PTR_LO_3 0x5681A4 + +#define mmDMA3_QM_CQ_PTR_HI_3 0x5681A8 + +#define mmDMA3_QM_CQ_TSIZE_3 0x5681AC + +#define mmDMA3_QM_CQ_CTL_3 0x5681B0 + +#define mmDMA3_QM_CQ_PTR_LO_4 0x5681B4 + +#define mmDMA3_QM_CQ_PTR_HI_4 0x5681B8 + +#define mmDMA3_QM_CQ_TSIZE_4 0x5681BC + +#define mmDMA3_QM_CQ_CTL_4 0x5681C0 + +#define mmDMA3_QM_CQ_PTR_LO_STS_0 0x5681C4 + +#define mmDMA3_QM_CQ_PTR_LO_STS_1 0x5681C8 + +#define mmDMA3_QM_CQ_PTR_LO_STS_2 0x5681CC + +#define mmDMA3_QM_CQ_PTR_LO_STS_3 0x5681D0 + +#define mmDMA3_QM_CQ_PTR_LO_STS_4 0x5681D4 + +#define mmDMA3_QM_CQ_PTR_HI_STS_0 0x5681D8 + +#define mmDMA3_QM_CQ_PTR_HI_STS_1 0x5681DC + +#define mmDMA3_QM_CQ_PTR_HI_STS_2 0x5681E0 + +#define mmDMA3_QM_CQ_PTR_HI_STS_3 0x5681E4 + +#define mmDMA3_QM_CQ_PTR_HI_STS_4 0x5681E8 + +#define mmDMA3_QM_CQ_TSIZE_STS_0 0x5681EC + +#define mmDMA3_QM_CQ_TSIZE_STS_1 0x5681F0 + +#define mmDMA3_QM_CQ_TSIZE_STS_2 0x5681F4 + +#define mmDMA3_QM_CQ_TSIZE_STS_3 0x5681F8 + +#define mmDMA3_QM_CQ_TSIZE_STS_4 0x5681FC + +#define mmDMA3_QM_CQ_CTL_STS_0 0x568200 + +#define mmDMA3_QM_CQ_CTL_STS_1 0x568204 + +#define mmDMA3_QM_CQ_CTL_STS_2 0x568208 + +#define mmDMA3_QM_CQ_CTL_STS_3 0x56820C + +#define mmDMA3_QM_CQ_CTL_STS_4 0x568210 + +#define mmDMA3_QM_CQ_IFIFO_CNT_0 0x568214 + +#define mmDMA3_QM_CQ_IFIFO_CNT_1 0x568218 + +#define mmDMA3_QM_CQ_IFIFO_CNT_2 0x56821C + +#define mmDMA3_QM_CQ_IFIFO_CNT_3 0x568220 + +#define mmDMA3_QM_CQ_IFIFO_CNT_4 0x568224 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_0 0x568228 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_1 0x56822C + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_2 0x568230 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_3 0x568234 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_LO_4 0x568238 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_0 0x56823C + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_1 0x568240 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_2 0x568244 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_3 0x568248 + +#define mmDMA3_QM_CP_MSG_BASE0_ADDR_HI_4 0x56824C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_0 0x568250 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_1 0x568254 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_2 0x568258 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_3 0x56825C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_LO_4 0x568260 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_0 0x568264 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_1 0x568268 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_2 0x56826C + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_3 0x568270 + +#define mmDMA3_QM_CP_MSG_BASE1_ADDR_HI_4 0x568274 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_0 0x568278 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_1 0x56827C + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_2 0x568280 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_3 0x568284 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_LO_4 0x568288 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_0 0x56828C + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_1 0x568290 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_2 0x568294 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_3 0x568298 + +#define mmDMA3_QM_CP_MSG_BASE2_ADDR_HI_4 0x56829C + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_0 0x5682A0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_1 0x5682A4 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_2 0x5682A8 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_3 0x5682AC + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_LO_4 0x5682B0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_0 0x5682B4 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_1 0x5682B8 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_2 0x5682BC + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_3 0x5682C0 + +#define mmDMA3_QM_CP_MSG_BASE3_ADDR_HI_4 0x5682C4 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_0 0x5682C8 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_1 0x5682CC + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_2 0x5682D0 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_3 0x5682D4 + +#define mmDMA3_QM_CP_LDMA_TSIZE_OFFSET_4 0x5682D8 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5682E0 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5682E4 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5682E8 + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5682EC + +#define mmDMA3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5682F0 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5682F4 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5682F8 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5682FC + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x568300 + +#define mmDMA3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x568304 + +#define mmDMA3_QM_CP_FENCE0_RDATA_0 0x568308 + +#define mmDMA3_QM_CP_FENCE0_RDATA_1 0x56830C + +#define mmDMA3_QM_CP_FENCE0_RDATA_2 0x568310 + +#define mmDMA3_QM_CP_FENCE0_RDATA_3 0x568314 + +#define mmDMA3_QM_CP_FENCE0_RDATA_4 0x568318 + +#define mmDMA3_QM_CP_FENCE1_RDATA_0 0x56831C + +#define mmDMA3_QM_CP_FENCE1_RDATA_1 0x568320 + +#define mmDMA3_QM_CP_FENCE1_RDATA_2 0x568324 + +#define mmDMA3_QM_CP_FENCE1_RDATA_3 0x568328 + +#define mmDMA3_QM_CP_FENCE1_RDATA_4 0x56832C + +#define mmDMA3_QM_CP_FENCE2_RDATA_0 0x568330 + +#define mmDMA3_QM_CP_FENCE2_RDATA_1 0x568334 + +#define mmDMA3_QM_CP_FENCE2_RDATA_2 0x568338 + +#define mmDMA3_QM_CP_FENCE2_RDATA_3 0x56833C + +#define mmDMA3_QM_CP_FENCE2_RDATA_4 0x568340 + +#define mmDMA3_QM_CP_FENCE3_RDATA_0 0x568344 + +#define mmDMA3_QM_CP_FENCE3_RDATA_1 0x568348 + +#define mmDMA3_QM_CP_FENCE3_RDATA_2 0x56834C + +#define mmDMA3_QM_CP_FENCE3_RDATA_3 0x568350 + +#define mmDMA3_QM_CP_FENCE3_RDATA_4 0x568354 + +#define mmDMA3_QM_CP_FENCE0_CNT_0 0x568358 + +#define mmDMA3_QM_CP_FENCE0_CNT_1 0x56835C + +#define mmDMA3_QM_CP_FENCE0_CNT_2 0x568360 + +#define mmDMA3_QM_CP_FENCE0_CNT_3 0x568364 + +#define mmDMA3_QM_CP_FENCE0_CNT_4 0x568368 + +#define mmDMA3_QM_CP_FENCE1_CNT_0 0x56836C + +#define mmDMA3_QM_CP_FENCE1_CNT_1 0x568370 + +#define mmDMA3_QM_CP_FENCE1_CNT_2 0x568374 + +#define mmDMA3_QM_CP_FENCE1_CNT_3 0x568378 + +#define mmDMA3_QM_CP_FENCE1_CNT_4 0x56837C + +#define mmDMA3_QM_CP_FENCE2_CNT_0 0x568380 + +#define mmDMA3_QM_CP_FENCE2_CNT_1 0x568384 + +#define mmDMA3_QM_CP_FENCE2_CNT_2 0x568388 + +#define mmDMA3_QM_CP_FENCE2_CNT_3 0x56838C + +#define mmDMA3_QM_CP_FENCE2_CNT_4 0x568390 + +#define mmDMA3_QM_CP_FENCE3_CNT_0 0x568394 + +#define mmDMA3_QM_CP_FENCE3_CNT_1 0x568398 + +#define mmDMA3_QM_CP_FENCE3_CNT_2 0x56839C + +#define mmDMA3_QM_CP_FENCE3_CNT_3 0x5683A0 + +#define mmDMA3_QM_CP_FENCE3_CNT_4 0x5683A4 + +#define mmDMA3_QM_CP_STS_0 0x5683A8 + +#define mmDMA3_QM_CP_STS_1 0x5683AC + +#define mmDMA3_QM_CP_STS_2 0x5683B0 + +#define mmDMA3_QM_CP_STS_3 0x5683B4 + +#define mmDMA3_QM_CP_STS_4 0x5683B8 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_0 0x5683BC + +#define mmDMA3_QM_CP_CURRENT_INST_LO_1 0x5683C0 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_2 0x5683C4 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_3 0x5683C8 + +#define mmDMA3_QM_CP_CURRENT_INST_LO_4 0x5683CC + +#define mmDMA3_QM_CP_CURRENT_INST_HI_0 0x5683D0 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_1 0x5683D4 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_2 0x5683D8 + +#define mmDMA3_QM_CP_CURRENT_INST_HI_3 0x5683DC + +#define mmDMA3_QM_CP_CURRENT_INST_HI_4 0x5683E0 + +#define mmDMA3_QM_CP_BARRIER_CFG_0 0x5683F4 + +#define mmDMA3_QM_CP_BARRIER_CFG_1 0x5683F8 + +#define mmDMA3_QM_CP_BARRIER_CFG_2 0x5683FC + +#define mmDMA3_QM_CP_BARRIER_CFG_3 0x568400 + +#define mmDMA3_QM_CP_BARRIER_CFG_4 0x568404 + +#define mmDMA3_QM_CP_DBG_0_0 0x568408 + +#define mmDMA3_QM_CP_DBG_0_1 0x56840C + +#define mmDMA3_QM_CP_DBG_0_2 0x568410 + +#define mmDMA3_QM_CP_DBG_0_3 0x568414 + +#define mmDMA3_QM_CP_DBG_0_4 0x568418 + +#define mmDMA3_QM_CP_ARUSER_31_11_0 0x56841C + +#define mmDMA3_QM_CP_ARUSER_31_11_1 0x568420 + +#define mmDMA3_QM_CP_ARUSER_31_11_2 0x568424 + +#define mmDMA3_QM_CP_ARUSER_31_11_3 0x568428 + +#define mmDMA3_QM_CP_ARUSER_31_11_4 0x56842C + +#define mmDMA3_QM_CP_AWUSER_31_11_0 0x568430 + +#define mmDMA3_QM_CP_AWUSER_31_11_1 0x568434 + +#define mmDMA3_QM_CP_AWUSER_31_11_2 0x568438 + +#define mmDMA3_QM_CP_AWUSER_31_11_3 0x56843C + +#define mmDMA3_QM_CP_AWUSER_31_11_4 0x568440 + +#define mmDMA3_QM_ARB_CFG_0 0x568A00 + +#define mmDMA3_QM_ARB_CHOISE_Q_PUSH 0x568A04 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_0 0x568A08 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_1 0x568A0C + +#define mmDMA3_QM_ARB_WRR_WEIGHT_2 0x568A10 + +#define mmDMA3_QM_ARB_WRR_WEIGHT_3 0x568A14 + +#define mmDMA3_QM_ARB_CFG_1 0x568A18 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_0 0x568A20 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_1 0x568A24 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_2 0x568A28 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_3 0x568A2C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_4 0x568A30 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_5 0x568A34 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_6 0x568A38 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_7 0x568A3C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_8 0x568A40 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_9 0x568A44 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_10 0x568A48 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_11 0x568A4C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_12 0x568A50 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_13 0x568A54 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_14 0x568A58 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_15 0x568A5C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_16 0x568A60 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_17 0x568A64 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_18 0x568A68 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_19 0x568A6C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_20 0x568A70 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_21 0x568A74 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_22 0x568A78 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_23 0x568A7C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_24 0x568A80 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_25 0x568A84 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_26 0x568A88 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_27 0x568A8C + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_28 0x568A90 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_29 0x568A94 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_30 0x568A98 + +#define mmDMA3_QM_ARB_MST_AVAIL_CRED_31 0x568A9C + +#define mmDMA3_QM_ARB_MST_CRED_INC 0x568AA0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x568AA4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x568AA8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x568AAC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x568AB0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x568AB4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x568AB8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x568ABC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x568AC0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x568AC4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x568AC8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x568ACC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x568AD0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x568AD4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x568AD8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x568ADC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x568AE0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x568AE4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x568AE8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x568AEC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x568AF0 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x568AF4 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x568AF8 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x568AFC + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x568B00 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x568B04 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x568B08 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x568B0C + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x568B10 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x568B14 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x568B18 + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x568B1C + +#define mmDMA3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x568B20 + +#define mmDMA3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x568B28 + +#define mmDMA3_QM_ARB_MST_SLAVE_EN 0x568B2C + +#define mmDMA3_QM_ARB_MST_QUIET_PER 0x568B34 + +#define mmDMA3_QM_ARB_SLV_CHOISE_WDT 0x568B38 + +#define mmDMA3_QM_ARB_SLV_ID 0x568B3C + +#define mmDMA3_QM_ARB_MSG_MAX_INFLIGHT 0x568B44 + +#define mmDMA3_QM_ARB_MSG_AWUSER_31_11 0x568B48 + +#define mmDMA3_QM_ARB_MSG_AWUSER_SEC_PROP 0x568B4C + +#define mmDMA3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x568B50 + +#define mmDMA3_QM_ARB_BASE_LO 0x568B54 + +#define mmDMA3_QM_ARB_BASE_HI 0x568B58 + +#define mmDMA3_QM_ARB_STATE_STS 0x568B80 + +#define mmDMA3_QM_ARB_CHOISE_FULLNESS_STS 0x568B84 + +#define mmDMA3_QM_ARB_MSG_STS 0x568B88 + +#define mmDMA3_QM_ARB_SLV_CHOISE_Q_HEAD 0x568B8C + +#define mmDMA3_QM_ARB_ERR_CAUSE 0x568B9C + +#define mmDMA3_QM_ARB_ERR_MSG_EN 0x568BA0 + +#define mmDMA3_QM_ARB_ERR_STS_DRP 0x568BA8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_0 0x568BB0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_1 0x568BB4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_2 0x568BB8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_3 0x568BBC + +#define mmDMA3_QM_ARB_MST_CRED_STS_4 0x568BC0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_5 0x568BC4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_6 0x568BC8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_7 0x568BCC + +#define mmDMA3_QM_ARB_MST_CRED_STS_8 0x568BD0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_9 0x568BD4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_10 0x568BD8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_11 0x568BDC + +#define mmDMA3_QM_ARB_MST_CRED_STS_12 0x568BE0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_13 0x568BE4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_14 0x568BE8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_15 0x568BEC + +#define mmDMA3_QM_ARB_MST_CRED_STS_16 0x568BF0 + +#define mmDMA3_QM_ARB_MST_CRED_STS_17 0x568BF4 + +#define mmDMA3_QM_ARB_MST_CRED_STS_18 0x568BF8 + +#define mmDMA3_QM_ARB_MST_CRED_STS_19 0x568BFC + +#define mmDMA3_QM_ARB_MST_CRED_STS_20 0x568C00 + +#define mmDMA3_QM_ARB_MST_CRED_STS_21 0x568C04 + +#define mmDMA3_QM_ARB_MST_CRED_STS_22 0x568C08 + +#define mmDMA3_QM_ARB_MST_CRED_STS_23 0x568C0C + +#define mmDMA3_QM_ARB_MST_CRED_STS_24 0x568C10 + +#define mmDMA3_QM_ARB_MST_CRED_STS_25 0x568C14 + +#define mmDMA3_QM_ARB_MST_CRED_STS_26 0x568C18 + +#define mmDMA3_QM_ARB_MST_CRED_STS_27 0x568C1C + +#define mmDMA3_QM_ARB_MST_CRED_STS_28 0x568C20 + +#define mmDMA3_QM_ARB_MST_CRED_STS_29 0x568C24 + +#define mmDMA3_QM_ARB_MST_CRED_STS_30 0x568C28 + +#define mmDMA3_QM_ARB_MST_CRED_STS_31 0x568C2C + +#define mmDMA3_QM_CGM_CFG 0x568C70 + +#define mmDMA3_QM_CGM_STS 0x568C74 + +#define mmDMA3_QM_CGM_CFG1 0x568C78 + +#define mmDMA3_QM_LOCAL_RANGE_BASE 0x568C80 + +#define mmDMA3_QM_LOCAL_RANGE_SIZE 0x568C84 + +#define mmDMA3_QM_CSMR_STRICT_PRIO_CFG 0x568C90 + +#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_1 0x568C94 + +#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_0 0x568C98 + +#define mmDMA3_QM_LBW_WR_RATE_LIM_CFG_1 0x568C9C + +#define mmDMA3_QM_HBW_RD_RATE_LIM_CFG_0 0x568CA0 + +#define mmDMA3_QM_GLBL_AXCACHE 0x568CA4 + +#define mmDMA3_QM_IND_GW_APB_CFG 0x568CB0 + +#define mmDMA3_QM_IND_GW_APB_WDATA 0x568CB4 + +#define mmDMA3_QM_IND_GW_APB_RDATA 0x568CB8 + +#define mmDMA3_QM_IND_GW_APB_STATUS 0x568CBC + +#define mmDMA3_QM_GLBL_ERR_ADDR_LO 0x568CD0 + +#define mmDMA3_QM_GLBL_ERR_ADDR_HI 0x568CD4 + +#define mmDMA3_QM_GLBL_ERR_WDATA 0x568CD8 + +#define mmDMA3_QM_GLBL_MEM_INIT_BUSY 0x568D00 + +#endif /* ASIC_REG_DMA3_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h new file mode 100644 index 000000000000..192d11404b1c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA4_CORE_REGS_H_ +#define ASIC_REG_DMA4_CORE_REGS_H_ + +/* + ***************************************** + * DMA4_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA4_CORE_CFG_0 0x580000 + +#define mmDMA4_CORE_CFG_1 0x580004 + +#define mmDMA4_CORE_LBW_MAX_OUTSTAND 0x580008 + +#define mmDMA4_CORE_SRC_BASE_LO 0x580014 + +#define mmDMA4_CORE_SRC_BASE_HI 0x580018 + +#define mmDMA4_CORE_DST_BASE_LO 0x58001C + +#define mmDMA4_CORE_DST_BASE_HI 0x580020 + +#define mmDMA4_CORE_SRC_TSIZE_1 0x58002C + +#define mmDMA4_CORE_SRC_STRIDE_1 0x580030 + +#define mmDMA4_CORE_SRC_TSIZE_2 0x580034 + +#define mmDMA4_CORE_SRC_STRIDE_2 0x580038 + +#define mmDMA4_CORE_SRC_TSIZE_3 0x58003C + +#define mmDMA4_CORE_SRC_STRIDE_3 0x580040 + +#define mmDMA4_CORE_SRC_TSIZE_4 0x580044 + +#define mmDMA4_CORE_SRC_STRIDE_4 0x580048 + +#define mmDMA4_CORE_SRC_TSIZE_0 0x58004C + +#define mmDMA4_CORE_DST_TSIZE_1 0x580054 + +#define mmDMA4_CORE_DST_STRIDE_1 0x580058 + +#define mmDMA4_CORE_DST_TSIZE_2 0x58005C + +#define mmDMA4_CORE_DST_STRIDE_2 0x580060 + +#define mmDMA4_CORE_DST_TSIZE_3 0x580064 + +#define mmDMA4_CORE_DST_STRIDE_3 0x580068 + +#define mmDMA4_CORE_DST_TSIZE_4 0x58006C + +#define mmDMA4_CORE_DST_STRIDE_4 0x580070 + +#define mmDMA4_CORE_DST_TSIZE_0 0x580074 + +#define mmDMA4_CORE_COMMIT 0x580078 + +#define mmDMA4_CORE_WR_COMP_WDATA 0x58007C + +#define mmDMA4_CORE_WR_COMP_ADDR_LO 0x580080 + +#define mmDMA4_CORE_WR_COMP_ADDR_HI 0x580084 + +#define mmDMA4_CORE_WR_COMP_AWUSER_31_11 0x580088 + +#define mmDMA4_CORE_TE_NUMROWS 0x580094 + +#define mmDMA4_CORE_PROT 0x5800B8 + +#define mmDMA4_CORE_SECURE_PROPS 0x5800F0 + +#define mmDMA4_CORE_NON_SECURE_PROPS 0x5800F4 + +#define mmDMA4_CORE_RD_MAX_OUTSTAND 0x580100 + +#define mmDMA4_CORE_RD_MAX_SIZE 0x580104 + +#define mmDMA4_CORE_RD_ARCACHE 0x580108 + +#define mmDMA4_CORE_RD_ARUSER_31_11 0x580110 + +#define mmDMA4_CORE_RD_INFLIGHTS 0x580114 + +#define mmDMA4_CORE_WR_MAX_OUTSTAND 0x580120 + +#define mmDMA4_CORE_WR_MAX_AWID 0x580124 + +#define mmDMA4_CORE_WR_AWCACHE 0x580128 + +#define mmDMA4_CORE_WR_AWUSER_31_11 0x580130 + +#define mmDMA4_CORE_WR_INFLIGHTS 0x580134 + +#define mmDMA4_CORE_RD_RATE_LIM_CFG_0 0x580150 + +#define mmDMA4_CORE_RD_RATE_LIM_CFG_1 0x580154 + +#define mmDMA4_CORE_WR_RATE_LIM_CFG_0 0x580158 + +#define mmDMA4_CORE_WR_RATE_LIM_CFG_1 0x58015C + +#define mmDMA4_CORE_ERR_CFG 0x580160 + +#define mmDMA4_CORE_ERR_CAUSE 0x580164 + +#define mmDMA4_CORE_ERRMSG_ADDR_LO 0x580170 + +#define mmDMA4_CORE_ERRMSG_ADDR_HI 0x580174 + +#define mmDMA4_CORE_ERRMSG_WDATA 0x580178 + +#define mmDMA4_CORE_STS0 0x580190 + +#define mmDMA4_CORE_STS1 0x580194 + +#define mmDMA4_CORE_RD_DBGMEM_ADD 0x580200 + +#define mmDMA4_CORE_RD_DBGMEM_DATA_WR 0x580204 + +#define mmDMA4_CORE_RD_DBGMEM_DATA_RD 0x580208 + +#define mmDMA4_CORE_RD_DBGMEM_CTRL 0x58020C + +#define mmDMA4_CORE_RD_DBGMEM_RC 0x580210 + +#define mmDMA4_CORE_DBG_HBW_AXI_AR_CNT 0x580220 + +#define mmDMA4_CORE_DBG_HBW_AXI_AW_CNT 0x580224 + +#define mmDMA4_CORE_DBG_LBW_AXI_AW_CNT 0x580228 + +#define mmDMA4_CORE_DBG_DESC_CNT 0x58022C + +#define mmDMA4_CORE_DBG_STS 0x580230 + +#define mmDMA4_CORE_DBG_RD_DESC_ID 0x580234 + +#define mmDMA4_CORE_DBG_WR_DESC_ID 0x580238 + +#endif /* ASIC_REG_DMA4_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h new file mode 100644 index 000000000000..f0cbda0d1e4d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma4_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA4_QM_REGS_H_ +#define ASIC_REG_DMA4_QM_REGS_H_ + +/* + ***************************************** + * DMA4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA4_QM_GLBL_CFG0 0x588000 + +#define mmDMA4_QM_GLBL_CFG1 0x588004 + +#define mmDMA4_QM_GLBL_PROT 0x588008 + +#define mmDMA4_QM_GLBL_ERR_CFG 0x58800C + +#define mmDMA4_QM_GLBL_SECURE_PROPS_0 0x588010 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_1 0x588014 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_2 0x588018 + +#define mmDMA4_QM_GLBL_SECURE_PROPS_3 0x58801C + +#define mmDMA4_QM_GLBL_SECURE_PROPS_4 0x588020 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 0x588024 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 0x588028 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 0x58802C + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 0x588030 + +#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 0x588034 + +#define mmDMA4_QM_GLBL_STS0 0x588038 + +#define mmDMA4_QM_GLBL_STS1_0 0x588040 + +#define mmDMA4_QM_GLBL_STS1_1 0x588044 + +#define mmDMA4_QM_GLBL_STS1_2 0x588048 + +#define mmDMA4_QM_GLBL_STS1_3 0x58804C + +#define mmDMA4_QM_GLBL_STS1_4 0x588050 + +#define mmDMA4_QM_GLBL_MSG_EN_0 0x588054 + +#define mmDMA4_QM_GLBL_MSG_EN_1 0x588058 + +#define mmDMA4_QM_GLBL_MSG_EN_2 0x58805C + +#define mmDMA4_QM_GLBL_MSG_EN_3 0x588060 + +#define mmDMA4_QM_GLBL_MSG_EN_4 0x588068 + +#define mmDMA4_QM_PQ_BASE_LO_0 0x588070 + +#define mmDMA4_QM_PQ_BASE_LO_1 0x588074 + +#define mmDMA4_QM_PQ_BASE_LO_2 0x588078 + +#define mmDMA4_QM_PQ_BASE_LO_3 0x58807C + +#define mmDMA4_QM_PQ_BASE_HI_0 0x588080 + +#define mmDMA4_QM_PQ_BASE_HI_1 0x588084 + +#define mmDMA4_QM_PQ_BASE_HI_2 0x588088 + +#define mmDMA4_QM_PQ_BASE_HI_3 0x58808C + +#define mmDMA4_QM_PQ_SIZE_0 0x588090 + +#define mmDMA4_QM_PQ_SIZE_1 0x588094 + +#define mmDMA4_QM_PQ_SIZE_2 0x588098 + +#define mmDMA4_QM_PQ_SIZE_3 0x58809C + +#define mmDMA4_QM_PQ_PI_0 0x5880A0 + +#define mmDMA4_QM_PQ_PI_1 0x5880A4 + +#define mmDMA4_QM_PQ_PI_2 0x5880A8 + +#define mmDMA4_QM_PQ_PI_3 0x5880AC + +#define mmDMA4_QM_PQ_CI_0 0x5880B0 + +#define mmDMA4_QM_PQ_CI_1 0x5880B4 + +#define mmDMA4_QM_PQ_CI_2 0x5880B8 + +#define mmDMA4_QM_PQ_CI_3 0x5880BC + +#define mmDMA4_QM_PQ_CFG0_0 0x5880C0 + +#define mmDMA4_QM_PQ_CFG0_1 0x5880C4 + +#define mmDMA4_QM_PQ_CFG0_2 0x5880C8 + +#define mmDMA4_QM_PQ_CFG0_3 0x5880CC + +#define mmDMA4_QM_PQ_CFG1_0 0x5880D0 + +#define mmDMA4_QM_PQ_CFG1_1 0x5880D4 + +#define mmDMA4_QM_PQ_CFG1_2 0x5880D8 + +#define mmDMA4_QM_PQ_CFG1_3 0x5880DC + +#define mmDMA4_QM_PQ_ARUSER_31_11_0 0x5880E0 + +#define mmDMA4_QM_PQ_ARUSER_31_11_1 0x5880E4 + +#define mmDMA4_QM_PQ_ARUSER_31_11_2 0x5880E8 + +#define mmDMA4_QM_PQ_ARUSER_31_11_3 0x5880EC + +#define mmDMA4_QM_PQ_STS0_0 0x5880F0 + +#define mmDMA4_QM_PQ_STS0_1 0x5880F4 + +#define mmDMA4_QM_PQ_STS0_2 0x5880F8 + +#define mmDMA4_QM_PQ_STS0_3 0x5880FC + +#define mmDMA4_QM_PQ_STS1_0 0x588100 + +#define mmDMA4_QM_PQ_STS1_1 0x588104 + +#define mmDMA4_QM_PQ_STS1_2 0x588108 + +#define mmDMA4_QM_PQ_STS1_3 0x58810C + +#define mmDMA4_QM_CQ_CFG0_0 0x588110 + +#define mmDMA4_QM_CQ_CFG0_1 0x588114 + +#define mmDMA4_QM_CQ_CFG0_2 0x588118 + +#define mmDMA4_QM_CQ_CFG0_3 0x58811C + +#define mmDMA4_QM_CQ_CFG0_4 0x588120 + +#define mmDMA4_QM_CQ_CFG1_0 0x588124 + +#define mmDMA4_QM_CQ_CFG1_1 0x588128 + +#define mmDMA4_QM_CQ_CFG1_2 0x58812C + +#define mmDMA4_QM_CQ_CFG1_3 0x588130 + +#define mmDMA4_QM_CQ_CFG1_4 0x588134 + +#define mmDMA4_QM_CQ_ARUSER_31_11_0 0x588138 + +#define mmDMA4_QM_CQ_ARUSER_31_11_1 0x58813C + +#define mmDMA4_QM_CQ_ARUSER_31_11_2 0x588140 + +#define mmDMA4_QM_CQ_ARUSER_31_11_3 0x588144 + +#define mmDMA4_QM_CQ_ARUSER_31_11_4 0x588148 + +#define mmDMA4_QM_CQ_STS0_0 0x58814C + +#define mmDMA4_QM_CQ_STS0_1 0x588150 + +#define mmDMA4_QM_CQ_STS0_2 0x588154 + +#define mmDMA4_QM_CQ_STS0_3 0x588158 + +#define mmDMA4_QM_CQ_STS0_4 0x58815C + +#define mmDMA4_QM_CQ_STS1_0 0x588160 + +#define mmDMA4_QM_CQ_STS1_1 0x588164 + +#define mmDMA4_QM_CQ_STS1_2 0x588168 + +#define mmDMA4_QM_CQ_STS1_3 0x58816C + +#define mmDMA4_QM_CQ_STS1_4 0x588170 + +#define mmDMA4_QM_CQ_PTR_LO_0 0x588174 + +#define mmDMA4_QM_CQ_PTR_HI_0 0x588178 + +#define mmDMA4_QM_CQ_TSIZE_0 0x58817C + +#define mmDMA4_QM_CQ_CTL_0 0x588180 + +#define mmDMA4_QM_CQ_PTR_LO_1 0x588184 + +#define mmDMA4_QM_CQ_PTR_HI_1 0x588188 + +#define mmDMA4_QM_CQ_TSIZE_1 0x58818C + +#define mmDMA4_QM_CQ_CTL_1 0x588190 + +#define mmDMA4_QM_CQ_PTR_LO_2 0x588194 + +#define mmDMA4_QM_CQ_PTR_HI_2 0x588198 + +#define mmDMA4_QM_CQ_TSIZE_2 0x58819C + +#define mmDMA4_QM_CQ_CTL_2 0x5881A0 + +#define mmDMA4_QM_CQ_PTR_LO_3 0x5881A4 + +#define mmDMA4_QM_CQ_PTR_HI_3 0x5881A8 + +#define mmDMA4_QM_CQ_TSIZE_3 0x5881AC + +#define mmDMA4_QM_CQ_CTL_3 0x5881B0 + +#define mmDMA4_QM_CQ_PTR_LO_4 0x5881B4 + +#define mmDMA4_QM_CQ_PTR_HI_4 0x5881B8 + +#define mmDMA4_QM_CQ_TSIZE_4 0x5881BC + +#define mmDMA4_QM_CQ_CTL_4 0x5881C0 + +#define mmDMA4_QM_CQ_PTR_LO_STS_0 0x5881C4 + +#define mmDMA4_QM_CQ_PTR_LO_STS_1 0x5881C8 + +#define mmDMA4_QM_CQ_PTR_LO_STS_2 0x5881CC + +#define mmDMA4_QM_CQ_PTR_LO_STS_3 0x5881D0 + +#define mmDMA4_QM_CQ_PTR_LO_STS_4 0x5881D4 + +#define mmDMA4_QM_CQ_PTR_HI_STS_0 0x5881D8 + +#define mmDMA4_QM_CQ_PTR_HI_STS_1 0x5881DC + +#define mmDMA4_QM_CQ_PTR_HI_STS_2 0x5881E0 + +#define mmDMA4_QM_CQ_PTR_HI_STS_3 0x5881E4 + +#define mmDMA4_QM_CQ_PTR_HI_STS_4 0x5881E8 + +#define mmDMA4_QM_CQ_TSIZE_STS_0 0x5881EC + +#define mmDMA4_QM_CQ_TSIZE_STS_1 0x5881F0 + +#define mmDMA4_QM_CQ_TSIZE_STS_2 0x5881F4 + +#define mmDMA4_QM_CQ_TSIZE_STS_3 0x5881F8 + +#define mmDMA4_QM_CQ_TSIZE_STS_4 0x5881FC + +#define mmDMA4_QM_CQ_CTL_STS_0 0x588200 + +#define mmDMA4_QM_CQ_CTL_STS_1 0x588204 + +#define mmDMA4_QM_CQ_CTL_STS_2 0x588208 + +#define mmDMA4_QM_CQ_CTL_STS_3 0x58820C + +#define mmDMA4_QM_CQ_CTL_STS_4 0x588210 + +#define mmDMA4_QM_CQ_IFIFO_CNT_0 0x588214 + +#define mmDMA4_QM_CQ_IFIFO_CNT_1 0x588218 + +#define mmDMA4_QM_CQ_IFIFO_CNT_2 0x58821C + +#define mmDMA4_QM_CQ_IFIFO_CNT_3 0x588220 + +#define mmDMA4_QM_CQ_IFIFO_CNT_4 0x588224 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 0x588228 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 0x58822C + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 0x588230 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 0x588234 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 0x588238 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 0x58823C + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 0x588240 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 0x588244 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 0x588248 + +#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 0x58824C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 0x588250 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 0x588254 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 0x588258 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 0x58825C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 0x588260 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 0x588264 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 0x588268 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 0x58826C + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 0x588270 + +#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 0x588274 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 0x588278 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 0x58827C + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 0x588280 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 0x588284 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 0x588288 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 0x58828C + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 0x588290 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 0x588294 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 0x588298 + +#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 0x58829C + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 0x5882A0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 0x5882A4 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 0x5882A8 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 0x5882AC + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 0x5882B0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 0x5882B4 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 0x5882B8 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 0x5882BC + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 0x5882C0 + +#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 0x5882C4 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 0x5882C8 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 0x5882CC + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 0x5882D0 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 0x5882D4 + +#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 0x5882D8 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5882E0 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5882E4 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5882E8 + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5882EC + +#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5882F0 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5882F4 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5882F8 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5882FC + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x588300 + +#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x588304 + +#define mmDMA4_QM_CP_FENCE0_RDATA_0 0x588308 + +#define mmDMA4_QM_CP_FENCE0_RDATA_1 0x58830C + +#define mmDMA4_QM_CP_FENCE0_RDATA_2 0x588310 + +#define mmDMA4_QM_CP_FENCE0_RDATA_3 0x588314 + +#define mmDMA4_QM_CP_FENCE0_RDATA_4 0x588318 + +#define mmDMA4_QM_CP_FENCE1_RDATA_0 0x58831C + +#define mmDMA4_QM_CP_FENCE1_RDATA_1 0x588320 + +#define mmDMA4_QM_CP_FENCE1_RDATA_2 0x588324 + +#define mmDMA4_QM_CP_FENCE1_RDATA_3 0x588328 + +#define mmDMA4_QM_CP_FENCE1_RDATA_4 0x58832C + +#define mmDMA4_QM_CP_FENCE2_RDATA_0 0x588330 + +#define mmDMA4_QM_CP_FENCE2_RDATA_1 0x588334 + +#define mmDMA4_QM_CP_FENCE2_RDATA_2 0x588338 + +#define mmDMA4_QM_CP_FENCE2_RDATA_3 0x58833C + +#define mmDMA4_QM_CP_FENCE2_RDATA_4 0x588340 + +#define mmDMA4_QM_CP_FENCE3_RDATA_0 0x588344 + +#define mmDMA4_QM_CP_FENCE3_RDATA_1 0x588348 + +#define mmDMA4_QM_CP_FENCE3_RDATA_2 0x58834C + +#define mmDMA4_QM_CP_FENCE3_RDATA_3 0x588350 + +#define mmDMA4_QM_CP_FENCE3_RDATA_4 0x588354 + +#define mmDMA4_QM_CP_FENCE0_CNT_0 0x588358 + +#define mmDMA4_QM_CP_FENCE0_CNT_1 0x58835C + +#define mmDMA4_QM_CP_FENCE0_CNT_2 0x588360 + +#define mmDMA4_QM_CP_FENCE0_CNT_3 0x588364 + +#define mmDMA4_QM_CP_FENCE0_CNT_4 0x588368 + +#define mmDMA4_QM_CP_FENCE1_CNT_0 0x58836C + +#define mmDMA4_QM_CP_FENCE1_CNT_1 0x588370 + +#define mmDMA4_QM_CP_FENCE1_CNT_2 0x588374 + +#define mmDMA4_QM_CP_FENCE1_CNT_3 0x588378 + +#define mmDMA4_QM_CP_FENCE1_CNT_4 0x58837C + +#define mmDMA4_QM_CP_FENCE2_CNT_0 0x588380 + +#define mmDMA4_QM_CP_FENCE2_CNT_1 0x588384 + +#define mmDMA4_QM_CP_FENCE2_CNT_2 0x588388 + +#define mmDMA4_QM_CP_FENCE2_CNT_3 0x58838C + +#define mmDMA4_QM_CP_FENCE2_CNT_4 0x588390 + +#define mmDMA4_QM_CP_FENCE3_CNT_0 0x588394 + +#define mmDMA4_QM_CP_FENCE3_CNT_1 0x588398 + +#define mmDMA4_QM_CP_FENCE3_CNT_2 0x58839C + +#define mmDMA4_QM_CP_FENCE3_CNT_3 0x5883A0 + +#define mmDMA4_QM_CP_FENCE3_CNT_4 0x5883A4 + +#define mmDMA4_QM_CP_STS_0 0x5883A8 + +#define mmDMA4_QM_CP_STS_1 0x5883AC + +#define mmDMA4_QM_CP_STS_2 0x5883B0 + +#define mmDMA4_QM_CP_STS_3 0x5883B4 + +#define mmDMA4_QM_CP_STS_4 0x5883B8 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_0 0x5883BC + +#define mmDMA4_QM_CP_CURRENT_INST_LO_1 0x5883C0 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_2 0x5883C4 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_3 0x5883C8 + +#define mmDMA4_QM_CP_CURRENT_INST_LO_4 0x5883CC + +#define mmDMA4_QM_CP_CURRENT_INST_HI_0 0x5883D0 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_1 0x5883D4 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_2 0x5883D8 + +#define mmDMA4_QM_CP_CURRENT_INST_HI_3 0x5883DC + +#define mmDMA4_QM_CP_CURRENT_INST_HI_4 0x5883E0 + +#define mmDMA4_QM_CP_BARRIER_CFG_0 0x5883F4 + +#define mmDMA4_QM_CP_BARRIER_CFG_1 0x5883F8 + +#define mmDMA4_QM_CP_BARRIER_CFG_2 0x5883FC + +#define mmDMA4_QM_CP_BARRIER_CFG_3 0x588400 + +#define mmDMA4_QM_CP_BARRIER_CFG_4 0x588404 + +#define mmDMA4_QM_CP_DBG_0_0 0x588408 + +#define mmDMA4_QM_CP_DBG_0_1 0x58840C + +#define mmDMA4_QM_CP_DBG_0_2 0x588410 + +#define mmDMA4_QM_CP_DBG_0_3 0x588414 + +#define mmDMA4_QM_CP_DBG_0_4 0x588418 + +#define mmDMA4_QM_CP_ARUSER_31_11_0 0x58841C + +#define mmDMA4_QM_CP_ARUSER_31_11_1 0x588420 + +#define mmDMA4_QM_CP_ARUSER_31_11_2 0x588424 + +#define mmDMA4_QM_CP_ARUSER_31_11_3 0x588428 + +#define mmDMA4_QM_CP_ARUSER_31_11_4 0x58842C + +#define mmDMA4_QM_CP_AWUSER_31_11_0 0x588430 + +#define mmDMA4_QM_CP_AWUSER_31_11_1 0x588434 + +#define mmDMA4_QM_CP_AWUSER_31_11_2 0x588438 + +#define mmDMA4_QM_CP_AWUSER_31_11_3 0x58843C + +#define mmDMA4_QM_CP_AWUSER_31_11_4 0x588440 + +#define mmDMA4_QM_ARB_CFG_0 0x588A00 + +#define mmDMA4_QM_ARB_CHOISE_Q_PUSH 0x588A04 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_0 0x588A08 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_1 0x588A0C + +#define mmDMA4_QM_ARB_WRR_WEIGHT_2 0x588A10 + +#define mmDMA4_QM_ARB_WRR_WEIGHT_3 0x588A14 + +#define mmDMA4_QM_ARB_CFG_1 0x588A18 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0 0x588A20 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1 0x588A24 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2 0x588A28 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3 0x588A2C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4 0x588A30 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5 0x588A34 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6 0x588A38 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7 0x588A3C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8 0x588A40 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9 0x588A44 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10 0x588A48 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11 0x588A4C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12 0x588A50 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13 0x588A54 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14 0x588A58 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15 0x588A5C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16 0x588A60 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17 0x588A64 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18 0x588A68 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19 0x588A6C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20 0x588A70 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21 0x588A74 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22 0x588A78 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23 0x588A7C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24 0x588A80 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25 0x588A84 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26 0x588A88 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27 0x588A8C + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28 0x588A90 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29 0x588A94 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30 0x588A98 + +#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31 0x588A9C + +#define mmDMA4_QM_ARB_MST_CRED_INC 0x588AA0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x588AA4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x588AA8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x588AAC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x588AB0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x588AB4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x588AB8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x588ABC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x588AC0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x588AC4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x588AC8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x588ACC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x588AD0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x588AD4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x588AD8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x588ADC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x588AE0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x588AE4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x588AE8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x588AEC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x588AF0 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x588AF4 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x588AF8 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x588AFC + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x588B00 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x588B04 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x588B08 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x588B0C + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x588B10 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x588B14 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x588B18 + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x588B1C + +#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x588B20 + +#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x588B28 + +#define mmDMA4_QM_ARB_MST_SLAVE_EN 0x588B2C + +#define mmDMA4_QM_ARB_MST_QUIET_PER 0x588B34 + +#define mmDMA4_QM_ARB_SLV_CHOISE_WDT 0x588B38 + +#define mmDMA4_QM_ARB_SLV_ID 0x588B3C + +#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT 0x588B44 + +#define mmDMA4_QM_ARB_MSG_AWUSER_31_11 0x588B48 + +#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP 0x588B4C + +#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x588B50 + +#define mmDMA4_QM_ARB_BASE_LO 0x588B54 + +#define mmDMA4_QM_ARB_BASE_HI 0x588B58 + +#define mmDMA4_QM_ARB_STATE_STS 0x588B80 + +#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS 0x588B84 + +#define mmDMA4_QM_ARB_MSG_STS 0x588B88 + +#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD 0x588B8C + +#define mmDMA4_QM_ARB_ERR_CAUSE 0x588B9C + +#define mmDMA4_QM_ARB_ERR_MSG_EN 0x588BA0 + +#define mmDMA4_QM_ARB_ERR_STS_DRP 0x588BA8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_0 0x588BB0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_1 0x588BB4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_2 0x588BB8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_3 0x588BBC + +#define mmDMA4_QM_ARB_MST_CRED_STS_4 0x588BC0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_5 0x588BC4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_6 0x588BC8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_7 0x588BCC + +#define mmDMA4_QM_ARB_MST_CRED_STS_8 0x588BD0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_9 0x588BD4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_10 0x588BD8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_11 0x588BDC + +#define mmDMA4_QM_ARB_MST_CRED_STS_12 0x588BE0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_13 0x588BE4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_14 0x588BE8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_15 0x588BEC + +#define mmDMA4_QM_ARB_MST_CRED_STS_16 0x588BF0 + +#define mmDMA4_QM_ARB_MST_CRED_STS_17 0x588BF4 + +#define mmDMA4_QM_ARB_MST_CRED_STS_18 0x588BF8 + +#define mmDMA4_QM_ARB_MST_CRED_STS_19 0x588BFC + +#define mmDMA4_QM_ARB_MST_CRED_STS_20 0x588C00 + +#define mmDMA4_QM_ARB_MST_CRED_STS_21 0x588C04 + +#define mmDMA4_QM_ARB_MST_CRED_STS_22 0x588C08 + +#define mmDMA4_QM_ARB_MST_CRED_STS_23 0x588C0C + +#define mmDMA4_QM_ARB_MST_CRED_STS_24 0x588C10 + +#define mmDMA4_QM_ARB_MST_CRED_STS_25 0x588C14 + +#define mmDMA4_QM_ARB_MST_CRED_STS_26 0x588C18 + +#define mmDMA4_QM_ARB_MST_CRED_STS_27 0x588C1C + +#define mmDMA4_QM_ARB_MST_CRED_STS_28 0x588C20 + +#define mmDMA4_QM_ARB_MST_CRED_STS_29 0x588C24 + +#define mmDMA4_QM_ARB_MST_CRED_STS_30 0x588C28 + +#define mmDMA4_QM_ARB_MST_CRED_STS_31 0x588C2C + +#define mmDMA4_QM_CGM_CFG 0x588C70 + +#define mmDMA4_QM_CGM_STS 0x588C74 + +#define mmDMA4_QM_CGM_CFG1 0x588C78 + +#define mmDMA4_QM_LOCAL_RANGE_BASE 0x588C80 + +#define mmDMA4_QM_LOCAL_RANGE_SIZE 0x588C84 + +#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG 0x588C90 + +#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 0x588C94 + +#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 0x588C98 + +#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 0x588C9C + +#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 0x588CA0 + +#define mmDMA4_QM_GLBL_AXCACHE 0x588CA4 + +#define mmDMA4_QM_IND_GW_APB_CFG 0x588CB0 + +#define mmDMA4_QM_IND_GW_APB_WDATA 0x588CB4 + +#define mmDMA4_QM_IND_GW_APB_RDATA 0x588CB8 + +#define mmDMA4_QM_IND_GW_APB_STATUS 0x588CBC + +#define mmDMA4_QM_GLBL_ERR_ADDR_LO 0x588CD0 + +#define mmDMA4_QM_GLBL_ERR_ADDR_HI 0x588CD4 + +#define mmDMA4_QM_GLBL_ERR_WDATA 0x588CD8 + +#define mmDMA4_QM_GLBL_MEM_INIT_BUSY 0x588D00 + +#endif /* ASIC_REG_DMA4_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h new file mode 100644 index 000000000000..6e07c6fb6fc9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA5_CORE_REGS_H_ +#define ASIC_REG_DMA5_CORE_REGS_H_ + +/* + ***************************************** + * DMA5_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA5_CORE_CFG_0 0x5A0000 + +#define mmDMA5_CORE_CFG_1 0x5A0004 + +#define mmDMA5_CORE_LBW_MAX_OUTSTAND 0x5A0008 + +#define mmDMA5_CORE_SRC_BASE_LO 0x5A0014 + +#define mmDMA5_CORE_SRC_BASE_HI 0x5A0018 + +#define mmDMA5_CORE_DST_BASE_LO 0x5A001C + +#define mmDMA5_CORE_DST_BASE_HI 0x5A0020 + +#define mmDMA5_CORE_SRC_TSIZE_1 0x5A002C + +#define mmDMA5_CORE_SRC_STRIDE_1 0x5A0030 + +#define mmDMA5_CORE_SRC_TSIZE_2 0x5A0034 + +#define mmDMA5_CORE_SRC_STRIDE_2 0x5A0038 + +#define mmDMA5_CORE_SRC_TSIZE_3 0x5A003C + +#define mmDMA5_CORE_SRC_STRIDE_3 0x5A0040 + +#define mmDMA5_CORE_SRC_TSIZE_4 0x5A0044 + +#define mmDMA5_CORE_SRC_STRIDE_4 0x5A0048 + +#define mmDMA5_CORE_SRC_TSIZE_0 0x5A004C + +#define mmDMA5_CORE_DST_TSIZE_1 0x5A0054 + +#define mmDMA5_CORE_DST_STRIDE_1 0x5A0058 + +#define mmDMA5_CORE_DST_TSIZE_2 0x5A005C + +#define mmDMA5_CORE_DST_STRIDE_2 0x5A0060 + +#define mmDMA5_CORE_DST_TSIZE_3 0x5A0064 + +#define mmDMA5_CORE_DST_STRIDE_3 0x5A0068 + +#define mmDMA5_CORE_DST_TSIZE_4 0x5A006C + +#define mmDMA5_CORE_DST_STRIDE_4 0x5A0070 + +#define mmDMA5_CORE_DST_TSIZE_0 0x5A0074 + +#define mmDMA5_CORE_COMMIT 0x5A0078 + +#define mmDMA5_CORE_WR_COMP_WDATA 0x5A007C + +#define mmDMA5_CORE_WR_COMP_ADDR_LO 0x5A0080 + +#define mmDMA5_CORE_WR_COMP_ADDR_HI 0x5A0084 + +#define mmDMA5_CORE_WR_COMP_AWUSER_31_11 0x5A0088 + +#define mmDMA5_CORE_TE_NUMROWS 0x5A0094 + +#define mmDMA5_CORE_PROT 0x5A00B8 + +#define mmDMA5_CORE_SECURE_PROPS 0x5A00F0 + +#define mmDMA5_CORE_NON_SECURE_PROPS 0x5A00F4 + +#define mmDMA5_CORE_RD_MAX_OUTSTAND 0x5A0100 + +#define mmDMA5_CORE_RD_MAX_SIZE 0x5A0104 + +#define mmDMA5_CORE_RD_ARCACHE 0x5A0108 + +#define mmDMA5_CORE_RD_ARUSER_31_11 0x5A0110 + +#define mmDMA5_CORE_RD_INFLIGHTS 0x5A0114 + +#define mmDMA5_CORE_WR_MAX_OUTSTAND 0x5A0120 + +#define mmDMA5_CORE_WR_MAX_AWID 0x5A0124 + +#define mmDMA5_CORE_WR_AWCACHE 0x5A0128 + +#define mmDMA5_CORE_WR_AWUSER_31_11 0x5A0130 + +#define mmDMA5_CORE_WR_INFLIGHTS 0x5A0134 + +#define mmDMA5_CORE_RD_RATE_LIM_CFG_0 0x5A0150 + +#define mmDMA5_CORE_RD_RATE_LIM_CFG_1 0x5A0154 + +#define mmDMA5_CORE_WR_RATE_LIM_CFG_0 0x5A0158 + +#define mmDMA5_CORE_WR_RATE_LIM_CFG_1 0x5A015C + +#define mmDMA5_CORE_ERR_CFG 0x5A0160 + +#define mmDMA5_CORE_ERR_CAUSE 0x5A0164 + +#define mmDMA5_CORE_ERRMSG_ADDR_LO 0x5A0170 + +#define mmDMA5_CORE_ERRMSG_ADDR_HI 0x5A0174 + +#define mmDMA5_CORE_ERRMSG_WDATA 0x5A0178 + +#define mmDMA5_CORE_STS0 0x5A0190 + +#define mmDMA5_CORE_STS1 0x5A0194 + +#define mmDMA5_CORE_RD_DBGMEM_ADD 0x5A0200 + +#define mmDMA5_CORE_RD_DBGMEM_DATA_WR 0x5A0204 + +#define mmDMA5_CORE_RD_DBGMEM_DATA_RD 0x5A0208 + +#define mmDMA5_CORE_RD_DBGMEM_CTRL 0x5A020C + +#define mmDMA5_CORE_RD_DBGMEM_RC 0x5A0210 + +#define mmDMA5_CORE_DBG_HBW_AXI_AR_CNT 0x5A0220 + +#define mmDMA5_CORE_DBG_HBW_AXI_AW_CNT 0x5A0224 + +#define mmDMA5_CORE_DBG_LBW_AXI_AW_CNT 0x5A0228 + +#define mmDMA5_CORE_DBG_DESC_CNT 0x5A022C + +#define mmDMA5_CORE_DBG_STS 0x5A0230 + +#define mmDMA5_CORE_DBG_RD_DESC_ID 0x5A0234 + +#define mmDMA5_CORE_DBG_WR_DESC_ID 0x5A0238 + +#endif /* ASIC_REG_DMA5_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h new file mode 100644 index 000000000000..0faea21756c5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma5_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA5_QM_REGS_H_ +#define ASIC_REG_DMA5_QM_REGS_H_ + +/* + ***************************************** + * DMA5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA5_QM_GLBL_CFG0 0x5A8000 + +#define mmDMA5_QM_GLBL_CFG1 0x5A8004 + +#define mmDMA5_QM_GLBL_PROT 0x5A8008 + +#define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C + +#define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A8010 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A8014 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A8018 + +#define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C + +#define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A8020 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A8024 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A8028 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A8030 + +#define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A8034 + +#define mmDMA5_QM_GLBL_STS0 0x5A8038 + +#define mmDMA5_QM_GLBL_STS1_0 0x5A8040 + +#define mmDMA5_QM_GLBL_STS1_1 0x5A8044 + +#define mmDMA5_QM_GLBL_STS1_2 0x5A8048 + +#define mmDMA5_QM_GLBL_STS1_3 0x5A804C + +#define mmDMA5_QM_GLBL_STS1_4 0x5A8050 + +#define mmDMA5_QM_GLBL_MSG_EN_0 0x5A8054 + +#define mmDMA5_QM_GLBL_MSG_EN_1 0x5A8058 + +#define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C + +#define mmDMA5_QM_GLBL_MSG_EN_3 0x5A8060 + +#define mmDMA5_QM_GLBL_MSG_EN_4 0x5A8068 + +#define mmDMA5_QM_PQ_BASE_LO_0 0x5A8070 + +#define mmDMA5_QM_PQ_BASE_LO_1 0x5A8074 + +#define mmDMA5_QM_PQ_BASE_LO_2 0x5A8078 + +#define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C + +#define mmDMA5_QM_PQ_BASE_HI_0 0x5A8080 + +#define mmDMA5_QM_PQ_BASE_HI_1 0x5A8084 + +#define mmDMA5_QM_PQ_BASE_HI_2 0x5A8088 + +#define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C + +#define mmDMA5_QM_PQ_SIZE_0 0x5A8090 + +#define mmDMA5_QM_PQ_SIZE_1 0x5A8094 + +#define mmDMA5_QM_PQ_SIZE_2 0x5A8098 + +#define mmDMA5_QM_PQ_SIZE_3 0x5A809C + +#define mmDMA5_QM_PQ_PI_0 0x5A80A0 + +#define mmDMA5_QM_PQ_PI_1 0x5A80A4 + +#define mmDMA5_QM_PQ_PI_2 0x5A80A8 + +#define mmDMA5_QM_PQ_PI_3 0x5A80AC + +#define mmDMA5_QM_PQ_CI_0 0x5A80B0 + +#define mmDMA5_QM_PQ_CI_1 0x5A80B4 + +#define mmDMA5_QM_PQ_CI_2 0x5A80B8 + +#define mmDMA5_QM_PQ_CI_3 0x5A80BC + +#define mmDMA5_QM_PQ_CFG0_0 0x5A80C0 + +#define mmDMA5_QM_PQ_CFG0_1 0x5A80C4 + +#define mmDMA5_QM_PQ_CFG0_2 0x5A80C8 + +#define mmDMA5_QM_PQ_CFG0_3 0x5A80CC + +#define mmDMA5_QM_PQ_CFG1_0 0x5A80D0 + +#define mmDMA5_QM_PQ_CFG1_1 0x5A80D4 + +#define mmDMA5_QM_PQ_CFG1_2 0x5A80D8 + +#define mmDMA5_QM_PQ_CFG1_3 0x5A80DC + +#define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0 + +#define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4 + +#define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8 + +#define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC + +#define mmDMA5_QM_PQ_STS0_0 0x5A80F0 + +#define mmDMA5_QM_PQ_STS0_1 0x5A80F4 + +#define mmDMA5_QM_PQ_STS0_2 0x5A80F8 + +#define mmDMA5_QM_PQ_STS0_3 0x5A80FC + +#define mmDMA5_QM_PQ_STS1_0 0x5A8100 + +#define mmDMA5_QM_PQ_STS1_1 0x5A8104 + +#define mmDMA5_QM_PQ_STS1_2 0x5A8108 + +#define mmDMA5_QM_PQ_STS1_3 0x5A810C + +#define mmDMA5_QM_CQ_CFG0_0 0x5A8110 + +#define mmDMA5_QM_CQ_CFG0_1 0x5A8114 + +#define mmDMA5_QM_CQ_CFG0_2 0x5A8118 + +#define mmDMA5_QM_CQ_CFG0_3 0x5A811C + +#define mmDMA5_QM_CQ_CFG0_4 0x5A8120 + +#define mmDMA5_QM_CQ_CFG1_0 0x5A8124 + +#define mmDMA5_QM_CQ_CFG1_1 0x5A8128 + +#define mmDMA5_QM_CQ_CFG1_2 0x5A812C + +#define mmDMA5_QM_CQ_CFG1_3 0x5A8130 + +#define mmDMA5_QM_CQ_CFG1_4 0x5A8134 + +#define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138 + +#define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C + +#define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140 + +#define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144 + +#define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148 + +#define mmDMA5_QM_CQ_STS0_0 0x5A814C + +#define mmDMA5_QM_CQ_STS0_1 0x5A8150 + +#define mmDMA5_QM_CQ_STS0_2 0x5A8154 + +#define mmDMA5_QM_CQ_STS0_3 0x5A8158 + +#define mmDMA5_QM_CQ_STS0_4 0x5A815C + +#define mmDMA5_QM_CQ_STS1_0 0x5A8160 + +#define mmDMA5_QM_CQ_STS1_1 0x5A8164 + +#define mmDMA5_QM_CQ_STS1_2 0x5A8168 + +#define mmDMA5_QM_CQ_STS1_3 0x5A816C + +#define mmDMA5_QM_CQ_STS1_4 0x5A8170 + +#define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174 + +#define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178 + +#define mmDMA5_QM_CQ_TSIZE_0 0x5A817C + +#define mmDMA5_QM_CQ_CTL_0 0x5A8180 + +#define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184 + +#define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188 + +#define mmDMA5_QM_CQ_TSIZE_1 0x5A818C + +#define mmDMA5_QM_CQ_CTL_1 0x5A8190 + +#define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194 + +#define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198 + +#define mmDMA5_QM_CQ_TSIZE_2 0x5A819C + +#define mmDMA5_QM_CQ_CTL_2 0x5A81A0 + +#define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4 + +#define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8 + +#define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC + +#define mmDMA5_QM_CQ_CTL_3 0x5A81B0 + +#define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4 + +#define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8 + +#define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC + +#define mmDMA5_QM_CQ_CTL_4 0x5A81C0 + +#define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4 + +#define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8 + +#define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC + +#define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0 + +#define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4 + +#define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8 + +#define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC + +#define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0 + +#define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4 + +#define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8 + +#define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC + +#define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0 + +#define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4 + +#define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8 + +#define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC + +#define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200 + +#define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204 + +#define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208 + +#define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C + +#define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210 + +#define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214 + +#define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218 + +#define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C + +#define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220 + +#define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248 + +#define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270 + +#define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298 + +#define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0 + +#define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4 + +#define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8 + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC + +#define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300 + +#define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304 + +#define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308 + +#define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C + +#define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310 + +#define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314 + +#define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318 + +#define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C + +#define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320 + +#define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324 + +#define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328 + +#define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C + +#define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330 + +#define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334 + +#define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338 + +#define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C + +#define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340 + +#define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344 + +#define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348 + +#define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C + +#define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350 + +#define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354 + +#define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358 + +#define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C + +#define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360 + +#define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364 + +#define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368 + +#define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C + +#define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370 + +#define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374 + +#define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378 + +#define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C + +#define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380 + +#define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384 + +#define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388 + +#define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C + +#define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390 + +#define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394 + +#define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398 + +#define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C + +#define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0 + +#define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4 + +#define mmDMA5_QM_CP_STS_0 0x5A83A8 + +#define mmDMA5_QM_CP_STS_1 0x5A83AC + +#define mmDMA5_QM_CP_STS_2 0x5A83B0 + +#define mmDMA5_QM_CP_STS_3 0x5A83B4 + +#define mmDMA5_QM_CP_STS_4 0x5A83B8 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC + +#define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8 + +#define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC + +#define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8 + +#define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC + +#define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0 + +#define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4 + +#define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8 + +#define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC + +#define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400 + +#define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404 + +#define mmDMA5_QM_CP_DBG_0_0 0x5A8408 + +#define mmDMA5_QM_CP_DBG_0_1 0x5A840C + +#define mmDMA5_QM_CP_DBG_0_2 0x5A8410 + +#define mmDMA5_QM_CP_DBG_0_3 0x5A8414 + +#define mmDMA5_QM_CP_DBG_0_4 0x5A8418 + +#define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C + +#define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420 + +#define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424 + +#define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428 + +#define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C + +#define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430 + +#define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434 + +#define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438 + +#define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C + +#define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440 + +#define mmDMA5_QM_ARB_CFG_0 0x5A8A00 + +#define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C + +#define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10 + +#define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14 + +#define mmDMA5_QM_ARB_CFG_1 0x5A8A18 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98 + +#define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C + +#define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18 + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C + +#define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20 + +#define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28 + +#define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C + +#define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34 + +#define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38 + +#define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C + +#define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44 + +#define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48 + +#define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C + +#define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50 + +#define mmDMA5_QM_ARB_BASE_LO 0x5A8B54 + +#define mmDMA5_QM_ARB_BASE_HI 0x5A8B58 + +#define mmDMA5_QM_ARB_STATE_STS 0x5A8B80 + +#define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84 + +#define mmDMA5_QM_ARB_MSG_STS 0x5A8B88 + +#define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C + +#define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C + +#define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0 + +#define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC + +#define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC + +#define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC + +#define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC + +#define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0 + +#define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4 + +#define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8 + +#define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC + +#define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00 + +#define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04 + +#define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08 + +#define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C + +#define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10 + +#define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14 + +#define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18 + +#define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C + +#define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20 + +#define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24 + +#define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28 + +#define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C + +#define mmDMA5_QM_CGM_CFG 0x5A8C70 + +#define mmDMA5_QM_CGM_STS 0x5A8C74 + +#define mmDMA5_QM_CGM_CFG1 0x5A8C78 + +#define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80 + +#define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84 + +#define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90 + +#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94 + +#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98 + +#define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C + +#define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0 + +#define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4 + +#define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0 + +#define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4 + +#define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8 + +#define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC + +#define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0 + +#define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4 + +#define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8 + +#define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00 + +#endif /* ASIC_REG_DMA5_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h new file mode 100644 index 000000000000..4962c13e2e2e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA6_CORE_REGS_H_ +#define ASIC_REG_DMA6_CORE_REGS_H_ + +/* + ***************************************** + * DMA6_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA6_CORE_CFG_0 0x5C0000 + +#define mmDMA6_CORE_CFG_1 0x5C0004 + +#define mmDMA6_CORE_LBW_MAX_OUTSTAND 0x5C0008 + +#define mmDMA6_CORE_SRC_BASE_LO 0x5C0014 + +#define mmDMA6_CORE_SRC_BASE_HI 0x5C0018 + +#define mmDMA6_CORE_DST_BASE_LO 0x5C001C + +#define mmDMA6_CORE_DST_BASE_HI 0x5C0020 + +#define mmDMA6_CORE_SRC_TSIZE_1 0x5C002C + +#define mmDMA6_CORE_SRC_STRIDE_1 0x5C0030 + +#define mmDMA6_CORE_SRC_TSIZE_2 0x5C0034 + +#define mmDMA6_CORE_SRC_STRIDE_2 0x5C0038 + +#define mmDMA6_CORE_SRC_TSIZE_3 0x5C003C + +#define mmDMA6_CORE_SRC_STRIDE_3 0x5C0040 + +#define mmDMA6_CORE_SRC_TSIZE_4 0x5C0044 + +#define mmDMA6_CORE_SRC_STRIDE_4 0x5C0048 + +#define mmDMA6_CORE_SRC_TSIZE_0 0x5C004C + +#define mmDMA6_CORE_DST_TSIZE_1 0x5C0054 + +#define mmDMA6_CORE_DST_STRIDE_1 0x5C0058 + +#define mmDMA6_CORE_DST_TSIZE_2 0x5C005C + +#define mmDMA6_CORE_DST_STRIDE_2 0x5C0060 + +#define mmDMA6_CORE_DST_TSIZE_3 0x5C0064 + +#define mmDMA6_CORE_DST_STRIDE_3 0x5C0068 + +#define mmDMA6_CORE_DST_TSIZE_4 0x5C006C + +#define mmDMA6_CORE_DST_STRIDE_4 0x5C0070 + +#define mmDMA6_CORE_DST_TSIZE_0 0x5C0074 + +#define mmDMA6_CORE_COMMIT 0x5C0078 + +#define mmDMA6_CORE_WR_COMP_WDATA 0x5C007C + +#define mmDMA6_CORE_WR_COMP_ADDR_LO 0x5C0080 + +#define mmDMA6_CORE_WR_COMP_ADDR_HI 0x5C0084 + +#define mmDMA6_CORE_WR_COMP_AWUSER_31_11 0x5C0088 + +#define mmDMA6_CORE_TE_NUMROWS 0x5C0094 + +#define mmDMA6_CORE_PROT 0x5C00B8 + +#define mmDMA6_CORE_SECURE_PROPS 0x5C00F0 + +#define mmDMA6_CORE_NON_SECURE_PROPS 0x5C00F4 + +#define mmDMA6_CORE_RD_MAX_OUTSTAND 0x5C0100 + +#define mmDMA6_CORE_RD_MAX_SIZE 0x5C0104 + +#define mmDMA6_CORE_RD_ARCACHE 0x5C0108 + +#define mmDMA6_CORE_RD_ARUSER_31_11 0x5C0110 + +#define mmDMA6_CORE_RD_INFLIGHTS 0x5C0114 + +#define mmDMA6_CORE_WR_MAX_OUTSTAND 0x5C0120 + +#define mmDMA6_CORE_WR_MAX_AWID 0x5C0124 + +#define mmDMA6_CORE_WR_AWCACHE 0x5C0128 + +#define mmDMA6_CORE_WR_AWUSER_31_11 0x5C0130 + +#define mmDMA6_CORE_WR_INFLIGHTS 0x5C0134 + +#define mmDMA6_CORE_RD_RATE_LIM_CFG_0 0x5C0150 + +#define mmDMA6_CORE_RD_RATE_LIM_CFG_1 0x5C0154 + +#define mmDMA6_CORE_WR_RATE_LIM_CFG_0 0x5C0158 + +#define mmDMA6_CORE_WR_RATE_LIM_CFG_1 0x5C015C + +#define mmDMA6_CORE_ERR_CFG 0x5C0160 + +#define mmDMA6_CORE_ERR_CAUSE 0x5C0164 + +#define mmDMA6_CORE_ERRMSG_ADDR_LO 0x5C0170 + +#define mmDMA6_CORE_ERRMSG_ADDR_HI 0x5C0174 + +#define mmDMA6_CORE_ERRMSG_WDATA 0x5C0178 + +#define mmDMA6_CORE_STS0 0x5C0190 + +#define mmDMA6_CORE_STS1 0x5C0194 + +#define mmDMA6_CORE_RD_DBGMEM_ADD 0x5C0200 + +#define mmDMA6_CORE_RD_DBGMEM_DATA_WR 0x5C0204 + +#define mmDMA6_CORE_RD_DBGMEM_DATA_RD 0x5C0208 + +#define mmDMA6_CORE_RD_DBGMEM_CTRL 0x5C020C + +#define mmDMA6_CORE_RD_DBGMEM_RC 0x5C0210 + +#define mmDMA6_CORE_DBG_HBW_AXI_AR_CNT 0x5C0220 + +#define mmDMA6_CORE_DBG_HBW_AXI_AW_CNT 0x5C0224 + +#define mmDMA6_CORE_DBG_LBW_AXI_AW_CNT 0x5C0228 + +#define mmDMA6_CORE_DBG_DESC_CNT 0x5C022C + +#define mmDMA6_CORE_DBG_STS 0x5C0230 + +#define mmDMA6_CORE_DBG_RD_DESC_ID 0x5C0234 + +#define mmDMA6_CORE_DBG_WR_DESC_ID 0x5C0238 + +#endif /* ASIC_REG_DMA6_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h new file mode 100644 index 000000000000..af87adb94c94 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma6_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA6_QM_REGS_H_ +#define ASIC_REG_DMA6_QM_REGS_H_ + +/* + ***************************************** + * DMA6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA6_QM_GLBL_CFG0 0x5C8000 + +#define mmDMA6_QM_GLBL_CFG1 0x5C8004 + +#define mmDMA6_QM_GLBL_PROT 0x5C8008 + +#define mmDMA6_QM_GLBL_ERR_CFG 0x5C800C + +#define mmDMA6_QM_GLBL_SECURE_PROPS_0 0x5C8010 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_1 0x5C8014 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_2 0x5C8018 + +#define mmDMA6_QM_GLBL_SECURE_PROPS_3 0x5C801C + +#define mmDMA6_QM_GLBL_SECURE_PROPS_4 0x5C8020 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 0x5C8024 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 0x5C8028 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 0x5C802C + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 0x5C8030 + +#define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 0x5C8034 + +#define mmDMA6_QM_GLBL_STS0 0x5C8038 + +#define mmDMA6_QM_GLBL_STS1_0 0x5C8040 + +#define mmDMA6_QM_GLBL_STS1_1 0x5C8044 + +#define mmDMA6_QM_GLBL_STS1_2 0x5C8048 + +#define mmDMA6_QM_GLBL_STS1_3 0x5C804C + +#define mmDMA6_QM_GLBL_STS1_4 0x5C8050 + +#define mmDMA6_QM_GLBL_MSG_EN_0 0x5C8054 + +#define mmDMA6_QM_GLBL_MSG_EN_1 0x5C8058 + +#define mmDMA6_QM_GLBL_MSG_EN_2 0x5C805C + +#define mmDMA6_QM_GLBL_MSG_EN_3 0x5C8060 + +#define mmDMA6_QM_GLBL_MSG_EN_4 0x5C8068 + +#define mmDMA6_QM_PQ_BASE_LO_0 0x5C8070 + +#define mmDMA6_QM_PQ_BASE_LO_1 0x5C8074 + +#define mmDMA6_QM_PQ_BASE_LO_2 0x5C8078 + +#define mmDMA6_QM_PQ_BASE_LO_3 0x5C807C + +#define mmDMA6_QM_PQ_BASE_HI_0 0x5C8080 + +#define mmDMA6_QM_PQ_BASE_HI_1 0x5C8084 + +#define mmDMA6_QM_PQ_BASE_HI_2 0x5C8088 + +#define mmDMA6_QM_PQ_BASE_HI_3 0x5C808C + +#define mmDMA6_QM_PQ_SIZE_0 0x5C8090 + +#define mmDMA6_QM_PQ_SIZE_1 0x5C8094 + +#define mmDMA6_QM_PQ_SIZE_2 0x5C8098 + +#define mmDMA6_QM_PQ_SIZE_3 0x5C809C + +#define mmDMA6_QM_PQ_PI_0 0x5C80A0 + +#define mmDMA6_QM_PQ_PI_1 0x5C80A4 + +#define mmDMA6_QM_PQ_PI_2 0x5C80A8 + +#define mmDMA6_QM_PQ_PI_3 0x5C80AC + +#define mmDMA6_QM_PQ_CI_0 0x5C80B0 + +#define mmDMA6_QM_PQ_CI_1 0x5C80B4 + +#define mmDMA6_QM_PQ_CI_2 0x5C80B8 + +#define mmDMA6_QM_PQ_CI_3 0x5C80BC + +#define mmDMA6_QM_PQ_CFG0_0 0x5C80C0 + +#define mmDMA6_QM_PQ_CFG0_1 0x5C80C4 + +#define mmDMA6_QM_PQ_CFG0_2 0x5C80C8 + +#define mmDMA6_QM_PQ_CFG0_3 0x5C80CC + +#define mmDMA6_QM_PQ_CFG1_0 0x5C80D0 + +#define mmDMA6_QM_PQ_CFG1_1 0x5C80D4 + +#define mmDMA6_QM_PQ_CFG1_2 0x5C80D8 + +#define mmDMA6_QM_PQ_CFG1_3 0x5C80DC + +#define mmDMA6_QM_PQ_ARUSER_31_11_0 0x5C80E0 + +#define mmDMA6_QM_PQ_ARUSER_31_11_1 0x5C80E4 + +#define mmDMA6_QM_PQ_ARUSER_31_11_2 0x5C80E8 + +#define mmDMA6_QM_PQ_ARUSER_31_11_3 0x5C80EC + +#define mmDMA6_QM_PQ_STS0_0 0x5C80F0 + +#define mmDMA6_QM_PQ_STS0_1 0x5C80F4 + +#define mmDMA6_QM_PQ_STS0_2 0x5C80F8 + +#define mmDMA6_QM_PQ_STS0_3 0x5C80FC + +#define mmDMA6_QM_PQ_STS1_0 0x5C8100 + +#define mmDMA6_QM_PQ_STS1_1 0x5C8104 + +#define mmDMA6_QM_PQ_STS1_2 0x5C8108 + +#define mmDMA6_QM_PQ_STS1_3 0x5C810C + +#define mmDMA6_QM_CQ_CFG0_0 0x5C8110 + +#define mmDMA6_QM_CQ_CFG0_1 0x5C8114 + +#define mmDMA6_QM_CQ_CFG0_2 0x5C8118 + +#define mmDMA6_QM_CQ_CFG0_3 0x5C811C + +#define mmDMA6_QM_CQ_CFG0_4 0x5C8120 + +#define mmDMA6_QM_CQ_CFG1_0 0x5C8124 + +#define mmDMA6_QM_CQ_CFG1_1 0x5C8128 + +#define mmDMA6_QM_CQ_CFG1_2 0x5C812C + +#define mmDMA6_QM_CQ_CFG1_3 0x5C8130 + +#define mmDMA6_QM_CQ_CFG1_4 0x5C8134 + +#define mmDMA6_QM_CQ_ARUSER_31_11_0 0x5C8138 + +#define mmDMA6_QM_CQ_ARUSER_31_11_1 0x5C813C + +#define mmDMA6_QM_CQ_ARUSER_31_11_2 0x5C8140 + +#define mmDMA6_QM_CQ_ARUSER_31_11_3 0x5C8144 + +#define mmDMA6_QM_CQ_ARUSER_31_11_4 0x5C8148 + +#define mmDMA6_QM_CQ_STS0_0 0x5C814C + +#define mmDMA6_QM_CQ_STS0_1 0x5C8150 + +#define mmDMA6_QM_CQ_STS0_2 0x5C8154 + +#define mmDMA6_QM_CQ_STS0_3 0x5C8158 + +#define mmDMA6_QM_CQ_STS0_4 0x5C815C + +#define mmDMA6_QM_CQ_STS1_0 0x5C8160 + +#define mmDMA6_QM_CQ_STS1_1 0x5C8164 + +#define mmDMA6_QM_CQ_STS1_2 0x5C8168 + +#define mmDMA6_QM_CQ_STS1_3 0x5C816C + +#define mmDMA6_QM_CQ_STS1_4 0x5C8170 + +#define mmDMA6_QM_CQ_PTR_LO_0 0x5C8174 + +#define mmDMA6_QM_CQ_PTR_HI_0 0x5C8178 + +#define mmDMA6_QM_CQ_TSIZE_0 0x5C817C + +#define mmDMA6_QM_CQ_CTL_0 0x5C8180 + +#define mmDMA6_QM_CQ_PTR_LO_1 0x5C8184 + +#define mmDMA6_QM_CQ_PTR_HI_1 0x5C8188 + +#define mmDMA6_QM_CQ_TSIZE_1 0x5C818C + +#define mmDMA6_QM_CQ_CTL_1 0x5C8190 + +#define mmDMA6_QM_CQ_PTR_LO_2 0x5C8194 + +#define mmDMA6_QM_CQ_PTR_HI_2 0x5C8198 + +#define mmDMA6_QM_CQ_TSIZE_2 0x5C819C + +#define mmDMA6_QM_CQ_CTL_2 0x5C81A0 + +#define mmDMA6_QM_CQ_PTR_LO_3 0x5C81A4 + +#define mmDMA6_QM_CQ_PTR_HI_3 0x5C81A8 + +#define mmDMA6_QM_CQ_TSIZE_3 0x5C81AC + +#define mmDMA6_QM_CQ_CTL_3 0x5C81B0 + +#define mmDMA6_QM_CQ_PTR_LO_4 0x5C81B4 + +#define mmDMA6_QM_CQ_PTR_HI_4 0x5C81B8 + +#define mmDMA6_QM_CQ_TSIZE_4 0x5C81BC + +#define mmDMA6_QM_CQ_CTL_4 0x5C81C0 + +#define mmDMA6_QM_CQ_PTR_LO_STS_0 0x5C81C4 + +#define mmDMA6_QM_CQ_PTR_LO_STS_1 0x5C81C8 + +#define mmDMA6_QM_CQ_PTR_LO_STS_2 0x5C81CC + +#define mmDMA6_QM_CQ_PTR_LO_STS_3 0x5C81D0 + +#define mmDMA6_QM_CQ_PTR_LO_STS_4 0x5C81D4 + +#define mmDMA6_QM_CQ_PTR_HI_STS_0 0x5C81D8 + +#define mmDMA6_QM_CQ_PTR_HI_STS_1 0x5C81DC + +#define mmDMA6_QM_CQ_PTR_HI_STS_2 0x5C81E0 + +#define mmDMA6_QM_CQ_PTR_HI_STS_3 0x5C81E4 + +#define mmDMA6_QM_CQ_PTR_HI_STS_4 0x5C81E8 + +#define mmDMA6_QM_CQ_TSIZE_STS_0 0x5C81EC + +#define mmDMA6_QM_CQ_TSIZE_STS_1 0x5C81F0 + +#define mmDMA6_QM_CQ_TSIZE_STS_2 0x5C81F4 + +#define mmDMA6_QM_CQ_TSIZE_STS_3 0x5C81F8 + +#define mmDMA6_QM_CQ_TSIZE_STS_4 0x5C81FC + +#define mmDMA6_QM_CQ_CTL_STS_0 0x5C8200 + +#define mmDMA6_QM_CQ_CTL_STS_1 0x5C8204 + +#define mmDMA6_QM_CQ_CTL_STS_2 0x5C8208 + +#define mmDMA6_QM_CQ_CTL_STS_3 0x5C820C + +#define mmDMA6_QM_CQ_CTL_STS_4 0x5C8210 + +#define mmDMA6_QM_CQ_IFIFO_CNT_0 0x5C8214 + +#define mmDMA6_QM_CQ_IFIFO_CNT_1 0x5C8218 + +#define mmDMA6_QM_CQ_IFIFO_CNT_2 0x5C821C + +#define mmDMA6_QM_CQ_IFIFO_CNT_3 0x5C8220 + +#define mmDMA6_QM_CQ_IFIFO_CNT_4 0x5C8224 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 0x5C8228 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 0x5C822C + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 0x5C8230 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 0x5C8234 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 0x5C8238 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 0x5C823C + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 0x5C8240 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 0x5C8244 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 0x5C8248 + +#define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 0x5C824C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 0x5C8250 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 0x5C8254 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 0x5C8258 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 0x5C825C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 0x5C8260 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 0x5C8264 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 0x5C8268 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 0x5C826C + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 0x5C8270 + +#define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 0x5C8274 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 0x5C8278 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 0x5C827C + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 0x5C8280 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 0x5C8284 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 0x5C8288 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 0x5C828C + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 0x5C8290 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 0x5C8294 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 0x5C8298 + +#define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 0x5C829C + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 0x5C82A0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 0x5C82A4 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 0x5C82A8 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 0x5C82AC + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 0x5C82B0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 0x5C82B4 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 0x5C82B8 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 0x5C82BC + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 0x5C82C0 + +#define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 0x5C82C4 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 0x5C82C8 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 0x5C82CC + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 0x5C82D0 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 0x5C82D4 + +#define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 0x5C82D8 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5C82E0 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5C82E4 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5C82E8 + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5C82EC + +#define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5C82F0 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5C82F4 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5C82F8 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5C82FC + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5C8300 + +#define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5C8304 + +#define mmDMA6_QM_CP_FENCE0_RDATA_0 0x5C8308 + +#define mmDMA6_QM_CP_FENCE0_RDATA_1 0x5C830C + +#define mmDMA6_QM_CP_FENCE0_RDATA_2 0x5C8310 + +#define mmDMA6_QM_CP_FENCE0_RDATA_3 0x5C8314 + +#define mmDMA6_QM_CP_FENCE0_RDATA_4 0x5C8318 + +#define mmDMA6_QM_CP_FENCE1_RDATA_0 0x5C831C + +#define mmDMA6_QM_CP_FENCE1_RDATA_1 0x5C8320 + +#define mmDMA6_QM_CP_FENCE1_RDATA_2 0x5C8324 + +#define mmDMA6_QM_CP_FENCE1_RDATA_3 0x5C8328 + +#define mmDMA6_QM_CP_FENCE1_RDATA_4 0x5C832C + +#define mmDMA6_QM_CP_FENCE2_RDATA_0 0x5C8330 + +#define mmDMA6_QM_CP_FENCE2_RDATA_1 0x5C8334 + +#define mmDMA6_QM_CP_FENCE2_RDATA_2 0x5C8338 + +#define mmDMA6_QM_CP_FENCE2_RDATA_3 0x5C833C + +#define mmDMA6_QM_CP_FENCE2_RDATA_4 0x5C8340 + +#define mmDMA6_QM_CP_FENCE3_RDATA_0 0x5C8344 + +#define mmDMA6_QM_CP_FENCE3_RDATA_1 0x5C8348 + +#define mmDMA6_QM_CP_FENCE3_RDATA_2 0x5C834C + +#define mmDMA6_QM_CP_FENCE3_RDATA_3 0x5C8350 + +#define mmDMA6_QM_CP_FENCE3_RDATA_4 0x5C8354 + +#define mmDMA6_QM_CP_FENCE0_CNT_0 0x5C8358 + +#define mmDMA6_QM_CP_FENCE0_CNT_1 0x5C835C + +#define mmDMA6_QM_CP_FENCE0_CNT_2 0x5C8360 + +#define mmDMA6_QM_CP_FENCE0_CNT_3 0x5C8364 + +#define mmDMA6_QM_CP_FENCE0_CNT_4 0x5C8368 + +#define mmDMA6_QM_CP_FENCE1_CNT_0 0x5C836C + +#define mmDMA6_QM_CP_FENCE1_CNT_1 0x5C8370 + +#define mmDMA6_QM_CP_FENCE1_CNT_2 0x5C8374 + +#define mmDMA6_QM_CP_FENCE1_CNT_3 0x5C8378 + +#define mmDMA6_QM_CP_FENCE1_CNT_4 0x5C837C + +#define mmDMA6_QM_CP_FENCE2_CNT_0 0x5C8380 + +#define mmDMA6_QM_CP_FENCE2_CNT_1 0x5C8384 + +#define mmDMA6_QM_CP_FENCE2_CNT_2 0x5C8388 + +#define mmDMA6_QM_CP_FENCE2_CNT_3 0x5C838C + +#define mmDMA6_QM_CP_FENCE2_CNT_4 0x5C8390 + +#define mmDMA6_QM_CP_FENCE3_CNT_0 0x5C8394 + +#define mmDMA6_QM_CP_FENCE3_CNT_1 0x5C8398 + +#define mmDMA6_QM_CP_FENCE3_CNT_2 0x5C839C + +#define mmDMA6_QM_CP_FENCE3_CNT_3 0x5C83A0 + +#define mmDMA6_QM_CP_FENCE3_CNT_4 0x5C83A4 + +#define mmDMA6_QM_CP_STS_0 0x5C83A8 + +#define mmDMA6_QM_CP_STS_1 0x5C83AC + +#define mmDMA6_QM_CP_STS_2 0x5C83B0 + +#define mmDMA6_QM_CP_STS_3 0x5C83B4 + +#define mmDMA6_QM_CP_STS_4 0x5C83B8 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_0 0x5C83BC + +#define mmDMA6_QM_CP_CURRENT_INST_LO_1 0x5C83C0 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_2 0x5C83C4 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_3 0x5C83C8 + +#define mmDMA6_QM_CP_CURRENT_INST_LO_4 0x5C83CC + +#define mmDMA6_QM_CP_CURRENT_INST_HI_0 0x5C83D0 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_1 0x5C83D4 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_2 0x5C83D8 + +#define mmDMA6_QM_CP_CURRENT_INST_HI_3 0x5C83DC + +#define mmDMA6_QM_CP_CURRENT_INST_HI_4 0x5C83E0 + +#define mmDMA6_QM_CP_BARRIER_CFG_0 0x5C83F4 + +#define mmDMA6_QM_CP_BARRIER_CFG_1 0x5C83F8 + +#define mmDMA6_QM_CP_BARRIER_CFG_2 0x5C83FC + +#define mmDMA6_QM_CP_BARRIER_CFG_3 0x5C8400 + +#define mmDMA6_QM_CP_BARRIER_CFG_4 0x5C8404 + +#define mmDMA6_QM_CP_DBG_0_0 0x5C8408 + +#define mmDMA6_QM_CP_DBG_0_1 0x5C840C + +#define mmDMA6_QM_CP_DBG_0_2 0x5C8410 + +#define mmDMA6_QM_CP_DBG_0_3 0x5C8414 + +#define mmDMA6_QM_CP_DBG_0_4 0x5C8418 + +#define mmDMA6_QM_CP_ARUSER_31_11_0 0x5C841C + +#define mmDMA6_QM_CP_ARUSER_31_11_1 0x5C8420 + +#define mmDMA6_QM_CP_ARUSER_31_11_2 0x5C8424 + +#define mmDMA6_QM_CP_ARUSER_31_11_3 0x5C8428 + +#define mmDMA6_QM_CP_ARUSER_31_11_4 0x5C842C + +#define mmDMA6_QM_CP_AWUSER_31_11_0 0x5C8430 + +#define mmDMA6_QM_CP_AWUSER_31_11_1 0x5C8434 + +#define mmDMA6_QM_CP_AWUSER_31_11_2 0x5C8438 + +#define mmDMA6_QM_CP_AWUSER_31_11_3 0x5C843C + +#define mmDMA6_QM_CP_AWUSER_31_11_4 0x5C8440 + +#define mmDMA6_QM_ARB_CFG_0 0x5C8A00 + +#define mmDMA6_QM_ARB_CHOISE_Q_PUSH 0x5C8A04 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_0 0x5C8A08 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_1 0x5C8A0C + +#define mmDMA6_QM_ARB_WRR_WEIGHT_2 0x5C8A10 + +#define mmDMA6_QM_ARB_WRR_WEIGHT_3 0x5C8A14 + +#define mmDMA6_QM_ARB_CFG_1 0x5C8A18 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_0 0x5C8A20 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_1 0x5C8A24 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_2 0x5C8A28 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_3 0x5C8A2C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_4 0x5C8A30 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_5 0x5C8A34 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_6 0x5C8A38 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_7 0x5C8A3C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_8 0x5C8A40 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_9 0x5C8A44 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_10 0x5C8A48 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_11 0x5C8A4C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_12 0x5C8A50 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_13 0x5C8A54 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_14 0x5C8A58 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_15 0x5C8A5C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_16 0x5C8A60 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_17 0x5C8A64 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_18 0x5C8A68 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_19 0x5C8A6C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_20 0x5C8A70 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_21 0x5C8A74 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_22 0x5C8A78 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_23 0x5C8A7C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_24 0x5C8A80 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_25 0x5C8A84 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_26 0x5C8A88 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_27 0x5C8A8C + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_28 0x5C8A90 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_29 0x5C8A94 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_30 0x5C8A98 + +#define mmDMA6_QM_ARB_MST_AVAIL_CRED_31 0x5C8A9C + +#define mmDMA6_QM_ARB_MST_CRED_INC 0x5C8AA0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5C8AA4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5C8AA8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5C8AAC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5C8AB0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5C8AB4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5C8AB8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5C8ABC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5C8AC0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5C8AC4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5C8AC8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5C8ACC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5C8AD0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5C8AD4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5C8AD8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5C8ADC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5C8AE0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5C8AE4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5C8AE8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5C8AEC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5C8AF0 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5C8AF4 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5C8AF8 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5C8AFC + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5C8B00 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5C8B04 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5C8B08 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5C8B0C + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5C8B10 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5C8B14 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5C8B18 + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5C8B1C + +#define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5C8B20 + +#define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5C8B28 + +#define mmDMA6_QM_ARB_MST_SLAVE_EN 0x5C8B2C + +#define mmDMA6_QM_ARB_MST_QUIET_PER 0x5C8B34 + +#define mmDMA6_QM_ARB_SLV_CHOISE_WDT 0x5C8B38 + +#define mmDMA6_QM_ARB_SLV_ID 0x5C8B3C + +#define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT 0x5C8B44 + +#define mmDMA6_QM_ARB_MSG_AWUSER_31_11 0x5C8B48 + +#define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP 0x5C8B4C + +#define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5C8B50 + +#define mmDMA6_QM_ARB_BASE_LO 0x5C8B54 + +#define mmDMA6_QM_ARB_BASE_HI 0x5C8B58 + +#define mmDMA6_QM_ARB_STATE_STS 0x5C8B80 + +#define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS 0x5C8B84 + +#define mmDMA6_QM_ARB_MSG_STS 0x5C8B88 + +#define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD 0x5C8B8C + +#define mmDMA6_QM_ARB_ERR_CAUSE 0x5C8B9C + +#define mmDMA6_QM_ARB_ERR_MSG_EN 0x5C8BA0 + +#define mmDMA6_QM_ARB_ERR_STS_DRP 0x5C8BA8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_0 0x5C8BB0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_1 0x5C8BB4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_2 0x5C8BB8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_3 0x5C8BBC + +#define mmDMA6_QM_ARB_MST_CRED_STS_4 0x5C8BC0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_5 0x5C8BC4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_6 0x5C8BC8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_7 0x5C8BCC + +#define mmDMA6_QM_ARB_MST_CRED_STS_8 0x5C8BD0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_9 0x5C8BD4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_10 0x5C8BD8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_11 0x5C8BDC + +#define mmDMA6_QM_ARB_MST_CRED_STS_12 0x5C8BE0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_13 0x5C8BE4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_14 0x5C8BE8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_15 0x5C8BEC + +#define mmDMA6_QM_ARB_MST_CRED_STS_16 0x5C8BF0 + +#define mmDMA6_QM_ARB_MST_CRED_STS_17 0x5C8BF4 + +#define mmDMA6_QM_ARB_MST_CRED_STS_18 0x5C8BF8 + +#define mmDMA6_QM_ARB_MST_CRED_STS_19 0x5C8BFC + +#define mmDMA6_QM_ARB_MST_CRED_STS_20 0x5C8C00 + +#define mmDMA6_QM_ARB_MST_CRED_STS_21 0x5C8C04 + +#define mmDMA6_QM_ARB_MST_CRED_STS_22 0x5C8C08 + +#define mmDMA6_QM_ARB_MST_CRED_STS_23 0x5C8C0C + +#define mmDMA6_QM_ARB_MST_CRED_STS_24 0x5C8C10 + +#define mmDMA6_QM_ARB_MST_CRED_STS_25 0x5C8C14 + +#define mmDMA6_QM_ARB_MST_CRED_STS_26 0x5C8C18 + +#define mmDMA6_QM_ARB_MST_CRED_STS_27 0x5C8C1C + +#define mmDMA6_QM_ARB_MST_CRED_STS_28 0x5C8C20 + +#define mmDMA6_QM_ARB_MST_CRED_STS_29 0x5C8C24 + +#define mmDMA6_QM_ARB_MST_CRED_STS_30 0x5C8C28 + +#define mmDMA6_QM_ARB_MST_CRED_STS_31 0x5C8C2C + +#define mmDMA6_QM_CGM_CFG 0x5C8C70 + +#define mmDMA6_QM_CGM_STS 0x5C8C74 + +#define mmDMA6_QM_CGM_CFG1 0x5C8C78 + +#define mmDMA6_QM_LOCAL_RANGE_BASE 0x5C8C80 + +#define mmDMA6_QM_LOCAL_RANGE_SIZE 0x5C8C84 + +#define mmDMA6_QM_CSMR_STRICT_PRIO_CFG 0x5C8C90 + +#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 0x5C8C94 + +#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 0x5C8C98 + +#define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 0x5C8C9C + +#define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 0x5C8CA0 + +#define mmDMA6_QM_GLBL_AXCACHE 0x5C8CA4 + +#define mmDMA6_QM_IND_GW_APB_CFG 0x5C8CB0 + +#define mmDMA6_QM_IND_GW_APB_WDATA 0x5C8CB4 + +#define mmDMA6_QM_IND_GW_APB_RDATA 0x5C8CB8 + +#define mmDMA6_QM_IND_GW_APB_STATUS 0x5C8CBC + +#define mmDMA6_QM_GLBL_ERR_ADDR_LO 0x5C8CD0 + +#define mmDMA6_QM_GLBL_ERR_ADDR_HI 0x5C8CD4 + +#define mmDMA6_QM_GLBL_ERR_WDATA 0x5C8CD8 + +#define mmDMA6_QM_GLBL_MEM_INIT_BUSY 0x5C8D00 + +#endif /* ASIC_REG_DMA6_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h new file mode 100644 index 000000000000..8dd705d20195 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_core_regs.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA7_CORE_REGS_H_ +#define ASIC_REG_DMA7_CORE_REGS_H_ + +/* + ***************************************** + * DMA7_CORE (Prototype: DMA_CORE) + ***************************************** + */ + +#define mmDMA7_CORE_CFG_0 0x5E0000 + +#define mmDMA7_CORE_CFG_1 0x5E0004 + +#define mmDMA7_CORE_LBW_MAX_OUTSTAND 0x5E0008 + +#define mmDMA7_CORE_SRC_BASE_LO 0x5E0014 + +#define mmDMA7_CORE_SRC_BASE_HI 0x5E0018 + +#define mmDMA7_CORE_DST_BASE_LO 0x5E001C + +#define mmDMA7_CORE_DST_BASE_HI 0x5E0020 + +#define mmDMA7_CORE_SRC_TSIZE_1 0x5E002C + +#define mmDMA7_CORE_SRC_STRIDE_1 0x5E0030 + +#define mmDMA7_CORE_SRC_TSIZE_2 0x5E0034 + +#define mmDMA7_CORE_SRC_STRIDE_2 0x5E0038 + +#define mmDMA7_CORE_SRC_TSIZE_3 0x5E003C + +#define mmDMA7_CORE_SRC_STRIDE_3 0x5E0040 + +#define mmDMA7_CORE_SRC_TSIZE_4 0x5E0044 + +#define mmDMA7_CORE_SRC_STRIDE_4 0x5E0048 + +#define mmDMA7_CORE_SRC_TSIZE_0 0x5E004C + +#define mmDMA7_CORE_DST_TSIZE_1 0x5E0054 + +#define mmDMA7_CORE_DST_STRIDE_1 0x5E0058 + +#define mmDMA7_CORE_DST_TSIZE_2 0x5E005C + +#define mmDMA7_CORE_DST_STRIDE_2 0x5E0060 + +#define mmDMA7_CORE_DST_TSIZE_3 0x5E0064 + +#define mmDMA7_CORE_DST_STRIDE_3 0x5E0068 + +#define mmDMA7_CORE_DST_TSIZE_4 0x5E006C + +#define mmDMA7_CORE_DST_STRIDE_4 0x5E0070 + +#define mmDMA7_CORE_DST_TSIZE_0 0x5E0074 + +#define mmDMA7_CORE_COMMIT 0x5E0078 + +#define mmDMA7_CORE_WR_COMP_WDATA 0x5E007C + +#define mmDMA7_CORE_WR_COMP_ADDR_LO 0x5E0080 + +#define mmDMA7_CORE_WR_COMP_ADDR_HI 0x5E0084 + +#define mmDMA7_CORE_WR_COMP_AWUSER_31_11 0x5E0088 + +#define mmDMA7_CORE_TE_NUMROWS 0x5E0094 + +#define mmDMA7_CORE_PROT 0x5E00B8 + +#define mmDMA7_CORE_SECURE_PROPS 0x5E00F0 + +#define mmDMA7_CORE_NON_SECURE_PROPS 0x5E00F4 + +#define mmDMA7_CORE_RD_MAX_OUTSTAND 0x5E0100 + +#define mmDMA7_CORE_RD_MAX_SIZE 0x5E0104 + +#define mmDMA7_CORE_RD_ARCACHE 0x5E0108 + +#define mmDMA7_CORE_RD_ARUSER_31_11 0x5E0110 + +#define mmDMA7_CORE_RD_INFLIGHTS 0x5E0114 + +#define mmDMA7_CORE_WR_MAX_OUTSTAND 0x5E0120 + +#define mmDMA7_CORE_WR_MAX_AWID 0x5E0124 + +#define mmDMA7_CORE_WR_AWCACHE 0x5E0128 + +#define mmDMA7_CORE_WR_AWUSER_31_11 0x5E0130 + +#define mmDMA7_CORE_WR_INFLIGHTS 0x5E0134 + +#define mmDMA7_CORE_RD_RATE_LIM_CFG_0 0x5E0150 + +#define mmDMA7_CORE_RD_RATE_LIM_CFG_1 0x5E0154 + +#define mmDMA7_CORE_WR_RATE_LIM_CFG_0 0x5E0158 + +#define mmDMA7_CORE_WR_RATE_LIM_CFG_1 0x5E015C + +#define mmDMA7_CORE_ERR_CFG 0x5E0160 + +#define mmDMA7_CORE_ERR_CAUSE 0x5E0164 + +#define mmDMA7_CORE_ERRMSG_ADDR_LO 0x5E0170 + +#define mmDMA7_CORE_ERRMSG_ADDR_HI 0x5E0174 + +#define mmDMA7_CORE_ERRMSG_WDATA 0x5E0178 + +#define mmDMA7_CORE_STS0 0x5E0190 + +#define mmDMA7_CORE_STS1 0x5E0194 + +#define mmDMA7_CORE_RD_DBGMEM_ADD 0x5E0200 + +#define mmDMA7_CORE_RD_DBGMEM_DATA_WR 0x5E0204 + +#define mmDMA7_CORE_RD_DBGMEM_DATA_RD 0x5E0208 + +#define mmDMA7_CORE_RD_DBGMEM_CTRL 0x5E020C + +#define mmDMA7_CORE_RD_DBGMEM_RC 0x5E0210 + +#define mmDMA7_CORE_DBG_HBW_AXI_AR_CNT 0x5E0220 + +#define mmDMA7_CORE_DBG_HBW_AXI_AW_CNT 0x5E0224 + +#define mmDMA7_CORE_DBG_LBW_AXI_AW_CNT 0x5E0228 + +#define mmDMA7_CORE_DBG_DESC_CNT 0x5E022C + +#define mmDMA7_CORE_DBG_STS 0x5E0230 + +#define mmDMA7_CORE_DBG_RD_DESC_ID 0x5E0234 + +#define mmDMA7_CORE_DBG_WR_DESC_ID 0x5E0238 + +#endif /* ASIC_REG_DMA7_CORE_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h new file mode 100644 index 000000000000..d6c631f63e3e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma7_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA7_QM_REGS_H_ +#define ASIC_REG_DMA7_QM_REGS_H_ + +/* + ***************************************** + * DMA7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmDMA7_QM_GLBL_CFG0 0x5E8000 + +#define mmDMA7_QM_GLBL_CFG1 0x5E8004 + +#define mmDMA7_QM_GLBL_PROT 0x5E8008 + +#define mmDMA7_QM_GLBL_ERR_CFG 0x5E800C + +#define mmDMA7_QM_GLBL_SECURE_PROPS_0 0x5E8010 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_1 0x5E8014 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_2 0x5E8018 + +#define mmDMA7_QM_GLBL_SECURE_PROPS_3 0x5E801C + +#define mmDMA7_QM_GLBL_SECURE_PROPS_4 0x5E8020 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_0 0x5E8024 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_1 0x5E8028 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_2 0x5E802C + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_3 0x5E8030 + +#define mmDMA7_QM_GLBL_NON_SECURE_PROPS_4 0x5E8034 + +#define mmDMA7_QM_GLBL_STS0 0x5E8038 + +#define mmDMA7_QM_GLBL_STS1_0 0x5E8040 + +#define mmDMA7_QM_GLBL_STS1_1 0x5E8044 + +#define mmDMA7_QM_GLBL_STS1_2 0x5E8048 + +#define mmDMA7_QM_GLBL_STS1_3 0x5E804C + +#define mmDMA7_QM_GLBL_STS1_4 0x5E8050 + +#define mmDMA7_QM_GLBL_MSG_EN_0 0x5E8054 + +#define mmDMA7_QM_GLBL_MSG_EN_1 0x5E8058 + +#define mmDMA7_QM_GLBL_MSG_EN_2 0x5E805C + +#define mmDMA7_QM_GLBL_MSG_EN_3 0x5E8060 + +#define mmDMA7_QM_GLBL_MSG_EN_4 0x5E8068 + +#define mmDMA7_QM_PQ_BASE_LO_0 0x5E8070 + +#define mmDMA7_QM_PQ_BASE_LO_1 0x5E8074 + +#define mmDMA7_QM_PQ_BASE_LO_2 0x5E8078 + +#define mmDMA7_QM_PQ_BASE_LO_3 0x5E807C + +#define mmDMA7_QM_PQ_BASE_HI_0 0x5E8080 + +#define mmDMA7_QM_PQ_BASE_HI_1 0x5E8084 + +#define mmDMA7_QM_PQ_BASE_HI_2 0x5E8088 + +#define mmDMA7_QM_PQ_BASE_HI_3 0x5E808C + +#define mmDMA7_QM_PQ_SIZE_0 0x5E8090 + +#define mmDMA7_QM_PQ_SIZE_1 0x5E8094 + +#define mmDMA7_QM_PQ_SIZE_2 0x5E8098 + +#define mmDMA7_QM_PQ_SIZE_3 0x5E809C + +#define mmDMA7_QM_PQ_PI_0 0x5E80A0 + +#define mmDMA7_QM_PQ_PI_1 0x5E80A4 + +#define mmDMA7_QM_PQ_PI_2 0x5E80A8 + +#define mmDMA7_QM_PQ_PI_3 0x5E80AC + +#define mmDMA7_QM_PQ_CI_0 0x5E80B0 + +#define mmDMA7_QM_PQ_CI_1 0x5E80B4 + +#define mmDMA7_QM_PQ_CI_2 0x5E80B8 + +#define mmDMA7_QM_PQ_CI_3 0x5E80BC + +#define mmDMA7_QM_PQ_CFG0_0 0x5E80C0 + +#define mmDMA7_QM_PQ_CFG0_1 0x5E80C4 + +#define mmDMA7_QM_PQ_CFG0_2 0x5E80C8 + +#define mmDMA7_QM_PQ_CFG0_3 0x5E80CC + +#define mmDMA7_QM_PQ_CFG1_0 0x5E80D0 + +#define mmDMA7_QM_PQ_CFG1_1 0x5E80D4 + +#define mmDMA7_QM_PQ_CFG1_2 0x5E80D8 + +#define mmDMA7_QM_PQ_CFG1_3 0x5E80DC + +#define mmDMA7_QM_PQ_ARUSER_31_11_0 0x5E80E0 + +#define mmDMA7_QM_PQ_ARUSER_31_11_1 0x5E80E4 + +#define mmDMA7_QM_PQ_ARUSER_31_11_2 0x5E80E8 + +#define mmDMA7_QM_PQ_ARUSER_31_11_3 0x5E80EC + +#define mmDMA7_QM_PQ_STS0_0 0x5E80F0 + +#define mmDMA7_QM_PQ_STS0_1 0x5E80F4 + +#define mmDMA7_QM_PQ_STS0_2 0x5E80F8 + +#define mmDMA7_QM_PQ_STS0_3 0x5E80FC + +#define mmDMA7_QM_PQ_STS1_0 0x5E8100 + +#define mmDMA7_QM_PQ_STS1_1 0x5E8104 + +#define mmDMA7_QM_PQ_STS1_2 0x5E8108 + +#define mmDMA7_QM_PQ_STS1_3 0x5E810C + +#define mmDMA7_QM_CQ_CFG0_0 0x5E8110 + +#define mmDMA7_QM_CQ_CFG0_1 0x5E8114 + +#define mmDMA7_QM_CQ_CFG0_2 0x5E8118 + +#define mmDMA7_QM_CQ_CFG0_3 0x5E811C + +#define mmDMA7_QM_CQ_CFG0_4 0x5E8120 + +#define mmDMA7_QM_CQ_CFG1_0 0x5E8124 + +#define mmDMA7_QM_CQ_CFG1_1 0x5E8128 + +#define mmDMA7_QM_CQ_CFG1_2 0x5E812C + +#define mmDMA7_QM_CQ_CFG1_3 0x5E8130 + +#define mmDMA7_QM_CQ_CFG1_4 0x5E8134 + +#define mmDMA7_QM_CQ_ARUSER_31_11_0 0x5E8138 + +#define mmDMA7_QM_CQ_ARUSER_31_11_1 0x5E813C + +#define mmDMA7_QM_CQ_ARUSER_31_11_2 0x5E8140 + +#define mmDMA7_QM_CQ_ARUSER_31_11_3 0x5E8144 + +#define mmDMA7_QM_CQ_ARUSER_31_11_4 0x5E8148 + +#define mmDMA7_QM_CQ_STS0_0 0x5E814C + +#define mmDMA7_QM_CQ_STS0_1 0x5E8150 + +#define mmDMA7_QM_CQ_STS0_2 0x5E8154 + +#define mmDMA7_QM_CQ_STS0_3 0x5E8158 + +#define mmDMA7_QM_CQ_STS0_4 0x5E815C + +#define mmDMA7_QM_CQ_STS1_0 0x5E8160 + +#define mmDMA7_QM_CQ_STS1_1 0x5E8164 + +#define mmDMA7_QM_CQ_STS1_2 0x5E8168 + +#define mmDMA7_QM_CQ_STS1_3 0x5E816C + +#define mmDMA7_QM_CQ_STS1_4 0x5E8170 + +#define mmDMA7_QM_CQ_PTR_LO_0 0x5E8174 + +#define mmDMA7_QM_CQ_PTR_HI_0 0x5E8178 + +#define mmDMA7_QM_CQ_TSIZE_0 0x5E817C + +#define mmDMA7_QM_CQ_CTL_0 0x5E8180 + +#define mmDMA7_QM_CQ_PTR_LO_1 0x5E8184 + +#define mmDMA7_QM_CQ_PTR_HI_1 0x5E8188 + +#define mmDMA7_QM_CQ_TSIZE_1 0x5E818C + +#define mmDMA7_QM_CQ_CTL_1 0x5E8190 + +#define mmDMA7_QM_CQ_PTR_LO_2 0x5E8194 + +#define mmDMA7_QM_CQ_PTR_HI_2 0x5E8198 + +#define mmDMA7_QM_CQ_TSIZE_2 0x5E819C + +#define mmDMA7_QM_CQ_CTL_2 0x5E81A0 + +#define mmDMA7_QM_CQ_PTR_LO_3 0x5E81A4 + +#define mmDMA7_QM_CQ_PTR_HI_3 0x5E81A8 + +#define mmDMA7_QM_CQ_TSIZE_3 0x5E81AC + +#define mmDMA7_QM_CQ_CTL_3 0x5E81B0 + +#define mmDMA7_QM_CQ_PTR_LO_4 0x5E81B4 + +#define mmDMA7_QM_CQ_PTR_HI_4 0x5E81B8 + +#define mmDMA7_QM_CQ_TSIZE_4 0x5E81BC + +#define mmDMA7_QM_CQ_CTL_4 0x5E81C0 + +#define mmDMA7_QM_CQ_PTR_LO_STS_0 0x5E81C4 + +#define mmDMA7_QM_CQ_PTR_LO_STS_1 0x5E81C8 + +#define mmDMA7_QM_CQ_PTR_LO_STS_2 0x5E81CC + +#define mmDMA7_QM_CQ_PTR_LO_STS_3 0x5E81D0 + +#define mmDMA7_QM_CQ_PTR_LO_STS_4 0x5E81D4 + +#define mmDMA7_QM_CQ_PTR_HI_STS_0 0x5E81D8 + +#define mmDMA7_QM_CQ_PTR_HI_STS_1 0x5E81DC + +#define mmDMA7_QM_CQ_PTR_HI_STS_2 0x5E81E0 + +#define mmDMA7_QM_CQ_PTR_HI_STS_3 0x5E81E4 + +#define mmDMA7_QM_CQ_PTR_HI_STS_4 0x5E81E8 + +#define mmDMA7_QM_CQ_TSIZE_STS_0 0x5E81EC + +#define mmDMA7_QM_CQ_TSIZE_STS_1 0x5E81F0 + +#define mmDMA7_QM_CQ_TSIZE_STS_2 0x5E81F4 + +#define mmDMA7_QM_CQ_TSIZE_STS_3 0x5E81F8 + +#define mmDMA7_QM_CQ_TSIZE_STS_4 0x5E81FC + +#define mmDMA7_QM_CQ_CTL_STS_0 0x5E8200 + +#define mmDMA7_QM_CQ_CTL_STS_1 0x5E8204 + +#define mmDMA7_QM_CQ_CTL_STS_2 0x5E8208 + +#define mmDMA7_QM_CQ_CTL_STS_3 0x5E820C + +#define mmDMA7_QM_CQ_CTL_STS_4 0x5E8210 + +#define mmDMA7_QM_CQ_IFIFO_CNT_0 0x5E8214 + +#define mmDMA7_QM_CQ_IFIFO_CNT_1 0x5E8218 + +#define mmDMA7_QM_CQ_IFIFO_CNT_2 0x5E821C + +#define mmDMA7_QM_CQ_IFIFO_CNT_3 0x5E8220 + +#define mmDMA7_QM_CQ_IFIFO_CNT_4 0x5E8224 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_0 0x5E8228 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_1 0x5E822C + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_2 0x5E8230 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_3 0x5E8234 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_LO_4 0x5E8238 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_0 0x5E823C + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_1 0x5E8240 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_2 0x5E8244 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_3 0x5E8248 + +#define mmDMA7_QM_CP_MSG_BASE0_ADDR_HI_4 0x5E824C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_0 0x5E8250 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_1 0x5E8254 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_2 0x5E8258 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_3 0x5E825C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_LO_4 0x5E8260 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_0 0x5E8264 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_1 0x5E8268 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_2 0x5E826C + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_3 0x5E8270 + +#define mmDMA7_QM_CP_MSG_BASE1_ADDR_HI_4 0x5E8274 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_0 0x5E8278 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_1 0x5E827C + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_2 0x5E8280 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_3 0x5E8284 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_LO_4 0x5E8288 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_0 0x5E828C + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_1 0x5E8290 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_2 0x5E8294 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_3 0x5E8298 + +#define mmDMA7_QM_CP_MSG_BASE2_ADDR_HI_4 0x5E829C + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_0 0x5E82A0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_1 0x5E82A4 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_2 0x5E82A8 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_3 0x5E82AC + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_LO_4 0x5E82B0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_0 0x5E82B4 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_1 0x5E82B8 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_2 0x5E82BC + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_3 0x5E82C0 + +#define mmDMA7_QM_CP_MSG_BASE3_ADDR_HI_4 0x5E82C4 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_0 0x5E82C8 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_1 0x5E82CC + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_2 0x5E82D0 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_3 0x5E82D4 + +#define mmDMA7_QM_CP_LDMA_TSIZE_OFFSET_4 0x5E82D8 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5E82E0 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5E82E4 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5E82E8 + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5E82EC + +#define mmDMA7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5E82F0 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5E82F4 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5E82F8 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5E82FC + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5E8300 + +#define mmDMA7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5E8304 + +#define mmDMA7_QM_CP_FENCE0_RDATA_0 0x5E8308 + +#define mmDMA7_QM_CP_FENCE0_RDATA_1 0x5E830C + +#define mmDMA7_QM_CP_FENCE0_RDATA_2 0x5E8310 + +#define mmDMA7_QM_CP_FENCE0_RDATA_3 0x5E8314 + +#define mmDMA7_QM_CP_FENCE0_RDATA_4 0x5E8318 + +#define mmDMA7_QM_CP_FENCE1_RDATA_0 0x5E831C + +#define mmDMA7_QM_CP_FENCE1_RDATA_1 0x5E8320 + +#define mmDMA7_QM_CP_FENCE1_RDATA_2 0x5E8324 + +#define mmDMA7_QM_CP_FENCE1_RDATA_3 0x5E8328 + +#define mmDMA7_QM_CP_FENCE1_RDATA_4 0x5E832C + +#define mmDMA7_QM_CP_FENCE2_RDATA_0 0x5E8330 + +#define mmDMA7_QM_CP_FENCE2_RDATA_1 0x5E8334 + +#define mmDMA7_QM_CP_FENCE2_RDATA_2 0x5E8338 + +#define mmDMA7_QM_CP_FENCE2_RDATA_3 0x5E833C + +#define mmDMA7_QM_CP_FENCE2_RDATA_4 0x5E8340 + +#define mmDMA7_QM_CP_FENCE3_RDATA_0 0x5E8344 + +#define mmDMA7_QM_CP_FENCE3_RDATA_1 0x5E8348 + +#define mmDMA7_QM_CP_FENCE3_RDATA_2 0x5E834C + +#define mmDMA7_QM_CP_FENCE3_RDATA_3 0x5E8350 + +#define mmDMA7_QM_CP_FENCE3_RDATA_4 0x5E8354 + +#define mmDMA7_QM_CP_FENCE0_CNT_0 0x5E8358 + +#define mmDMA7_QM_CP_FENCE0_CNT_1 0x5E835C + +#define mmDMA7_QM_CP_FENCE0_CNT_2 0x5E8360 + +#define mmDMA7_QM_CP_FENCE0_CNT_3 0x5E8364 + +#define mmDMA7_QM_CP_FENCE0_CNT_4 0x5E8368 + +#define mmDMA7_QM_CP_FENCE1_CNT_0 0x5E836C + +#define mmDMA7_QM_CP_FENCE1_CNT_1 0x5E8370 + +#define mmDMA7_QM_CP_FENCE1_CNT_2 0x5E8374 + +#define mmDMA7_QM_CP_FENCE1_CNT_3 0x5E8378 + +#define mmDMA7_QM_CP_FENCE1_CNT_4 0x5E837C + +#define mmDMA7_QM_CP_FENCE2_CNT_0 0x5E8380 + +#define mmDMA7_QM_CP_FENCE2_CNT_1 0x5E8384 + +#define mmDMA7_QM_CP_FENCE2_CNT_2 0x5E8388 + +#define mmDMA7_QM_CP_FENCE2_CNT_3 0x5E838C + +#define mmDMA7_QM_CP_FENCE2_CNT_4 0x5E8390 + +#define mmDMA7_QM_CP_FENCE3_CNT_0 0x5E8394 + +#define mmDMA7_QM_CP_FENCE3_CNT_1 0x5E8398 + +#define mmDMA7_QM_CP_FENCE3_CNT_2 0x5E839C + +#define mmDMA7_QM_CP_FENCE3_CNT_3 0x5E83A0 + +#define mmDMA7_QM_CP_FENCE3_CNT_4 0x5E83A4 + +#define mmDMA7_QM_CP_STS_0 0x5E83A8 + +#define mmDMA7_QM_CP_STS_1 0x5E83AC + +#define mmDMA7_QM_CP_STS_2 0x5E83B0 + +#define mmDMA7_QM_CP_STS_3 0x5E83B4 + +#define mmDMA7_QM_CP_STS_4 0x5E83B8 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_0 0x5E83BC + +#define mmDMA7_QM_CP_CURRENT_INST_LO_1 0x5E83C0 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_2 0x5E83C4 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_3 0x5E83C8 + +#define mmDMA7_QM_CP_CURRENT_INST_LO_4 0x5E83CC + +#define mmDMA7_QM_CP_CURRENT_INST_HI_0 0x5E83D0 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_1 0x5E83D4 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_2 0x5E83D8 + +#define mmDMA7_QM_CP_CURRENT_INST_HI_3 0x5E83DC + +#define mmDMA7_QM_CP_CURRENT_INST_HI_4 0x5E83E0 + +#define mmDMA7_QM_CP_BARRIER_CFG_0 0x5E83F4 + +#define mmDMA7_QM_CP_BARRIER_CFG_1 0x5E83F8 + +#define mmDMA7_QM_CP_BARRIER_CFG_2 0x5E83FC + +#define mmDMA7_QM_CP_BARRIER_CFG_3 0x5E8400 + +#define mmDMA7_QM_CP_BARRIER_CFG_4 0x5E8404 + +#define mmDMA7_QM_CP_DBG_0_0 0x5E8408 + +#define mmDMA7_QM_CP_DBG_0_1 0x5E840C + +#define mmDMA7_QM_CP_DBG_0_2 0x5E8410 + +#define mmDMA7_QM_CP_DBG_0_3 0x5E8414 + +#define mmDMA7_QM_CP_DBG_0_4 0x5E8418 + +#define mmDMA7_QM_CP_ARUSER_31_11_0 0x5E841C + +#define mmDMA7_QM_CP_ARUSER_31_11_1 0x5E8420 + +#define mmDMA7_QM_CP_ARUSER_31_11_2 0x5E8424 + +#define mmDMA7_QM_CP_ARUSER_31_11_3 0x5E8428 + +#define mmDMA7_QM_CP_ARUSER_31_11_4 0x5E842C + +#define mmDMA7_QM_CP_AWUSER_31_11_0 0x5E8430 + +#define mmDMA7_QM_CP_AWUSER_31_11_1 0x5E8434 + +#define mmDMA7_QM_CP_AWUSER_31_11_2 0x5E8438 + +#define mmDMA7_QM_CP_AWUSER_31_11_3 0x5E843C + +#define mmDMA7_QM_CP_AWUSER_31_11_4 0x5E8440 + +#define mmDMA7_QM_ARB_CFG_0 0x5E8A00 + +#define mmDMA7_QM_ARB_CHOISE_Q_PUSH 0x5E8A04 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_0 0x5E8A08 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_1 0x5E8A0C + +#define mmDMA7_QM_ARB_WRR_WEIGHT_2 0x5E8A10 + +#define mmDMA7_QM_ARB_WRR_WEIGHT_3 0x5E8A14 + +#define mmDMA7_QM_ARB_CFG_1 0x5E8A18 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_0 0x5E8A20 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_1 0x5E8A24 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_2 0x5E8A28 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_3 0x5E8A2C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_4 0x5E8A30 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_5 0x5E8A34 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_6 0x5E8A38 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_7 0x5E8A3C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_8 0x5E8A40 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_9 0x5E8A44 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_10 0x5E8A48 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_11 0x5E8A4C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_12 0x5E8A50 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_13 0x5E8A54 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_14 0x5E8A58 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_15 0x5E8A5C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_16 0x5E8A60 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_17 0x5E8A64 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_18 0x5E8A68 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_19 0x5E8A6C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_20 0x5E8A70 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_21 0x5E8A74 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_22 0x5E8A78 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_23 0x5E8A7C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_24 0x5E8A80 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_25 0x5E8A84 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_26 0x5E8A88 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_27 0x5E8A8C + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_28 0x5E8A90 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_29 0x5E8A94 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_30 0x5E8A98 + +#define mmDMA7_QM_ARB_MST_AVAIL_CRED_31 0x5E8A9C + +#define mmDMA7_QM_ARB_MST_CRED_INC 0x5E8AA0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5E8AA4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5E8AA8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5E8AAC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5E8AB0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5E8AB4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5E8AB8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5E8ABC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5E8AC0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5E8AC4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5E8AC8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5E8ACC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5E8AD0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5E8AD4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5E8AD8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5E8ADC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5E8AE0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5E8AE4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5E8AE8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5E8AEC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5E8AF0 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5E8AF4 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5E8AF8 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5E8AFC + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5E8B00 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5E8B04 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5E8B08 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5E8B0C + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5E8B10 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5E8B14 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5E8B18 + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5E8B1C + +#define mmDMA7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5E8B20 + +#define mmDMA7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5E8B28 + +#define mmDMA7_QM_ARB_MST_SLAVE_EN 0x5E8B2C + +#define mmDMA7_QM_ARB_MST_QUIET_PER 0x5E8B34 + +#define mmDMA7_QM_ARB_SLV_CHOISE_WDT 0x5E8B38 + +#define mmDMA7_QM_ARB_SLV_ID 0x5E8B3C + +#define mmDMA7_QM_ARB_MSG_MAX_INFLIGHT 0x5E8B44 + +#define mmDMA7_QM_ARB_MSG_AWUSER_31_11 0x5E8B48 + +#define mmDMA7_QM_ARB_MSG_AWUSER_SEC_PROP 0x5E8B4C + +#define mmDMA7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5E8B50 + +#define mmDMA7_QM_ARB_BASE_LO 0x5E8B54 + +#define mmDMA7_QM_ARB_BASE_HI 0x5E8B58 + +#define mmDMA7_QM_ARB_STATE_STS 0x5E8B80 + +#define mmDMA7_QM_ARB_CHOISE_FULLNESS_STS 0x5E8B84 + +#define mmDMA7_QM_ARB_MSG_STS 0x5E8B88 + +#define mmDMA7_QM_ARB_SLV_CHOISE_Q_HEAD 0x5E8B8C + +#define mmDMA7_QM_ARB_ERR_CAUSE 0x5E8B9C + +#define mmDMA7_QM_ARB_ERR_MSG_EN 0x5E8BA0 + +#define mmDMA7_QM_ARB_ERR_STS_DRP 0x5E8BA8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_0 0x5E8BB0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_1 0x5E8BB4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_2 0x5E8BB8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_3 0x5E8BBC + +#define mmDMA7_QM_ARB_MST_CRED_STS_4 0x5E8BC0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_5 0x5E8BC4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_6 0x5E8BC8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_7 0x5E8BCC + +#define mmDMA7_QM_ARB_MST_CRED_STS_8 0x5E8BD0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_9 0x5E8BD4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_10 0x5E8BD8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_11 0x5E8BDC + +#define mmDMA7_QM_ARB_MST_CRED_STS_12 0x5E8BE0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_13 0x5E8BE4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_14 0x5E8BE8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_15 0x5E8BEC + +#define mmDMA7_QM_ARB_MST_CRED_STS_16 0x5E8BF0 + +#define mmDMA7_QM_ARB_MST_CRED_STS_17 0x5E8BF4 + +#define mmDMA7_QM_ARB_MST_CRED_STS_18 0x5E8BF8 + +#define mmDMA7_QM_ARB_MST_CRED_STS_19 0x5E8BFC + +#define mmDMA7_QM_ARB_MST_CRED_STS_20 0x5E8C00 + +#define mmDMA7_QM_ARB_MST_CRED_STS_21 0x5E8C04 + +#define mmDMA7_QM_ARB_MST_CRED_STS_22 0x5E8C08 + +#define mmDMA7_QM_ARB_MST_CRED_STS_23 0x5E8C0C + +#define mmDMA7_QM_ARB_MST_CRED_STS_24 0x5E8C10 + +#define mmDMA7_QM_ARB_MST_CRED_STS_25 0x5E8C14 + +#define mmDMA7_QM_ARB_MST_CRED_STS_26 0x5E8C18 + +#define mmDMA7_QM_ARB_MST_CRED_STS_27 0x5E8C1C + +#define mmDMA7_QM_ARB_MST_CRED_STS_28 0x5E8C20 + +#define mmDMA7_QM_ARB_MST_CRED_STS_29 0x5E8C24 + +#define mmDMA7_QM_ARB_MST_CRED_STS_30 0x5E8C28 + +#define mmDMA7_QM_ARB_MST_CRED_STS_31 0x5E8C2C + +#define mmDMA7_QM_CGM_CFG 0x5E8C70 + +#define mmDMA7_QM_CGM_STS 0x5E8C74 + +#define mmDMA7_QM_CGM_CFG1 0x5E8C78 + +#define mmDMA7_QM_LOCAL_RANGE_BASE 0x5E8C80 + +#define mmDMA7_QM_LOCAL_RANGE_SIZE 0x5E8C84 + +#define mmDMA7_QM_CSMR_STRICT_PRIO_CFG 0x5E8C90 + +#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_1 0x5E8C94 + +#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_0 0x5E8C98 + +#define mmDMA7_QM_LBW_WR_RATE_LIM_CFG_1 0x5E8C9C + +#define mmDMA7_QM_HBW_RD_RATE_LIM_CFG_0 0x5E8CA0 + +#define mmDMA7_QM_GLBL_AXCACHE 0x5E8CA4 + +#define mmDMA7_QM_IND_GW_APB_CFG 0x5E8CB0 + +#define mmDMA7_QM_IND_GW_APB_WDATA 0x5E8CB4 + +#define mmDMA7_QM_IND_GW_APB_RDATA 0x5E8CB8 + +#define mmDMA7_QM_IND_GW_APB_STATUS 0x5E8CBC + +#define mmDMA7_QM_GLBL_ERR_ADDR_LO 0x5E8CD0 + +#define mmDMA7_QM_GLBL_ERR_ADDR_HI 0x5E8CD4 + +#define mmDMA7_QM_GLBL_ERR_WDATA 0x5E8CD8 + +#define mmDMA7_QM_GLBL_MEM_INIT_BUSY 0x5E8D00 + +#endif /* ASIC_REG_DMA7_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h new file mode 100644 index 000000000000..8c1c72df4469 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_N_DOWN_CH0_PERM_SEL 0x4E1108 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_0 0x4E1114 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_1 0x4E1118 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_2 0x4E111C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_3 0x4E1120 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_4 0x4E1124 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_5 0x4E1128 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_6 0x4E112C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_7 0x4E1130 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_8 0x4E1134 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_9 0x4E1138 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_10 0x4E113C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_11 0x4E1140 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_12 0x4E1144 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_13 0x4E1148 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_14 0x4E114C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_15 0x4E1150 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_16 0x4E1154 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_17 0x4E1158 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_18 0x4E115C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_19 0x4E1160 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_20 0x4E1164 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_21 0x4E1168 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_22 0x4E116C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_23 0x4E1170 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_24 0x4E1174 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_25 0x4E1178 + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_26 0x4E117C + +#define mmDMA_IF_E_N_DOWN_CH0_HBM_POLY_H3_27 0x4E1180 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_0 0x4E1184 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_1 0x4E1188 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_2 0x4E118C + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_3 0x4E1190 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_4 0x4E1194 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_5 0x4E1198 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_6 0x4E119C + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_7 0x4E11A0 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_8 0x4E11A4 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_9 0x4E11A8 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_10 0x4E11AC + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_11 0x4E11B0 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_12 0x4E11B4 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_13 0x4E11B8 + +#define mmDMA_IF_E_N_DOWN_CH0_SRAM_POLY_H3_14 0x4E11BC + +#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_SRAM_EN 0x4E126C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_EN 0x4E1274 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_SAT 0x4E1278 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_RST 0x4E127C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4E1280 + +#define mmDMA_IF_E_N_DOWN_CH0_SCRAM_HBM_EN 0x4E1284 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_EN 0x4E1288 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_SAT 0x4E128C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_RST 0x4E1290 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4E1294 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_EN 0x4E129C + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_SAT 0x4E12A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RST 0x4E12A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4E12AC + +#define mmDMA_IF_E_N_DOWN_CH0_RL_SRAM_RED 0x4E12B4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_EN 0x4E12EC + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_EN 0x4E12F0 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4E12F4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4E12F8 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4E1404 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4E1408 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4E140C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4E1410 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4E1414 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4E1418 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4E141C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4E1420 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4E1424 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4E1428 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4E142C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4E1430 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4E1434 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4E1438 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_0 0x4E1450 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_SEL_1 0x4E1454 + +#define mmDMA_IF_E_N_DOWN_CH0_NON_LIN_EN 0x4E1480 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_0 0x4E1500 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_1 0x4E1504 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_2 0x4E1508 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_3 0x4E150C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_BANK_4 0x4E1510 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4E1514 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4E1520 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4E1524 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4E1528 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4E152C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4E1530 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4E1534 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4E1538 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4E153C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4E1540 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4E1550 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4E1554 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4E1558 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4E155C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4E1560 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4E1564 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4E1568 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4E156C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4E1570 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4E1574 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4E1578 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4E157C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4E1580 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4E1584 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4E1588 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4E158C + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4E1590 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4E1594 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4E1598 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4E15E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4E15E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4E15EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4E15F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4E15F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4E15F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4E15FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4E1600 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4E1604 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4E1608 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4E160C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4E1610 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4E1614 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4E1618 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4E161C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4E1620 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4E1624 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4E1628 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4E162C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4E1630 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4E1634 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4E1638 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4E163C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4E1640 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4E1644 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4E1648 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4E164C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4E1650 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4E1654 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4E1658 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4E165C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4E1660 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4E1664 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4E1668 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4E166C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4E1670 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4E1674 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4E1678 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4E167C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4E1680 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4E1684 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4E1688 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4E168C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4E1690 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4E1694 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4E1698 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4E169C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4E16A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4E16A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4E16A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4E16AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4E16B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4E16B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4E16B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4E16BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4E16C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4E16C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4E16C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4E16CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4E16D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4E16D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4E16D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4E16DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4E16E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4E16E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4E16E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4E16EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4E16F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4E16F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4E16F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4E16FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4E1700 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4E1704 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4E1708 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4E170C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4E1710 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4E1714 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4E1718 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4E171C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4E1720 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4E1724 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4E1728 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4E172C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4E1730 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4E1734 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4E1738 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4E173C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4E1740 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4E1744 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4E1748 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4E174C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4E1750 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4E1754 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4E1758 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4E175C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4E1760 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4E1764 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4E1768 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4E176C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4E1770 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4E1774 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4E1778 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4E177C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4E1780 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4E1784 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4E1788 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4E178C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4E1790 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4E1794 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4E1798 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4E179C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4E17A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4E17A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4E17A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4E17AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4E17B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4E17B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4E17B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4E17BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4E17C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4E17C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4E17C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4E17CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4E17D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4E17D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4E17D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4E17DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4E17E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4E1824 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4E1828 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4E182C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4E1830 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4E1834 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4E1838 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4E183C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4E1840 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4E1844 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4E1848 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4E184C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4E1850 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4E1854 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4E1858 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4E185C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4E1860 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4E1864 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4E1868 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4E186C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4E1870 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4E1874 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4E1878 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4E187C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4E1880 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4E1884 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4E1888 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4E188C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4E1890 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4E1894 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4E1898 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4E189C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4E18A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4E18A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4E18A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4E18AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4E18B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4E18B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4E18B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4E18BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4E18C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4E18C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4E18C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4E18CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4E18D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4E18D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4E18D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4E18DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4E18E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4E18E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4E18E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4E18EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4E18F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4E18F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4E18F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4E18FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4E1900 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4E1904 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4E1908 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4E190C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4E1910 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4E1914 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4E1918 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4E191C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4E1920 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4E1924 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4E1928 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4E192C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4E1930 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4E1934 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4E1938 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4E193C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4E1940 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4E1944 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4E1948 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4E194C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4E1950 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4E1954 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4E1958 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4E195C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4E1960 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4E1964 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4E1968 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4E196C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4E1970 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4E1974 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4E1978 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4E197C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4E1980 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4E1984 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4E1988 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4E198C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4E1990 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4E1994 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4E1998 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4E199C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4E19A0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4E19A4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4E19A8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4E19AC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4E19B0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4E19B4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4E19B8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4E19BC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4E19C0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4E19C4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4E19C8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4E19CC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4E19D0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4E19D4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4E19D8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4E19DC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4E19E0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4E19E4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4E19E8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4E19EC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4E19F0 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4E19F4 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4E19F8 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4E19FC + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4E1A00 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4E1A04 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4E1A08 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4E1A0C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4E1A10 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4E1A14 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4E1A18 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4E1A1C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4E1A20 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4E1A64 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4E1A68 + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4E1A6C + +#define mmDMA_IF_E_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4E1A70 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_CFG 0x4E1B64 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_SHIFT 0x4E1B68 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4E1B6C + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4E1B70 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4E1B74 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4E1B78 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4E1B7C + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4E1B80 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4E1B84 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4E1B88 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_0 0x4E1BAC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_1 0x4E1BB0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_2 0x4E1BB4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_3 0x4E1BB8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_4 0x4E1BBC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_5 0x4E1BC0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_6 0x4E1BC4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_TOKEN_7 0x4E1BC8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_0 0x4E1BEC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_1 0x4E1BF0 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_2 0x4E1BF4 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_3 0x4E1BF8 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_4 0x4E1BFC + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_5 0x4E1C00 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_6 0x4E1C04 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_BANK_ID_7 0x4E1C08 + +#define mmDMA_IF_E_N_DOWN_CH0_RGL_WDT 0x4E1C2C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E1C30 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E1C34 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E1C38 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E1C3C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E1C40 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E1C44 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E1C48 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E1C4C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4E1C50 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4E1C54 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4E1C58 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4E1C5C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4E1C60 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4E1C64 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4E1C68 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4E1C6C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E1C70 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E1C74 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E1C78 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E1C7C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E1C80 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E1C84 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E1C88 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E1C8C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4E1C90 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4E1C94 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4E1C98 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4E1C9C + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4E1CA0 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4E1CA4 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4E1CA8 + +#define mmDMA_IF_E_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4E1CAC + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4E1CB0 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4E1CB4 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4E1CB8 + +#define mmDMA_IF_E_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4E1CBC + +#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h new file mode 100644 index 000000000000..b2b593fcec30 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_N_DOWN_CH1_PERM_SEL 0x4E2108 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_0 0x4E2114 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_1 0x4E2118 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_2 0x4E211C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_3 0x4E2120 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_4 0x4E2124 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_5 0x4E2128 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_6 0x4E212C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_7 0x4E2130 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_8 0x4E2134 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_9 0x4E2138 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_10 0x4E213C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_11 0x4E2140 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_12 0x4E2144 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_13 0x4E2148 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_14 0x4E214C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_15 0x4E2150 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_16 0x4E2154 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_17 0x4E2158 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_18 0x4E215C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_19 0x4E2160 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_20 0x4E2164 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_21 0x4E2168 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_22 0x4E216C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_23 0x4E2170 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_24 0x4E2174 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_25 0x4E2178 + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_26 0x4E217C + +#define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_27 0x4E2180 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_0 0x4E2184 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_1 0x4E2188 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_2 0x4E218C + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_3 0x4E2190 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_4 0x4E2194 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_5 0x4E2198 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_6 0x4E219C + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_7 0x4E21A0 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_8 0x4E21A4 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_9 0x4E21A8 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_10 0x4E21AC + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_11 0x4E21B0 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_12 0x4E21B4 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_13 0x4E21B8 + +#define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_14 0x4E21BC + +#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN 0x4E226C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN 0x4E2274 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT 0x4E2278 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST 0x4E227C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4E2280 + +#define mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN 0x4E2284 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_EN 0x4E2288 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_SAT 0x4E228C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_RST 0x4E2290 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4E2294 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN 0x4E229C + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT 0x4E22A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST 0x4E22A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4E22AC + +#define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RED 0x4E22B4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN 0x4E22EC + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN 0x4E22F0 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4E22F4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4E22F8 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4E2404 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4E2408 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4E240C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4E2410 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4E2414 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4E2418 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4E241C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4E2420 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4E2424 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4E2428 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4E242C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4E2430 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4E2434 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4E2438 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0 0x4E2450 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1 0x4E2454 + +#define mmDMA_IF_E_N_DOWN_CH1_NON_LIN_EN 0x4E2480 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_0 0x4E2500 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_1 0x4E2504 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_2 0x4E2508 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_3 0x4E250C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_4 0x4E2510 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4E2514 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4E2520 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4E2524 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4E2528 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4E252C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4E2530 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4E2534 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4E2538 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4E253C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4E2540 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4E2550 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4E2554 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4E2558 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4E255C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4E2560 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4E2564 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4E2568 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4E256C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4E2570 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4E2574 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4E2578 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4E257C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4E2580 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4E2584 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4E2588 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4E258C + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4E2590 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4E2594 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4E2598 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4E25E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4E25E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4E25EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4E25F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4E25F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4E25F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4E25FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4E2600 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4E2604 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4E2608 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4E260C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4E2610 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4E2614 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4E2618 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4E261C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4E2620 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4E2624 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4E2628 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4E262C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4E2630 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4E2634 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4E2638 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4E263C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4E2640 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4E2644 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4E2648 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4E264C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4E2650 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4E2654 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4E2658 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4E265C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4E2660 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4E2664 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4E2668 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4E266C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4E2670 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4E2674 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4E2678 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4E267C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4E2680 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4E2684 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4E2688 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4E268C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4E2690 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4E2694 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4E2698 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4E269C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4E26A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4E26A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4E26A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4E26AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4E26B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4E26B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4E26B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4E26BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4E26C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4E26C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4E26C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4E26CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4E26D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4E26D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4E26D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4E26DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4E26E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4E26E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4E26E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4E26EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4E26F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4E26F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4E26F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4E26FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4E2700 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4E2704 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4E2708 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4E270C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4E2710 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4E2714 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4E2718 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4E271C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4E2720 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4E2724 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4E2728 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4E272C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4E2730 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4E2734 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4E2738 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4E273C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4E2740 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4E2744 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4E2748 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4E274C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4E2750 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4E2754 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4E2758 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4E275C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4E2760 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4E2764 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4E2768 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4E276C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4E2770 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4E2774 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4E2778 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4E277C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4E2780 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4E2784 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4E2788 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4E278C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4E2790 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4E2794 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4E2798 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4E279C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4E27A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4E27A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4E27A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4E27AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4E27B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4E27B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4E27B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4E27BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4E27C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4E27C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4E27C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4E27CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4E27D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4E27D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4E27D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4E27DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4E27E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4E2824 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4E2828 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4E282C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4E2830 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4E2834 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4E2838 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4E283C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4E2840 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4E2844 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4E2848 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4E284C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4E2850 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4E2854 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4E2858 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4E285C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4E2860 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4E2864 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4E2868 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4E286C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4E2870 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4E2874 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4E2878 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4E287C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4E2880 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4E2884 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4E2888 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4E288C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4E2890 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4E2894 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4E2898 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4E289C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4E28A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4E28A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4E28A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4E28AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4E28B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4E28B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4E28B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4E28BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4E28C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4E28C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4E28C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4E28CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4E28D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4E28D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4E28D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4E28DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4E28E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4E28E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4E28E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4E28EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4E28F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4E28F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4E28F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4E28FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4E2900 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4E2904 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4E2908 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4E290C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4E2910 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4E2914 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4E2918 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4E291C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4E2920 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4E2924 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4E2928 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4E292C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4E2930 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4E2934 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4E2938 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4E293C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4E2940 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4E2944 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4E2948 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4E294C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4E2950 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4E2954 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4E2958 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4E295C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4E2960 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4E2964 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4E2968 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4E296C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4E2970 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4E2974 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4E2978 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4E297C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4E2980 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4E2984 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4E2988 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4E298C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4E2990 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4E2994 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4E2998 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4E299C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4E29A0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4E29A4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4E29A8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4E29AC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4E29B0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4E29B4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4E29B8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4E29BC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4E29C0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4E29C4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4E29C8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4E29CC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4E29D0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4E29D4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4E29D8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4E29DC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4E29E0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4E29E4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4E29E8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4E29EC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4E29F0 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4E29F4 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4E29F8 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4E29FC + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4E2A00 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4E2A04 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4E2A08 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4E2A0C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4E2A10 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4E2A14 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4E2A18 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4E2A1C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4E2A20 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4E2A64 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4E2A68 + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4E2A6C + +#define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4E2A70 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_CFG 0x4E2B64 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_SHIFT 0x4E2B68 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4E2B6C + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4E2B70 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4E2B74 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4E2B78 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4E2B7C + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4E2B80 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4E2B84 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4E2B88 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_0 0x4E2BAC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_1 0x4E2BB0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_2 0x4E2BB4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_3 0x4E2BB8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_4 0x4E2BBC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_5 0x4E2BC0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_6 0x4E2BC4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_7 0x4E2BC8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_0 0x4E2BEC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_1 0x4E2BF0 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_2 0x4E2BF4 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_3 0x4E2BF8 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_4 0x4E2BFC + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_5 0x4E2C00 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_6 0x4E2C04 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_7 0x4E2C08 + +#define mmDMA_IF_E_N_DOWN_CH1_RGL_WDT 0x4E2C2C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E2C30 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E2C34 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E2C38 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E2C3C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E2C40 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E2C44 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E2C48 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E2C4C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4E2C50 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4E2C54 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4E2C58 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4E2C5C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4E2C60 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4E2C64 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4E2C68 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4E2C6C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E2C70 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E2C74 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E2C78 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E2C7C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E2C80 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E2C84 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E2C88 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E2C8C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4E2C90 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4E2C94 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4E2C98 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4E2C9C + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4E2CA0 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4E2CA4 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4E2CA8 + +#define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4E2CAC + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4E2CB0 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4E2CB4 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4E2CB8 + +#define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4E2CBC + +#endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h new file mode 100644 index 000000000000..8a10c6a76156 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_n_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_N_REGS_H_ +#define ASIC_REG_DMA_IF_E_N_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_N (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_E_N_HBM0_WR_CRED_CNT 0x4E0000 + +#define mmDMA_IF_E_N_HBM1_WR_CRED_CNT 0x4E0004 + +#define mmDMA_IF_E_N_HBM0_RD_CRED_CNT 0x4E0008 + +#define mmDMA_IF_E_N_HBM1_RD_CRED_CNT 0x4E000C + +#define mmDMA_IF_E_N_HBM_LIMITER_0 0x4E0030 + +#define mmDMA_IF_E_N_HBM_LIMITER_1 0x4E0034 + +#define mmDMA_IF_E_N_HBM_LIMITER_2 0x4E0038 + +#define mmDMA_IF_E_N_HBM_LIMITER_3 0x4E003C + +#define mmDMA_IF_E_N_HBM_ALMOST_EN_0 0x4E0040 + +#define mmDMA_IF_E_N_HBM_ALMOST_EN_1 0x4E0044 + +#define mmDMA_IF_E_N_HBM_CRED_EN_0 0x4E0050 + +#define mmDMA_IF_E_N_HBM_CRED_EN_1 0x4E0054 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_0 0x4E0100 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_1 0x4E0104 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_2 0x4E0108 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_3 0x4E010C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_4 0x4E0110 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_5 0x4E0114 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_6 0x4E0118 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_7 0x4E011C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_8 0x4E0120 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_9 0x4E0124 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_10 0x4E0128 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_11 0x4E012C + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_12 0x4E0130 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_13 0x4E0134 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_14 0x4E0138 + +#define mmDMA_IF_E_N_SOB_MIN_RPROT_15 0x4E013C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_0 0x4E0140 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_1 0x4E0144 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_2 0x4E0148 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_3 0x4E014C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_4 0x4E0150 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_5 0x4E0154 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_6 0x4E0158 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_7 0x4E015C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_8 0x4E0160 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_9 0x4E0164 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_10 0x4E0168 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_11 0x4E016C + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_12 0x4E0170 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_13 0x4E0174 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_14 0x4E0178 + +#define mmDMA_IF_E_N_SOB_MAX_RPROT_15 0x4E017C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_0 0x4E0180 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_1 0x4E0184 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_2 0x4E0188 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_3 0x4E018C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_4 0x4E0190 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_5 0x4E0194 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_6 0x4E0198 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_7 0x4E019C + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_8 0x4E01A0 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_9 0x4E01A4 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_10 0x4E01A8 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_11 0x4E01AC + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_12 0x4E01B0 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_13 0x4E01B4 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_14 0x4E01B8 + +#define mmDMA_IF_E_N_SOB_MIN_WPROT_15 0x4E01BC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_0 0x4E01C0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_1 0x4E01C4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_2 0x4E01C8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_3 0x4E01CC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_4 0x4E01D0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_5 0x4E01D4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_6 0x4E01D8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_7 0x4E01DC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_8 0x4E01E0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_9 0x4E01E4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_10 0x4E01E8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_11 0x4E01EC + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_12 0x4E01F0 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_13 0x4E01F4 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_14 0x4E01F8 + +#define mmDMA_IF_E_N_SOB_MAX_WPROT_15 0x4E01FC + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_0 0x4E0200 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_1 0x4E0204 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_2 0x4E0208 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_3 0x4E020C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_4 0x4E0210 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_5 0x4E0214 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_6 0x4E0218 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_7 0x4E021C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_8 0x4E0220 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_9 0x4E0224 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_10 0x4E0228 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_11 0x4E022C + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_12 0x4E0230 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_13 0x4E0234 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_14 0x4E0238 + +#define mmDMA_IF_E_N_SOB_MIN_RPRIV_15 0x4E023C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_0 0x4E0240 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_1 0x4E0244 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_2 0x4E0248 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_3 0x4E024C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_4 0x4E0250 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_5 0x4E0254 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_6 0x4E0258 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_7 0x4E025C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_8 0x4E0260 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_9 0x4E0264 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_10 0x4E0268 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_11 0x4E026C + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_12 0x4E0270 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_13 0x4E0274 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_14 0x4E0278 + +#define mmDMA_IF_E_N_SOB_MAX_RPRIV_15 0x4E027C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_0 0x4E0280 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_1 0x4E0284 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_2 0x4E0288 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_3 0x4E028C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_4 0x4E0290 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_5 0x4E0294 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_6 0x4E0298 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_7 0x4E029C + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_8 0x4E02A0 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_9 0x4E02A4 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_10 0x4E02A8 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_11 0x4E02AC + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_12 0x4E02B0 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_13 0x4E02B4 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_14 0x4E02B8 + +#define mmDMA_IF_E_N_SOB_MIN_WPRIV_15 0x4E02BC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_0 0x4E02C0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_1 0x4E02C4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_2 0x4E02C8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_3 0x4E02CC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_4 0x4E02D0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_5 0x4E02D4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_6 0x4E02D8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_7 0x4E02DC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_8 0x4E02E0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_9 0x4E02E4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_10 0x4E02E8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_11 0x4E02EC + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_12 0x4E02F0 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_13 0x4E02F4 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_14 0x4E02F8 + +#define mmDMA_IF_E_N_SOB_MAX_WPRIV_15 0x4E02FC + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_0 0x4E0300 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_1 0x4E0304 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_2 0x4E0308 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_3 0x4E030C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_4 0x4E0310 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_5 0x4E0314 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_6 0x4E0318 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_7 0x4E031C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_8 0x4E0320 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_9 0x4E0324 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_10 0x4E0328 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_11 0x4E032C + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_12 0x4E0330 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_13 0x4E0334 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_14 0x4E0338 + +#define mmDMA_IF_E_N_DMA0_MIN_RPROT_15 0x4E033C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_0 0x4E0340 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_1 0x4E0344 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_2 0x4E0348 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_3 0x4E034C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_4 0x4E0350 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_5 0x4E0354 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_6 0x4E0358 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_7 0x4E035C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_8 0x4E0360 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_9 0x4E0364 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_10 0x4E0368 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_11 0x4E036C + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_12 0x4E0370 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_13 0x4E0374 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_14 0x4E0378 + +#define mmDMA_IF_E_N_DMA0_MAX_RPROT_15 0x4E037C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_0 0x4E0380 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_1 0x4E0384 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_2 0x4E0388 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_3 0x4E038C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_4 0x4E0390 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_5 0x4E0394 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_6 0x4E0398 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_7 0x4E039C + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_8 0x4E03A0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_9 0x4E03A4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_10 0x4E03A8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_11 0x4E03AC + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_12 0x4E03B0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_13 0x4E03B4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_14 0x4E03B8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPROT_15 0x4E03BC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_0 0x4E03C0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_1 0x4E03C4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_2 0x4E03C8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_3 0x4E03CC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_4 0x4E03D0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_5 0x4E03D4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_6 0x4E03D8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_7 0x4E03DC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_8 0x4E03E0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_9 0x4E03E4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_10 0x4E03E8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_11 0x4E03EC + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_12 0x4E03F0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_13 0x4E03F4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_14 0x4E03F8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPROT_15 0x4E03FC + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_0 0x4E0400 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_1 0x4E0404 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_2 0x4E0408 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_3 0x4E040C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_4 0x4E0410 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_5 0x4E0414 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_6 0x4E0418 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_7 0x4E041C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_8 0x4E0420 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_9 0x4E0424 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_10 0x4E0428 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_11 0x4E042C + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_12 0x4E0430 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_13 0x4E0434 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_14 0x4E0438 + +#define mmDMA_IF_E_N_DMA0_MIN_RPRIV_15 0x4E043C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_0 0x4E0440 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_1 0x4E0444 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_2 0x4E0448 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_3 0x4E044C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_4 0x4E0450 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_5 0x4E0454 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_6 0x4E0458 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_7 0x4E045C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_8 0x4E0460 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_9 0x4E0464 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_10 0x4E0468 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_11 0x4E046C + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_12 0x4E0470 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_13 0x4E0474 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_14 0x4E0478 + +#define mmDMA_IF_E_N_DMA0_MAX_RPRIV_15 0x4E047C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_0 0x4E0480 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_1 0x4E0484 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_2 0x4E0488 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_3 0x4E048C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_4 0x4E0490 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_5 0x4E0494 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_6 0x4E0498 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_7 0x4E049C + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_8 0x4E04A0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_9 0x4E04A4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_10 0x4E04A8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_11 0x4E04AC + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_12 0x4E04B0 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_13 0x4E04B4 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_14 0x4E04B8 + +#define mmDMA_IF_E_N_DMA0_MIN_WPRIV_15 0x4E04BC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_0 0x4E04C0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_1 0x4E04C4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_2 0x4E04C8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_3 0x4E04CC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_4 0x4E04D0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_5 0x4E04D4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_6 0x4E04D8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_7 0x4E04DC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_8 0x4E04E0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_9 0x4E04E4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_10 0x4E04E8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_11 0x4E04EC + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_12 0x4E04F0 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_13 0x4E04F4 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_14 0x4E04F8 + +#define mmDMA_IF_E_N_DMA0_MAX_WPRIV_15 0x4E04FC + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_0 0x4E0500 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_1 0x4E0504 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_2 0x4E0508 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_3 0x4E050C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_4 0x4E0510 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_5 0x4E0514 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_6 0x4E0518 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_7 0x4E051C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_8 0x4E0520 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_9 0x4E0524 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_10 0x4E0528 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_11 0x4E052C + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_12 0x4E0530 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_13 0x4E0534 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_14 0x4E0538 + +#define mmDMA_IF_E_N_DMA1_MIN_RPROT_15 0x4E053C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_0 0x4E0540 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_1 0x4E0544 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_2 0x4E0548 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_3 0x4E054C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_4 0x4E0550 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_5 0x4E0554 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_6 0x4E0558 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_7 0x4E055C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_8 0x4E0560 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_9 0x4E0564 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_10 0x4E0568 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_11 0x4E056C + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_12 0x4E0570 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_13 0x4E0574 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_14 0x4E0578 + +#define mmDMA_IF_E_N_DMA1_MAX_RPROT_15 0x4E057C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_0 0x4E0580 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_1 0x4E0584 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_2 0x4E0588 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_3 0x4E058C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_4 0x4E0590 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_5 0x4E0594 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_6 0x4E0598 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_7 0x4E059C + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_8 0x4E05A0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_9 0x4E05A4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_10 0x4E05A8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_11 0x4E05AC + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_12 0x4E05B0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_13 0x4E05B4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_14 0x4E05B8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPROT_15 0x4E05BC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_0 0x4E05C0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_1 0x4E05C4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_2 0x4E05C8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_3 0x4E05CC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_4 0x4E05D0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_5 0x4E05D4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_6 0x4E05D8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_7 0x4E05DC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_8 0x4E05E0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_9 0x4E05E4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_10 0x4E05E8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_11 0x4E05EC + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_12 0x4E05F0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_13 0x4E05F4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_14 0x4E05F8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPROT_15 0x4E05FC + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_0 0x4E0600 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_1 0x4E0604 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_2 0x4E0608 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_3 0x4E060C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_4 0x4E0610 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_5 0x4E0614 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_6 0x4E0618 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_7 0x4E061C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_8 0x4E0620 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_9 0x4E0624 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_10 0x4E0628 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_11 0x4E062C + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_12 0x4E0630 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_13 0x4E0634 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_14 0x4E0638 + +#define mmDMA_IF_E_N_DMA1_MIN_RPRIV_15 0x4E063C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_0 0x4E0640 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_1 0x4E0644 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_2 0x4E0648 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_3 0x4E064C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_4 0x4E0650 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_5 0x4E0654 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_6 0x4E0658 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_7 0x4E065C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_8 0x4E0660 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_9 0x4E0664 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_10 0x4E0668 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_11 0x4E066C + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_12 0x4E0670 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_13 0x4E0674 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_14 0x4E0678 + +#define mmDMA_IF_E_N_DMA1_MAX_RPRIV_15 0x4E067C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_0 0x4E0680 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_1 0x4E0684 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_2 0x4E0688 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_3 0x4E068C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_4 0x4E0690 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_5 0x4E0694 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_6 0x4E0698 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_7 0x4E069C + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_8 0x4E06A0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_9 0x4E06A4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_10 0x4E06A8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_11 0x4E06AC + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_12 0x4E06B0 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_13 0x4E06B4 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_14 0x4E06B8 + +#define mmDMA_IF_E_N_DMA1_MIN_WPRIV_15 0x4E06BC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_0 0x4E06C0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_1 0x4E06C4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_2 0x4E06C8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_3 0x4E06CC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_4 0x4E06D0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_5 0x4E06D4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_6 0x4E06D8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_7 0x4E06DC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_8 0x4E06E0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_9 0x4E06E4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_10 0x4E06E8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_11 0x4E06EC + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_12 0x4E06F0 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_13 0x4E06F4 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_14 0x4E06F8 + +#define mmDMA_IF_E_N_DMA1_MAX_WPRIV_15 0x4E06FC + +#define mmDMA_IF_E_N_SOB_HIT_RPROT 0x4E0700 + +#define mmDMA_IF_E_N_SOB_HIT_WPROT 0x4E0704 + +#define mmDMA_IF_E_N_SOB_HIT_RPRIV 0x4E070C + +#define mmDMA_IF_E_N_SOB_HIT_WPRIV 0x4E0710 + +#define mmDMA_IF_E_N_DMA0_HIT_RPROT 0x4E071C + +#define mmDMA_IF_E_N_DMA0_HIT_WPROT 0x4E0720 + +#define mmDMA_IF_E_N_DMA0_HIT_RPRIV 0x4E0724 + +#define mmDMA_IF_E_N_DMA0_HIT_WPRIV 0x4E0728 + +#define mmDMA_IF_E_N_DMA1_HIT_RPROT 0x4E0730 + +#define mmDMA_IF_E_N_DMA1_HIT_WPROT 0x4E0734 + +#define mmDMA_IF_E_N_DMA1_HIT_RPRIV 0x4E0738 + +#define mmDMA_IF_E_N_DMA1_HIT_WPRIV 0x4E073C + +#define mmDMA_IF_E_N_HBM_BIN 0x4E0800 + +#define mmDMA_IF_E_N_MME_BIN 0x4E0804 + +#define mmDMA_IF_E_N_TPC_BIN 0x4E0808 + +#define mmDMA_IF_E_N_DMA_BIN 0x4E080C + +#define mmDMA_IF_E_N_SOB_CG_EN 0x4E0810 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_0 0x4E0820 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_1 0x4E0824 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_2 0x4E0828 + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_3 0x4E082C + +#define mmDMA_IF_E_N_HBM_I2C_ADDR_4 0x4E0830 + +#define mmDMA_IF_E_N_HBM_MISC 0x4E0834 + +#endif /* ASIC_REG_DMA_IF_E_N_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h new file mode 100644 index 000000000000..cd61289a1e8a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_S_DOWN_CH0_PERM_SEL 0x4A1108 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_0 0x4A1114 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_1 0x4A1118 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_2 0x4A111C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_3 0x4A1120 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_4 0x4A1124 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_5 0x4A1128 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_6 0x4A112C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_7 0x4A1130 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_8 0x4A1134 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_9 0x4A1138 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_10 0x4A113C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_11 0x4A1140 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_12 0x4A1144 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_13 0x4A1148 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_14 0x4A114C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_15 0x4A1150 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_16 0x4A1154 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_17 0x4A1158 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_18 0x4A115C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_19 0x4A1160 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_20 0x4A1164 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_21 0x4A1168 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_22 0x4A116C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_23 0x4A1170 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_24 0x4A1174 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_25 0x4A1178 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_26 0x4A117C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_27 0x4A1180 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_0 0x4A1184 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_1 0x4A1188 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_2 0x4A118C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_3 0x4A1190 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_4 0x4A1194 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_5 0x4A1198 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_6 0x4A119C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_7 0x4A11A0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_8 0x4A11A4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_9 0x4A11A8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_10 0x4A11AC + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_11 0x4A11B0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_12 0x4A11B4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_13 0x4A11B8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_14 0x4A11BC + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN 0x4A126C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN 0x4A1274 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT 0x4A1278 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST 0x4A127C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT 0x4A1280 + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN 0x4A1284 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_EN 0x4A1288 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_SAT 0x4A128C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_RST 0x4A1290 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_TIMEOUT 0x4A1294 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN 0x4A129C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT 0x4A12A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST 0x4A12A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4A12AC + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RED 0x4A12B4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN 0x4A12EC + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN 0x4A12F0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4A12F4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4A12F8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4A1404 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4A1408 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4A140C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4A1410 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4A1414 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4A1418 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x4A141C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x4A1420 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4A1424 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4A1428 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4A142C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4A1430 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4A1434 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4A1438 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0 0x4A1450 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1 0x4A1454 + +#define mmDMA_IF_E_S_DOWN_CH0_NON_LIN_EN 0x4A1480 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_0 0x4A1500 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_1 0x4A1504 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_2 0x4A1508 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_3 0x4A150C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_4 0x4A1510 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x4A1514 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x4A1520 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x4A1524 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x4A1528 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x4A152C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x4A1530 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x4A1534 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x4A1538 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x4A153C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x4A1540 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_0 0x4A1550 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_1 0x4A1554 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_2 0x4A1558 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_3 0x4A155C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_4 0x4A1560 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_5 0x4A1564 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_6 0x4A1568 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_7 0x4A156C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_8 0x4A1570 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_9 0x4A1574 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_10 0x4A1578 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_11 0x4A157C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_12 0x4A1580 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_13 0x4A1584 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_14 0x4A1588 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_15 0x4A158C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_16 0x4A1590 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_17 0x4A1594 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18 0x4A1598 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4A15E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4A15E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4A15EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4A15F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4A15F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4A15F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4A15FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4A1600 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4A1604 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4A1608 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4A160C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4A1610 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4A1614 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4A1618 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4A161C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4A1620 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4A1624 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4A1628 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4A162C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4A1630 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4A1634 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4A1638 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4A163C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4A1640 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4A1644 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4A1648 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4A164C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4A1650 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4A1654 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4A1658 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4A165C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4A1660 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4A1664 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4A1668 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4A166C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4A1670 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4A1674 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4A1678 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4A167C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4A1680 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4A1684 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4A1688 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4A168C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4A1690 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4A1694 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4A1698 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4A169C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4A16A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4A16A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4A16A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4A16AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4A16B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4A16B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4A16B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4A16BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4A16C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4A16C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4A16C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4A16CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4A16D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4A16D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4A16D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4A16DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4A16E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4A16E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4A16E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4A16EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4A16F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4A16F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4A16F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4A16FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4A1700 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4A1704 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4A1708 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4A170C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4A1710 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4A1714 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4A1718 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4A171C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4A1720 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4A1724 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4A1728 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4A172C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4A1730 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4A1734 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4A1738 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4A173C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4A1740 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4A1744 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4A1748 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4A174C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4A1750 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4A1754 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4A1758 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4A175C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4A1760 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4A1764 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4A1768 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4A176C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4A1770 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4A1774 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4A1778 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4A177C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4A1780 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4A1784 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4A1788 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4A178C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4A1790 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4A1794 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4A1798 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4A179C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4A17A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4A17A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4A17A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4A17AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4A17B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4A17B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4A17B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4A17BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4A17C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4A17C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4A17C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4A17CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4A17D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4A17D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4A17D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4A17DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4A17E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4A1824 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4A1828 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4A182C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4A1830 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4A1834 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4A1838 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4A183C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4A1840 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4A1844 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4A1848 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4A184C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4A1850 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4A1854 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4A1858 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4A185C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4A1860 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4A1864 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4A1868 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4A186C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4A1870 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4A1874 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4A1878 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4A187C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4A1880 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4A1884 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4A1888 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4A188C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4A1890 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4A1894 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4A1898 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4A189C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4A18A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4A18A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4A18A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4A18AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4A18B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4A18B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4A18B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4A18BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4A18C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4A18C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4A18C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4A18CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4A18D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4A18D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4A18D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4A18DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4A18E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4A18E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4A18E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4A18EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4A18F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4A18F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4A18F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4A18FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4A1900 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4A1904 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4A1908 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4A190C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4A1910 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4A1914 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4A1918 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4A191C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4A1920 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4A1924 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4A1928 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4A192C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4A1930 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4A1934 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4A1938 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4A193C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4A1940 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4A1944 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4A1948 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4A194C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4A1950 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4A1954 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4A1958 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4A195C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4A1960 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4A1964 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4A1968 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4A196C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4A1970 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4A1974 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4A1978 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4A197C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4A1980 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4A1984 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4A1988 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4A198C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4A1990 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4A1994 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4A1998 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4A199C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4A19A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4A19A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4A19A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4A19AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4A19B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4A19B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4A19B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4A19BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4A19C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4A19C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4A19C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4A19CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4A19D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4A19D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4A19D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4A19DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4A19E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4A19E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4A19E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4A19EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4A19F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4A19F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4A19F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4A19FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4A1A00 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4A1A04 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4A1A08 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4A1A0C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4A1A10 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4A1A14 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4A1A18 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4A1A1C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4A1A20 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x4A1A64 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x4A1A68 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4A1A6C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4A1A70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_CFG 0x4A1B64 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_SHIFT 0x4A1B68 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4A1B6C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4A1B70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4A1B74 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4A1B78 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4A1B7C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4A1B80 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4A1B84 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4A1B88 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_0 0x4A1BAC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_1 0x4A1BB0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_2 0x4A1BB4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_3 0x4A1BB8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_4 0x4A1BBC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_5 0x4A1BC0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_6 0x4A1BC4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_7 0x4A1BC8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_0 0x4A1BEC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_1 0x4A1BF0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_2 0x4A1BF4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_3 0x4A1BF8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_4 0x4A1BFC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_5 0x4A1C00 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_6 0x4A1C04 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_7 0x4A1C08 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_WDT 0x4A1C2C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A1C30 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A1C34 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A1C38 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A1C3C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A1C40 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A1C44 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A1C48 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A1C4C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4A1C50 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4A1C54 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4A1C58 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4A1C5C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4A1C60 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4A1C64 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4A1C68 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4A1C6C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A1C70 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A1C74 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A1C78 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A1C7C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A1C80 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A1C84 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A1C88 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A1C8C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4A1C90 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4A1C94 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4A1C98 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4A1C9C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4A1CA0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4A1CA4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4A1CA8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4A1CAC + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x4A1CB0 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x4A1CB4 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x4A1CB8 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x4A1CBC + +#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h new file mode 100644 index 000000000000..3f32370a14c7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_S_DOWN_CH1_PERM_SEL 0x4A2108 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_0 0x4A2114 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_1 0x4A2118 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_2 0x4A211C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_3 0x4A2120 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_4 0x4A2124 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_5 0x4A2128 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_6 0x4A212C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_7 0x4A2130 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_8 0x4A2134 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_9 0x4A2138 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_10 0x4A213C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_11 0x4A2140 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_12 0x4A2144 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_13 0x4A2148 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_14 0x4A214C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_15 0x4A2150 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_16 0x4A2154 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_17 0x4A2158 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_18 0x4A215C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_19 0x4A2160 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_20 0x4A2164 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_21 0x4A2168 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_22 0x4A216C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_23 0x4A2170 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_24 0x4A2174 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_25 0x4A2178 + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_26 0x4A217C + +#define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_27 0x4A2180 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_0 0x4A2184 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_1 0x4A2188 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_2 0x4A218C + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_3 0x4A2190 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_4 0x4A2194 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_5 0x4A2198 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_6 0x4A219C + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_7 0x4A21A0 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_8 0x4A21A4 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_9 0x4A21A8 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_10 0x4A21AC + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_11 0x4A21B0 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_12 0x4A21B4 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_13 0x4A21B8 + +#define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_14 0x4A21BC + +#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN 0x4A226C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN 0x4A2274 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT 0x4A2278 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST 0x4A227C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT 0x4A2280 + +#define mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN 0x4A2284 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_EN 0x4A2288 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_SAT 0x4A228C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_RST 0x4A2290 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_TIMEOUT 0x4A2294 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN 0x4A229C + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT 0x4A22A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST 0x4A22A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4A22AC + +#define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RED 0x4A22B4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN 0x4A22EC + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN 0x4A22F0 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4A22F4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4A22F8 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4A2404 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4A2408 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4A240C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4A2410 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4A2414 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4A2418 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x4A241C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x4A2420 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4A2424 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4A2428 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4A242C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4A2430 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4A2434 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4A2438 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0 0x4A2450 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1 0x4A2454 + +#define mmDMA_IF_E_S_DOWN_CH1_NON_LIN_EN 0x4A2480 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_0 0x4A2500 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_1 0x4A2504 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_2 0x4A2508 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_3 0x4A250C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_4 0x4A2510 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x4A2514 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x4A2520 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x4A2524 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x4A2528 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x4A252C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x4A2530 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x4A2534 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x4A2538 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x4A253C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x4A2540 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_0 0x4A2550 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_1 0x4A2554 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_2 0x4A2558 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_3 0x4A255C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_4 0x4A2560 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_5 0x4A2564 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_6 0x4A2568 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_7 0x4A256C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_8 0x4A2570 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_9 0x4A2574 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_10 0x4A2578 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_11 0x4A257C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_12 0x4A2580 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_13 0x4A2584 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_14 0x4A2588 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_15 0x4A258C + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_16 0x4A2590 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_17 0x4A2594 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18 0x4A2598 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4A25E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4A25E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4A25EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4A25F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4A25F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4A25F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4A25FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4A2600 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4A2604 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4A2608 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4A260C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4A2610 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4A2614 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4A2618 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4A261C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4A2620 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4A2624 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4A2628 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4A262C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4A2630 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4A2634 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4A2638 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4A263C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4A2640 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4A2644 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4A2648 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4A264C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4A2650 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4A2654 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4A2658 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4A265C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4A2660 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4A2664 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4A2668 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4A266C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4A2670 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4A2674 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4A2678 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4A267C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4A2680 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4A2684 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4A2688 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4A268C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4A2690 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4A2694 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4A2698 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4A269C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4A26A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4A26A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4A26A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4A26AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4A26B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4A26B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4A26B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4A26BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4A26C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4A26C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4A26C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4A26CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4A26D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4A26D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4A26D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4A26DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4A26E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4A26E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4A26E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4A26EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4A26F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4A26F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4A26F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4A26FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4A2700 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4A2704 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4A2708 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4A270C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4A2710 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4A2714 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4A2718 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4A271C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4A2720 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4A2724 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4A2728 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4A272C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4A2730 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4A2734 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4A2738 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4A273C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4A2740 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4A2744 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4A2748 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4A274C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4A2750 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4A2754 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4A2758 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4A275C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4A2760 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4A2764 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4A2768 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4A276C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4A2770 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4A2774 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4A2778 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4A277C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4A2780 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4A2784 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4A2788 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4A278C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4A2790 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4A2794 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4A2798 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4A279C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4A27A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4A27A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4A27A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4A27AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4A27B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4A27B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4A27B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4A27BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4A27C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4A27C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4A27C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4A27CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4A27D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4A27D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4A27D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4A27DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4A27E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4A2824 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4A2828 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4A282C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4A2830 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4A2834 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4A2838 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4A283C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4A2840 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4A2844 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4A2848 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4A284C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4A2850 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4A2854 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4A2858 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4A285C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4A2860 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4A2864 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4A2868 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4A286C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4A2870 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4A2874 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4A2878 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4A287C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4A2880 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4A2884 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4A2888 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4A288C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4A2890 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4A2894 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4A2898 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4A289C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4A28A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4A28A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4A28A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4A28AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4A28B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4A28B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4A28B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4A28BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4A28C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4A28C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4A28C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4A28CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4A28D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4A28D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4A28D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4A28DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4A28E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4A28E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4A28E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4A28EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4A28F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4A28F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4A28F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4A28FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4A2900 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4A2904 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4A2908 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4A290C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4A2910 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4A2914 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4A2918 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4A291C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4A2920 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4A2924 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4A2928 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4A292C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4A2930 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4A2934 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4A2938 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4A293C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4A2940 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4A2944 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4A2948 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4A294C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4A2950 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4A2954 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4A2958 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4A295C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4A2960 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4A2964 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4A2968 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4A296C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4A2970 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4A2974 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4A2978 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4A297C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4A2980 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4A2984 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4A2988 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4A298C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4A2990 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4A2994 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4A2998 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4A299C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4A29A0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4A29A4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4A29A8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4A29AC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4A29B0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4A29B4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4A29B8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4A29BC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4A29C0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4A29C4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4A29C8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4A29CC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4A29D0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4A29D4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4A29D8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4A29DC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4A29E0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4A29E4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4A29E8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4A29EC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4A29F0 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4A29F4 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4A29F8 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4A29FC + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4A2A00 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4A2A04 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4A2A08 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4A2A0C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4A2A10 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4A2A14 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4A2A18 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4A2A1C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4A2A20 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x4A2A64 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x4A2A68 + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4A2A6C + +#define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4A2A70 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_CFG 0x4A2B64 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_SHIFT 0x4A2B68 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4A2B6C + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4A2B70 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4A2B74 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4A2B78 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4A2B7C + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4A2B80 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4A2B84 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4A2B88 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_0 0x4A2BAC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_1 0x4A2BB0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_2 0x4A2BB4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_3 0x4A2BB8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_4 0x4A2BBC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_5 0x4A2BC0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_6 0x4A2BC4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_7 0x4A2BC8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_0 0x4A2BEC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_1 0x4A2BF0 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_2 0x4A2BF4 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_3 0x4A2BF8 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_4 0x4A2BFC + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_5 0x4A2C00 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_6 0x4A2C04 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_7 0x4A2C08 + +#define mmDMA_IF_E_S_DOWN_CH1_RGL_WDT 0x4A2C2C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A2C30 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A2C34 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A2C38 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A2C3C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A2C40 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A2C44 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A2C48 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A2C4C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4A2C50 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4A2C54 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4A2C58 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4A2C5C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4A2C60 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4A2C64 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4A2C68 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4A2C6C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A2C70 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A2C74 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A2C78 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A2C7C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A2C80 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A2C84 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A2C88 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A2C8C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4A2C90 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4A2C94 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4A2C98 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4A2C9C + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4A2CA0 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4A2CA4 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4A2CA8 + +#define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4A2CAC + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x4A2CB0 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x4A2CB4 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x4A2CB8 + +#define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x4A2CBC + +#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h new file mode 100644 index 000000000000..78c18da7154b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_e_s_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_E_S_HBM0_WR_CRED_CNT 0x4A0000 + +#define mmDMA_IF_E_S_HBM1_WR_CRED_CNT 0x4A0004 + +#define mmDMA_IF_E_S_HBM0_RD_CRED_CNT 0x4A0008 + +#define mmDMA_IF_E_S_HBM1_RD_CRED_CNT 0x4A000C + +#define mmDMA_IF_E_S_HBM_LIMITER_0 0x4A0030 + +#define mmDMA_IF_E_S_HBM_LIMITER_1 0x4A0034 + +#define mmDMA_IF_E_S_HBM_LIMITER_2 0x4A0038 + +#define mmDMA_IF_E_S_HBM_LIMITER_3 0x4A003C + +#define mmDMA_IF_E_S_HBM_ALMOST_EN_0 0x4A0040 + +#define mmDMA_IF_E_S_HBM_ALMOST_EN_1 0x4A0044 + +#define mmDMA_IF_E_S_HBM_CRED_EN_0 0x4A0050 + +#define mmDMA_IF_E_S_HBM_CRED_EN_1 0x4A0054 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_0 0x4A0100 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_1 0x4A0104 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_2 0x4A0108 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_3 0x4A010C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_4 0x4A0110 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_5 0x4A0114 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_6 0x4A0118 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_7 0x4A011C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_8 0x4A0120 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_9 0x4A0124 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_10 0x4A0128 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_11 0x4A012C + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_12 0x4A0130 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_13 0x4A0134 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_14 0x4A0138 + +#define mmDMA_IF_E_S_SOB_MIN_RPROT_15 0x4A013C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_0 0x4A0140 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_1 0x4A0144 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_2 0x4A0148 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_3 0x4A014C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_4 0x4A0150 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_5 0x4A0154 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_6 0x4A0158 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_7 0x4A015C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_8 0x4A0160 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_9 0x4A0164 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_10 0x4A0168 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_11 0x4A016C + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_12 0x4A0170 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_13 0x4A0174 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_14 0x4A0178 + +#define mmDMA_IF_E_S_SOB_MAX_RPROT_15 0x4A017C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_0 0x4A0180 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_1 0x4A0184 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_2 0x4A0188 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_3 0x4A018C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_4 0x4A0190 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_5 0x4A0194 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_6 0x4A0198 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_7 0x4A019C + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_8 0x4A01A0 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_9 0x4A01A4 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_10 0x4A01A8 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_11 0x4A01AC + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_12 0x4A01B0 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_13 0x4A01B4 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_14 0x4A01B8 + +#define mmDMA_IF_E_S_SOB_MIN_WPROT_15 0x4A01BC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_0 0x4A01C0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_1 0x4A01C4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_2 0x4A01C8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_3 0x4A01CC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_4 0x4A01D0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_5 0x4A01D4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_6 0x4A01D8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_7 0x4A01DC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_8 0x4A01E0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_9 0x4A01E4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_10 0x4A01E8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_11 0x4A01EC + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_12 0x4A01F0 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_13 0x4A01F4 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_14 0x4A01F8 + +#define mmDMA_IF_E_S_SOB_MAX_WPROT_15 0x4A01FC + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_0 0x4A0200 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_1 0x4A0204 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_2 0x4A0208 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_3 0x4A020C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_4 0x4A0210 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_5 0x4A0214 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_6 0x4A0218 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_7 0x4A021C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_8 0x4A0220 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_9 0x4A0224 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_10 0x4A0228 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_11 0x4A022C + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_12 0x4A0230 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_13 0x4A0234 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_14 0x4A0238 + +#define mmDMA_IF_E_S_SOB_MIN_RPRIV_15 0x4A023C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_0 0x4A0240 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_1 0x4A0244 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_2 0x4A0248 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_3 0x4A024C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_4 0x4A0250 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_5 0x4A0254 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_6 0x4A0258 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_7 0x4A025C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_8 0x4A0260 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_9 0x4A0264 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_10 0x4A0268 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_11 0x4A026C + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_12 0x4A0270 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_13 0x4A0274 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_14 0x4A0278 + +#define mmDMA_IF_E_S_SOB_MAX_RPRIV_15 0x4A027C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_0 0x4A0280 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_1 0x4A0284 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_2 0x4A0288 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_3 0x4A028C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_4 0x4A0290 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_5 0x4A0294 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_6 0x4A0298 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_7 0x4A029C + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_8 0x4A02A0 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_9 0x4A02A4 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_10 0x4A02A8 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_11 0x4A02AC + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_12 0x4A02B0 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_13 0x4A02B4 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_14 0x4A02B8 + +#define mmDMA_IF_E_S_SOB_MIN_WPRIV_15 0x4A02BC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_0 0x4A02C0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_1 0x4A02C4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_2 0x4A02C8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_3 0x4A02CC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_4 0x4A02D0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_5 0x4A02D4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_6 0x4A02D8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_7 0x4A02DC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_8 0x4A02E0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_9 0x4A02E4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_10 0x4A02E8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_11 0x4A02EC + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_12 0x4A02F0 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_13 0x4A02F4 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_14 0x4A02F8 + +#define mmDMA_IF_E_S_SOB_MAX_WPRIV_15 0x4A02FC + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_0 0x4A0300 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_1 0x4A0304 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_2 0x4A0308 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_3 0x4A030C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_4 0x4A0310 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_5 0x4A0314 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_6 0x4A0318 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_7 0x4A031C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_8 0x4A0320 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_9 0x4A0324 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_10 0x4A0328 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_11 0x4A032C + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_12 0x4A0330 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_13 0x4A0334 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_14 0x4A0338 + +#define mmDMA_IF_E_S_DMA0_MIN_RPROT_15 0x4A033C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_0 0x4A0340 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_1 0x4A0344 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_2 0x4A0348 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_3 0x4A034C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_4 0x4A0350 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_5 0x4A0354 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_6 0x4A0358 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_7 0x4A035C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_8 0x4A0360 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_9 0x4A0364 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_10 0x4A0368 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_11 0x4A036C + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_12 0x4A0370 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_13 0x4A0374 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_14 0x4A0378 + +#define mmDMA_IF_E_S_DMA0_MAX_RPROT_15 0x4A037C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_0 0x4A0380 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_1 0x4A0384 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_2 0x4A0388 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_3 0x4A038C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_4 0x4A0390 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_5 0x4A0394 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_6 0x4A0398 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_7 0x4A039C + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_8 0x4A03A0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_9 0x4A03A4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_10 0x4A03A8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_11 0x4A03AC + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_12 0x4A03B0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_13 0x4A03B4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_14 0x4A03B8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPROT_15 0x4A03BC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_0 0x4A03C0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_1 0x4A03C4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_2 0x4A03C8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_3 0x4A03CC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_4 0x4A03D0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_5 0x4A03D4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_6 0x4A03D8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_7 0x4A03DC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_8 0x4A03E0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_9 0x4A03E4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_10 0x4A03E8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_11 0x4A03EC + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_12 0x4A03F0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_13 0x4A03F4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_14 0x4A03F8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPROT_15 0x4A03FC + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_0 0x4A0400 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_1 0x4A0404 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_2 0x4A0408 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_3 0x4A040C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_4 0x4A0410 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_5 0x4A0414 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_6 0x4A0418 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_7 0x4A041C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_8 0x4A0420 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_9 0x4A0424 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_10 0x4A0428 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_11 0x4A042C + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_12 0x4A0430 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_13 0x4A0434 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_14 0x4A0438 + +#define mmDMA_IF_E_S_DMA0_MIN_RPRIV_15 0x4A043C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_0 0x4A0440 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_1 0x4A0444 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_2 0x4A0448 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_3 0x4A044C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_4 0x4A0450 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_5 0x4A0454 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_6 0x4A0458 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_7 0x4A045C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_8 0x4A0460 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_9 0x4A0464 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_10 0x4A0468 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_11 0x4A046C + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_12 0x4A0470 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_13 0x4A0474 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_14 0x4A0478 + +#define mmDMA_IF_E_S_DMA0_MAX_RPRIV_15 0x4A047C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_0 0x4A0480 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_1 0x4A0484 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_2 0x4A0488 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_3 0x4A048C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_4 0x4A0490 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_5 0x4A0494 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_6 0x4A0498 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_7 0x4A049C + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_8 0x4A04A0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_9 0x4A04A4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_10 0x4A04A8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_11 0x4A04AC + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_12 0x4A04B0 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_13 0x4A04B4 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_14 0x4A04B8 + +#define mmDMA_IF_E_S_DMA0_MIN_WPRIV_15 0x4A04BC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_0 0x4A04C0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_1 0x4A04C4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_2 0x4A04C8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_3 0x4A04CC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_4 0x4A04D0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_5 0x4A04D4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_6 0x4A04D8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_7 0x4A04DC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_8 0x4A04E0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_9 0x4A04E4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_10 0x4A04E8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_11 0x4A04EC + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_12 0x4A04F0 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_13 0x4A04F4 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_14 0x4A04F8 + +#define mmDMA_IF_E_S_DMA0_MAX_WPRIV_15 0x4A04FC + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_0 0x4A0500 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_1 0x4A0504 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_2 0x4A0508 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_3 0x4A050C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_4 0x4A0510 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_5 0x4A0514 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_6 0x4A0518 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_7 0x4A051C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_8 0x4A0520 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_9 0x4A0524 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_10 0x4A0528 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_11 0x4A052C + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_12 0x4A0530 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_13 0x4A0534 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_14 0x4A0538 + +#define mmDMA_IF_E_S_DMA1_MIN_RPROT_15 0x4A053C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_0 0x4A0540 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_1 0x4A0544 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_2 0x4A0548 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_3 0x4A054C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_4 0x4A0550 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_5 0x4A0554 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_6 0x4A0558 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_7 0x4A055C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_8 0x4A0560 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_9 0x4A0564 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_10 0x4A0568 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_11 0x4A056C + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_12 0x4A0570 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_13 0x4A0574 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_14 0x4A0578 + +#define mmDMA_IF_E_S_DMA1_MAX_RPROT_15 0x4A057C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_0 0x4A0580 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_1 0x4A0584 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_2 0x4A0588 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_3 0x4A058C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_4 0x4A0590 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_5 0x4A0594 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_6 0x4A0598 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_7 0x4A059C + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_8 0x4A05A0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_9 0x4A05A4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_10 0x4A05A8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_11 0x4A05AC + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_12 0x4A05B0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_13 0x4A05B4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_14 0x4A05B8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPROT_15 0x4A05BC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_0 0x4A05C0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_1 0x4A05C4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_2 0x4A05C8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_3 0x4A05CC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_4 0x4A05D0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_5 0x4A05D4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_6 0x4A05D8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_7 0x4A05DC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_8 0x4A05E0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_9 0x4A05E4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_10 0x4A05E8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_11 0x4A05EC + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_12 0x4A05F0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_13 0x4A05F4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_14 0x4A05F8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPROT_15 0x4A05FC + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_0 0x4A0600 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_1 0x4A0604 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_2 0x4A0608 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_3 0x4A060C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_4 0x4A0610 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_5 0x4A0614 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_6 0x4A0618 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_7 0x4A061C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_8 0x4A0620 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_9 0x4A0624 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_10 0x4A0628 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_11 0x4A062C + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_12 0x4A0630 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_13 0x4A0634 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_14 0x4A0638 + +#define mmDMA_IF_E_S_DMA1_MIN_RPRIV_15 0x4A063C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_0 0x4A0640 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_1 0x4A0644 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_2 0x4A0648 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_3 0x4A064C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_4 0x4A0650 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_5 0x4A0654 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_6 0x4A0658 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_7 0x4A065C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_8 0x4A0660 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_9 0x4A0664 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_10 0x4A0668 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_11 0x4A066C + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_12 0x4A0670 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_13 0x4A0674 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_14 0x4A0678 + +#define mmDMA_IF_E_S_DMA1_MAX_RPRIV_15 0x4A067C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_0 0x4A0680 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_1 0x4A0684 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_2 0x4A0688 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_3 0x4A068C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_4 0x4A0690 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_5 0x4A0694 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_6 0x4A0698 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_7 0x4A069C + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_8 0x4A06A0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_9 0x4A06A4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_10 0x4A06A8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_11 0x4A06AC + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_12 0x4A06B0 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_13 0x4A06B4 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_14 0x4A06B8 + +#define mmDMA_IF_E_S_DMA1_MIN_WPRIV_15 0x4A06BC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_0 0x4A06C0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_1 0x4A06C4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_2 0x4A06C8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_3 0x4A06CC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_4 0x4A06D0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_5 0x4A06D4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_6 0x4A06D8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_7 0x4A06DC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_8 0x4A06E0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_9 0x4A06E4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_10 0x4A06E8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_11 0x4A06EC + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_12 0x4A06F0 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_13 0x4A06F4 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_14 0x4A06F8 + +#define mmDMA_IF_E_S_DMA1_MAX_WPRIV_15 0x4A06FC + +#define mmDMA_IF_E_S_SOB_HIT_RPROT 0x4A0700 + +#define mmDMA_IF_E_S_SOB_HIT_WPROT 0x4A0704 + +#define mmDMA_IF_E_S_SOB_HIT_RPRIV 0x4A070C + +#define mmDMA_IF_E_S_SOB_HIT_WPRIV 0x4A0710 + +#define mmDMA_IF_E_S_DMA0_HIT_RPROT 0x4A071C + +#define mmDMA_IF_E_S_DMA0_HIT_WPROT 0x4A0720 + +#define mmDMA_IF_E_S_DMA0_HIT_RPRIV 0x4A0724 + +#define mmDMA_IF_E_S_DMA0_HIT_WPRIV 0x4A0728 + +#define mmDMA_IF_E_S_DMA1_HIT_RPROT 0x4A0730 + +#define mmDMA_IF_E_S_DMA1_HIT_WPROT 0x4A0734 + +#define mmDMA_IF_E_S_DMA1_HIT_RPRIV 0x4A0738 + +#define mmDMA_IF_E_S_DMA1_HIT_WPRIV 0x4A073C + +#define mmDMA_IF_E_S_HBM_BIN 0x4A0800 + +#define mmDMA_IF_E_S_MME_BIN 0x4A0804 + +#define mmDMA_IF_E_S_TPC_BIN 0x4A0808 + +#define mmDMA_IF_E_S_DMA_BIN 0x4A080C + +#define mmDMA_IF_E_S_SOB_CG_EN 0x4A0810 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_0 0x4A0820 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_1 0x4A0824 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_2 0x4A0828 + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_3 0x4A082C + +#define mmDMA_IF_E_S_HBM_I2C_ADDR_4 0x4A0830 + +#define mmDMA_IF_E_S_HBM_MISC 0x4A0834 + +#endif /* ASIC_REG_DMA_IF_E_S_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h new file mode 100644 index 000000000000..4ccaf8712948 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_N_DOWN_CH0_PERM_SEL 0x4C1108 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_0 0x4C1114 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_1 0x4C1118 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_2 0x4C111C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_3 0x4C1120 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_4 0x4C1124 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_5 0x4C1128 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_6 0x4C112C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_7 0x4C1130 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_8 0x4C1134 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_9 0x4C1138 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_10 0x4C113C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_11 0x4C1140 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_12 0x4C1144 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_13 0x4C1148 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_14 0x4C114C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_15 0x4C1150 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_16 0x4C1154 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_17 0x4C1158 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_18 0x4C115C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_19 0x4C1160 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_20 0x4C1164 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_21 0x4C1168 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_22 0x4C116C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_23 0x4C1170 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_24 0x4C1174 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_25 0x4C1178 + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_26 0x4C117C + +#define mmDMA_IF_W_N_DOWN_CH0_HBM_POLY_H3_27 0x4C1180 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_0 0x4C1184 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_1 0x4C1188 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_2 0x4C118C + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_3 0x4C1190 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_4 0x4C1194 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_5 0x4C1198 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_6 0x4C119C + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_7 0x4C11A0 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_8 0x4C11A4 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_9 0x4C11A8 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_10 0x4C11AC + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_11 0x4C11B0 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_12 0x4C11B4 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_13 0x4C11B8 + +#define mmDMA_IF_W_N_DOWN_CH0_SRAM_POLY_H3_14 0x4C11BC + +#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_SRAM_EN 0x4C126C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_EN 0x4C1274 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_SAT 0x4C1278 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_RST 0x4C127C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_HBM_TIMEOUT 0x4C1280 + +#define mmDMA_IF_W_N_DOWN_CH0_SCRAM_HBM_EN 0x4C1284 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_EN 0x4C1288 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_SAT 0x4C128C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_RST 0x4C1290 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_PCI_TIMEOUT 0x4C1294 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_EN 0x4C129C + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_SAT 0x4C12A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RST 0x4C12A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_TIMEOUT 0x4C12AC + +#define mmDMA_IF_W_N_DOWN_CH0_RL_SRAM_RED 0x4C12B4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_EN 0x4C12EC + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_EN 0x4C12F0 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_WR_SIZE 0x4C12F4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_WR_SIZE 0x4C12F8 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4C1404 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4C1408 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4C140C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4C1410 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4C1414 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4C1418 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_HBM_RD_SIZE 0x4C141C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_PCI_RD_SIZE 0x4C1420 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4C1424 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4C1428 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4C142C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4C1430 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4C1434 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4C1438 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_0 0x4C1450 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_SEL_1 0x4C1454 + +#define mmDMA_IF_W_N_DOWN_CH0_NON_LIN_EN 0x4C1480 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_0 0x4C1500 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_1 0x4C1504 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_2 0x4C1508 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_3 0x4C150C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_BANK_4 0x4C1510 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_0 0x4C1514 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_1 0x4C1520 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_2 0x4C1524 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_3 0x4C1528 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_4 0x4C152C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_5 0x4C1530 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_6 0x4C1534 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_7 0x4C1538 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_8 0x4C153C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_SRAM_OFFSET_9 0x4C1540 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_0 0x4C1550 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_1 0x4C1554 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_2 0x4C1558 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_3 0x4C155C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_4 0x4C1560 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_5 0x4C1564 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_6 0x4C1568 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_7 0x4C156C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_8 0x4C1570 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_9 0x4C1574 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_10 0x4C1578 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_11 0x4C157C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_12 0x4C1580 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_13 0x4C1584 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_14 0x4C1588 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_15 0x4C158C + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_16 0x4C1590 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_17 0x4C1594 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_OFFSET_18 0x4C1598 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4C15E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4C15E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4C15EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4C15F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4C15F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4C15F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4C15FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4C1600 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4C1604 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4C1608 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4C160C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4C1610 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4C1614 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4C1618 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4C161C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4C1620 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4C1624 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4C1628 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4C162C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4C1630 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4C1634 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4C1638 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4C163C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4C1640 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4C1644 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4C1648 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4C164C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4C1650 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4C1654 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4C1658 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4C165C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4C1660 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4C1664 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4C1668 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4C166C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4C1670 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4C1674 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4C1678 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4C167C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4C1680 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4C1684 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4C1688 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4C168C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4C1690 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4C1694 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4C1698 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4C169C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4C16A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4C16A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4C16A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4C16AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4C16B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4C16B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4C16B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4C16BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4C16C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4C16C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4C16C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4C16CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4C16D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4C16D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4C16D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4C16DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4C16E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4C16E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4C16E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4C16EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4C16F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4C16F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4C16F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4C16FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4C1700 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4C1704 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4C1708 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4C170C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4C1710 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4C1714 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4C1718 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4C171C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4C1720 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4C1724 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4C1728 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4C172C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4C1730 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4C1734 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4C1738 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4C173C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4C1740 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4C1744 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4C1748 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4C174C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4C1750 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4C1754 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4C1758 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4C175C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4C1760 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4C1764 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4C1768 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4C176C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4C1770 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4C1774 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4C1778 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4C177C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4C1780 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4C1784 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4C1788 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4C178C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4C1790 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4C1794 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4C1798 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4C179C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4C17A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4C17A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4C17A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4C17AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4C17B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4C17B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4C17B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4C17BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4C17C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4C17C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4C17C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4C17CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4C17D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4C17D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4C17D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4C17DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4C17E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4C1824 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4C1828 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4C182C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4C1830 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4C1834 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4C1838 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4C183C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4C1840 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4C1844 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4C1848 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4C184C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4C1850 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4C1854 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4C1858 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4C185C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4C1860 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4C1864 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4C1868 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4C186C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4C1870 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4C1874 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4C1878 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4C187C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4C1880 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4C1884 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4C1888 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4C188C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4C1890 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4C1894 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4C1898 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4C189C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4C18A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4C18A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4C18A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4C18AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4C18B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4C18B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4C18B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4C18BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4C18C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4C18C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4C18C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4C18CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4C18D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4C18D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4C18D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4C18DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4C18E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4C18E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4C18E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4C18EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4C18F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4C18F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4C18F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4C18FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4C1900 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4C1904 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4C1908 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4C190C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4C1910 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4C1914 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4C1918 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4C191C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4C1920 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4C1924 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4C1928 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4C192C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4C1930 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4C1934 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4C1938 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4C193C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4C1940 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4C1944 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4C1948 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4C194C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4C1950 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4C1954 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4C1958 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4C195C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4C1960 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4C1964 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4C1968 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4C196C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4C1970 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4C1974 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4C1978 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4C197C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4C1980 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4C1984 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4C1988 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4C198C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4C1990 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4C1994 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4C1998 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4C199C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4C19A0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4C19A4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4C19A8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4C19AC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4C19B0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4C19B4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4C19B8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4C19BC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4C19C0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4C19C4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4C19C8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4C19CC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4C19D0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4C19D4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4C19D8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4C19DC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4C19E0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4C19E4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4C19E8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4C19EC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4C19F0 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4C19F4 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4C19F8 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4C19FC + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4C1A00 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4C1A04 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4C1A08 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4C1A0C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4C1A10 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4C1A14 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4C1A18 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4C1A1C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4C1A20 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AW 0x4C1A64 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_SEC_HIT_AR 0x4C1A68 + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4C1A6C + +#define mmDMA_IF_W_N_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4C1A70 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_CFG 0x4C1B64 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_SHIFT 0x4C1B68 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4C1B6C + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4C1B70 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4C1B74 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4C1B78 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4C1B7C + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4C1B80 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4C1B84 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4C1B88 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_0 0x4C1BAC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_1 0x4C1BB0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_2 0x4C1BB4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_3 0x4C1BB8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_4 0x4C1BBC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_5 0x4C1BC0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_6 0x4C1BC4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_TOKEN_7 0x4C1BC8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_0 0x4C1BEC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_1 0x4C1BF0 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_2 0x4C1BF4 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_3 0x4C1BF8 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_4 0x4C1BFC + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_5 0x4C1C00 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_6 0x4C1C04 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_BANK_ID_7 0x4C1C08 + +#define mmDMA_IF_W_N_DOWN_CH0_RGL_WDT 0x4C1C2C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C1C30 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C1C34 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C1C38 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C1C3C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C1C40 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C1C44 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C1C48 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C1C4C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4C1C50 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4C1C54 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4C1C58 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4C1C5C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4C1C60 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4C1C64 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4C1C68 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4C1C6C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C1C70 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C1C74 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C1C78 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C1C7C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C1C80 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C1C84 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C1C88 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C1C8C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4C1C90 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4C1C94 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4C1C98 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4C1C9C + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4C1CA0 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4C1CA4 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4C1CA8 + +#define mmDMA_IF_W_N_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4C1CAC + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_0 0x4C1CB0 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_1 0x4C1CB4 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_2 0x4C1CB8 + +#define mmDMA_IF_W_N_DOWN_CH0_NL_HBM_PC_SEL_3 0x4C1CBC + +#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h new file mode 100644 index 000000000000..9236f4183084 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_N_DOWN_CH1_PERM_SEL 0x4C2108 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_0 0x4C2114 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_1 0x4C2118 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_2 0x4C211C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_3 0x4C2120 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_4 0x4C2124 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_5 0x4C2128 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_6 0x4C212C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_7 0x4C2130 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_8 0x4C2134 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_9 0x4C2138 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_10 0x4C213C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_11 0x4C2140 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_12 0x4C2144 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_13 0x4C2148 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_14 0x4C214C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_15 0x4C2150 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_16 0x4C2154 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_17 0x4C2158 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_18 0x4C215C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_19 0x4C2160 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_20 0x4C2164 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_21 0x4C2168 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_22 0x4C216C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_23 0x4C2170 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_24 0x4C2174 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_25 0x4C2178 + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_26 0x4C217C + +#define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_27 0x4C2180 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_0 0x4C2184 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_1 0x4C2188 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_2 0x4C218C + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_3 0x4C2190 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_4 0x4C2194 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_5 0x4C2198 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_6 0x4C219C + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_7 0x4C21A0 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_8 0x4C21A4 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_9 0x4C21A8 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_10 0x4C21AC + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_11 0x4C21B0 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_12 0x4C21B4 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_13 0x4C21B8 + +#define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_14 0x4C21BC + +#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN 0x4C226C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN 0x4C2274 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT 0x4C2278 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST 0x4C227C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4C2280 + +#define mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN 0x4C2284 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_EN 0x4C2288 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_SAT 0x4C228C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_RST 0x4C2290 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4C2294 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN 0x4C229C + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT 0x4C22A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST 0x4C22A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4C22AC + +#define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RED 0x4C22B4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN 0x4C22EC + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN 0x4C22F0 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4C22F4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4C22F8 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4C2404 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4C2408 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4C240C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4C2410 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4C2414 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4C2418 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4C241C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4C2420 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4C2424 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4C2428 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4C242C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4C2430 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4C2434 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4C2438 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0 0x4C2450 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1 0x4C2454 + +#define mmDMA_IF_W_N_DOWN_CH1_NON_LIN_EN 0x4C2480 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_0 0x4C2500 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_1 0x4C2504 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_2 0x4C2508 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_3 0x4C250C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_4 0x4C2510 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4C2514 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4C2520 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4C2524 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4C2528 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4C252C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4C2530 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4C2534 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4C2538 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4C253C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4C2540 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4C2550 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4C2554 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4C2558 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4C255C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4C2560 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4C2564 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4C2568 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4C256C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4C2570 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4C2574 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4C2578 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4C257C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4C2580 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4C2584 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4C2588 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4C258C + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4C2590 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4C2594 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4C2598 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4C25E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4C25E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4C25EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4C25F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4C25F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4C25F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4C25FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4C2600 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4C2604 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4C2608 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4C260C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4C2610 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4C2614 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4C2618 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4C261C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4C2620 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4C2624 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4C2628 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4C262C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4C2630 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4C2634 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4C2638 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4C263C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4C2640 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4C2644 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4C2648 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4C264C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4C2650 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4C2654 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4C2658 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4C265C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4C2660 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4C2664 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4C2668 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4C266C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4C2670 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4C2674 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4C2678 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4C267C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4C2680 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4C2684 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4C2688 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4C268C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4C2690 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4C2694 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4C2698 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4C269C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4C26A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4C26A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4C26A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4C26AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4C26B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4C26B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4C26B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4C26BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4C26C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4C26C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4C26C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4C26CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4C26D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4C26D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4C26D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4C26DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4C26E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4C26E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4C26E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4C26EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4C26F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4C26F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4C26F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4C26FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4C2700 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4C2704 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4C2708 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4C270C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4C2710 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4C2714 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4C2718 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4C271C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4C2720 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4C2724 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4C2728 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4C272C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4C2730 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4C2734 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4C2738 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4C273C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4C2740 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4C2744 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4C2748 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4C274C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4C2750 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4C2754 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4C2758 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4C275C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4C2760 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4C2764 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4C2768 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4C276C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4C2770 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4C2774 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4C2778 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4C277C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4C2780 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4C2784 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4C2788 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4C278C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4C2790 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4C2794 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4C2798 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4C279C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4C27A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4C27A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4C27A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4C27AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4C27B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4C27B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4C27B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4C27BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4C27C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4C27C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4C27C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4C27CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4C27D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4C27D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4C27D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4C27DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4C27E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4C2824 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4C2828 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4C282C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4C2830 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4C2834 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4C2838 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4C283C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4C2840 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4C2844 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4C2848 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4C284C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4C2850 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4C2854 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4C2858 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4C285C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4C2860 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4C2864 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4C2868 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4C286C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4C2870 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4C2874 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4C2878 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4C287C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4C2880 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4C2884 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4C2888 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4C288C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4C2890 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4C2894 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4C2898 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4C289C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4C28A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4C28A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4C28A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4C28AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4C28B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4C28B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4C28B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4C28BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4C28C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4C28C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4C28C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4C28CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4C28D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4C28D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4C28D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4C28DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4C28E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4C28E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4C28E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4C28EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4C28F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4C28F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4C28F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4C28FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4C2900 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4C2904 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4C2908 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4C290C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4C2910 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4C2914 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4C2918 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4C291C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4C2920 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4C2924 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4C2928 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4C292C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4C2930 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4C2934 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4C2938 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4C293C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4C2940 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4C2944 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4C2948 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4C294C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4C2950 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4C2954 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4C2958 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4C295C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4C2960 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4C2964 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4C2968 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4C296C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4C2970 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4C2974 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4C2978 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4C297C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4C2980 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4C2984 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4C2988 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4C298C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4C2990 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4C2994 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4C2998 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4C299C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4C29A0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4C29A4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4C29A8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4C29AC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4C29B0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4C29B4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4C29B8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4C29BC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4C29C0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4C29C4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4C29C8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4C29CC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4C29D0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4C29D4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4C29D8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4C29DC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4C29E0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4C29E4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4C29E8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4C29EC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4C29F0 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4C29F4 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4C29F8 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4C29FC + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4C2A00 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4C2A04 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4C2A08 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4C2A0C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4C2A10 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4C2A14 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4C2A18 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4C2A1C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4C2A20 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4C2A64 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4C2A68 + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4C2A6C + +#define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4C2A70 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_CFG 0x4C2B64 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_SHIFT 0x4C2B68 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4C2B6C + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4C2B70 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4C2B74 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4C2B78 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4C2B7C + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4C2B80 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4C2B84 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4C2B88 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_0 0x4C2BAC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_1 0x4C2BB0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_2 0x4C2BB4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_3 0x4C2BB8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_4 0x4C2BBC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_5 0x4C2BC0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_6 0x4C2BC4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_7 0x4C2BC8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_0 0x4C2BEC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_1 0x4C2BF0 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_2 0x4C2BF4 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_3 0x4C2BF8 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_4 0x4C2BFC + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_5 0x4C2C00 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_6 0x4C2C04 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_7 0x4C2C08 + +#define mmDMA_IF_W_N_DOWN_CH1_RGL_WDT 0x4C2C2C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C2C30 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C2C34 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C2C38 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C2C3C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C2C40 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C2C44 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C2C48 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C2C4C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4C2C50 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4C2C54 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4C2C58 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4C2C5C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4C2C60 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4C2C64 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4C2C68 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4C2C6C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C2C70 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C2C74 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C2C78 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C2C7C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C2C80 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C2C84 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C2C88 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C2C8C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4C2C90 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4C2C94 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4C2C98 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4C2C9C + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4C2CA0 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4C2CA4 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4C2CA8 + +#define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4C2CAC + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4C2CB0 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4C2CB4 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4C2CB8 + +#define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4C2CBC + +#endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h new file mode 100644 index 000000000000..da60893a5fab --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_n_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_N_REGS_H_ +#define ASIC_REG_DMA_IF_W_N_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_N (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_W_N_HBM0_WR_CRED_CNT 0x4C0000 + +#define mmDMA_IF_W_N_HBM1_WR_CRED_CNT 0x4C0004 + +#define mmDMA_IF_W_N_HBM0_RD_CRED_CNT 0x4C0008 + +#define mmDMA_IF_W_N_HBM1_RD_CRED_CNT 0x4C000C + +#define mmDMA_IF_W_N_HBM_LIMITER_0 0x4C0030 + +#define mmDMA_IF_W_N_HBM_LIMITER_1 0x4C0034 + +#define mmDMA_IF_W_N_HBM_LIMITER_2 0x4C0038 + +#define mmDMA_IF_W_N_HBM_LIMITER_3 0x4C003C + +#define mmDMA_IF_W_N_HBM_ALMOST_EN_0 0x4C0040 + +#define mmDMA_IF_W_N_HBM_ALMOST_EN_1 0x4C0044 + +#define mmDMA_IF_W_N_HBM_CRED_EN_0 0x4C0050 + +#define mmDMA_IF_W_N_HBM_CRED_EN_1 0x4C0054 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_0 0x4C0100 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_1 0x4C0104 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_2 0x4C0108 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_3 0x4C010C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_4 0x4C0110 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_5 0x4C0114 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_6 0x4C0118 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_7 0x4C011C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_8 0x4C0120 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_9 0x4C0124 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_10 0x4C0128 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_11 0x4C012C + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_12 0x4C0130 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_13 0x4C0134 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_14 0x4C0138 + +#define mmDMA_IF_W_N_SOB_MIN_RPROT_15 0x4C013C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_0 0x4C0140 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_1 0x4C0144 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_2 0x4C0148 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_3 0x4C014C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_4 0x4C0150 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_5 0x4C0154 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_6 0x4C0158 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_7 0x4C015C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_8 0x4C0160 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_9 0x4C0164 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_10 0x4C0168 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_11 0x4C016C + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_12 0x4C0170 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_13 0x4C0174 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_14 0x4C0178 + +#define mmDMA_IF_W_N_SOB_MAX_RPROT_15 0x4C017C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_0 0x4C0180 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_1 0x4C0184 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_2 0x4C0188 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_3 0x4C018C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_4 0x4C0190 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_5 0x4C0194 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_6 0x4C0198 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_7 0x4C019C + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_8 0x4C01A0 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_9 0x4C01A4 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_10 0x4C01A8 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_11 0x4C01AC + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_12 0x4C01B0 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_13 0x4C01B4 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_14 0x4C01B8 + +#define mmDMA_IF_W_N_SOB_MIN_WPROT_15 0x4C01BC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_0 0x4C01C0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_1 0x4C01C4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_2 0x4C01C8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_3 0x4C01CC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_4 0x4C01D0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_5 0x4C01D4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_6 0x4C01D8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_7 0x4C01DC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_8 0x4C01E0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_9 0x4C01E4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_10 0x4C01E8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_11 0x4C01EC + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_12 0x4C01F0 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_13 0x4C01F4 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_14 0x4C01F8 + +#define mmDMA_IF_W_N_SOB_MAX_WPROT_15 0x4C01FC + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_0 0x4C0200 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_1 0x4C0204 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_2 0x4C0208 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_3 0x4C020C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_4 0x4C0210 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_5 0x4C0214 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_6 0x4C0218 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_7 0x4C021C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_8 0x4C0220 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_9 0x4C0224 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_10 0x4C0228 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_11 0x4C022C + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_12 0x4C0230 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_13 0x4C0234 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_14 0x4C0238 + +#define mmDMA_IF_W_N_SOB_MIN_RPRIV_15 0x4C023C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_0 0x4C0240 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_1 0x4C0244 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_2 0x4C0248 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_3 0x4C024C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_4 0x4C0250 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_5 0x4C0254 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_6 0x4C0258 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_7 0x4C025C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_8 0x4C0260 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_9 0x4C0264 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_10 0x4C0268 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_11 0x4C026C + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_12 0x4C0270 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_13 0x4C0274 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_14 0x4C0278 + +#define mmDMA_IF_W_N_SOB_MAX_RPRIV_15 0x4C027C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_0 0x4C0280 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_1 0x4C0284 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_2 0x4C0288 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_3 0x4C028C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_4 0x4C0290 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_5 0x4C0294 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_6 0x4C0298 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_7 0x4C029C + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_8 0x4C02A0 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_9 0x4C02A4 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_10 0x4C02A8 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_11 0x4C02AC + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_12 0x4C02B0 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_13 0x4C02B4 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_14 0x4C02B8 + +#define mmDMA_IF_W_N_SOB_MIN_WPRIV_15 0x4C02BC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_0 0x4C02C0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_1 0x4C02C4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_2 0x4C02C8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_3 0x4C02CC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_4 0x4C02D0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_5 0x4C02D4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_6 0x4C02D8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_7 0x4C02DC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_8 0x4C02E0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_9 0x4C02E4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_10 0x4C02E8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_11 0x4C02EC + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_12 0x4C02F0 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_13 0x4C02F4 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_14 0x4C02F8 + +#define mmDMA_IF_W_N_SOB_MAX_WPRIV_15 0x4C02FC + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_0 0x4C0300 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_1 0x4C0304 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_2 0x4C0308 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_3 0x4C030C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_4 0x4C0310 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_5 0x4C0314 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_6 0x4C0318 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_7 0x4C031C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_8 0x4C0320 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_9 0x4C0324 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_10 0x4C0328 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_11 0x4C032C + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_12 0x4C0330 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_13 0x4C0334 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_14 0x4C0338 + +#define mmDMA_IF_W_N_DMA0_MIN_RPROT_15 0x4C033C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_0 0x4C0340 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_1 0x4C0344 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_2 0x4C0348 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_3 0x4C034C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_4 0x4C0350 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_5 0x4C0354 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_6 0x4C0358 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_7 0x4C035C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_8 0x4C0360 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_9 0x4C0364 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_10 0x4C0368 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_11 0x4C036C + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_12 0x4C0370 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_13 0x4C0374 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_14 0x4C0378 + +#define mmDMA_IF_W_N_DMA0_MAX_RPROT_15 0x4C037C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_0 0x4C0380 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_1 0x4C0384 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_2 0x4C0388 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_3 0x4C038C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_4 0x4C0390 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_5 0x4C0394 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_6 0x4C0398 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_7 0x4C039C + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_8 0x4C03A0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_9 0x4C03A4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_10 0x4C03A8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_11 0x4C03AC + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_12 0x4C03B0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_13 0x4C03B4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_14 0x4C03B8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPROT_15 0x4C03BC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_0 0x4C03C0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_1 0x4C03C4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_2 0x4C03C8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_3 0x4C03CC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_4 0x4C03D0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_5 0x4C03D4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_6 0x4C03D8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_7 0x4C03DC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_8 0x4C03E0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_9 0x4C03E4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_10 0x4C03E8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_11 0x4C03EC + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_12 0x4C03F0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_13 0x4C03F4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_14 0x4C03F8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPROT_15 0x4C03FC + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_0 0x4C0400 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_1 0x4C0404 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_2 0x4C0408 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_3 0x4C040C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_4 0x4C0410 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_5 0x4C0414 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_6 0x4C0418 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_7 0x4C041C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_8 0x4C0420 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_9 0x4C0424 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_10 0x4C0428 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_11 0x4C042C + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_12 0x4C0430 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_13 0x4C0434 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_14 0x4C0438 + +#define mmDMA_IF_W_N_DMA0_MIN_RPRIV_15 0x4C043C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_0 0x4C0440 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_1 0x4C0444 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_2 0x4C0448 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_3 0x4C044C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_4 0x4C0450 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_5 0x4C0454 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_6 0x4C0458 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_7 0x4C045C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_8 0x4C0460 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_9 0x4C0464 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_10 0x4C0468 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_11 0x4C046C + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_12 0x4C0470 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_13 0x4C0474 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_14 0x4C0478 + +#define mmDMA_IF_W_N_DMA0_MAX_RPRIV_15 0x4C047C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_0 0x4C0480 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_1 0x4C0484 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_2 0x4C0488 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_3 0x4C048C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_4 0x4C0490 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_5 0x4C0494 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_6 0x4C0498 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_7 0x4C049C + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_8 0x4C04A0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_9 0x4C04A4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_10 0x4C04A8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_11 0x4C04AC + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_12 0x4C04B0 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_13 0x4C04B4 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_14 0x4C04B8 + +#define mmDMA_IF_W_N_DMA0_MIN_WPRIV_15 0x4C04BC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_0 0x4C04C0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_1 0x4C04C4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_2 0x4C04C8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_3 0x4C04CC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_4 0x4C04D0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_5 0x4C04D4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_6 0x4C04D8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_7 0x4C04DC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_8 0x4C04E0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_9 0x4C04E4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_10 0x4C04E8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_11 0x4C04EC + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_12 0x4C04F0 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_13 0x4C04F4 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_14 0x4C04F8 + +#define mmDMA_IF_W_N_DMA0_MAX_WPRIV_15 0x4C04FC + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_0 0x4C0500 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_1 0x4C0504 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_2 0x4C0508 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_3 0x4C050C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_4 0x4C0510 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_5 0x4C0514 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_6 0x4C0518 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_7 0x4C051C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_8 0x4C0520 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_9 0x4C0524 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_10 0x4C0528 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_11 0x4C052C + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_12 0x4C0530 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_13 0x4C0534 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_14 0x4C0538 + +#define mmDMA_IF_W_N_DMA1_MIN_RPROT_15 0x4C053C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_0 0x4C0540 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_1 0x4C0544 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_2 0x4C0548 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_3 0x4C054C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_4 0x4C0550 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_5 0x4C0554 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_6 0x4C0558 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_7 0x4C055C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_8 0x4C0560 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_9 0x4C0564 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_10 0x4C0568 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_11 0x4C056C + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_12 0x4C0570 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_13 0x4C0574 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_14 0x4C0578 + +#define mmDMA_IF_W_N_DMA1_MAX_RPROT_15 0x4C057C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_0 0x4C0580 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_1 0x4C0584 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_2 0x4C0588 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_3 0x4C058C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_4 0x4C0590 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_5 0x4C0594 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_6 0x4C0598 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_7 0x4C059C + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_8 0x4C05A0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_9 0x4C05A4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_10 0x4C05A8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_11 0x4C05AC + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_12 0x4C05B0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_13 0x4C05B4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_14 0x4C05B8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPROT_15 0x4C05BC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_0 0x4C05C0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_1 0x4C05C4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_2 0x4C05C8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_3 0x4C05CC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_4 0x4C05D0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_5 0x4C05D4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_6 0x4C05D8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_7 0x4C05DC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_8 0x4C05E0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_9 0x4C05E4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_10 0x4C05E8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_11 0x4C05EC + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_12 0x4C05F0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_13 0x4C05F4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_14 0x4C05F8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPROT_15 0x4C05FC + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_0 0x4C0600 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_1 0x4C0604 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_2 0x4C0608 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_3 0x4C060C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_4 0x4C0610 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_5 0x4C0614 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_6 0x4C0618 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_7 0x4C061C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_8 0x4C0620 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_9 0x4C0624 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_10 0x4C0628 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_11 0x4C062C + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_12 0x4C0630 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_13 0x4C0634 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_14 0x4C0638 + +#define mmDMA_IF_W_N_DMA1_MIN_RPRIV_15 0x4C063C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_0 0x4C0640 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_1 0x4C0644 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_2 0x4C0648 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_3 0x4C064C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_4 0x4C0650 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_5 0x4C0654 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_6 0x4C0658 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_7 0x4C065C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_8 0x4C0660 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_9 0x4C0664 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_10 0x4C0668 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_11 0x4C066C + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_12 0x4C0670 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_13 0x4C0674 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_14 0x4C0678 + +#define mmDMA_IF_W_N_DMA1_MAX_RPRIV_15 0x4C067C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_0 0x4C0680 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_1 0x4C0684 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_2 0x4C0688 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_3 0x4C068C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_4 0x4C0690 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_5 0x4C0694 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_6 0x4C0698 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_7 0x4C069C + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_8 0x4C06A0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_9 0x4C06A4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_10 0x4C06A8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_11 0x4C06AC + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_12 0x4C06B0 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_13 0x4C06B4 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_14 0x4C06B8 + +#define mmDMA_IF_W_N_DMA1_MIN_WPRIV_15 0x4C06BC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_0 0x4C06C0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_1 0x4C06C4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_2 0x4C06C8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_3 0x4C06CC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_4 0x4C06D0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_5 0x4C06D4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_6 0x4C06D8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_7 0x4C06DC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_8 0x4C06E0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_9 0x4C06E4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_10 0x4C06E8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_11 0x4C06EC + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_12 0x4C06F0 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_13 0x4C06F4 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_14 0x4C06F8 + +#define mmDMA_IF_W_N_DMA1_MAX_WPRIV_15 0x4C06FC + +#define mmDMA_IF_W_N_SOB_HIT_RPROT 0x4C0700 + +#define mmDMA_IF_W_N_SOB_HIT_WPROT 0x4C0704 + +#define mmDMA_IF_W_N_SOB_HIT_RPRIV 0x4C070C + +#define mmDMA_IF_W_N_SOB_HIT_WPRIV 0x4C0710 + +#define mmDMA_IF_W_N_DMA0_HIT_RPROT 0x4C071C + +#define mmDMA_IF_W_N_DMA0_HIT_WPROT 0x4C0720 + +#define mmDMA_IF_W_N_DMA0_HIT_RPRIV 0x4C0724 + +#define mmDMA_IF_W_N_DMA0_HIT_WPRIV 0x4C0728 + +#define mmDMA_IF_W_N_DMA1_HIT_RPROT 0x4C0730 + +#define mmDMA_IF_W_N_DMA1_HIT_WPROT 0x4C0734 + +#define mmDMA_IF_W_N_DMA1_HIT_RPRIV 0x4C0738 + +#define mmDMA_IF_W_N_DMA1_HIT_WPRIV 0x4C073C + +#define mmDMA_IF_W_N_HBM_BIN 0x4C0800 + +#define mmDMA_IF_W_N_MME_BIN 0x4C0804 + +#define mmDMA_IF_W_N_TPC_BIN 0x4C0808 + +#define mmDMA_IF_W_N_DMA_BIN 0x4C080C + +#define mmDMA_IF_W_N_SOB_CG_EN 0x4C0810 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_0 0x4C0820 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_1 0x4C0824 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_2 0x4C0828 + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_3 0x4C082C + +#define mmDMA_IF_W_N_HBM_I2C_ADDR_4 0x4C0830 + +#define mmDMA_IF_W_N_HBM_MISC 0x4C0834 + +#endif /* ASIC_REG_DMA_IF_W_N_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h new file mode 100644 index 000000000000..56ffc920d58a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL 0x481108 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0 0x481114 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1 0x481118 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2 0x48111C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3 0x481120 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4 0x481124 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5 0x481128 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6 0x48112C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7 0x481130 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8 0x481134 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9 0x481138 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10 0x48113C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11 0x481140 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12 0x481144 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13 0x481148 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14 0x48114C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15 0x481150 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16 0x481154 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17 0x481158 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18 0x48115C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19 0x481160 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20 0x481164 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21 0x481168 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22 0x48116C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23 0x481170 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24 0x481174 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25 0x481178 + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26 0x48117C + +#define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27 0x481180 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0 0x481184 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1 0x481188 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2 0x48118C + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3 0x481190 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4 0x481194 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5 0x481198 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6 0x48119C + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7 0x4811A0 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8 0x4811A4 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9 0x4811A8 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10 0x4811AC + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11 0x4811B0 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_12 0x4811B4 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_13 0x4811B8 + +#define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_14 0x4811BC + +#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN 0x48126C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN 0x481274 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT 0x481278 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST 0x48127C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT 0x481280 + +#define mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN 0x481284 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_EN 0x481288 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_SAT 0x48128C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_RST 0x481290 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_TIMEOUT 0x481294 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN 0x48129C + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT 0x4812A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST 0x4812A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4812AC + +#define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RED 0x4812B4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN 0x4812EC + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN 0x4812F0 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4812F4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4812F8 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x481404 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x481408 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x48140C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x481410 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x481414 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x481418 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x48141C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x481420 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x481424 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x481428 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x48142C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x481430 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x481434 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x481438 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0 0x481450 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1 0x481454 + +#define mmDMA_IF_W_S_DOWN_CH0_NON_LIN_EN 0x481480 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_0 0x481500 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_1 0x481504 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_2 0x481508 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_3 0x48150C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_4 0x481510 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x481514 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x481520 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x481524 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x481528 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x48152C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x481530 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x481534 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x481538 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x48153C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x481540 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_0 0x481550 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_1 0x481554 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_2 0x481558 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_3 0x48155C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_4 0x481560 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_5 0x481564 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_6 0x481568 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_7 0x48156C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_8 0x481570 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_9 0x481574 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_10 0x481578 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_11 0x48157C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_12 0x481580 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_13 0x481584 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_14 0x481588 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_15 0x48158C + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_16 0x481590 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_17 0x481594 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18 0x481598 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4815E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4815E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4815EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4815F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4815F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4815F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4815FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x481600 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x481604 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x481608 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x48160C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x481610 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x481614 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x481618 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x48161C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x481620 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x481624 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x481628 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x48162C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x481630 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x481634 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x481638 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x48163C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x481640 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x481644 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x481648 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x48164C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x481650 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x481654 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x481658 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x48165C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x481660 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x481664 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x481668 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x48166C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x481670 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x481674 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x481678 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x48167C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x481680 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x481684 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x481688 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x48168C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x481690 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x481694 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x481698 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x48169C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4816A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4816A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4816A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4816AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4816B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4816B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4816B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4816BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4816C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4816C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4816C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4816CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4816D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4816D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4816D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4816DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4816E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4816E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4816E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4816EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4816F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4816F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4816F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4816FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x481700 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x481704 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x481708 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x48170C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x481710 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x481714 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x481718 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x48171C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x481720 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x481724 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x481728 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x48172C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x481730 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x481734 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x481738 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x48173C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x481740 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x481744 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x481748 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x48174C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x481750 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x481754 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x481758 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x48175C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x481760 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x481764 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x481768 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x48176C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x481770 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x481774 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x481778 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x48177C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x481780 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x481784 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x481788 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x48178C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x481790 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x481794 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x481798 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x48179C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4817A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4817A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4817A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4817AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4817B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4817B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4817B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4817BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4817C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4817C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4817C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4817CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4817D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4817D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4817D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4817DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4817E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x481824 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x481828 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x48182C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x481830 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x481834 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x481838 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x48183C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x481840 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x481844 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x481848 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x48184C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x481850 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x481854 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x481858 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x48185C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x481860 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x481864 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x481868 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x48186C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x481870 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x481874 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x481878 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x48187C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x481880 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x481884 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x481888 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x48188C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x481890 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x481894 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x481898 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x48189C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4818A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4818A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4818A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4818AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4818B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4818B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4818B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4818BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4818C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4818C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4818C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4818CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4818D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4818D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4818D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4818DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4818E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4818E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4818E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4818EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4818F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4818F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4818F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4818FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x481900 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x481904 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x481908 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x48190C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x481910 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x481914 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x481918 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x48191C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x481920 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x481924 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x481928 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x48192C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x481930 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x481934 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x481938 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x48193C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x481940 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x481944 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x481948 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x48194C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x481950 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x481954 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x481958 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x48195C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x481960 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x481964 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x481968 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x48196C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x481970 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x481974 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x481978 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x48197C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x481980 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x481984 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x481988 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x48198C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x481990 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x481994 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x481998 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x48199C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4819A0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4819A4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4819A8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4819AC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4819B0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4819B4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4819B8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4819BC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4819C0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4819C4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4819C8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4819CC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4819D0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4819D4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4819D8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4819DC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4819E0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4819E4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4819E8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4819EC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4819F0 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4819F4 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4819F8 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4819FC + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x481A00 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x481A04 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x481A08 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x481A0C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x481A10 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x481A14 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x481A18 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x481A1C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x481A20 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x481A64 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x481A68 + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x481A6C + +#define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x481A70 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_CFG 0x481B64 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_SHIFT 0x481B68 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x481B6C + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x481B70 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x481B74 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x481B78 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x481B7C + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x481B80 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x481B84 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x481B88 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_0 0x481BAC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_1 0x481BB0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_2 0x481BB4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_3 0x481BB8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_4 0x481BBC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_5 0x481BC0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_6 0x481BC4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_7 0x481BC8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_0 0x481BEC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_1 0x481BF0 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_2 0x481BF4 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_3 0x481BF8 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_4 0x481BFC + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_5 0x481C00 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_6 0x481C04 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_7 0x481C08 + +#define mmDMA_IF_W_S_DOWN_CH0_RGL_WDT 0x481C2C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x481C30 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x481C34 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x481C38 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x481C3C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x481C40 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x481C44 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x481C48 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x481C4C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x481C50 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x481C54 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x481C58 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x481C5C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x481C60 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x481C64 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x481C68 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x481C6C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x481C70 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x481C74 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x481C78 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x481C7C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x481C80 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x481C84 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x481C88 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x481C8C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x481C90 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x481C94 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x481C98 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x481C9C + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x481CA0 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x481CA4 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x481CA8 + +#define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x481CAC + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x481CB0 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x481CB4 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x481CB8 + +#define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x481CBC + +#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h new file mode 100644 index 000000000000..cbc642918deb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_down_ch1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S_DOWN_CH1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_W_S_DOWN_CH1_PERM_SEL 0x482108 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_0 0x482114 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_1 0x482118 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_2 0x48211C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_3 0x482120 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_4 0x482124 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_5 0x482128 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_6 0x48212C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_7 0x482130 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_8 0x482134 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_9 0x482138 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_10 0x48213C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_11 0x482140 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_12 0x482144 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_13 0x482148 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_14 0x48214C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_15 0x482150 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_16 0x482154 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_17 0x482158 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_18 0x48215C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_19 0x482160 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_20 0x482164 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_21 0x482168 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_22 0x48216C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_23 0x482170 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_24 0x482174 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_25 0x482178 + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_26 0x48217C + +#define mmDMA_IF_W_S_DOWN_CH1_HBM_POLY_H3_27 0x482180 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_0 0x482184 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_1 0x482188 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_2 0x48218C + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_3 0x482190 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_4 0x482194 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_5 0x482198 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_6 0x48219C + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_7 0x4821A0 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_8 0x4821A4 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_9 0x4821A8 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_10 0x4821AC + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_11 0x4821B0 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_12 0x4821B4 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_13 0x4821B8 + +#define mmDMA_IF_W_S_DOWN_CH1_SRAM_POLY_H3_14 0x4821BC + +#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_SRAM_EN 0x48226C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_EN 0x482274 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_SAT 0x482278 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_RST 0x48227C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_HBM_TIMEOUT 0x482280 + +#define mmDMA_IF_W_S_DOWN_CH1_SCRAM_HBM_EN 0x482284 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_EN 0x482288 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_SAT 0x48228C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_RST 0x482290 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_PCI_TIMEOUT 0x482294 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_EN 0x48229C + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_SAT 0x4822A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RST 0x4822A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4822AC + +#define mmDMA_IF_W_S_DOWN_CH1_RL_SRAM_RED 0x4822B4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_EN 0x4822EC + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_EN 0x4822F0 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4822F4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4822F8 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x482404 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x482408 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x48240C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x482410 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x482414 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x482418 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x48241C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x482420 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x482424 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x482428 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x48242C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x482430 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x482434 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x482438 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_0 0x482450 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_SEL_1 0x482454 + +#define mmDMA_IF_W_S_DOWN_CH1_NON_LIN_EN 0x482480 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_0 0x482500 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_1 0x482504 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_2 0x482508 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_3 0x48250C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_BANK_4 0x482510 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x482514 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x482520 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x482524 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x482528 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x48252C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x482530 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x482534 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x482538 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x48253C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x482540 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_0 0x482550 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_1 0x482554 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_2 0x482558 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_3 0x48255C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_4 0x482560 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_5 0x482564 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_6 0x482568 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_7 0x48256C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_8 0x482570 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_9 0x482574 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_10 0x482578 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_11 0x48257C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_12 0x482580 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_13 0x482584 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_14 0x482588 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_15 0x48258C + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_16 0x482590 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_17 0x482594 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_OFFSET_18 0x482598 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4825E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4825E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4825EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4825F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4825F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4825F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4825FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x482600 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x482604 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x482608 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x48260C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x482610 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x482614 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x482618 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x48261C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x482620 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x482624 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x482628 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x48262C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x482630 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x482634 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x482638 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x48263C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x482640 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x482644 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x482648 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x48264C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x482650 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x482654 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x482658 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x48265C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x482660 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x482664 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x482668 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x48266C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x482670 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x482674 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x482678 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x48267C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x482680 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x482684 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x482688 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x48268C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x482690 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x482694 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x482698 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x48269C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4826A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4826A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4826A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4826AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4826B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4826B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4826B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4826BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4826C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4826C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4826C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4826CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4826D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4826D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4826D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4826DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4826E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4826E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4826E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4826EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4826F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4826F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4826F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4826FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x482700 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x482704 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x482708 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x48270C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x482710 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x482714 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x482718 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x48271C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x482720 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x482724 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x482728 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x48272C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x482730 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x482734 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x482738 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x48273C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x482740 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x482744 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x482748 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x48274C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x482750 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x482754 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x482758 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x48275C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x482760 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x482764 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x482768 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x48276C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x482770 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x482774 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x482778 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x48277C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x482780 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x482784 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x482788 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x48278C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x482790 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x482794 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x482798 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x48279C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4827A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4827A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4827A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4827AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4827B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4827B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4827B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4827BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4827C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4827C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4827C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4827CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4827D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4827D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4827D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4827DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4827E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x482824 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x482828 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x48282C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x482830 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x482834 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x482838 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x48283C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x482840 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x482844 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x482848 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x48284C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x482850 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x482854 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x482858 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x48285C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x482860 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x482864 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x482868 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x48286C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x482870 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x482874 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x482878 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x48287C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x482880 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x482884 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x482888 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x48288C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x482890 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x482894 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x482898 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x48289C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4828A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4828A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4828A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4828AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4828B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4828B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4828B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4828BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4828C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4828C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4828C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4828CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4828D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4828D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4828D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4828DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4828E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4828E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4828E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4828EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4828F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4828F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4828F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4828FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x482900 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x482904 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x482908 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x48290C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x482910 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x482914 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x482918 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x48291C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x482920 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x482924 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x482928 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x48292C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x482930 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x482934 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x482938 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x48293C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x482940 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x482944 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x482948 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x48294C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x482950 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x482954 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x482958 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x48295C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x482960 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x482964 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x482968 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x48296C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x482970 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x482974 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x482978 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x48297C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x482980 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x482984 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x482988 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x48298C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x482990 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x482994 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x482998 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x48299C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4829A0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4829A4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4829A8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4829AC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4829B0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4829B4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4829B8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4829BC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4829C0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4829C4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4829C8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4829CC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4829D0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4829D4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4829D8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4829DC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4829E0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4829E4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4829E8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4829EC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4829F0 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4829F4 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4829F8 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4829FC + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x482A00 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x482A04 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x482A08 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x482A0C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x482A10 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x482A14 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x482A18 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x482A1C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x482A20 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x482A64 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x482A68 + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x482A6C + +#define mmDMA_IF_W_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x482A70 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_CFG 0x482B64 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_SHIFT 0x482B68 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x482B6C + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x482B70 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x482B74 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x482B78 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x482B7C + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x482B80 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x482B84 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x482B88 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_0 0x482BAC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_1 0x482BB0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_2 0x482BB4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_3 0x482BB8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_4 0x482BBC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_5 0x482BC0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_6 0x482BC4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_TOKEN_7 0x482BC8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_0 0x482BEC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_1 0x482BF0 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_2 0x482BF4 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_3 0x482BF8 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_4 0x482BFC + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_5 0x482C00 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_6 0x482C04 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_BANK_ID_7 0x482C08 + +#define mmDMA_IF_W_S_DOWN_CH1_RGL_WDT 0x482C2C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x482C30 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x482C34 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x482C38 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x482C3C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x482C40 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x482C44 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x482C48 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x482C4C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x482C50 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x482C54 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x482C58 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x482C5C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x482C60 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x482C64 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x482C68 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x482C6C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x482C70 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x482C74 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x482C78 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x482C7C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x482C80 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x482C84 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x482C88 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x482C8C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x482C90 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x482C94 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x482C98 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x482C9C + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x482CA0 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x482CA4 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x482CA8 + +#define mmDMA_IF_W_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x482CAC + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x482CB0 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x482CB4 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x482CB8 + +#define mmDMA_IF_W_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x482CBC + +#endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h new file mode 100644 index 000000000000..2382bc41bea6 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/dma_if_w_s_regs.h @@ -0,0 +1,860 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_W_S_REGS_H_ +#define ASIC_REG_DMA_IF_W_S_REGS_H_ + +/* + ***************************************** + * DMA_IF_W_S (Prototype: DMA_IF) + ***************************************** + */ + +#define mmDMA_IF_W_S_HBM0_WR_CRED_CNT 0x480000 + +#define mmDMA_IF_W_S_HBM1_WR_CRED_CNT 0x480004 + +#define mmDMA_IF_W_S_HBM0_RD_CRED_CNT 0x480008 + +#define mmDMA_IF_W_S_HBM1_RD_CRED_CNT 0x48000C + +#define mmDMA_IF_W_S_HBM_LIMITER_0 0x480030 + +#define mmDMA_IF_W_S_HBM_LIMITER_1 0x480034 + +#define mmDMA_IF_W_S_HBM_LIMITER_2 0x480038 + +#define mmDMA_IF_W_S_HBM_LIMITER_3 0x48003C + +#define mmDMA_IF_W_S_HBM_ALMOST_EN_0 0x480040 + +#define mmDMA_IF_W_S_HBM_ALMOST_EN_1 0x480044 + +#define mmDMA_IF_W_S_HBM_CRED_EN_0 0x480050 + +#define mmDMA_IF_W_S_HBM_CRED_EN_1 0x480054 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_0 0x480100 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_1 0x480104 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_2 0x480108 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_3 0x48010C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_4 0x480110 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_5 0x480114 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_6 0x480118 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_7 0x48011C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_8 0x480120 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_9 0x480124 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_10 0x480128 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_11 0x48012C + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_12 0x480130 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_13 0x480134 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_14 0x480138 + +#define mmDMA_IF_W_S_SOB_MIN_RPROT_15 0x48013C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_0 0x480140 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_1 0x480144 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_2 0x480148 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_3 0x48014C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_4 0x480150 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_5 0x480154 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_6 0x480158 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_7 0x48015C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_8 0x480160 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_9 0x480164 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_10 0x480168 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_11 0x48016C + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_12 0x480170 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_13 0x480174 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_14 0x480178 + +#define mmDMA_IF_W_S_SOB_MAX_RPROT_15 0x48017C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_0 0x480180 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_1 0x480184 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_2 0x480188 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_3 0x48018C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_4 0x480190 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_5 0x480194 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_6 0x480198 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_7 0x48019C + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_8 0x4801A0 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_9 0x4801A4 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_10 0x4801A8 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_11 0x4801AC + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_12 0x4801B0 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_13 0x4801B4 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_14 0x4801B8 + +#define mmDMA_IF_W_S_SOB_MIN_WPROT_15 0x4801BC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_0 0x4801C0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_1 0x4801C4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_2 0x4801C8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_3 0x4801CC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_4 0x4801D0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_5 0x4801D4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_6 0x4801D8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_7 0x4801DC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_8 0x4801E0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_9 0x4801E4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_10 0x4801E8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_11 0x4801EC + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_12 0x4801F0 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_13 0x4801F4 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_14 0x4801F8 + +#define mmDMA_IF_W_S_SOB_MAX_WPROT_15 0x4801FC + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_0 0x480200 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_1 0x480204 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_2 0x480208 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_3 0x48020C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_4 0x480210 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_5 0x480214 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_6 0x480218 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_7 0x48021C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_8 0x480220 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_9 0x480224 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_10 0x480228 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_11 0x48022C + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_12 0x480230 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_13 0x480234 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_14 0x480238 + +#define mmDMA_IF_W_S_SOB_MIN_RPRIV_15 0x48023C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_0 0x480240 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_1 0x480244 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_2 0x480248 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_3 0x48024C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_4 0x480250 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_5 0x480254 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_6 0x480258 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_7 0x48025C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_8 0x480260 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_9 0x480264 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_10 0x480268 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_11 0x48026C + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_12 0x480270 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_13 0x480274 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_14 0x480278 + +#define mmDMA_IF_W_S_SOB_MAX_RPRIV_15 0x48027C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_0 0x480280 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_1 0x480284 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_2 0x480288 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_3 0x48028C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_4 0x480290 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_5 0x480294 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_6 0x480298 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_7 0x48029C + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_8 0x4802A0 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_9 0x4802A4 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_10 0x4802A8 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_11 0x4802AC + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_12 0x4802B0 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_13 0x4802B4 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_14 0x4802B8 + +#define mmDMA_IF_W_S_SOB_MIN_WPRIV_15 0x4802BC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_0 0x4802C0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_1 0x4802C4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_2 0x4802C8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_3 0x4802CC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_4 0x4802D0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_5 0x4802D4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_6 0x4802D8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_7 0x4802DC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_8 0x4802E0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_9 0x4802E4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_10 0x4802E8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_11 0x4802EC + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_12 0x4802F0 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_13 0x4802F4 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_14 0x4802F8 + +#define mmDMA_IF_W_S_SOB_MAX_WPRIV_15 0x4802FC + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_0 0x480300 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_1 0x480304 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_2 0x480308 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_3 0x48030C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_4 0x480310 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_5 0x480314 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_6 0x480318 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_7 0x48031C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_8 0x480320 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_9 0x480324 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_10 0x480328 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_11 0x48032C + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_12 0x480330 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_13 0x480334 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_14 0x480338 + +#define mmDMA_IF_W_S_DMA0_MIN_RPROT_15 0x48033C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_0 0x480340 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_1 0x480344 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_2 0x480348 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_3 0x48034C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_4 0x480350 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_5 0x480354 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_6 0x480358 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_7 0x48035C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_8 0x480360 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_9 0x480364 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_10 0x480368 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_11 0x48036C + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_12 0x480370 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_13 0x480374 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_14 0x480378 + +#define mmDMA_IF_W_S_DMA0_MAX_RPROT_15 0x48037C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_0 0x480380 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_1 0x480384 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_2 0x480388 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_3 0x48038C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_4 0x480390 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_5 0x480394 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_6 0x480398 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_7 0x48039C + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_8 0x4803A0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_9 0x4803A4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_10 0x4803A8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_11 0x4803AC + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_12 0x4803B0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_13 0x4803B4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_14 0x4803B8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPROT_15 0x4803BC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_0 0x4803C0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_1 0x4803C4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_2 0x4803C8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_3 0x4803CC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_4 0x4803D0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_5 0x4803D4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_6 0x4803D8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_7 0x4803DC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_8 0x4803E0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_9 0x4803E4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_10 0x4803E8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_11 0x4803EC + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_12 0x4803F0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_13 0x4803F4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_14 0x4803F8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPROT_15 0x4803FC + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_0 0x480400 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_1 0x480404 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_2 0x480408 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_3 0x48040C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_4 0x480410 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_5 0x480414 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_6 0x480418 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_7 0x48041C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_8 0x480420 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_9 0x480424 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_10 0x480428 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_11 0x48042C + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_12 0x480430 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_13 0x480434 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_14 0x480438 + +#define mmDMA_IF_W_S_DMA0_MIN_RPRIV_15 0x48043C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_0 0x480440 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_1 0x480444 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_2 0x480448 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_3 0x48044C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_4 0x480450 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_5 0x480454 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_6 0x480458 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_7 0x48045C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_8 0x480460 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_9 0x480464 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_10 0x480468 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_11 0x48046C + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_12 0x480470 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_13 0x480474 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_14 0x480478 + +#define mmDMA_IF_W_S_DMA0_MAX_RPRIV_15 0x48047C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_0 0x480480 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_1 0x480484 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_2 0x480488 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_3 0x48048C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_4 0x480490 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_5 0x480494 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_6 0x480498 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_7 0x48049C + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_8 0x4804A0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_9 0x4804A4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_10 0x4804A8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_11 0x4804AC + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_12 0x4804B0 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_13 0x4804B4 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_14 0x4804B8 + +#define mmDMA_IF_W_S_DMA0_MIN_WPRIV_15 0x4804BC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_0 0x4804C0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_1 0x4804C4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_2 0x4804C8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_3 0x4804CC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_4 0x4804D0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_5 0x4804D4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_6 0x4804D8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_7 0x4804DC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_8 0x4804E0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_9 0x4804E4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_10 0x4804E8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_11 0x4804EC + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_12 0x4804F0 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_13 0x4804F4 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_14 0x4804F8 + +#define mmDMA_IF_W_S_DMA0_MAX_WPRIV_15 0x4804FC + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_0 0x480500 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_1 0x480504 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_2 0x480508 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_3 0x48050C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_4 0x480510 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_5 0x480514 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_6 0x480518 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_7 0x48051C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_8 0x480520 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_9 0x480524 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_10 0x480528 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_11 0x48052C + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_12 0x480530 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_13 0x480534 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_14 0x480538 + +#define mmDMA_IF_W_S_DMA1_MIN_RPROT_15 0x48053C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_0 0x480540 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_1 0x480544 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_2 0x480548 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_3 0x48054C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_4 0x480550 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_5 0x480554 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_6 0x480558 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_7 0x48055C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_8 0x480560 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_9 0x480564 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_10 0x480568 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_11 0x48056C + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_12 0x480570 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_13 0x480574 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_14 0x480578 + +#define mmDMA_IF_W_S_DMA1_MAX_RPROT_15 0x48057C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_0 0x480580 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_1 0x480584 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_2 0x480588 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_3 0x48058C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_4 0x480590 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_5 0x480594 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_6 0x480598 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_7 0x48059C + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_8 0x4805A0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_9 0x4805A4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_10 0x4805A8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_11 0x4805AC + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_12 0x4805B0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_13 0x4805B4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_14 0x4805B8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPROT_15 0x4805BC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_0 0x4805C0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_1 0x4805C4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_2 0x4805C8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_3 0x4805CC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_4 0x4805D0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_5 0x4805D4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_6 0x4805D8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_7 0x4805DC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_8 0x4805E0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_9 0x4805E4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_10 0x4805E8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_11 0x4805EC + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_12 0x4805F0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_13 0x4805F4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_14 0x4805F8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPROT_15 0x4805FC + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_0 0x480600 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_1 0x480604 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_2 0x480608 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_3 0x48060C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_4 0x480610 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_5 0x480614 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_6 0x480618 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_7 0x48061C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_8 0x480620 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_9 0x480624 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_10 0x480628 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_11 0x48062C + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_12 0x480630 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_13 0x480634 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_14 0x480638 + +#define mmDMA_IF_W_S_DMA1_MIN_RPRIV_15 0x48063C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_0 0x480640 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_1 0x480644 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_2 0x480648 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_3 0x48064C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_4 0x480650 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_5 0x480654 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_6 0x480658 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_7 0x48065C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_8 0x480660 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_9 0x480664 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_10 0x480668 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_11 0x48066C + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_12 0x480670 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_13 0x480674 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_14 0x480678 + +#define mmDMA_IF_W_S_DMA1_MAX_RPRIV_15 0x48067C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_0 0x480680 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_1 0x480684 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_2 0x480688 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_3 0x48068C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_4 0x480690 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_5 0x480694 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_6 0x480698 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_7 0x48069C + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_8 0x4806A0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_9 0x4806A4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_10 0x4806A8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_11 0x4806AC + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_12 0x4806B0 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_13 0x4806B4 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_14 0x4806B8 + +#define mmDMA_IF_W_S_DMA1_MIN_WPRIV_15 0x4806BC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_0 0x4806C0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_1 0x4806C4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_2 0x4806C8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_3 0x4806CC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_4 0x4806D0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_5 0x4806D4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_6 0x4806D8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_7 0x4806DC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_8 0x4806E0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_9 0x4806E4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_10 0x4806E8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_11 0x4806EC + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_12 0x4806F0 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_13 0x4806F4 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_14 0x4806F8 + +#define mmDMA_IF_W_S_DMA1_MAX_WPRIV_15 0x4806FC + +#define mmDMA_IF_W_S_SOB_HIT_RPROT 0x480700 + +#define mmDMA_IF_W_S_SOB_HIT_WPROT 0x480704 + +#define mmDMA_IF_W_S_SOB_HIT_RPRIV 0x48070C + +#define mmDMA_IF_W_S_SOB_HIT_WPRIV 0x480710 + +#define mmDMA_IF_W_S_DMA0_HIT_RPROT 0x48071C + +#define mmDMA_IF_W_S_DMA0_HIT_WPROT 0x480720 + +#define mmDMA_IF_W_S_DMA0_HIT_RPRIV 0x480724 + +#define mmDMA_IF_W_S_DMA0_HIT_WPRIV 0x480728 + +#define mmDMA_IF_W_S_DMA1_HIT_RPROT 0x480730 + +#define mmDMA_IF_W_S_DMA1_HIT_WPROT 0x480734 + +#define mmDMA_IF_W_S_DMA1_HIT_RPRIV 0x480738 + +#define mmDMA_IF_W_S_DMA1_HIT_WPRIV 0x48073C + +#define mmDMA_IF_W_S_HBM_BIN 0x480800 + +#define mmDMA_IF_W_S_MME_BIN 0x480804 + +#define mmDMA_IF_W_S_TPC_BIN 0x480808 + +#define mmDMA_IF_W_S_DMA_BIN 0x48080C + +#define mmDMA_IF_W_S_SOB_CG_EN 0x480810 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_0 0x480820 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_1 0x480824 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_2 0x480828 + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_3 0x48082C + +#define mmDMA_IF_W_S_HBM_I2C_ADDR_4 0x480830 + +#define mmDMA_IF_W_S_HBM_MISC 0x480834 + +#endif /* ASIC_REG_DMA_IF_W_S_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h new file mode 100644 index 000000000000..c7596aac7a5c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_blocks.h @@ -0,0 +1,4974 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI_BLOCKS_H_ +#define GAUDI_BLOCKS_H_ + +#define mmNIC0_PHY0_BASE 0x0ull +#define NIC0_PHY0_MAX_OFFSET 0x9F13 +#define mmMME0_ACC_BASE 0x7FFC020000ull +#define MME0_ACC_MAX_OFFSET 0x5C00 +#define MME0_ACC_SECTION 0x20000 +#define mmMME0_SBAB_BASE 0x7FFC040000ull +#define MME0_SBAB_MAX_OFFSET 0x5800 +#define MME0_SBAB_SECTION 0x1000 +#define mmMME0_PRTN_BASE 0x7FFC041000ull +#define MME0_PRTN_MAX_OFFSET 0x5000 +#define MME0_PRTN_SECTION 0x1F000 +#define mmMME0_CTRL_BASE 0x7FFC060000ull +#define MME0_CTRL_MAX_OFFSET 0xDA80 +#define MME0_CTRL_SECTION 0x8000 +#define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull +#define ARCH_MME0_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME0_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull +#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull +#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull +#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull +#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull +#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull +#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull +#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull +#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull +#define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME0_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull +#define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull +#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull +#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull +#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull +#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull +#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull +#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull +#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull +#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull +#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull +#define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull +#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull +#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull +#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull +#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull +#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull +#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull +#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull +#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull +#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull +#define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull +#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull +#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull +#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull +#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull +#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull +#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull +#define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME0_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull +#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull +#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull +#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull +#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull +#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull +#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull +#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC +#define mmMME0_QM_BASE 0x7FFC068000ull +#define MME0_QM_MAX_OFFSET 0xD040 +#define MME0_QM_SECTION 0x38000 +#define mmMME1_ACC_BASE 0x7FFC0A0000ull +#define MME1_ACC_MAX_OFFSET 0x5C00 +#define MME1_ACC_SECTION 0x20000 +#define mmMME1_SBAB_BASE 0x7FFC0C0000ull +#define MME1_SBAB_MAX_OFFSET 0x5800 +#define MME1_SBAB_SECTION 0x1000 +#define mmMME1_PRTN_BASE 0x7FFC0C1000ull +#define MME1_PRTN_MAX_OFFSET 0x5000 +#define MME1_PRTN_SECTION 0x1F000 +#define mmMME1_CTRL_BASE 0x7FFC0E0000ull +#define MME1_CTRL_MAX_OFFSET 0xDA80 +#define MME1_CTRL_SECTION 0x8000 +#define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull +#define ARCH_MME1_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME1_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull +#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull +#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull +#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull +#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull +#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull +#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull +#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull +#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull +#define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME1_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull +#define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull +#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull +#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull +#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull +#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull +#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull +#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull +#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull +#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull +#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull +#define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull +#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull +#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull +#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull +#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull +#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull +#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull +#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull +#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull +#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull +#define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull +#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull +#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull +#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull +#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull +#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull +#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull +#define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME1_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull +#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull +#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull +#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull +#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull +#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull +#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull +#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC +#define mmMME1_QM_BASE 0x7FFC0E8000ull +#define MME1_QM_MAX_OFFSET 0xD040 +#define MME1_QM_SECTION 0x38000 +#define mmMME2_ACC_BASE 0x7FFC120000ull +#define MME2_ACC_MAX_OFFSET 0x5C00 +#define MME2_ACC_SECTION 0x20000 +#define mmMME2_SBAB_BASE 0x7FFC140000ull +#define MME2_SBAB_MAX_OFFSET 0x5800 +#define MME2_SBAB_SECTION 0x1000 +#define mmMME2_PRTN_BASE 0x7FFC141000ull +#define MME2_PRTN_MAX_OFFSET 0x5000 +#define MME2_PRTN_SECTION 0x1F000 +#define mmMME2_CTRL_BASE 0x7FFC160000ull +#define MME2_CTRL_MAX_OFFSET 0xDA80 +#define MME2_CTRL_SECTION 0x8000 +#define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull +#define ARCH_MME2_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME2_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull +#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull +#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull +#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull +#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull +#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull +#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull +#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull +#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull +#define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME2_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull +#define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull +#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull +#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull +#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull +#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull +#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull +#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull +#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull +#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull +#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull +#define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull +#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull +#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull +#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull +#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull +#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull +#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull +#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull +#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull +#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull +#define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull +#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull +#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull +#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull +#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull +#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull +#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull +#define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME2_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull +#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull +#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull +#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull +#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull +#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull +#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull +#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC +#define mmMME2_QM_BASE 0x7FFC168000ull +#define MME2_QM_MAX_OFFSET 0xD040 +#define MME2_QM_SECTION 0x38000 +#define mmMME3_ACC_BASE 0x7FFC1A0000ull +#define MME3_ACC_MAX_OFFSET 0x5C00 +#define MME3_ACC_SECTION 0x20000 +#define mmMME3_SBAB_BASE 0x7FFC1C0000ull +#define MME3_SBAB_MAX_OFFSET 0x5800 +#define MME3_SBAB_SECTION 0x1000 +#define mmMME3_PRTN_BASE 0x7FFC1C1000ull +#define MME3_PRTN_MAX_OFFSET 0x5000 +#define MME3_PRTN_SECTION 0x1F000 +#define mmMME3_CTRL_BASE 0x7FFC1E0000ull +#define MME3_CTRL_MAX_OFFSET 0xDA80 +#define MME3_CTRL_SECTION 0x8000 +#define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull +#define ARCH_MME3_CTRL_MAX_OFFSET 0x3400 +#define ARCH_MME3_CTRL_SECTION 0x3400 +#define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull +#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull +#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull +#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull +#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull +#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull +#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull +#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull +#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull +#define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define ARCH_DESC_MME3_CTRL_SECTION 0x2340 +#define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull +#define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_0_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull +#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull +#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull +#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull +#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull +#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull +#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull +#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull +#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull +#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull +#define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_1_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull +#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull +#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull +#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull +#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull +#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull +#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull +#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull +#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull +#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull +#define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_2_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull +#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull +#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull +#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull +#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull +#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull +#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull +#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull +#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull +#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400 +#define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull +#define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400 +#define SHADOW_3_MME3_CTRL_SECTION 0x3400 +#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull +#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull +#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull +#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull +#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull +#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull +#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 +#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00 +#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull +#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull +#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 +#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 +#define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull +#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400 +#define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC +#define mmMME3_QM_BASE 0x7FFC1E8000ull +#define MME3_QM_MAX_OFFSET 0xD040 +#define MME3_QM_SECTION 0x18000 +#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull +#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull +#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull +#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull +#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull +#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull +#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull +#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull +#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull +#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull +#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull +#define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull +#define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull +#define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull +#define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull +#define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y0_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull +#define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y0_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull +#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull +#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull +#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull +#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull +#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull +#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull +#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull +#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull +#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull +#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull +#define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull +#define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull +#define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull +#define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull +#define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y1_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull +#define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y1_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull +#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull +#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull +#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull +#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull +#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull +#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull +#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull +#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull +#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull +#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull +#define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull +#define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull +#define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull +#define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull +#define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y2_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull +#define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y2_X7_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull +#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X0_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull +#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X0_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull +#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X1_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull +#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X1_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull +#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X2_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull +#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X2_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull +#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X3_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull +#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X3_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull +#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X4_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull +#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X4_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull +#define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X5_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull +#define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X5_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull +#define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X6_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull +#define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X6_RTR_SECTION 0x7000 +#define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull +#define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000 +#define SRAM_Y3_X7_BANK_SECTION 0x1000 +#define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull +#define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340 +#define SRAM_Y3_X7_RTR_SECTION 0x7000 +#define mmSIF_RTR_0_BASE 0x7FFC300000ull +#define SIF_RTR_0_MAX_OFFSET 0x6500 +#define SIF_RTR_0_SECTION 0x6000 +#define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull +#define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_0_SECTION 0xA000 +#define mmSIF_RTR_1_BASE 0x7FFC310000ull +#define SIF_RTR_1_MAX_OFFSET 0x6500 +#define SIF_RTR_1_SECTION 0x6000 +#define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull +#define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_1_SECTION 0xA000 +#define mmSIF_RTR_2_BASE 0x7FFC320000ull +#define SIF_RTR_2_MAX_OFFSET 0x6500 +#define SIF_RTR_2_SECTION 0x6000 +#define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull +#define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_2_SECTION 0xA000 +#define mmSIF_RTR_3_BASE 0x7FFC330000ull +#define SIF_RTR_3_MAX_OFFSET 0x6500 +#define SIF_RTR_3_SECTION 0x6000 +#define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull +#define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_3_SECTION 0xA000 +#define mmSIF_RTR_4_BASE 0x7FFC340000ull +#define SIF_RTR_4_MAX_OFFSET 0x6500 +#define SIF_RTR_4_SECTION 0x6000 +#define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull +#define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_4_SECTION 0xA000 +#define mmSIF_RTR_5_BASE 0x7FFC350000ull +#define SIF_RTR_5_MAX_OFFSET 0x6500 +#define SIF_RTR_5_SECTION 0x6000 +#define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull +#define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_5_SECTION 0xA000 +#define mmSIF_RTR_6_BASE 0x7FFC360000ull +#define SIF_RTR_6_MAX_OFFSET 0x6500 +#define SIF_RTR_6_SECTION 0x6000 +#define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull +#define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_6_SECTION 0xA000 +#define mmSIF_RTR_7_BASE 0x7FFC370000ull +#define SIF_RTR_7_MAX_OFFSET 0x6500 +#define SIF_RTR_7_SECTION 0x6000 +#define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull +#define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 +#define SIF_RTR_CTRL_7_SECTION 0xA000 +#define mmNIF_RTR_0_BASE 0x7FFC380000ull +#define NIF_RTR_0_MAX_OFFSET 0x6500 +#define NIF_RTR_0_SECTION 0x6000 +#define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull +#define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_0_SECTION 0xA000 +#define mmNIF_RTR_1_BASE 0x7FFC390000ull +#define NIF_RTR_1_MAX_OFFSET 0x6500 +#define NIF_RTR_1_SECTION 0x6000 +#define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull +#define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_1_SECTION 0xA000 +#define mmNIF_RTR_2_BASE 0x7FFC3A0000ull +#define NIF_RTR_2_MAX_OFFSET 0x6500 +#define NIF_RTR_2_SECTION 0x6000 +#define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull +#define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_2_SECTION 0xA000 +#define mmNIF_RTR_3_BASE 0x7FFC3B0000ull +#define NIF_RTR_3_MAX_OFFSET 0x6500 +#define NIF_RTR_3_SECTION 0x6000 +#define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull +#define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_3_SECTION 0xA000 +#define mmNIF_RTR_4_BASE 0x7FFC3C0000ull +#define NIF_RTR_4_MAX_OFFSET 0x6500 +#define NIF_RTR_4_SECTION 0x6000 +#define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull +#define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_4_SECTION 0xA000 +#define mmNIF_RTR_5_BASE 0x7FFC3D0000ull +#define NIF_RTR_5_MAX_OFFSET 0x6500 +#define NIF_RTR_5_SECTION 0x6000 +#define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull +#define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_5_SECTION 0xA000 +#define mmNIF_RTR_6_BASE 0x7FFC3E0000ull +#define NIF_RTR_6_MAX_OFFSET 0x6500 +#define NIF_RTR_6_SECTION 0x6000 +#define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull +#define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_6_SECTION 0xA000 +#define mmNIF_RTR_7_BASE 0x7FFC3F0000ull +#define NIF_RTR_7_MAX_OFFSET 0x6500 +#define NIF_RTR_7_SECTION 0x6000 +#define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull +#define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 +#define NIF_RTR_CTRL_7_SECTION 0x4B000 +#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x2180 +#define CPU_CA53_CFG_SECTION 0x1000 +#define mmCPU_IF_BASE 0x7FFC442000ull +#define CPU_IF_MAX_OFFSET 0x43C0 +#define CPU_IF_SECTION 0x2000 +#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x3C000 +#define mmDMA_IF_W_S_BASE 0x7FFC480000ull +#define DMA_IF_W_S_MAX_OFFSET 0x8380 +#define DMA_IF_W_S_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull +#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull +#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000 +#define mmDMA_W_PLL_BASE 0x7FFC487000ull +#define DMA_W_PLL_MAX_OFFSET 0x5200 +#define DMA_W_PLL_SECTION 0x1000 +#define mmIF_W_PLL_BASE 0x7FFC488000ull +#define IF_W_PLL_MAX_OFFSET 0x5200 +#define IF_W_PLL_SECTION 0x1000 +#define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull +#define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_W_S_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull +#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_W_S_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull +#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_W_S_SECTION 0xF000 +#define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull +#define DMA_IF_E_S_MAX_OFFSET 0x8380 +#define DMA_IF_E_S_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull +#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull +#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000 +#define mmIF_E_PLL_BASE 0x7FFC4A7000ull +#define IF_E_PLL_MAX_OFFSET 0x5200 +#define IF_E_PLL_SECTION 0x1000 +#define mmDMA_E_PLL_BASE 0x7FFC4A8000ull +#define DMA_E_PLL_MAX_OFFSET 0x5200 +#define DMA_E_PLL_SECTION 0x1000 +#define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull +#define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_E_S_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull +#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_E_S_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull +#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_E_S_SECTION 0xF000 +#define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull +#define DMA_IF_W_N_MAX_OFFSET 0x8380 +#define DMA_IF_W_N_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull +#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull +#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000 +#define mmMESH_W_PLL_BASE 0x7FFC4C7000ull +#define MESH_W_PLL_MAX_OFFSET 0x5200 +#define MESH_W_PLL_SECTION 0x1000 +#define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull +#define SRAM_W_PLL_MAX_OFFSET 0x5200 +#define SRAM_W_PLL_SECTION 0x1000 +#define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull +#define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_W_N_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull +#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_W_N_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull +#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_W_N_SECTION 0xF000 +#define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull +#define DMA_IF_E_N_MAX_OFFSET 0x8380 +#define DMA_IF_E_N_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull +#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00 +#define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull +#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00 +#define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000 +#define mmMESH_E_PLL_BASE 0x7FFC4E7000ull +#define MESH_E_PLL_MAX_OFFSET 0x5200 +#define MESH_E_PLL_SECTION 0x1000 +#define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull +#define SRAM_E_PLL_MAX_OFFSET 0x5200 +#define SRAM_E_PLL_SECTION 0x1000 +#define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull +#define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500 +#define DMA_IF_E_N_DOWN_SECTION 0x7000 +#define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull +#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00 +#define SYNC_MNGR_GLBL_E_N_SECTION 0x1000 +#define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull +#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00 +#define SYNC_MNGR_OBJS_E_N_SECTION 0xF000 +#define mmDMA0_CORE_BASE 0x7FFC500000ull +#define DMA0_CORE_MAX_OFFSET 0x23C0 +#define DMA0_CORE_SECTION 0x8000 +#define mmDMA0_QM_BASE 0x7FFC508000ull +#define DMA0_QM_MAX_OFFSET 0xD040 +#define DMA0_QM_SECTION 0x18000 +#define mmDMA1_CORE_BASE 0x7FFC520000ull +#define DMA1_CORE_MAX_OFFSET 0x23C0 +#define DMA1_CORE_SECTION 0x8000 +#define mmDMA1_QM_BASE 0x7FFC528000ull +#define DMA1_QM_MAX_OFFSET 0xD040 +#define DMA1_QM_SECTION 0x18000 +#define mmDMA2_CORE_BASE 0x7FFC540000ull +#define DMA2_CORE_MAX_OFFSET 0x23C0 +#define DMA2_CORE_SECTION 0x8000 +#define mmDMA2_QM_BASE 0x7FFC548000ull +#define DMA2_QM_MAX_OFFSET 0xD040 +#define DMA2_QM_SECTION 0x18000 +#define mmDMA3_CORE_BASE 0x7FFC560000ull +#define DMA3_CORE_MAX_OFFSET 0x23C0 +#define DMA3_CORE_SECTION 0x8000 +#define mmDMA3_QM_BASE 0x7FFC568000ull +#define DMA3_QM_MAX_OFFSET 0xD040 +#define DMA3_QM_SECTION 0x18000 +#define mmDMA4_CORE_BASE 0x7FFC580000ull +#define DMA4_CORE_MAX_OFFSET 0x23C0 +#define DMA4_CORE_SECTION 0x8000 +#define mmDMA4_QM_BASE 0x7FFC588000ull +#define DMA4_QM_MAX_OFFSET 0xD040 +#define DMA4_QM_SECTION 0x18000 +#define mmDMA5_CORE_BASE 0x7FFC5A0000ull +#define DMA5_CORE_MAX_OFFSET 0x23C0 +#define DMA5_CORE_SECTION 0x8000 +#define mmDMA5_QM_BASE 0x7FFC5A8000ull +#define DMA5_QM_MAX_OFFSET 0xD040 +#define DMA5_QM_SECTION 0x18000 +#define mmDMA6_CORE_BASE 0x7FFC5C0000ull +#define DMA6_CORE_MAX_OFFSET 0x23C0 +#define DMA6_CORE_SECTION 0x8000 +#define mmDMA6_QM_BASE 0x7FFC5C8000ull +#define DMA6_QM_MAX_OFFSET 0xD040 +#define DMA6_QM_SECTION 0x18000 +#define mmDMA7_CORE_BASE 0x7FFC5E0000ull +#define DMA7_CORE_MAX_OFFSET 0x23C0 +#define DMA7_CORE_SECTION 0x8000 +#define mmDMA7_QM_BASE 0x7FFC5E8000ull +#define DMA7_QM_MAX_OFFSET 0xD040 +#define DMA7_QM_SECTION 0x18000 +#define mmHBM0_BASE 0x7FFC600000ull +#define HBM0_MAX_OFFSET 0x8F58 +#define HBM0_SECTION 0x80000 +#define mmHBM1_BASE 0x7FFC680000ull +#define HBM1_MAX_OFFSET 0x8F58 +#define HBM1_SECTION 0x80000 +#define mmHBM2_BASE 0x7FFC700000ull +#define HBM2_MAX_OFFSET 0x8F58 +#define HBM2_SECTION 0x80000 +#define mmHBM3_BASE 0x7FFC780000ull +#define HBM3_MAX_OFFSET 0x8F58 +#define HBM3_SECTION 0x80000 +#define mmGIC_BASE 0x7FFC800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 +#define mmPCIE_WRAP_BASE 0x7FFCC01000ull +#define PCIE_WRAP_MAX_OFFSET 0xDF00 +#define PCIE_WRAP_SECTION 0x1000 +#define mmPCIE_DBI_BASE 0x7FFCC02000ull +#define PCIE_DBI_MAX_OFFSET 0xC040 +#define PCIE_DBI_SECTION 0x2000 +#define mmPCIE_CORE_BASE 0x7FFCC04000ull +#define PCIE_CORE_MAX_OFFSET 0x9BC0 +#define PCIE_CORE_SECTION 0x3000 +#define mmPCIE_AUX_BASE 0x7FFCC07000ull +#define PCIE_AUX_MAX_OFFSET 0x9C40 +#define PCIE_AUX_SECTION 0x9000 +#define mmPCIE_PHY_BASE 0x7FFCC10000ull +#define PCIE_PHY_MAX_OFFSET 0x9640 +#define PCIE_PHY_SECTION 0x1000 +#define mmMMU_UP_BASE 0x7FFCC11000ull +#define MMU_UP_MAX_OFFSET 0x7000 +#define MMU_UP_SECTION 0x1000 +#define mmSTLB_BASE 0x7FFCC12000ull +#define STLB_MAX_OFFSET 0x8800 +#define STLB_SECTION 0x1000 +#define mmPCIE_MSI_BASE 0x7FFCC13000ull +#define PCIE_MSI_MAX_OFFSET 0x8000 +#define PCIE_MSI_SECTION 0x2D000 +#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x1000 +#define PSOC_I2C_M0_SECTION 0x1000 +#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x1000 +#define PSOC_I2C_M1_SECTION 0x1000 +#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x1000 +#define PSOC_I2C_S_SECTION 0x1000 +#define mmPSOC_SPI_BASE 0x7FFCC43000ull +#define PSOC_SPI_MAX_OFFSET 0x1000 +#define PSOC_SPI_SECTION 0x2000 +#define mmPSOC_UART_0_BASE 0x7FFCC45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 +#define mmPSOC_UART_1_BASE 0x7FFCC46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 +#define mmPSOC_TIMER_BASE 0x7FFCC47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 +#define mmPSOC_WDOG_BASE 0x7FFCC48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 +#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 +#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x3040 +#define PSOC_EFUSE_SECTION 0x1000 +#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80 +#define PSOC_GLOBAL_CONF_SECTION 0x1000 +#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 +#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 +#define mmPSOC_BTL_BASE 0x7FFCC4E000ull +#define PSOC_BTL_MAX_OFFSET 0x1480 +#define PSOC_BTL_SECTION 0x1000 +#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x1680 +#define PSOC_CS_TRACE_SECTION 0x1000 +#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 +#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x1000 +#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 +#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040 +#define PSOC_DFT_EFUSE_SECTION 0x1000 +#define mmPSOC_RPM_0_BASE 0x7FFCC54000ull +#define PSOC_RPM_0_MAX_OFFSET 0x8800 +#define PSOC_RPM_0_SECTION 0x1000 +#define mmPSOC_RPM_1_BASE 0x7FFCC55000ull +#define PSOC_RPM_1_MAX_OFFSET 0x8800 +#define PSOC_RPM_1_SECTION 0x1000 +#define mmPSOC_RPM_2_BASE 0x7FFCC56000ull +#define PSOC_RPM_2_MAX_OFFSET 0x8800 +#define PSOC_RPM_2_SECTION 0x1000 +#define mmPSOC_RPM_3_BASE 0x7FFCC57000ull +#define PSOC_RPM_3_MAX_OFFSET 0x8800 +#define PSOC_RPM_3_SECTION 0x19000 +#define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull +#define PSOC_CPU_PLL_MAX_OFFSET 0x5200 +#define PSOC_CPU_PLL_SECTION 0x1000 +#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull +#define PSOC_MME_PLL_MAX_OFFSET 0x5200 +#define PSOC_MME_PLL_SECTION 0x1000 +#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull +#define PSOC_PCI_PLL_MAX_OFFSET 0x5200 +#define PSOC_PCI_PLL_SECTION 0x1000 +#define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull +#define PSOC_TPC_PLL_MAX_OFFSET 0x5200 +#define PSOC_TPC_PLL_SECTION 0x1000 +#define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull +#define PSOC_HBM_PLL_MAX_OFFSET 0x5200 +#define PSOC_HBM_PLL_SECTION 0x1000 +#define mmPSOC_PM_BASE 0x7FFCC75000ull +#define PSOC_PM_MAX_OFFSET 0x1F00 +#define PSOC_PM_SECTION 0x1000 +#define mmPSOC_TS_BASE 0x7FFCC76000ull +#define PSOC_TS_MAX_OFFSET 0xE640 +#define PSOC_TS_SECTION 0x2000 +#define mmPSOC_PWM0_BASE 0x7FFCC78000ull +#define PSOC_PWM0_MAX_OFFSET 0x5800 +#define PSOC_PWM0_SECTION 0x1000 +#define mmPSOC_PWM1_BASE 0x7FFCC79000ull +#define PSOC_PWM1_MAX_OFFSET 0x5800 +#define PSOC_PWM1_SECTION 0x1000 +#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull +#define PSOC_PWM2_MAX_OFFSET 0x5800 +#define PSOC_PWM2_SECTION 0x1000 +#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull +#define PSOC_PWM3_MAX_OFFSET 0x5800 +#define PSOC_PWM3_SECTION 0x1000 +#define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull +#define PSOC_GPIO5_MAX_OFFSET 0x1000 +#define PSOC_GPIO5_SECTION 0x1000 +#define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull +#define PSOC_GPIO6_MAX_OFFSET 0x1000 +#define PSOC_GPIO6_SECTION 0x3000 +#define mmPCIE_PMA_0_BASE 0x7FFCC80000ull +#define PCIE_PMA_0_MAX_OFFSET 0x10003 +#define PCIE_PMA_0_SECTION 0x10000 +#define mmPCIE_PMA_1_BASE 0x7FFCC90000ull +#define PCIE_PMA_1_MAX_OFFSET 0x10003 +#define PCIE_PMA_1_SECTION 0x10000 +#define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull +#define PCIE_PMA_2_MAX_OFFSET 0x10003 +#define PCIE_PMA_2_SECTION 0x10000 +#define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull +#define PCIE_PMA_3_MAX_OFFSET 0x10003 +#define PCIE_PMA_3_SECTION 0x10000 +#define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull +#define NIC0_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH0_SECTION 0x1000 +#define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull +#define NIC0_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH1_SECTION 0x1000 +#define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull +#define NIC0_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH2_SECTION 0x1000 +#define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull +#define NIC0_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC0_MAC_CH3_SECTION 0x1000 +#define mmNIC0_STAT_BASE 0x7FFCCC4000ull +#define NIC0_STAT_MAX_OFFSET 0x4D00 +#define NIC0_STAT_SECTION 0x1000 +#define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull +#define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC0_MAC_XPCS91_SECTION 0x3000 +#define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull +#define NIC0_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC0_MAC_CORE_SECTION 0x1000 +#define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull +#define NIC0_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC0_MAC_AUX_SECTION 0xF000 +#define mmNIC0_PHY_BASE 0x7FFCCD8000ull +#define NIC0_PHY_MAX_OFFSET 0x3400 +#define NIC0_PHY_SECTION 0x8000 +#define mmNIC0_QM0_BASE 0x7FFCCE0000ull +#define NIC0_QM0_MAX_OFFSET 0xD040 +#define NIC0_QM0_SECTION 0x2000 +#define mmNIC0_QM1_BASE 0x7FFCCE2000ull +#define NIC0_QM1_MAX_OFFSET 0xD040 +#define NIC0_QM1_SECTION 0x2000 +#define mmNIC0_QPC0_BASE 0x7FFCCE4000ull +#define NIC0_QPC0_MAX_OFFSET 0x7140 +#define NIC0_QPC0_SECTION 0x1000 +#define mmNIC0_QPC1_BASE 0x7FFCCE5000ull +#define NIC0_QPC1_MAX_OFFSET 0x7140 +#define NIC0_QPC1_SECTION 0x3000 +#define mmNIC0_RXB_BASE 0x7FFCCE8000ull +#define NIC0_RXB_MAX_OFFSET 0x6040 +#define NIC0_RXB_SECTION 0x1000 +#define mmNIC0_RXE0_BASE 0x7FFCCE9000ull +#define NIC0_RXE0_MAX_OFFSET 0x2FC0 +#define NIC0_RXE0_SECTION 0x1000 +#define mmNIC0_RXE1_BASE 0x7FFCCEA000ull +#define NIC0_RXE1_MAX_OFFSET 0x2FC0 +#define NIC0_RXE1_SECTION 0x1000 +#define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull +#define NIC0_RX_GW_MAX_OFFSET 0x4540 +#define NIC0_RX_GW_SECTION 0x5000 +#define mmNIC0_TXS0_BASE 0x7FFCCF0000ull +#define NIC0_TXS0_MAX_OFFSET 0x19C0 +#define NIC0_TXS0_SECTION 0x1000 +#define mmNIC0_TXS1_BASE 0x7FFCCF1000ull +#define NIC0_TXS1_MAX_OFFSET 0x19C0 +#define NIC0_TXS1_SECTION 0x1000 +#define mmNIC0_TXE0_BASE 0x7FFCCF2000ull +#define NIC0_TXE0_MAX_OFFSET 0x2040 +#define NIC0_TXE0_SECTION 0x1000 +#define mmNIC0_TXE1_BASE 0x7FFCCF3000ull +#define NIC0_TXE1_MAX_OFFSET 0x2040 +#define NIC0_TXE1_SECTION 0x1000 +#define mmNIC0_TXB_BASE 0x7FFCCF4000ull +#define NIC0_TXB_MAX_OFFSET 0xD400 +#define NIC0_TXB_SECTION 0x1000 +#define mmNIC0_TMR_BASE 0x7FFCCF5000ull +#define NIC0_TMR_MAX_OFFSET 0x1600 +#define NIC0_TMR_SECTION 0x1000 +#define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull +#define NIC0_TX_GW_MAX_OFFSET 0x1400 +#define NIC0_TX_GW_SECTION 0x2000 +#define mmNIC0_TS_BASE 0x7FFCCF8000ull +#define NIC0_TS_MAX_OFFSET 0xE640 +#define NIC0_TS_SECTION 0x1000 +#define mmNIC0_PLL_BASE 0x7FFCCF9000ull +#define NIC0_PLL_MAX_OFFSET 0x5200 +#define NIC0_PLL_SECTION 0x1000 +#define mmNIC0_PM_BASE 0x7FFCCFA000ull +#define NIC0_PM_MAX_OFFSET 0x1F00 +#define NIC0_PM_SECTION 0x6000 +#define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull +#define NIC1_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH0_SECTION 0x1000 +#define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull +#define NIC1_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH1_SECTION 0x1000 +#define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull +#define NIC1_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH2_SECTION 0x1000 +#define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull +#define NIC1_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC1_MAC_CH3_SECTION 0x1000 +#define mmNIC1_STAT_BASE 0x7FFCD04000ull +#define NIC1_STAT_MAX_OFFSET 0x4D00 +#define NIC1_STAT_SECTION 0x1000 +#define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull +#define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC1_MAC_XPCS91_SECTION 0x3000 +#define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull +#define NIC1_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC1_MAC_CORE_SECTION 0x1000 +#define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull +#define NIC1_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC1_MAC_AUX_SECTION 0xF000 +#define mmNIC1_PHY_BASE 0x7FFCD18000ull +#define NIC1_PHY_MAX_OFFSET 0x3400 +#define NIC1_PHY_SECTION 0x8000 +#define mmNIC1_QM0_BASE 0x7FFCD20000ull +#define NIC1_QM0_MAX_OFFSET 0xD040 +#define NIC1_QM0_SECTION 0x2000 +#define mmNIC1_QM1_BASE 0x7FFCD22000ull +#define NIC1_QM1_MAX_OFFSET 0xD040 +#define NIC1_QM1_SECTION 0x2000 +#define mmNIC1_QPC0_BASE 0x7FFCD24000ull +#define NIC1_QPC0_MAX_OFFSET 0x7140 +#define NIC1_QPC0_SECTION 0x1000 +#define mmNIC1_QPC1_BASE 0x7FFCD25000ull +#define NIC1_QPC1_MAX_OFFSET 0x7140 +#define NIC1_QPC1_SECTION 0x3000 +#define mmNIC1_RXB_BASE 0x7FFCD28000ull +#define NIC1_RXB_MAX_OFFSET 0x6040 +#define NIC1_RXB_SECTION 0x1000 +#define mmNIC1_RXE0_BASE 0x7FFCD29000ull +#define NIC1_RXE0_MAX_OFFSET 0x2FC0 +#define NIC1_RXE0_SECTION 0x1000 +#define mmNIC1_RXE1_BASE 0x7FFCD2A000ull +#define NIC1_RXE1_MAX_OFFSET 0x2FC0 +#define NIC1_RXE1_SECTION 0x1000 +#define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull +#define NIC1_RX_GW_MAX_OFFSET 0x4540 +#define NIC1_RX_GW_SECTION 0x5000 +#define mmNIC1_TXS0_BASE 0x7FFCD30000ull +#define NIC1_TXS0_MAX_OFFSET 0x19C0 +#define NIC1_TXS0_SECTION 0x1000 +#define mmNIC1_TXS1_BASE 0x7FFCD31000ull +#define NIC1_TXS1_MAX_OFFSET 0x19C0 +#define NIC1_TXS1_SECTION 0x1000 +#define mmNIC1_TXE0_BASE 0x7FFCD32000ull +#define NIC1_TXE0_MAX_OFFSET 0x2040 +#define NIC1_TXE0_SECTION 0x1000 +#define mmNIC1_TXE1_BASE 0x7FFCD33000ull +#define NIC1_TXE1_MAX_OFFSET 0x2040 +#define NIC1_TXE1_SECTION 0x1000 +#define mmNIC1_TXB_BASE 0x7FFCD34000ull +#define NIC1_TXB_MAX_OFFSET 0xD400 +#define NIC1_TXB_SECTION 0x1000 +#define mmNIC1_TMR_BASE 0x7FFCD35000ull +#define NIC1_TMR_MAX_OFFSET 0x1600 +#define NIC1_TMR_SECTION 0x1000 +#define mmNIC1_TX_GW_BASE 0x7FFCD36000ull +#define NIC1_TX_GW_MAX_OFFSET 0x1400 +#define NIC1_TX_GW_SECTION 0x2000 +#define mmNIC1_TS_BASE 0x7FFCD38000ull +#define NIC1_TS_MAX_OFFSET 0xE640 +#define NIC1_TS_SECTION 0x1000 +#define mmNIC1_PLL_BASE 0x7FFCD39000ull +#define NIC1_PLL_MAX_OFFSET 0x5200 +#define NIC1_PLL_SECTION 0x1000 +#define mmNIC1_PM_BASE 0x7FFCD3A000ull +#define NIC1_PM_MAX_OFFSET 0x1F00 +#define NIC1_PM_SECTION 0x6000 +#define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull +#define NIC2_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH0_SECTION 0x1000 +#define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull +#define NIC2_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH1_SECTION 0x1000 +#define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull +#define NIC2_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH2_SECTION 0x1000 +#define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull +#define NIC2_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC2_MAC_CH3_SECTION 0x1000 +#define mmNIC2_STAT_BASE 0x7FFCD44000ull +#define NIC2_STAT_MAX_OFFSET 0x4D00 +#define NIC2_STAT_SECTION 0x1000 +#define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull +#define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC2_MAC_XPCS91_SECTION 0x3000 +#define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull +#define NIC2_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC2_MAC_CORE_SECTION 0x1000 +#define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull +#define NIC2_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC2_MAC_AUX_SECTION 0xF000 +#define mmNIC2_PHY_BASE 0x7FFCD58000ull +#define NIC2_PHY_MAX_OFFSET 0x3400 +#define NIC2_PHY_SECTION 0x8000 +#define mmNIC2_QM0_BASE 0x7FFCD60000ull +#define NIC2_QM0_MAX_OFFSET 0xD040 +#define NIC2_QM0_SECTION 0x2000 +#define mmNIC2_QM1_BASE 0x7FFCD62000ull +#define NIC2_QM1_MAX_OFFSET 0xD040 +#define NIC2_QM1_SECTION 0x2000 +#define mmNIC2_QPC0_BASE 0x7FFCD64000ull +#define NIC2_QPC0_MAX_OFFSET 0x7140 +#define NIC2_QPC0_SECTION 0x1000 +#define mmNIC2_QPC1_BASE 0x7FFCD65000ull +#define NIC2_QPC1_MAX_OFFSET 0x7140 +#define NIC2_QPC1_SECTION 0x3000 +#define mmNIC2_RXB_BASE 0x7FFCD68000ull +#define NIC2_RXB_MAX_OFFSET 0x6040 +#define NIC2_RXB_SECTION 0x1000 +#define mmNIC2_RXE0_BASE 0x7FFCD69000ull +#define NIC2_RXE0_MAX_OFFSET 0x2FC0 +#define NIC2_RXE0_SECTION 0x1000 +#define mmNIC2_RXE1_BASE 0x7FFCD6A000ull +#define NIC2_RXE1_MAX_OFFSET 0x2FC0 +#define NIC2_RXE1_SECTION 0x1000 +#define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull +#define NIC2_RX_GW_MAX_OFFSET 0x4540 +#define NIC2_RX_GW_SECTION 0x5000 +#define mmNIC2_TXS0_BASE 0x7FFCD70000ull +#define NIC2_TXS0_MAX_OFFSET 0x19C0 +#define NIC2_TXS0_SECTION 0x1000 +#define mmNIC2_TXS1_BASE 0x7FFCD71000ull +#define NIC2_TXS1_MAX_OFFSET 0x19C0 +#define NIC2_TXS1_SECTION 0x1000 +#define mmNIC2_TXE0_BASE 0x7FFCD72000ull +#define NIC2_TXE0_MAX_OFFSET 0x2040 +#define NIC2_TXE0_SECTION 0x1000 +#define mmNIC2_TXE1_BASE 0x7FFCD73000ull +#define NIC2_TXE1_MAX_OFFSET 0x2040 +#define NIC2_TXE1_SECTION 0x1000 +#define mmNIC2_TXB_BASE 0x7FFCD74000ull +#define NIC2_TXB_MAX_OFFSET 0xD400 +#define NIC2_TXB_SECTION 0x1000 +#define mmNIC2_TMR_BASE 0x7FFCD75000ull +#define NIC2_TMR_MAX_OFFSET 0x1600 +#define NIC2_TMR_SECTION 0x1000 +#define mmNIC2_TX_GW_BASE 0x7FFCD76000ull +#define NIC2_TX_GW_MAX_OFFSET 0x1400 +#define NIC2_TX_GW_SECTION 0x2000 +#define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull +#define NIC2_HBM_PLL_MAX_OFFSET 0x5200 +#define NIC2_HBM_PLL_SECTION 0x1000 +#define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull +#define NIC2_MME_PLL_MAX_OFFSET 0x5200 +#define NIC2_MME_PLL_SECTION 0x1000 +#define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull +#define NIC2_TPC_PLL_MAX_OFFSET 0x5200 +#define NIC2_TPC_PLL_SECTION 0x6000 +#define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull +#define NIC3_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH0_SECTION 0x1000 +#define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull +#define NIC3_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH1_SECTION 0x1000 +#define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull +#define NIC3_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH2_SECTION 0x1000 +#define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull +#define NIC3_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC3_MAC_CH3_SECTION 0x1000 +#define mmNIC3_STAT_BASE 0x7FFCD84000ull +#define NIC3_STAT_MAX_OFFSET 0x4D00 +#define NIC3_STAT_SECTION 0x1000 +#define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull +#define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC3_MAC_XPCS91_SECTION 0x3000 +#define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull +#define NIC3_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC3_MAC_CORE_SECTION 0x1000 +#define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull +#define NIC3_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC3_MAC_AUX_SECTION 0xF000 +#define mmNIC3_PHY_BASE 0x7FFCD98000ull +#define NIC3_PHY_MAX_OFFSET 0x3400 +#define NIC3_PHY_SECTION 0x8000 +#define mmNIC3_QM0_BASE 0x7FFCDA0000ull +#define NIC3_QM0_MAX_OFFSET 0xD040 +#define NIC3_QM0_SECTION 0x2000 +#define mmNIC3_QM1_BASE 0x7FFCDA2000ull +#define NIC3_QM1_MAX_OFFSET 0xD040 +#define NIC3_QM1_SECTION 0x2000 +#define mmNIC3_QPC0_BASE 0x7FFCDA4000ull +#define NIC3_QPC0_MAX_OFFSET 0x7140 +#define NIC3_QPC0_SECTION 0x1000 +#define mmNIC3_QPC1_BASE 0x7FFCDA5000ull +#define NIC3_QPC1_MAX_OFFSET 0x7140 +#define NIC3_QPC1_SECTION 0x3000 +#define mmNIC3_RXB_BASE 0x7FFCDA8000ull +#define NIC3_RXB_MAX_OFFSET 0x6040 +#define NIC3_RXB_SECTION 0x1000 +#define mmNIC3_RXE0_BASE 0x7FFCDA9000ull +#define NIC3_RXE0_MAX_OFFSET 0x2FC0 +#define NIC3_RXE0_SECTION 0x1000 +#define mmNIC3_RXE1_BASE 0x7FFCDAA000ull +#define NIC3_RXE1_MAX_OFFSET 0x2FC0 +#define NIC3_RXE1_SECTION 0x1000 +#define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull +#define NIC3_RX_GW_MAX_OFFSET 0x4540 +#define NIC3_RX_GW_SECTION 0x5000 +#define mmNIC3_TXS0_BASE 0x7FFCDB0000ull +#define NIC3_TXS0_MAX_OFFSET 0x19C0 +#define NIC3_TXS0_SECTION 0x1000 +#define mmNIC3_TXS1_BASE 0x7FFCDB1000ull +#define NIC3_TXS1_MAX_OFFSET 0x19C0 +#define NIC3_TXS1_SECTION 0x1000 +#define mmNIC3_TXE0_BASE 0x7FFCDB2000ull +#define NIC3_TXE0_MAX_OFFSET 0x2040 +#define NIC3_TXE0_SECTION 0x1000 +#define mmNIC3_TXE1_BASE 0x7FFCDB3000ull +#define NIC3_TXE1_MAX_OFFSET 0x2040 +#define NIC3_TXE1_SECTION 0x1000 +#define mmNIC3_TXB_BASE 0x7FFCDB4000ull +#define NIC3_TXB_MAX_OFFSET 0xD400 +#define NIC3_TXB_SECTION 0x1000 +#define mmNIC3_TMR_BASE 0x7FFCDB5000ull +#define NIC3_TMR_MAX_OFFSET 0x1600 +#define NIC3_TMR_SECTION 0x1000 +#define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull +#define NIC3_TX_GW_MAX_OFFSET 0x1400 +#define NIC3_TX_GW_SECTION 0x2000 +#define mmNIC3_TS_BASE 0x7FFCDB8000ull +#define NIC3_TS_MAX_OFFSET 0xE640 +#define NIC3_TS_SECTION 0x2000 +#define mmNIC3_PM_BASE 0x7FFCDBA000ull +#define NIC3_PM_MAX_OFFSET 0x1F00 +#define NIC3_PM_SECTION 0x6000 +#define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull +#define NIC4_MAC_CH0_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH0_SECTION 0x1000 +#define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull +#define NIC4_MAC_CH1_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH1_SECTION 0x1000 +#define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull +#define NIC4_MAC_CH2_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH2_SECTION 0x1000 +#define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull +#define NIC4_MAC_CH3_MAX_OFFSET 0x8400 +#define NIC4_MAC_CH3_SECTION 0x1000 +#define mmNIC4_STAT_BASE 0x7FFCDC4000ull +#define NIC4_STAT_MAX_OFFSET 0x4D00 +#define NIC4_STAT_SECTION 0x1000 +#define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull +#define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380 +#define NIC4_MAC_XPCS91_SECTION 0x3000 +#define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull +#define NIC4_MAC_CORE_MAX_OFFSET 0x5400 +#define NIC4_MAC_CORE_SECTION 0x1000 +#define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull +#define NIC4_MAC_AUX_MAX_OFFSET 0x3000 +#define NIC4_MAC_AUX_SECTION 0xF000 +#define mmNIC4_PHY_BASE 0x7FFCDD8000ull +#define NIC4_PHY_MAX_OFFSET 0x3400 +#define NIC4_PHY_SECTION 0x8000 +#define mmNIC4_QM0_BASE 0x7FFCDE0000ull +#define NIC4_QM0_MAX_OFFSET 0xD040 +#define NIC4_QM0_SECTION 0x2000 +#define mmNIC4_QM1_BASE 0x7FFCDE2000ull +#define NIC4_QM1_MAX_OFFSET 0xD040 +#define NIC4_QM1_SECTION 0x2000 +#define mmNIC4_QPC0_BASE 0x7FFCDE4000ull +#define NIC4_QPC0_MAX_OFFSET 0x7140 +#define NIC4_QPC0_SECTION 0x1000 +#define mmNIC4_QPC1_BASE 0x7FFCDE5000ull +#define NIC4_QPC1_MAX_OFFSET 0x7140 +#define NIC4_QPC1_SECTION 0x3000 +#define mmNIC4_RXB_BASE 0x7FFCDE8000ull +#define NIC4_RXB_MAX_OFFSET 0x6040 +#define NIC4_RXB_SECTION 0x1000 +#define mmNIC4_RXE0_BASE 0x7FFCDE9000ull +#define NIC4_RXE0_MAX_OFFSET 0x2FC0 +#define NIC4_RXE0_SECTION 0x1000 +#define mmNIC4_RXE1_BASE 0x7FFCDEA000ull +#define NIC4_RXE1_MAX_OFFSET 0x2FC0 +#define NIC4_RXE1_SECTION 0x1000 +#define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull +#define NIC4_RX_GW_MAX_OFFSET 0x4540 +#define NIC4_RX_GW_SECTION 0x5000 +#define mmNIC4_TXS0_BASE 0x7FFCDF0000ull +#define NIC4_TXS0_MAX_OFFSET 0x19C0 +#define NIC4_TXS0_SECTION 0x1000 +#define mmNIC4_TXS1_BASE 0x7FFCDF1000ull +#define NIC4_TXS1_MAX_OFFSET 0x19C0 +#define NIC4_TXS1_SECTION 0x1000 +#define mmNIC4_TXE0_BASE 0x7FFCDF2000ull +#define NIC4_TXE0_MAX_OFFSET 0x2040 +#define NIC4_TXE0_SECTION 0x1000 +#define mmNIC4_TXE1_BASE 0x7FFCDF3000ull +#define NIC4_TXE1_MAX_OFFSET 0x2040 +#define NIC4_TXE1_SECTION 0x1000 +#define mmNIC4_TXB_BASE 0x7FFCDF4000ull +#define NIC4_TXB_MAX_OFFSET 0xD400 +#define NIC4_TXB_SECTION 0x1000 +#define mmNIC4_TMR_BASE 0x7FFCDF5000ull +#define NIC4_TMR_MAX_OFFSET 0x1600 +#define NIC4_TMR_SECTION 0x1000 +#define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull +#define NIC4_TX_GW_MAX_OFFSET 0x1400 +#define NIC4_TX_GW_SECTION 0x10000 +#define mmTPC0_CFG_BASE 0x7FFCE06000ull +#define TPC0_CFG_MAX_OFFSET 0xE400 +#define TPC0_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull +#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull +#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull +#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull +#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull +#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull +#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull +#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull +#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull +#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull +#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull +#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull +#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull +#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull +#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull +#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull +#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull +#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 +#define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull +#define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC0_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull +#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull +#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull +#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull +#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull +#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull +#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull +#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull +#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull +#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull +#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull +#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull +#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull +#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull +#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull +#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull +#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull +#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 +#define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull +#define QM_TPC0_CFG_MAX_OFFSET 0xB800 +#define QM_TPC0_CFG_SECTION 0x2780 +#define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull +#define TPC0_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC0_E2E_CRED_SECTION 0x1000 +#define mmTPC0_QM_BASE 0x7FFCE08000ull +#define TPC0_QM_MAX_OFFSET 0xD040 +#define TPC0_QM_SECTION 0x3E000 +#define mmTPC1_CFG_BASE 0x7FFCE46000ull +#define TPC1_CFG_MAX_OFFSET 0xE400 +#define TPC1_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull +#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull +#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull +#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull +#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull +#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull +#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull +#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull +#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull +#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull +#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull +#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull +#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull +#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull +#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull +#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull +#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull +#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 +#define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull +#define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC1_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull +#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull +#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull +#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull +#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull +#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull +#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull +#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull +#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull +#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull +#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull +#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull +#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull +#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull +#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull +#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull +#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull +#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 +#define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull +#define QM_TPC1_CFG_MAX_OFFSET 0xB800 +#define QM_TPC1_CFG_SECTION 0x2780 +#define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull +#define TPC1_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC1_E2E_CRED_SECTION 0x1000 +#define mmTPC1_QM_BASE 0x7FFCE48000ull +#define TPC1_QM_MAX_OFFSET 0xD040 +#define TPC1_QM_SECTION 0x3E000 +#define mmTPC2_CFG_BASE 0x7FFCE86000ull +#define TPC2_CFG_MAX_OFFSET 0xE400 +#define TPC2_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull +#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull +#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull +#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull +#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull +#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull +#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull +#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull +#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull +#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull +#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull +#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull +#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull +#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull +#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull +#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull +#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull +#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 +#define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull +#define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC2_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull +#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull +#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull +#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull +#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull +#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull +#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull +#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull +#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull +#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull +#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull +#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull +#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull +#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull +#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull +#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull +#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull +#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 +#define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull +#define QM_TPC2_CFG_MAX_OFFSET 0xB800 +#define QM_TPC2_CFG_SECTION 0x2780 +#define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull +#define TPC2_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC2_E2E_CRED_SECTION 0x1000 +#define mmTPC2_QM_BASE 0x7FFCE88000ull +#define TPC2_QM_MAX_OFFSET 0xD040 +#define TPC2_QM_SECTION 0x3E000 +#define mmTPC3_CFG_BASE 0x7FFCEC6000ull +#define TPC3_CFG_MAX_OFFSET 0xE400 +#define TPC3_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull +#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull +#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull +#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull +#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull +#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull +#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull +#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull +#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull +#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull +#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull +#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull +#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull +#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull +#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull +#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull +#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull +#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 +#define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull +#define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC3_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull +#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull +#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull +#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull +#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull +#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull +#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull +#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull +#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull +#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull +#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull +#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull +#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull +#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull +#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull +#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull +#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull +#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 +#define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull +#define QM_TPC3_CFG_MAX_OFFSET 0xB800 +#define QM_TPC3_CFG_SECTION 0x2780 +#define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull +#define TPC3_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC3_E2E_CRED_SECTION 0x1000 +#define mmTPC3_QM_BASE 0x7FFCEC8000ull +#define TPC3_QM_MAX_OFFSET 0xD040 +#define TPC3_QM_SECTION 0x3E000 +#define mmTPC4_CFG_BASE 0x7FFCF06000ull +#define TPC4_CFG_MAX_OFFSET 0xE400 +#define TPC4_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull +#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull +#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull +#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull +#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull +#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull +#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull +#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull +#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull +#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull +#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull +#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull +#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull +#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull +#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull +#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull +#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull +#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 +#define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull +#define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC4_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull +#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull +#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull +#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull +#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull +#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull +#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull +#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull +#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull +#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull +#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull +#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull +#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull +#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull +#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull +#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull +#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull +#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 +#define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull +#define QM_TPC4_CFG_MAX_OFFSET 0xB800 +#define QM_TPC4_CFG_SECTION 0x2780 +#define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull +#define TPC4_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC4_E2E_CRED_SECTION 0x1000 +#define mmTPC4_QM_BASE 0x7FFCF08000ull +#define TPC4_QM_MAX_OFFSET 0xD040 +#define TPC4_QM_SECTION 0x3E000 +#define mmTPC5_CFG_BASE 0x7FFCF46000ull +#define TPC5_CFG_MAX_OFFSET 0xE400 +#define TPC5_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull +#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull +#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull +#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull +#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull +#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull +#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull +#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull +#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull +#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull +#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull +#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull +#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull +#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull +#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull +#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull +#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull +#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 +#define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull +#define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC5_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull +#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull +#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull +#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull +#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull +#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull +#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull +#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull +#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull +#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull +#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull +#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull +#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull +#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull +#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull +#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull +#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull +#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 +#define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull +#define QM_TPC5_CFG_MAX_OFFSET 0xB800 +#define QM_TPC5_CFG_SECTION 0x2780 +#define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull +#define TPC5_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC5_E2E_CRED_SECTION 0x1000 +#define mmTPC5_QM_BASE 0x7FFCF48000ull +#define TPC5_QM_MAX_OFFSET 0xD040 +#define TPC5_QM_SECTION 0x3E000 +#define mmTPC6_CFG_BASE 0x7FFCF86000ull +#define TPC6_CFG_MAX_OFFSET 0xE400 +#define TPC6_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull +#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull +#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull +#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull +#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull +#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull +#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull +#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull +#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull +#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull +#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull +#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull +#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull +#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull +#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull +#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull +#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull +#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 +#define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull +#define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC6_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull +#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull +#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull +#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull +#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull +#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull +#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull +#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull +#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull +#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull +#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull +#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull +#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull +#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull +#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull +#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull +#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull +#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 +#define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull +#define QM_TPC6_CFG_MAX_OFFSET 0xB800 +#define QM_TPC6_CFG_SECTION 0x2780 +#define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull +#define TPC6_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC6_E2E_CRED_SECTION 0x1000 +#define mmTPC6_QM_BASE 0x7FFCF88000ull +#define TPC6_QM_MAX_OFFSET 0xD040 +#define TPC6_QM_SECTION 0x3E000 +#define mmTPC7_CFG_BASE 0x7FFCFC6000ull +#define TPC7_CFG_MAX_OFFSET 0xE400 +#define TPC7_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull +#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull +#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull +#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull +#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull +#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull +#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull +#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull +#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull +#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull +#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull +#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull +#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull +#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull +#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull +#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull +#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull +#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 +#define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull +#define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC7_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull +#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull +#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull +#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull +#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull +#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull +#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull +#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull +#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull +#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull +#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull +#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull +#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull +#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull +#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull +#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull +#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull +#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 +#define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull +#define QM_TPC7_CFG_MAX_OFFSET 0xB800 +#define QM_TPC7_CFG_SECTION 0x2780 +#define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull +#define TPC7_E2E_CRED_MAX_OFFSET 0x1680 +#define TPC7_E2E_CRED_SECTION 0x1000 +#define mmTPC7_QM_BASE 0x7FFCFC8000ull +#define TPC7_QM_MAX_OFFSET 0xD040 +#define TPC7_QM_SECTION 0x1038000 +#define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull +#define MME_S_ROM_TABLE_MAX_OFFSET 0x1000 +#define MME_S_ROM_TABLE_SECTION 0x21000 +#define mmMME0_ACC_STM_BASE 0x7FFE021000ull +#define MME0_ACC_STM_MAX_OFFSET 0x1000 +#define MME0_ACC_STM_SECTION 0x1000 +#define mmMME0_ACC_CTI_BASE 0x7FFE022000ull +#define MME0_ACC_CTI_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI_SECTION 0x1000 +#define mmMME0_ACC_ETF_BASE 0x7FFE023000ull +#define MME0_ACC_ETF_MAX_OFFSET 0x1000 +#define MME0_ACC_ETF_SECTION 0x1000 +#define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull +#define MME0_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME0_ACC_SPMU_SECTION 0x1000 +#define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull +#define MME0_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI0_SECTION 0x1000 +#define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull +#define MME0_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME0_ACC_CTI1_SECTION 0x1000 +#define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull +#define MME0_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME0_ACC_BMON0_SECTION 0x9000 +#define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull +#define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME0_ACC_FUNNEL_SECTION 0x11000 +#define mmMME0_SBAB_STM_BASE 0x7FFE041000ull +#define MME0_SBAB_STM_MAX_OFFSET 0x1000 +#define MME0_SBAB_STM_SECTION 0x1000 +#define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull +#define MME0_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI_SECTION 0x1000 +#define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull +#define MME0_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME0_SBAB_ETF_SECTION 0x1000 +#define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull +#define MME0_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME0_SBAB_SPMU_SECTION 0x1000 +#define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull +#define MME0_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI0_SECTION 0x1000 +#define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull +#define MME0_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME0_SBAB_CTI1_SECTION 0x1000 +#define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull +#define MME0_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME0_SBAB_BMON0_SECTION 0x1000 +#define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull +#define MME0_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME0_SBAB_BMON1_SECTION 0x19000 +#define mmMME0_CTRL_STM_BASE 0x7FFE061000ull +#define MME0_CTRL_STM_MAX_OFFSET 0x1000 +#define MME0_CTRL_STM_SECTION 0x1000 +#define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull +#define MME0_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI_SECTION 0x1000 +#define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull +#define MME0_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME0_CTRL_ETF_SECTION 0x1000 +#define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull +#define MME0_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME0_CTRL_SPMU_SECTION 0x1000 +#define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull +#define MME0_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI0_SECTION 0x1000 +#define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull +#define MME0_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME0_CTRL_CTI1_SECTION 0x1000 +#define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull +#define MME0_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME0_CTRL_BMON0_SECTION 0x1000 +#define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull +#define MME0_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME0_CTRL_BMON1_SECTION 0x39000 +#define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull +#define MME1_ACC_STM_MAX_OFFSET 0x1000 +#define MME1_ACC_STM_SECTION 0x1000 +#define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull +#define MME1_ACC_CTI_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI_SECTION 0x1000 +#define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull +#define MME1_ACC_ETF_MAX_OFFSET 0x1000 +#define MME1_ACC_ETF_SECTION 0x1000 +#define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull +#define MME1_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME1_ACC_SPMU_SECTION 0x1000 +#define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull +#define MME1_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI0_SECTION 0x1000 +#define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull +#define MME1_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME1_ACC_CTI1_SECTION 0x1000 +#define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull +#define MME1_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME1_ACC_BMON0_SECTION 0x9000 +#define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull +#define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME1_ACC_FUNNEL_SECTION 0x11000 +#define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull +#define MME1_SBAB_STM_MAX_OFFSET 0x1000 +#define MME1_SBAB_STM_SECTION 0x1000 +#define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull +#define MME1_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI_SECTION 0x1000 +#define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull +#define MME1_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME1_SBAB_ETF_SECTION 0x1000 +#define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull +#define MME1_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME1_SBAB_SPMU_SECTION 0x1000 +#define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull +#define MME1_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI0_SECTION 0x1000 +#define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull +#define MME1_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME1_SBAB_CTI1_SECTION 0x1000 +#define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull +#define MME1_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME1_SBAB_BMON0_SECTION 0x1000 +#define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull +#define MME1_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME1_SBAB_BMON1_SECTION 0x19000 +#define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull +#define MME1_CTRL_STM_MAX_OFFSET 0x1000 +#define MME1_CTRL_STM_SECTION 0x1000 +#define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull +#define MME1_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI_SECTION 0x1000 +#define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull +#define MME1_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME1_CTRL_ETF_SECTION 0x1000 +#define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull +#define MME1_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME1_CTRL_SPMU_SECTION 0x1000 +#define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull +#define MME1_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI0_SECTION 0x1000 +#define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull +#define MME1_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME1_CTRL_CTI1_SECTION 0x1000 +#define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull +#define MME1_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME1_CTRL_BMON0_SECTION 0x1000 +#define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull +#define MME1_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME1_CTRL_BMON1_SECTION 0x18000 +#define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull +#define MME_N_ROM_TABLE_MAX_OFFSET 0x1000 +#define MME_N_ROM_TABLE_SECTION 0x21000 +#define mmMME2_ACC_STM_BASE 0x7FFE121000ull +#define MME2_ACC_STM_MAX_OFFSET 0x1000 +#define MME2_ACC_STM_SECTION 0x1000 +#define mmMME2_ACC_CTI_BASE 0x7FFE122000ull +#define MME2_ACC_CTI_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI_SECTION 0x1000 +#define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull +#define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000 +#define MME2_MME2_ACC_ETF_SECTION 0x1000 +#define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull +#define MME2_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME2_ACC_SPMU_SECTION 0x1000 +#define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull +#define MME2_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI0_SECTION 0x1000 +#define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull +#define MME2_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME2_ACC_CTI1_SECTION 0x1000 +#define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull +#define MME2_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME2_ACC_BMON0_SECTION 0x9000 +#define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull +#define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME2_ACC_FUNNEL_SECTION 0x11000 +#define mmMME2_SBAB_STM_BASE 0x7FFE141000ull +#define MME2_SBAB_STM_MAX_OFFSET 0x1000 +#define MME2_SBAB_STM_SECTION 0x1000 +#define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull +#define MME2_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI_SECTION 0x1000 +#define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull +#define MME2_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME2_SBAB_ETF_SECTION 0x1000 +#define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull +#define MME2_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME2_SBAB_SPMU_SECTION 0x1000 +#define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull +#define MME2_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI0_SECTION 0x1000 +#define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull +#define MME2_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME2_SBAB_CTI1_SECTION 0x1000 +#define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull +#define MME2_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME2_SBAB_BMON0_SECTION 0x1000 +#define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull +#define MME2_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME2_SBAB_BMON1_SECTION 0x19000 +#define mmMME2_CTRL_STM_BASE 0x7FFE161000ull +#define MME2_CTRL_STM_MAX_OFFSET 0x1000 +#define MME2_CTRL_STM_SECTION 0x1000 +#define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull +#define MME2_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI_SECTION 0x1000 +#define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull +#define MME2_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME2_CTRL_ETF_SECTION 0x1000 +#define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull +#define MME2_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME2_CTRL_SPMU_SECTION 0x1000 +#define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull +#define MME2_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI0_SECTION 0x1000 +#define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull +#define MME2_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME2_CTRL_CTI1_SECTION 0x1000 +#define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull +#define MME2_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME2_CTRL_BMON0_SECTION 0x1000 +#define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull +#define MME2_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME2_CTRL_BMON1_SECTION 0x39000 +#define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull +#define MME3_ACC_STM_MAX_OFFSET 0x1000 +#define MME3_ACC_STM_SECTION 0x1000 +#define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull +#define MME3_ACC_CTI_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI_SECTION 0x1000 +#define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull +#define MME3_ACC_ETF_MAX_OFFSET 0x1000 +#define MME3_ACC_ETF_SECTION 0x1000 +#define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull +#define MME3_ACC_SPMU_MAX_OFFSET 0x1000 +#define MME3_ACC_SPMU_SECTION 0x1000 +#define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull +#define MME3_ACC_CTI0_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI0_SECTION 0x1000 +#define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull +#define MME3_ACC_CTI1_MAX_OFFSET 0x1000 +#define MME3_ACC_CTI1_SECTION 0x1000 +#define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull +#define MME3_ACC_BMON0_MAX_OFFSET 0x1000 +#define MME3_ACC_BMON0_SECTION 0x9000 +#define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull +#define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000 +#define MME3_ACC_FUNNEL_SECTION 0x11000 +#define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull +#define MME3_SBAB_STM_MAX_OFFSET 0x1000 +#define MME3_SBAB_STM_SECTION 0x1000 +#define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull +#define MME3_SBAB_CTI_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI_SECTION 0x1000 +#define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull +#define MME3_SBAB_ETF_MAX_OFFSET 0x1000 +#define MME3_SBAB_ETF_SECTION 0x1000 +#define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull +#define MME3_SBAB_SPMU_MAX_OFFSET 0x1000 +#define MME3_SBAB_SPMU_SECTION 0x1000 +#define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull +#define MME3_SBAB_CTI0_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI0_SECTION 0x1000 +#define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull +#define MME3_SBAB_CTI1_MAX_OFFSET 0x1000 +#define MME3_SBAB_CTI1_SECTION 0x1000 +#define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull +#define MME3_SBAB_BMON0_MAX_OFFSET 0x1000 +#define MME3_SBAB_BMON0_SECTION 0x1000 +#define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull +#define MME3_SBAB_BMON1_MAX_OFFSET 0x1000 +#define MME3_SBAB_BMON1_SECTION 0x19000 +#define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull +#define MME3_CTRL_STM_MAX_OFFSET 0x1000 +#define MME3_CTRL_STM_SECTION 0x1000 +#define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull +#define MME3_CTRL_CTI_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI_SECTION 0x1000 +#define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull +#define MME3_CTRL_ETF_MAX_OFFSET 0x1000 +#define MME3_CTRL_ETF_SECTION 0x1000 +#define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull +#define MME3_CTRL_SPMU_MAX_OFFSET 0x1000 +#define MME3_CTRL_SPMU_SECTION 0x1000 +#define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull +#define MME3_CTRL_CTI0_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI0_SECTION 0x1000 +#define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull +#define MME3_CTRL_CTI1_MAX_OFFSET 0x1000 +#define MME3_CTRL_CTI1_SECTION 0x1000 +#define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull +#define MME3_CTRL_BMON0_MAX_OFFSET 0x1000 +#define MME3_CTRL_BMON0_SECTION 0x1000 +#define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull +#define MME3_CTRL_BMON1_MAX_OFFSET 0x1000 +#define MME3_CTRL_BMON1_SECTION 0x18000 +#define mmIC_ROM_TABLE_BASE 0x7FFE200000ull +#define IC_ROM_TABLE_MAX_OFFSET 0x1000 +#define IC_ROM_TABLE_SECTION 0x1000 +#define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull +#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull +#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull +#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull +#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull +#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull +#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull +#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull +#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y0_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull +#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull +#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull +#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull +#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull +#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull +#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull +#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull +#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y1_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull +#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull +#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull +#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull +#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull +#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull +#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull +#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull +#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y2_X7_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull +#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X0_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull +#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X1_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull +#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X2_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull +#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X4_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull +#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X3_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull +#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X5_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull +#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X6_FUNNEL_SECTION 0x8000 +#define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull +#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000 +#define SRAM_Y3_X7_FUNNEL_SECTION 0x7000 +#define mmIF_ROM_TABLE_BASE 0x7FFE300000ull +#define IF_ROM_TABLE_MAX_OFFSET 0x1000 +#define IF_ROM_TABLE_SECTION 0x1000 +#define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull +#define SIF_FUNNEL_0_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_0_SECTION 0x10000 +#define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull +#define SIF_FUNNEL_1_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_1_SECTION 0x10000 +#define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull +#define SIF_FUNNEL_2_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_2_SECTION 0x10000 +#define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull +#define SIF_FUNNEL_3_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_3_SECTION 0x10000 +#define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull +#define SIF_FUNNEL_4_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_4_SECTION 0x10000 +#define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull +#define SIF_FUNNEL_5_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_5_SECTION 0x10000 +#define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull +#define SIF_FUNNEL_6_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_6_SECTION 0x10000 +#define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull +#define SIF_FUNNEL_7_MAX_OFFSET 0x1000 +#define SIF_FUNNEL_7_SECTION 0x10000 +#define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull +#define NIF_FUNNEL_0_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_0_SECTION 0x10000 +#define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull +#define NIF_FUNNEL_1_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_1_SECTION 0x10000 +#define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull +#define NIF_FUNNEL_2_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_2_SECTION 0x10000 +#define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull +#define NIF_FUNNEL_3_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_3_SECTION 0x10000 +#define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull +#define NIF_FUNNEL_4_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_4_SECTION 0x10000 +#define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull +#define NIF_FUNNEL_5_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_5_SECTION 0x10000 +#define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull +#define NIF_FUNNEL_6_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_6_SECTION 0x10000 +#define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull +#define NIF_FUNNEL_7_MAX_OFFSET 0x1000 +#define NIF_FUNNEL_7_SECTION 0xF000 +#define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull +#define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_IF_ROM_TABLE_SECTION 0x1000 +#define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull +#define DMA_IF_W_S_STM_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_STM_SECTION 0x1000 +#define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull +#define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull +#define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_ETF_SECTION 0x2000 +#define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull +#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull +#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull +#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull +#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull +#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull +#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull +#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull +#define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_W_S_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull +#define DMA_IF_E_S_STM_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_STM_SECTION 0x1000 +#define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull +#define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull +#define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_ETF_SECTION 0x2000 +#define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull +#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull +#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull +#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull +#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull +#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull +#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull +#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull +#define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_E_S_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull +#define DMA_IF_W_N_STM_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_STM_SECTION 0x1000 +#define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull +#define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull +#define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_ETF_SECTION 0x2000 +#define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull +#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull +#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull +#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull +#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull +#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull +#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull +#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull +#define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_W_N_FUNNEL_SECTION 0x12000 +#define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull +#define DMA_IF_E_N_STM_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_STM_SECTION 0x1000 +#define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull +#define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull +#define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_ETF_SECTION 0x2000 +#define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull +#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull +#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull +#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull +#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull +#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull +#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000 +#define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull +#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000 +#define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull +#define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000 +#define DMA_IF_E_N_FUNNEL_SECTION 0x11000 +#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull +#define CPU_ROM_TABLE_MAX_OFFSET 0x1000 +#define CPU_ROM_TABLE_SECTION 0x1000 +#define mmCPU_ETF_0_BASE 0x7FFE481000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 +#define mmCPU_ETF_1_BASE 0x7FFE482000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 +#define mmCPU_CTI_BASE 0x7FFE484000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 +#define mmCPU_FUNNEL_BASE 0x7FFE485000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 +#define mmCPU_STM_BASE 0x7FFE486000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 +#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 +#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 +#define mmCPU_WR_BMON_BASE 0x7FFE489000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 +#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x76000 +#define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull +#define DMA_ROM_TABLE_MAX_OFFSET 0x1000 +#define DMA_ROM_TABLE_SECTION 0x1000 +#define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull +#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_STM_SECTION 0x1000 +#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull +#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull +#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull +#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_0_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull +#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull +#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_0_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull +#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_0_SECTION 0x1000 +#define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull +#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_0_BMON_1_SECTION 0x19000 +#define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull +#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_STM_SECTION 0x1000 +#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull +#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull +#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull +#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_1_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull +#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull +#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_1_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull +#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_0_SECTION 0x1000 +#define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull +#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_1_BMON_1_SECTION 0x19000 +#define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull +#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_STM_SECTION 0x1000 +#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull +#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull +#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull +#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_2_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull +#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull +#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_2_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull +#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_0_SECTION 0x1000 +#define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull +#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_2_BMON_1_SECTION 0x19000 +#define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull +#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_STM_SECTION 0x1000 +#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull +#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull +#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull +#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_3_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull +#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull +#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_3_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull +#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_0_SECTION 0x1000 +#define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull +#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_3_BMON_1_SECTION 0x19000 +#define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull +#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_STM_SECTION 0x1000 +#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull +#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull +#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull +#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_4_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull +#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull +#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_4_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull +#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_0_SECTION 0x1000 +#define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull +#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_4_BMON_1_SECTION 0x19000 +#define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull +#define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_STM_SECTION 0x1000 +#define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull +#define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull +#define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull +#define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_5_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull +#define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull +#define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_5_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull +#define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_0_SECTION 0x1000 +#define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull +#define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_5_BMON_1_SECTION 0x19000 +#define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull +#define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_STM_SECTION 0x1000 +#define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull +#define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull +#define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull +#define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_6_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull +#define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull +#define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_6_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull +#define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_0_SECTION 0x1000 +#define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull +#define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_6_BMON_1_SECTION 0x19000 +#define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull +#define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_STM_SECTION 0x1000 +#define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull +#define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_CTI_SECTION 0x1000 +#define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull +#define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_ETF_SECTION 0x1000 +#define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull +#define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000 +#define DMA_CH_7_CS_SPMU_SECTION 0x1000 +#define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull +#define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_CTI_SECTION 0x1000 +#define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull +#define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000 +#define DMA_CH_7_USER_CTI_SECTION 0x1000 +#define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull +#define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_0_SECTION 0x1000 +#define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull +#define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000 +#define DMA_CH_7_BMON_1_SECTION 0x18000 +#define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull +#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_W_S_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull +#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_E_S_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull +#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_W_N_SECTION 0x80000 +#define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull +#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000 +#define NIC_TPC_FUNNEL_E_N_SECTION 0x80000 +#define mmCA53_BASE 0x7FFE800000ull +#define CA53_MAX_OFFSET 0x141000 +#define CA53_SECTION 0x400000 +#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 +#define mmPCIE_STM_BASE 0x7FFEC01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 +#define mmPCIE_ETF_BASE 0x7FFEC02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 +#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 +#define mmPCIE_SPMU_BASE 0x7FFEC04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 +#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x1000 +#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull +#define PCIE_FUNNEL_MAX_OFFSET 0x1000 +#define PCIE_FUNNEL_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 +#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 +#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 +#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x7000 +#define mmMMU_CS_STM_BASE 0x7FFEC11000ull +#define MMU_CS_STM_MAX_OFFSET 0x1000 +#define MMU_CS_STM_SECTION 0x1000 +#define mmMMU_CS_CTI_BASE 0x7FFEC12000ull +#define MMU_CS_CTI_MAX_OFFSET 0x1000 +#define MMU_CS_CTI_SECTION 0x1000 +#define mmMMU_CS_ETF_BASE 0x7FFEC13000ull +#define MMU_CS_ETF_MAX_OFFSET 0x1000 +#define MMU_CS_ETF_SECTION 0x1000 +#define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull +#define MMU_CS_SPMU_MAX_OFFSET 0x1000 +#define MMU_CS_SPMU_SECTION 0x1000 +#define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull +#define MMU_BMON_CTI_MAX_OFFSET 0x1000 +#define MMU_BMON_CTI_SECTION 0x1000 +#define mmMMU_USER_CTI_BASE 0x7FFEC16000ull +#define MMU_USER_CTI_MAX_OFFSET 0x1000 +#define MMU_USER_CTI_SECTION 0x1000 +#define mmMMU_BMON_0_BASE 0x7FFEC17000ull +#define MMU_BMON_0_MAX_OFFSET 0x1000 +#define MMU_BMON_0_SECTION 0x1000 +#define mmMMU_BMON_1_BASE 0x7FFEC18000ull +#define MMU_BMON_1_MAX_OFFSET 0x1000 +#define MMU_BMON_1_SECTION 0x28000 +#define mmPSOC_CTI_BASE 0x7FFEC40000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 +#define mmPSOC_STM_BASE 0x7FFEC41000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 +#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 +#define mmPSOC_ETR_BASE 0x7FFEC43000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 +#define mmPSOC_ETF_BASE 0x7FFEC44000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 +#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xB000 +#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x70000 +#define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull +#define NIC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC0_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull +#define STM_0_NIC0_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC0_DBG_SECTION 0x1000 +#define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull +#define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC0_DBG_SECTION 0x1000 +#define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull +#define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC0_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull +#define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC0_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull +#define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC0_DBG_SECTION 0xB000 +#define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull +#define STM_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC0_DBG_SECTION 0x1000 +#define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull +#define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC0_DBG_SECTION 0x1000 +#define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull +#define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC0_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull +#define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC0_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull +#define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC0_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull +#define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC0_DBG_SECTION 0x1000 +#define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull +#define BMON0_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC0_DBG_SECTION 0x1000 +#define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull +#define BMON1_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC0_DBG_SECTION 0x1000 +#define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull +#define BMON2_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC0_DBG_SECTION 0x1000 +#define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull +#define BMON3_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC0_DBG_SECTION 0x1000 +#define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull +#define BMON4_NIC0_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC0_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull +#define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC0_DBG_SECTION 0x1F000 +#define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull +#define NIC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC1_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull +#define STM_0_NIC1_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC1_DBG_SECTION 0x1000 +#define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull +#define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC1_DBG_SECTION 0x1000 +#define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull +#define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC1_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull +#define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC1_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull +#define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC1_DBG_SECTION 0xB000 +#define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull +#define STM_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC1_DBG_SECTION 0x1000 +#define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull +#define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC1_DBG_SECTION 0x1000 +#define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull +#define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC1_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull +#define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC1_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull +#define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC1_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull +#define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC1_DBG_SECTION 0x1000 +#define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull +#define BMON0_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC1_DBG_SECTION 0x1000 +#define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull +#define BMON1_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC1_DBG_SECTION 0x1000 +#define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull +#define BMON2_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC1_DBG_SECTION 0x1000 +#define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull +#define BMON3_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC1_DBG_SECTION 0x1000 +#define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull +#define BMON4_NIC1_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC1_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull +#define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC1_DBG_SECTION 0x1F000 +#define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull +#define NIC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC2_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull +#define STM_0_NIC2_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC2_DBG_SECTION 0x1000 +#define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull +#define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC2_DBG_SECTION 0x1000 +#define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull +#define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC2_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull +#define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC2_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull +#define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC2_DBG_SECTION 0xB000 +#define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull +#define STM_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC2_DBG_SECTION 0x1000 +#define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull +#define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC2_DBG_SECTION 0x1000 +#define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull +#define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC2_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull +#define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC2_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull +#define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC2_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull +#define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC2_DBG_SECTION 0x1000 +#define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull +#define BMON0_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC2_DBG_SECTION 0x1000 +#define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull +#define BMON1_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC2_DBG_SECTION 0x1000 +#define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull +#define BMON2_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC2_DBG_SECTION 0x1000 +#define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull +#define BMON3_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC2_DBG_SECTION 0x1000 +#define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull +#define BMON4_NIC2_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC2_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull +#define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC2_DBG_SECTION 0x1F000 +#define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull +#define NIC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC3_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull +#define STM_0_NIC3_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC3_DBG_SECTION 0x1000 +#define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull +#define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC3_DBG_SECTION 0x1000 +#define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull +#define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC3_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull +#define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC3_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull +#define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC3_DBG_SECTION 0xB000 +#define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull +#define STM_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC3_DBG_SECTION 0x1000 +#define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull +#define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC3_DBG_SECTION 0x1000 +#define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull +#define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC3_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull +#define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC3_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull +#define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC3_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull +#define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC3_DBG_SECTION 0x1000 +#define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull +#define BMON0_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC3_DBG_SECTION 0x1000 +#define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull +#define BMON1_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC3_DBG_SECTION 0x1000 +#define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull +#define BMON2_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC3_DBG_SECTION 0x1000 +#define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull +#define BMON3_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC3_DBG_SECTION 0x1000 +#define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull +#define BMON4_NIC3_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC3_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull +#define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC3_DBG_SECTION 0x1F000 +#define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull +#define NIC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define NIC4_ROM_TABLE_SECTION 0x1000 +#define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull +#define STM_0_NIC4_DBG_MAX_OFFSET 0x21000 +#define STM_0_NIC4_DBG_SECTION 0x1000 +#define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull +#define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define CTI_0_NIC4_DBG_SECTION 0x1000 +#define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull +#define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define ETF_0_NIC4_DBG_SECTION 0x1000 +#define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull +#define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define SPMU_0_NIC4_DBG_SECTION 0x2000 +#define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull +#define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_0_NIC4_DBG_SECTION 0xB000 +#define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull +#define STM_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define STM_1_NIC4_DBG_SECTION 0x1000 +#define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull +#define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define CTI_1_NIC4_DBG_SECTION 0x1000 +#define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull +#define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define ETF_1_NIC4_DBG_SECTION 0x1000 +#define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull +#define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define SPMU_1_NIC4_DBG_SECTION 0x1000 +#define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull +#define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON_CTI_NIC4_DBG_SECTION 0x1000 +#define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull +#define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 +#define USER_CTI_1_NIC4_DBG_SECTION 0x1000 +#define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull +#define BMON0_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON0_NIC4_DBG_SECTION 0x1000 +#define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull +#define BMON1_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON1_NIC4_DBG_SECTION 0x1000 +#define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull +#define BMON2_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON2_NIC4_DBG_SECTION 0x1000 +#define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull +#define BMON3_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON3_NIC4_DBG_SECTION 0x1000 +#define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull +#define BMON4_NIC4_DBG_MAX_OFFSET 0x1000 +#define BMON4_NIC4_DBG_SECTION 0x6000 +#define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull +#define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000 +#define FUNNEL_NIC4_DBG_SECTION 0x21F000 +#define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull +#define TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC0_ROM_TABLE_SECTION 0x1000 +#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull +#define TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC0_EML_SPMU_SECTION 0x1000 +#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull +#define TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define TPC0_EML_ETF_SECTION 0x1000 +#define mmTPC0_EML_STM_BASE 0x7FFF003000ull +#define TPC0_EML_STM_MAX_OFFSET 0x1000 +#define TPC0_EML_STM_SECTION 0x2000 +#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull +#define TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define TPC0_EML_CTI_SECTION 0x1000 +#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull +#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC0_EML_FUNNEL_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull +#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull +#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull +#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull +#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC0_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull +#define TPC0_EML_CFG_MAX_OFFSET 0x3380 +#define TPC0_EML_CFG_SECTION 0x1000 +#define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull +#define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC0_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull +#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull +#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull +#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull +#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull +#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull +#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull +#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull +#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull +#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull +#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull +#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull +#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull +#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull +#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull +#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull +#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull +#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull +#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull +#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull +#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull +#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull +#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull +#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull +#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull +#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull +#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull +#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull +#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull +#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull +#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull +#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull +#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull +#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull +#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull +#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull +#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC0_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull +#define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC0_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull +#define TPC0_EML_CS_MAX_OFFSET 0x1000 +#define TPC0_EML_CS_SECTION 0x1000 +#define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull +#define TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC1_ROM_TABLE_SECTION 0x1000 +#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull +#define TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC1_EML_SPMU_SECTION 0x1000 +#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull +#define TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define TPC1_EML_ETF_SECTION 0x1000 +#define mmTPC1_EML_STM_BASE 0x7FFF203000ull +#define TPC1_EML_STM_MAX_OFFSET 0x1000 +#define TPC1_EML_STM_SECTION 0x2000 +#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull +#define TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define TPC1_EML_CTI_SECTION 0x1000 +#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull +#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC1_EML_FUNNEL_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull +#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull +#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull +#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull +#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC1_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull +#define TPC1_EML_CFG_MAX_OFFSET 0x3380 +#define TPC1_EML_CFG_SECTION 0x1000 +#define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull +#define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC1_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull +#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull +#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull +#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull +#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull +#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull +#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull +#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull +#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull +#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull +#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull +#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull +#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull +#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull +#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull +#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull +#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull +#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull +#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull +#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull +#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull +#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull +#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull +#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull +#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull +#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull +#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull +#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull +#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull +#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull +#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull +#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull +#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull +#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull +#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull +#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull +#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC1_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull +#define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC1_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull +#define TPC1_EML_CS_MAX_OFFSET 0x1000 +#define TPC1_EML_CS_SECTION 0x1000 +#define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull +#define TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC2_ROM_TABLE_SECTION 0x1000 +#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull +#define TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC2_EML_SPMU_SECTION 0x1000 +#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull +#define TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define TPC2_EML_ETF_SECTION 0x1000 +#define mmTPC2_EML_STM_BASE 0x7FFF403000ull +#define TPC2_EML_STM_MAX_OFFSET 0x1000 +#define TPC2_EML_STM_SECTION 0x2000 +#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull +#define TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define TPC2_EML_CTI_SECTION 0x1000 +#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull +#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC2_EML_FUNNEL_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull +#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull +#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull +#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull +#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC2_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull +#define TPC2_EML_CFG_MAX_OFFSET 0x3380 +#define TPC2_EML_CFG_SECTION 0x1000 +#define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull +#define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC2_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull +#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull +#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull +#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull +#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull +#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull +#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull +#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull +#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull +#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull +#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull +#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull +#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull +#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull +#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull +#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull +#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull +#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull +#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull +#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull +#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull +#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull +#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull +#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull +#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull +#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull +#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull +#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull +#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull +#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull +#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull +#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull +#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull +#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull +#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull +#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull +#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC2_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull +#define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC2_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull +#define TPC2_EML_CS_MAX_OFFSET 0x1000 +#define TPC2_EML_CS_SECTION 0x1000 +#define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull +#define TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC3_ROM_TABLE_SECTION 0x1000 +#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull +#define TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC3_EML_SPMU_SECTION 0x1000 +#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull +#define TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define TPC3_EML_ETF_SECTION 0x1000 +#define mmTPC3_EML_STM_BASE 0x7FFF603000ull +#define TPC3_EML_STM_MAX_OFFSET 0x1000 +#define TPC3_EML_STM_SECTION 0x2000 +#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull +#define TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define TPC3_EML_CTI_SECTION 0x1000 +#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull +#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC3_EML_FUNNEL_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull +#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull +#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull +#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull +#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC3_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull +#define TPC3_EML_CFG_MAX_OFFSET 0x3380 +#define TPC3_EML_CFG_SECTION 0x1000 +#define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull +#define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC3_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull +#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull +#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull +#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull +#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull +#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull +#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull +#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull +#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull +#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull +#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull +#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull +#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull +#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull +#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull +#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull +#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull +#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull +#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull +#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull +#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull +#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull +#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull +#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull +#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull +#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull +#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull +#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull +#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull +#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull +#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull +#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull +#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull +#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull +#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull +#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull +#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC3_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull +#define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC3_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull +#define TPC3_EML_CS_MAX_OFFSET 0x1000 +#define TPC3_EML_CS_SECTION 0x1000 +#define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull +#define TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC4_ROM_TABLE_SECTION 0x1000 +#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull +#define TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC4_EML_SPMU_SECTION 0x1000 +#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull +#define TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define TPC4_EML_ETF_SECTION 0x1000 +#define mmTPC4_EML_STM_BASE 0x7FFF803000ull +#define TPC4_EML_STM_MAX_OFFSET 0x1000 +#define TPC4_EML_STM_SECTION 0x2000 +#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull +#define TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define TPC4_EML_CTI_SECTION 0x1000 +#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull +#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC4_EML_FUNNEL_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull +#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull +#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull +#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull +#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC4_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull +#define TPC4_EML_CFG_MAX_OFFSET 0x3380 +#define TPC4_EML_CFG_SECTION 0x1000 +#define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull +#define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC4_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull +#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull +#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull +#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull +#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull +#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull +#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull +#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull +#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull +#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull +#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull +#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull +#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull +#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull +#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull +#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull +#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull +#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull +#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull +#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull +#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull +#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull +#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull +#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull +#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull +#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull +#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull +#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull +#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull +#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull +#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull +#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull +#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull +#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull +#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull +#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull +#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC4_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull +#define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC4_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull +#define TPC4_EML_CS_MAX_OFFSET 0x1000 +#define TPC4_EML_CS_SECTION 0x1000 +#define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull +#define TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC5_ROM_TABLE_SECTION 0x1000 +#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull +#define TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC5_EML_SPMU_SECTION 0x1000 +#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull +#define TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define TPC5_EML_ETF_SECTION 0x1000 +#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull +#define TPC5_EML_STM_MAX_OFFSET 0x1000 +#define TPC5_EML_STM_SECTION 0x2000 +#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull +#define TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define TPC5_EML_CTI_SECTION 0x1000 +#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull +#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC5_EML_FUNNEL_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull +#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull +#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull +#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull +#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC5_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull +#define TPC5_EML_CFG_MAX_OFFSET 0x3380 +#define TPC5_EML_CFG_SECTION 0x1000 +#define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull +#define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC5_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull +#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull +#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull +#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull +#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull +#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull +#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull +#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull +#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull +#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull +#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull +#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull +#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull +#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull +#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull +#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull +#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull +#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull +#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull +#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull +#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull +#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull +#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull +#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull +#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull +#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull +#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull +#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull +#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull +#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull +#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull +#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull +#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull +#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull +#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull +#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull +#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC5_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull +#define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC5_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull +#define TPC5_EML_CS_MAX_OFFSET 0x1000 +#define TPC5_EML_CS_SECTION 0x1000 +#define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull +#define TPC6_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC6_ROM_TABLE_SECTION 0x1000 +#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull +#define TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC6_EML_SPMU_SECTION 0x1000 +#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull +#define TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define TPC6_EML_ETF_SECTION 0x1000 +#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull +#define TPC6_EML_STM_MAX_OFFSET 0x1000 +#define TPC6_EML_STM_SECTION 0x2000 +#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull +#define TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define TPC6_EML_CTI_SECTION 0x1000 +#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull +#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC6_EML_FUNNEL_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull +#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull +#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull +#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull +#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC6_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull +#define TPC6_EML_CFG_MAX_OFFSET 0x3380 +#define TPC6_EML_CFG_SECTION 0x1000 +#define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull +#define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC6_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull +#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull +#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull +#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull +#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull +#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull +#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull +#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull +#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull +#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull +#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull +#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull +#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull +#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull +#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull +#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull +#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull +#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull +#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull +#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull +#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull +#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull +#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull +#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull +#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull +#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull +#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull +#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull +#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull +#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull +#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull +#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull +#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull +#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull +#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull +#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull +#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC6_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull +#define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC6_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull +#define TPC6_EML_CS_MAX_OFFSET 0x1000 +#define TPC6_EML_CS_SECTION 0x1000 +#define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull +#define TPC7_ROM_TABLE_MAX_OFFSET 0x1000 +#define TPC7_ROM_TABLE_SECTION 0x1000 +#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull +#define TPC7_EML_SPMU_MAX_OFFSET 0x1000 +#define TPC7_EML_SPMU_SECTION 0x1000 +#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull +#define TPC7_EML_ETF_MAX_OFFSET 0x1000 +#define TPC7_EML_ETF_SECTION 0x1000 +#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull +#define TPC7_EML_STM_MAX_OFFSET 0x1000 +#define TPC7_EML_STM_SECTION 0x2000 +#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull +#define TPC7_EML_CTI_MAX_OFFSET 0x1000 +#define TPC7_EML_CTI_SECTION 0x1000 +#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull +#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 +#define TPC7_EML_FUNNEL_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull +#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_0_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull +#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_1_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull +#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_2_SECTION 0x1000 +#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull +#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define TPC7_EML_BUSMON_3_SECTION 0x36000 +#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull +#define TPC7_EML_CFG_MAX_OFFSET 0x3380 +#define TPC7_EML_CFG_SECTION 0x1000 +#define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull +#define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400 +#define TPC7_EML_TPC_CFG_SECTION 0x4000 +#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull +#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull +#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull +#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull +#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull +#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull +#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull +#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull +#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull +#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull +#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull +#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull +#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull +#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull +#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull +#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull +#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull +#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 +#define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull +#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780 +#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull +#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull +#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull +#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull +#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull +#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull +#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull +#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull +#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull +#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull +#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull +#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull +#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull +#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull +#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull +#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull +#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 +#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 +#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull +#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 +#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 +#define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull +#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 +#define QM_TPC7_EML_TPC_CFG_SECTION 0x2780 +#define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull +#define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040 +#define TPC7_EML_TPC_QM_SECTION 0x1BD000 +#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull +#define TPC7_EML_CS_MAX_OFFSET 0x1000 + +#endif /* GAUDI_BLOCKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h new file mode 100644 index 000000000000..85e3b5148595 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/gaudi_regs.h @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef ASIC_REG_GAUDI_REGS_H_ +#define ASIC_REG_GAUDI_REGS_H_ + +#include "gaudi_blocks.h" +#include "psoc_global_conf_regs.h" +#include "psoc_timestamp_regs.h" +#include "cpu_if_regs.h" +#include "mmu_up_regs.h" +#include "stlb_regs.h" +#include "dma0_qm_regs.h" +#include "dma1_qm_regs.h" +#include "dma2_qm_regs.h" +#include "dma3_qm_regs.h" +#include "dma4_qm_regs.h" +#include "dma5_qm_regs.h" +#include "dma6_qm_regs.h" +#include "dma7_qm_regs.h" +#include "dma0_core_regs.h" +#include "dma1_core_regs.h" +#include "dma2_core_regs.h" +#include "dma3_core_regs.h" +#include "dma4_core_regs.h" +#include "dma5_core_regs.h" +#include "dma6_core_regs.h" +#include "dma7_core_regs.h" +#include "mme0_ctrl_regs.h" +#include "mme1_ctrl_regs.h" +#include "mme2_ctrl_regs.h" +#include "mme3_ctrl_regs.h" +#include "mme0_qm_regs.h" +#include "mme2_qm_regs.h" +#include "tpc0_cfg_regs.h" +#include "tpc1_cfg_regs.h" +#include "tpc2_cfg_regs.h" +#include "tpc3_cfg_regs.h" +#include "tpc4_cfg_regs.h" +#include "tpc5_cfg_regs.h" +#include "tpc6_cfg_regs.h" +#include "tpc7_cfg_regs.h" +#include "tpc0_qm_regs.h" +#include "tpc1_qm_regs.h" +#include "tpc2_qm_regs.h" +#include "tpc3_qm_regs.h" +#include "tpc4_qm_regs.h" +#include "tpc5_qm_regs.h" +#include "tpc6_qm_regs.h" +#include "tpc7_qm_regs.h" +#include "dma_if_e_n_down_ch0_regs.h" +#include "dma_if_e_n_down_ch1_regs.h" +#include "dma_if_e_s_down_ch0_regs.h" +#include "dma_if_e_s_down_ch1_regs.h" +#include "dma_if_w_n_down_ch0_regs.h" +#include "dma_if_w_n_down_ch1_regs.h" +#include "dma_if_w_s_down_ch0_regs.h" +#include "dma_if_w_s_down_ch1_regs.h" +#include "dma_if_e_n_regs.h" +#include "dma_if_e_s_regs.h" +#include "dma_if_w_n_regs.h" +#include "dma_if_w_s_regs.h" +#include "nif_rtr_ctrl_0_regs.h" +#include "nif_rtr_ctrl_1_regs.h" +#include "nif_rtr_ctrl_2_regs.h" +#include "nif_rtr_ctrl_3_regs.h" +#include "nif_rtr_ctrl_4_regs.h" +#include "nif_rtr_ctrl_5_regs.h" +#include "nif_rtr_ctrl_6_regs.h" +#include "nif_rtr_ctrl_7_regs.h" +#include "sif_rtr_ctrl_0_regs.h" +#include "sif_rtr_ctrl_1_regs.h" +#include "sif_rtr_ctrl_2_regs.h" +#include "sif_rtr_ctrl_3_regs.h" +#include "sif_rtr_ctrl_4_regs.h" +#include "sif_rtr_ctrl_5_regs.h" +#include "sif_rtr_ctrl_6_regs.h" +#include "sif_rtr_ctrl_7_regs.h" +#include "psoc_etr_regs.h" + +#include "dma0_qm_masks.h" +#include "mme0_qm_masks.h" +#include "tpc0_qm_masks.h" +#include "dma0_core_masks.h" +#include "tpc0_cfg_masks.h" +#include "psoc_global_conf_masks.h" + +#include "psoc_pci_pll_regs.h" +#include "psoc_hbm_pll_regs.h" + +#define GAUDI_ECC_MEM_SEL_OFFSET 0xF18 +#define GAUDI_ECC_ADDRESS_OFFSET 0xF1C +#define GAUDI_ECC_SYNDROME_OFFSET 0xF20 +#define GAUDI_ECC_SERR0_OFFSET 0xF30 +#define GAUDI_ECC_SERR1_OFFSET 0xF34 +#define GAUDI_ECC_SERR2_OFFSET 0xF38 +#define GAUDI_ECC_SERR3_OFFSET 0xF3C +#define GAUDI_ECC_DERR0_OFFSET 0xF40 +#define GAUDI_ECC_DERR1_OFFSET 0xF44 +#define GAUDI_ECC_DERR2_OFFSET 0xF48 +#define GAUDI_ECC_DERR3_OFFSET 0xF4C + +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 0x495800 +#define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x496000 +#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4B2000 +#define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x4B6000 +#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4D2000 +#define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4D6000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4F2000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4F2004 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4F3FFC +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4F4000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4F6000 +#define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 0x4F67FC + +#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x300400 +#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x310400 +#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x320400 +#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x330400 +#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x340400 +#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x350400 +#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x360400 +#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x370400 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x300490 +#define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x310490 +#define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x320490 +#define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x330490 +#define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x340490 +#define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x350490 +#define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x360490 +#define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x370490 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x300410 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x310410 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x320410 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x330410 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x340410 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x350410 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x360410 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x370410 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x300450 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x310450 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x320450 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x330450 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x340450 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x350450 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x360450 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x370450 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3004A0 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3104A0 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3204A0 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3304A0 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3404A0 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3504A0 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3604A0 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3704A0 + +#define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3004E0 +#define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3104E0 +#define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3204E0 +#define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3304E0 +#define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3404E0 +#define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3504E0 +#define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3604E0 +#define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3704E0 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x380400 +#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x390400 +#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x3A0400 +#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x3B0400 +#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x3C0400 +#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x3D0400 +#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x3E0400 +#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x3F0400 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x380490 +#define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x390490 +#define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x3A0490 +#define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x3B0490 +#define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x3C0490 +#define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x3D0490 +#define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x3E0490 +#define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x3F0490 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x380410 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x390410 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x3A0410 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x3B0410 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x3C0410 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x3D0410 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x3E0410 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x3F0410 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x380450 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x390450 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x3A0450 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x3B0450 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x3C0450 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x3D0450 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x3E0450 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x3F0450 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3804A0 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3904A0 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3A04A0 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3B04A0 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3C04A0 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3D04A0 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3E04A0 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3F04A0 + +#define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3804E0 +#define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3904E0 +#define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3A04E0 +#define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3B04E0 +#define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3C04E0 +#define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3D04E0 +#define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3E04E0 +#define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3F04E0 + +#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0 0x489030 +#define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1 0x489034 + +#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0 0x4A9030 +#define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1 0x4A9034 + +#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0 0x4C9030 +#define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1 0x4C9034 + +#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0 0x4E9030 +#define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1 0x4E9034 + +#define mmMME1_QM_GLBL_CFG0 0xE8000 +#define mmMME1_QM_GLBL_STS0 0xE8038 + +#define mmMME0_SBAB_SB_STALL 0x4002C +#define mmMME0_SBAB_ARUSER0 0x40034 +#define mmMME0_SBAB_ARUSER1 0x40038 +#define mmMME0_SBAB_PROT 0x40050 + +#define mmMME1_SBAB_SB_STALL 0xC002C +#define mmMME1_SBAB_ARUSER0 0xC0034 +#define mmMME1_SBAB_ARUSER1 0xC0038 +#define mmMME1_SBAB_PROT 0xC0050 + +#define mmMME2_SBAB_SB_STALL 0x14002C +#define mmMME2_SBAB_ARUSER0 0x140034 +#define mmMME2_SBAB_ARUSER1 0x140038 +#define mmMME2_SBAB_PROT 0x140050 + +#define mmMME3_SBAB_SB_STALL 0x1C002C +#define mmMME3_SBAB_ARUSER0 0x1C0034 +#define mmMME3_SBAB_ARUSER1 0x1C0038 +#define mmMME3_SBAB_PROT 0x1C0050 + +#define mmMME0_ACC_ACC_STALL 0x20028 +#define mmMME0_ACC_WBC 0x20038 +#define mmMME0_ACC_PROT 0x20050 + +#define mmMME1_ACC_ACC_STALL 0xA0028 +#define mmMME1_ACC_WBC 0xA0038 +#define mmMME1_ACC_PROT 0xA0050 + +#define mmMME2_ACC_ACC_STALL 0x120028 +#define mmMME2_ACC_WBC 0x120038 +#define mmMME2_ACC_PROT 0x120050 + +#define mmMME3_ACC_ACC_STALL 0x1A0028 +#define mmMME3_ACC_WBC 0x1A0038 +#define mmMME3_ACC_PROT 0x1A0050 + +#define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 + +#define mmPSOC_EFUSE_READ 0xC4A000 +#define mmPSOC_EFUSE_DATA_0 0xC4A080 + +#define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20 +#define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48 +#define mmPCIE_WRAP_HBW_DRAIN_CFG 0xC01D54 +#define mmPCIE_WRAP_LBW_DRAIN_CFG 0xC01D5C + +#define mmPCIE_MSI_INTR_0 0xC13000 + +#define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000 + +#define mmPCIE_AUX_DBI 0xC07490 + +#endif /* ASIC_REG_GAUDI_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h new file mode 100644 index 000000000000..083d073a0128 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_CTRL_REGS_H_ +#define ASIC_REG_MME0_CTRL_REGS_H_ + +/* + ***************************************** + * MME0_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME0_CTRL_ARCH_STATUS 0x60000 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_S 0x60008 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_L 0x6000C + +#define mmMME0_CTRL_ARCH_BASE_ADDR_HIGH_O 0x60010 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_S 0x60014 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_L 0x60018 + +#define mmMME0_CTRL_ARCH_BASE_ADDR_LOW_O 0x6001C + +#define mmMME0_CTRL_ARCH_HEADER_LOW 0x60020 + +#define mmMME0_CTRL_ARCH_HEADER_HIGH 0x60024 + +#define mmMME0_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x60028 + +#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x6002C + +#define mmMME0_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x60030 + +#define mmMME0_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x60034 + +#define mmMME0_CTRL_ARCH_OUTER_LOOP 0x60038 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x6003C + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x60040 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x60044 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x60048 + +#define mmMME0_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x6004C + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x60050 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x60054 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x60058 + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x6005C + +#define mmMME0_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x60060 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x60064 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x60068 + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x6006C + +#define mmMME0_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x60070 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x60074 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x60078 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x6007C + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x60080 + +#define mmMME0_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60084 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x60088 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x6008C + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x60090 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x60094 + +#define mmMME0_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x60098 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_0 0x6009C + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_1 0x600A0 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_2 0x600A4 + +#define mmMME0_CTRL_ARCH_AGU_S_START_OFFSET_3 0x600A8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x600AC + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x600B0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x600B4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x600B8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x600BC + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x600C0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x600C4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x600C8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x600CC + +#define mmMME0_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x600D0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x600D4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x600D8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x600DC + +#define mmMME0_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x600E0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x600E4 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x600E8 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x600EC + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x600F0 + +#define mmMME0_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x600F4 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x600F8 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x600FC + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60100 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60104 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60108 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x6010C + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x60110 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x60114 + +#define mmMME0_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x60118 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6011C + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60120 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60124 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60128 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6012C + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x60130 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x60134 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x60138 + +#define mmMME0_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x6013C + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x60140 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x60144 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x60148 + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x6014C + +#define mmMME0_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x60150 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x60154 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x60158 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x6015C + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x60160 + +#define mmMME0_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x60164 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x60168 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x6016C + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x60170 + +#define mmMME0_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x60174 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x60178 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x6017C + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x60180 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x60184 + +#define mmMME0_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60188 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6018C + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60190 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60194 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60198 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6019C + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x601A0 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x601A4 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x601A8 + +#define mmMME0_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x601AC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x601B0 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x601B4 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x601B8 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x601BC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x601C0 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x601C4 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x601C8 + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x601CC + +#define mmMME0_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x601D0 + +#define mmMME0_CTRL_ARCH_DESC_SB_REPEAT 0x601D4 + +#define mmMME0_CTRL_ARCH_DESC_RATE_LIMITER 0x601D8 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x601DC + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x601E0 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x601E4 + +#define mmMME0_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x601E8 + +#define mmMME0_CTRL_ARCH_DESC_AXI_USER_DATA 0x601EC + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_S 0x601F0 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x601F4 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x601F8 + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x601FC + +#define mmMME0_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x60200 + +#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_S 0x60204 + +#define mmMME0_CTRL_ARCH_DESC_PADDING_VALUE_L 0x60208 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_S 0x6020C + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x60210 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x60214 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x60218 + +#define mmMME0_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x6021C + +#define mmMME0_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x60220 + +#define mmMME0_CTRL_ARCH_DESC_DUMMY 0x60224 + +#define mmMME0_CTRL_CMD 0x60280 + +#define mmMME0_CTRL_STATUS1 0x60284 + +#define mmMME0_CTRL_RESET 0x60288 + +#define mmMME0_CTRL_QM_STALL 0x6028C + +#define mmMME0_CTRL_SYNC_OBJECT_FIFO_TH 0x60290 + +#define mmMME0_CTRL_EUS_ROLLUP_CNT_ADD 0x60294 + +#define mmMME0_CTRL_INTR_CAUSE 0x60298 + +#define mmMME0_CTRL_INTR_MASK 0x6029C + +#define mmMME0_CTRL_LOG_SHADOW 0x602A0 + +#define mmMME0_CTRL_PCU_RL_DESC0 0x602A4 + +#define mmMME0_CTRL_PCU_RL_TOKEN_UPDATE 0x602A8 + +#define mmMME0_CTRL_PCU_RL_TH 0x602AC + +#define mmMME0_CTRL_PCU_RL_MIN 0x602B0 + +#define mmMME0_CTRL_PCU_RL_CTRL_EN 0x602B4 + +#define mmMME0_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x602B8 + +#define mmMME0_CTRL_PCU_DUMMY_A_BF16 0x602BC + +#define mmMME0_CTRL_PCU_DUMMY_B_BF16 0x602C0 + +#define mmMME0_CTRL_PCU_DUMMY_A_FP32_ODD 0x602C4 + +#define mmMME0_CTRL_PCU_DUMMY_A_FP32_EVEN 0x602C8 + +#define mmMME0_CTRL_PCU_DUMMY_B_FP32_ODD 0x602CC + +#define mmMME0_CTRL_PCU_DUMMY_B_FP32_EVEN 0x602D0 + +#define mmMME0_CTRL_PROT 0x602D4 + +#define mmMME0_CTRL_EU_POWER_SAVE_DISABLE 0x602D8 + +#define mmMME0_CTRL_CS_DBG_BLOCK_ID 0x602DC + +#define mmMME0_CTRL_CS_DBG_STATUS_DROP_CNT 0x602E0 + +#define mmMME0_CTRL_TE_CLOSE_CGATE 0x602E4 + +#define mmMME0_CTRL_AGU_SM_INFLIGHT_CNTR 0x602E8 + +#define mmMME0_CTRL_AGU_SM_TOTAL_CNTR 0x602EC + +#define mmMME0_CTRL_EZSYNC_OUT_CREDIT 0x602F0 + +#define mmMME0_CTRL_PCU_RL_SAT_SEC 0x602F4 + +#define mmMME0_CTRL_AGU_SYNC_MSG_AXI_USER 0x602F8 + +#define mmMME0_CTRL_QM_SLV_LBW_CLK_EN 0x602FC + +#define mmMME0_CTRL_SHADOW_0_STATUS 0x60400 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x60408 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x6040C + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x60410 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x60414 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x60418 + +#define mmMME0_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x6041C + +#define mmMME0_CTRL_SHADOW_0_HEADER_LOW 0x60420 + +#define mmMME0_CTRL_SHADOW_0_HEADER_HIGH 0x60424 + +#define mmMME0_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x60428 + +#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x6042C + +#define mmMME0_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x60430 + +#define mmMME0_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x60434 + +#define mmMME0_CTRL_SHADOW_0_OUTER_LOOP 0x60438 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x6043C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x60440 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x60444 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x60448 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x6044C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x60450 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x60454 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x60458 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x6045C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x60460 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x60464 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x60468 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x6046C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x60470 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x60474 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x60478 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x6047C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x60480 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60484 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x60488 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x6048C + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x60490 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x60494 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x60498 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x6049C + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x604A0 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x604A4 + +#define mmMME0_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x604A8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x604AC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x604B0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x604B4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x604B8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x604BC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x604C0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x604C4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x604C8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x604CC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x604D0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x604D4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x604D8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x604DC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x604E0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x604E4 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x604E8 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x604EC + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x604F0 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x604F4 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x604F8 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x604FC + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60500 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60504 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60508 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x6050C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x60510 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x60514 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x60518 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6051C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60520 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60524 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60528 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x6052C + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x60530 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x60534 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x60538 + +#define mmMME0_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x6053C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x60540 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x60544 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x60548 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x6054C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x60550 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x60554 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x60558 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x6055C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x60560 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x60564 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x60568 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x6056C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x60570 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x60574 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x60578 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x6057C + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x60580 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x60584 + +#define mmMME0_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60588 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6058C + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60590 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60594 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60598 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6059C + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x605A0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x605A4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x605A8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x605AC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x605B0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x605B4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x605B8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x605BC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x605C0 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x605C4 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x605C8 + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x605CC + +#define mmMME0_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x605D0 + +#define mmMME0_CTRL_SHADOW_0_DESC_SB_REPEAT 0x605D4 + +#define mmMME0_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x605D8 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x605DC + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x605E0 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x605E4 + +#define mmMME0_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x605E8 + +#define mmMME0_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x605EC + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x605F0 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x605F4 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x605F8 + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x605FC + +#define mmMME0_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x60600 + +#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x60604 + +#define mmMME0_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x60608 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x6060C + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x60610 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x60614 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x60618 + +#define mmMME0_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x6061C + +#define mmMME0_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x60620 + +#define mmMME0_CTRL_SHADOW_0_DESC_DUMMY 0x60624 + +#define mmMME0_CTRL_SHADOW_1_STATUS 0x60680 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x60688 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x6068C + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x60690 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x60694 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x60698 + +#define mmMME0_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x6069C + +#define mmMME0_CTRL_SHADOW_1_HEADER_LOW 0x606A0 + +#define mmMME0_CTRL_SHADOW_1_HEADER_HIGH 0x606A4 + +#define mmMME0_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x606A8 + +#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x606AC + +#define mmMME0_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x606B0 + +#define mmMME0_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x606B4 + +#define mmMME0_CTRL_SHADOW_1_OUTER_LOOP 0x606B8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x606BC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x606C0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x606C4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x606C8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x606CC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x606D0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x606D4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x606D8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x606DC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x606E0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x606E4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x606E8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x606EC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x606F0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x606F4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x606F8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x606FC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x60700 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60704 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x60708 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x6070C + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x60710 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x60714 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x60718 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x6071C + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x60720 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x60724 + +#define mmMME0_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x60728 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x6072C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x60730 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x60734 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x60738 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x6073C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x60740 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x60744 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x60748 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x6074C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x60750 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x60754 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x60758 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x6075C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x60760 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x60764 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x60768 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x6076C + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x60770 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60774 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60778 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x6077C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60780 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60784 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60788 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x6078C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x60790 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x60794 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x60798 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x6079C + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x607A0 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x607A4 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x607A8 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x607AC + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x607B0 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x607B4 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x607B8 + +#define mmMME0_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x607BC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x607C0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x607C4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x607C8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x607CC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x607D0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x607D4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x607D8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x607DC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x607E0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x607E4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x607E8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x607EC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x607F0 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x607F4 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x607F8 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x607FC + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x60800 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x60804 + +#define mmMME0_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60808 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x6080C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60810 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60814 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60818 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x6081C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x60820 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x60824 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x60828 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x6082C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60830 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60834 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60838 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x6083C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60840 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x60844 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x60848 + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x6084C + +#define mmMME0_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x60850 + +#define mmMME0_CTRL_SHADOW_1_DESC_SB_REPEAT 0x60854 + +#define mmMME0_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x60858 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x6085C + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60860 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x60864 + +#define mmMME0_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x60868 + +#define mmMME0_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x6086C + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x60870 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x60874 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x60878 + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x6087C + +#define mmMME0_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x60880 + +#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x60884 + +#define mmMME0_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x60888 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x6088C + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x60890 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x60894 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x60898 + +#define mmMME0_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x6089C + +#define mmMME0_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x608A0 + +#define mmMME0_CTRL_SHADOW_1_DESC_DUMMY 0x608A4 + +#define mmMME0_CTRL_SHADOW_2_STATUS 0x60900 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x60908 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x6090C + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x60910 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x60914 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x60918 + +#define mmMME0_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x6091C + +#define mmMME0_CTRL_SHADOW_2_HEADER_LOW 0x60920 + +#define mmMME0_CTRL_SHADOW_2_HEADER_HIGH 0x60924 + +#define mmMME0_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x60928 + +#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x6092C + +#define mmMME0_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x60930 + +#define mmMME0_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x60934 + +#define mmMME0_CTRL_SHADOW_2_OUTER_LOOP 0x60938 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x6093C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x60940 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x60944 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x60948 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x6094C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x60950 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x60954 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x60958 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x6095C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x60960 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x60964 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x60968 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x6096C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x60970 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x60974 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x60978 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x6097C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x60980 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60984 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x60988 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x6098C + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x60990 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x60994 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x60998 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x6099C + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x609A0 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x609A4 + +#define mmMME0_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x609A8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x609AC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x609B0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x609B4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x609B8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x609BC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x609C0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x609C4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x609C8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x609CC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x609D0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x609D4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x609D8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x609DC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x609E0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x609E4 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x609E8 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x609EC + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x609F0 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x609F4 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x609F8 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x609FC + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60A00 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60A04 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60A08 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x60A0C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x60A10 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x60A14 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x60A18 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60A1C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60A20 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60A24 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60A28 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60A2C + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x60A30 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x60A34 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x60A38 + +#define mmMME0_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x60A3C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x60A40 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x60A44 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x60A48 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x60A4C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x60A50 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x60A54 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x60A58 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x60A5C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x60A60 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x60A64 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x60A68 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x60A6C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x60A70 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x60A74 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x60A78 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x60A7C + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x60A80 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x60A84 + +#define mmMME0_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60A88 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60A8C + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60A90 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60A94 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60A98 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60A9C + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x60AA0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x60AA4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x60AA8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x60AAC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60AB0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60AB4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60AB8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60ABC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60AC0 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x60AC4 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x60AC8 + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x60ACC + +#define mmMME0_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x60AD0 + +#define mmMME0_CTRL_SHADOW_2_DESC_SB_REPEAT 0x60AD4 + +#define mmMME0_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x60AD8 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60ADC + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60AE0 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x60AE4 + +#define mmMME0_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x60AE8 + +#define mmMME0_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x60AEC + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x60AF0 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x60AF4 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x60AF8 + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x60AFC + +#define mmMME0_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x60B00 + +#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x60B04 + +#define mmMME0_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x60B08 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x60B0C + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x60B10 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x60B14 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x60B18 + +#define mmMME0_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x60B1C + +#define mmMME0_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x60B20 + +#define mmMME0_CTRL_SHADOW_2_DESC_DUMMY 0x60B24 + +#define mmMME0_CTRL_SHADOW_3_STATUS 0x60B80 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x60B88 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x60B8C + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x60B90 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x60B94 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x60B98 + +#define mmMME0_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x60B9C + +#define mmMME0_CTRL_SHADOW_3_HEADER_LOW 0x60BA0 + +#define mmMME0_CTRL_SHADOW_3_HEADER_HIGH 0x60BA4 + +#define mmMME0_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x60BA8 + +#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x60BAC + +#define mmMME0_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x60BB0 + +#define mmMME0_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x60BB4 + +#define mmMME0_CTRL_SHADOW_3_OUTER_LOOP 0x60BB8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x60BBC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x60BC0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x60BC4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x60BC8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x60BCC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x60BD0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x60BD4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x60BD8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x60BDC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x60BE0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x60BE4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x60BE8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x60BEC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x60BF0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x60BF4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x60BF8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x60BFC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x60C00 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x60C04 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x60C08 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x60C0C + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x60C10 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x60C14 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x60C18 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x60C1C + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x60C20 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x60C24 + +#define mmMME0_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x60C28 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x60C2C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x60C30 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x60C34 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x60C38 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x60C3C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x60C40 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x60C44 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x60C48 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x60C4C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x60C50 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x60C54 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x60C58 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x60C5C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x60C60 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x60C64 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x60C68 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x60C6C + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x60C70 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x60C74 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x60C78 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x60C7C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x60C80 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x60C84 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x60C88 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x60C8C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x60C90 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x60C94 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x60C98 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x60C9C + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x60CA0 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x60CA4 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x60CA8 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x60CAC + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x60CB0 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x60CB4 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x60CB8 + +#define mmMME0_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x60CBC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x60CC0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x60CC4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x60CC8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x60CCC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x60CD0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x60CD4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x60CD8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x60CDC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x60CE0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x60CE4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x60CE8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x60CEC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x60CF0 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x60CF4 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x60CF8 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x60CFC + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x60D00 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x60D04 + +#define mmMME0_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x60D08 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x60D0C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x60D10 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x60D14 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x60D18 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x60D1C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x60D20 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x60D24 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x60D28 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x60D2C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x60D30 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x60D34 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x60D38 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x60D3C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x60D40 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x60D44 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x60D48 + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x60D4C + +#define mmMME0_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x60D50 + +#define mmMME0_CTRL_SHADOW_3_DESC_SB_REPEAT 0x60D54 + +#define mmMME0_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x60D58 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x60D5C + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x60D60 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x60D64 + +#define mmMME0_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x60D68 + +#define mmMME0_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x60D6C + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x60D70 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x60D74 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x60D78 + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x60D7C + +#define mmMME0_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x60D80 + +#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x60D84 + +#define mmMME0_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x60D88 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x60D8C + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x60D90 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x60D94 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x60D98 + +#define mmMME0_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x60D9C + +#define mmMME0_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x60DA0 + +#define mmMME0_CTRL_SHADOW_3_DESC_DUMMY 0x60DA4 + +#endif /* ASIC_REG_MME0_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h new file mode 100644 index 000000000000..e6dd30ce0ca7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_QM_MASKS_H_ +#define ASIC_REG_MME0_QM_MASKS_H_ + +/* + ***************************************** + * MME0_QM (Prototype: QMAN) + ***************************************** + */ + +/* MME0_QM_GLBL_CFG0 */ +#define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define MME0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define MME0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* MME0_QM_GLBL_CFG1 */ +#define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define MME0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define MME0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define MME0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define MME0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define MME0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define MME0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* MME0_QM_GLBL_PROT */ +#define MME0_QM_GLBL_PROT_PQF_SHIFT 0 +#define MME0_QM_GLBL_PROT_PQF_MASK 0xF +#define MME0_QM_GLBL_PROT_CQF_SHIFT 4 +#define MME0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define MME0_QM_GLBL_PROT_CP_SHIFT 9 +#define MME0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define MME0_QM_GLBL_PROT_ERR_SHIFT 14 +#define MME0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define MME0_QM_GLBL_PROT_ARB_SHIFT 15 +#define MME0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* MME0_QM_GLBL_ERR_CFG */ +#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define MME0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* MME0_QM_GLBL_SECURE_PROPS */ +#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define MME0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define MME0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* MME0_QM_GLBL_NON_SECURE_PROPS */ +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define MME0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* MME0_QM_GLBL_STS0 */ +#define MME0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define MME0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define MME0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define MME0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define MME0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define MME0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define MME0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define MME0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define MME0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define MME0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define MME0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define MME0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define MME0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define MME0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* MME0_QM_GLBL_STS1 */ +#define MME0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define MME0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define MME0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_STS1_4 */ +#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_MSG_EN */ +#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define MME0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_GLBL_MSG_EN_4 */ +#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define MME0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define MME0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define MME0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define MME0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define MME0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define MME0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* MME0_QM_PQ_BASE_LO */ +#define MME0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define MME0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_BASE_HI */ +#define MME0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define MME0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_SIZE */ +#define MME0_QM_PQ_SIZE_VAL_SHIFT 0 +#define MME0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_PI */ +#define MME0_QM_PQ_PI_VAL_SHIFT 0 +#define MME0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_CI */ +#define MME0_QM_PQ_CI_VAL_SHIFT 0 +#define MME0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_PQ_CFG0 */ +#define MME0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define MME0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* MME0_QM_PQ_CFG1 */ +#define MME0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME0_QM_PQ_ARUSER_31_11 */ +#define MME0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_PQ_STS0 */ +#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define MME0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define MME0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define MME0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME0_QM_PQ_STS1 */ +#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define MME0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define MME0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define MME0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* MME0_QM_CQ_CFG0 */ +#define MME0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define MME0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* MME0_QM_CQ_CFG1 */ +#define MME0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define MME0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define MME0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* MME0_QM_CQ_ARUSER_31_11 */ +#define MME0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_CQ_STS0 */ +#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define MME0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define MME0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define MME0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* MME0_QM_CQ_STS1 */ +#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define MME0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define MME0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define MME0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* MME0_QM_CQ_PTR_LO_0 */ +#define MME0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_0 */ +#define MME0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_0 */ +#define MME0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_0 */ +#define MME0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_1 */ +#define MME0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_1 */ +#define MME0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_1 */ +#define MME0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_1 */ +#define MME0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_2 */ +#define MME0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_2 */ +#define MME0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_2 */ +#define MME0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_2 */ +#define MME0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_3 */ +#define MME0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_3 */ +#define MME0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_3 */ +#define MME0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_3 */ +#define MME0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_4 */ +#define MME0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_4 */ +#define MME0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_4 */ +#define MME0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_4 */ +#define MME0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_PTR_LO_STS */ +#define MME0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_PTR_HI_STS */ +#define MME0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_TSIZE_STS */ +#define MME0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define MME0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CQ_CTL_STS */ +#define MME0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define MME0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define MME0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define MME0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* MME0_QM_CQ_IFIFO_CNT */ +#define MME0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define MME0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* MME0_QM_CP_MSG_BASE0_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE0_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE1_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE1_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE2_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE2_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE3_ADDR_LO */ +#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_MSG_BASE3_ADDR_HI */ +#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_TSIZE_OFFSET */ +#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define MME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_FENCE0_RDATA */ +#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE1_RDATA */ +#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE2_RDATA */ +#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE3_RDATA */ +#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* MME0_QM_CP_FENCE0_CNT */ +#define MME0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE1_CNT */ +#define MME0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE2_CNT */ +#define MME0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_FENCE3_CNT */ +#define MME0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define MME0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* MME0_QM_CP_STS */ +#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define MME0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define MME0_QM_CP_STS_ERDY_SHIFT 16 +#define MME0_QM_CP_STS_ERDY_MASK 0x10000 +#define MME0_QM_CP_STS_RRDY_SHIFT 17 +#define MME0_QM_CP_STS_RRDY_MASK 0x20000 +#define MME0_QM_CP_STS_MRDY_SHIFT 18 +#define MME0_QM_CP_STS_MRDY_MASK 0x40000 +#define MME0_QM_CP_STS_SW_STOP_SHIFT 19 +#define MME0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define MME0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define MME0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define MME0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* MME0_QM_CP_CURRENT_INST_LO */ +#define MME0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define MME0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_CURRENT_INST_HI */ +#define MME0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define MME0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_CP_BARRIER_CFG */ +#define MME0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define MME0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define MME0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define MME0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* MME0_QM_CP_DBG_0 */ +#define MME0_QM_CP_DBG_0_CS_SHIFT 0 +#define MME0_QM_CP_DBG_0_CS_MASK 0xF +#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define MME0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define MME0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define MME0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define MME0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define MME0_QM_CP_DBG_0_STALL_SHIFT 7 +#define MME0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* MME0_QM_CP_ARUSER_31_11 */ +#define MME0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_CP_AWUSER_31_11 */ +#define MME0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_ARB_CFG_0 */ +#define MME0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define MME0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define MME0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define MME0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define MME0_QM_ARB_CFG_0_EN_SHIFT 8 +#define MME0_QM_ARB_CFG_0_EN_MASK 0x100 +#define MME0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define MME0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define MME0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* MME0_QM_ARB_CHOISE_Q_PUSH */ +#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define MME0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* MME0_QM_ARB_WRR_WEIGHT */ +#define MME0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define MME0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_CFG_1 */ +#define MME0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define MME0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* MME0_QM_ARB_MST_AVAIL_CRED */ +#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* MME0_QM_ARB_MST_CRED_INC */ +#define MME0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_SLAVE_EN */ +#define MME0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_MST_QUIET_PER */ +#define MME0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_CHOISE_WDT */ +#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_SLV_ID */ +#define MME0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* MME0_QM_ARB_MSG_MAX_INFLIGHT */ +#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define MME0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* MME0_QM_ARB_MSG_AWUSER_31_11 */ +#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* MME0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define MME0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define MME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* MME0_QM_ARB_BASE_LO */ +#define MME0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define MME0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_BASE_HI */ +#define MME0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define MME0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_STATE_STS */ +#define MME0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_ARB_CHOISE_FULLNESS_STS */ +#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* MME0_QM_ARB_MSG_STS */ +#define MME0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define MME0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define MME0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* MME0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define MME0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* MME0_QM_ARB_ERR_CAUSE */ +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define MME0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define MME0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* MME0_QM_ARB_ERR_MSG_EN */ +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define MME0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define MME0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* MME0_QM_ARB_ERR_STS_DRP */ +#define MME0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define MME0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* MME0_QM_ARB_MST_CRED_STS */ +#define MME0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define MME0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* MME0_QM_CGM_CFG */ +#define MME0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define MME0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define MME0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define MME0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define MME0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define MME0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define MME0_QM_CGM_CFG_EN_SHIFT 31 +#define MME0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* MME0_QM_CGM_STS */ +#define MME0_QM_CGM_STS_ST_SHIFT 0 +#define MME0_QM_CGM_STS_ST_MASK 0x3 +#define MME0_QM_CGM_STS_CG_SHIFT 4 +#define MME0_QM_CGM_STS_CG_MASK 0x10 +#define MME0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define MME0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define MME0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define MME0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define MME0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define MME0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* MME0_QM_CGM_CFG1 */ +#define MME0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define MME0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* MME0_QM_LOCAL_RANGE_BASE */ +#define MME0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define MME0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* MME0_QM_LOCAL_RANGE_SIZE */ +#define MME0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define MME0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* MME0_QM_CSMR_STRICT_PRIO_CFG */ +#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define MME0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* MME0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* MME0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* MME0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define MME0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* MME0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define MME0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* MME0_QM_GLBL_AXCACHE */ +#define MME0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define MME0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define MME0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define MME0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* MME0_QM_IND_GW_APB_CFG */ +#define MME0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define MME0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define MME0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define MME0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* MME0_QM_IND_GW_APB_WDATA */ +#define MME0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define MME0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_IND_GW_APB_RDATA */ +#define MME0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define MME0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_IND_GW_APB_STATUS */ +#define MME0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define MME0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define MME0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define MME0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* MME0_QM_GLBL_ERR_ADDR_LO */ +#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_ERR_ADDR_HI */ +#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_ERR_WDATA */ +#define MME0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define MME0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* MME0_QM_GLBL_MEM_INIT_BUSY */ +#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define MME0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_MME0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h new file mode 100644 index 000000000000..4f078b328b00 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME0_QM_REGS_H_ +#define ASIC_REG_MME0_QM_REGS_H_ + +/* + ***************************************** + * MME0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME0_QM_GLBL_CFG0 0x68000 + +#define mmMME0_QM_GLBL_CFG1 0x68004 + +#define mmMME0_QM_GLBL_PROT 0x68008 + +#define mmMME0_QM_GLBL_ERR_CFG 0x6800C + +#define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010 + +#define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014 + +#define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018 + +#define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C + +#define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1 0x68028 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2 0x6802C + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3 0x68030 + +#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4 0x68034 + +#define mmMME0_QM_GLBL_STS0 0x68038 + +#define mmMME0_QM_GLBL_STS1_0 0x68040 + +#define mmMME0_QM_GLBL_STS1_1 0x68044 + +#define mmMME0_QM_GLBL_STS1_2 0x68048 + +#define mmMME0_QM_GLBL_STS1_3 0x6804C + +#define mmMME0_QM_GLBL_STS1_4 0x68050 + +#define mmMME0_QM_GLBL_MSG_EN_0 0x68054 + +#define mmMME0_QM_GLBL_MSG_EN_1 0x68058 + +#define mmMME0_QM_GLBL_MSG_EN_2 0x6805C + +#define mmMME0_QM_GLBL_MSG_EN_3 0x68060 + +#define mmMME0_QM_GLBL_MSG_EN_4 0x68068 + +#define mmMME0_QM_PQ_BASE_LO_0 0x68070 + +#define mmMME0_QM_PQ_BASE_LO_1 0x68074 + +#define mmMME0_QM_PQ_BASE_LO_2 0x68078 + +#define mmMME0_QM_PQ_BASE_LO_3 0x6807C + +#define mmMME0_QM_PQ_BASE_HI_0 0x68080 + +#define mmMME0_QM_PQ_BASE_HI_1 0x68084 + +#define mmMME0_QM_PQ_BASE_HI_2 0x68088 + +#define mmMME0_QM_PQ_BASE_HI_3 0x6808C + +#define mmMME0_QM_PQ_SIZE_0 0x68090 + +#define mmMME0_QM_PQ_SIZE_1 0x68094 + +#define mmMME0_QM_PQ_SIZE_2 0x68098 + +#define mmMME0_QM_PQ_SIZE_3 0x6809C + +#define mmMME0_QM_PQ_PI_0 0x680A0 + +#define mmMME0_QM_PQ_PI_1 0x680A4 + +#define mmMME0_QM_PQ_PI_2 0x680A8 + +#define mmMME0_QM_PQ_PI_3 0x680AC + +#define mmMME0_QM_PQ_CI_0 0x680B0 + +#define mmMME0_QM_PQ_CI_1 0x680B4 + +#define mmMME0_QM_PQ_CI_2 0x680B8 + +#define mmMME0_QM_PQ_CI_3 0x680BC + +#define mmMME0_QM_PQ_CFG0_0 0x680C0 + +#define mmMME0_QM_PQ_CFG0_1 0x680C4 + +#define mmMME0_QM_PQ_CFG0_2 0x680C8 + +#define mmMME0_QM_PQ_CFG0_3 0x680CC + +#define mmMME0_QM_PQ_CFG1_0 0x680D0 + +#define mmMME0_QM_PQ_CFG1_1 0x680D4 + +#define mmMME0_QM_PQ_CFG1_2 0x680D8 + +#define mmMME0_QM_PQ_CFG1_3 0x680DC + +#define mmMME0_QM_PQ_ARUSER_31_11_0 0x680E0 + +#define mmMME0_QM_PQ_ARUSER_31_11_1 0x680E4 + +#define mmMME0_QM_PQ_ARUSER_31_11_2 0x680E8 + +#define mmMME0_QM_PQ_ARUSER_31_11_3 0x680EC + +#define mmMME0_QM_PQ_STS0_0 0x680F0 + +#define mmMME0_QM_PQ_STS0_1 0x680F4 + +#define mmMME0_QM_PQ_STS0_2 0x680F8 + +#define mmMME0_QM_PQ_STS0_3 0x680FC + +#define mmMME0_QM_PQ_STS1_0 0x68100 + +#define mmMME0_QM_PQ_STS1_1 0x68104 + +#define mmMME0_QM_PQ_STS1_2 0x68108 + +#define mmMME0_QM_PQ_STS1_3 0x6810C + +#define mmMME0_QM_CQ_CFG0_0 0x68110 + +#define mmMME0_QM_CQ_CFG0_1 0x68114 + +#define mmMME0_QM_CQ_CFG0_2 0x68118 + +#define mmMME0_QM_CQ_CFG0_3 0x6811C + +#define mmMME0_QM_CQ_CFG0_4 0x68120 + +#define mmMME0_QM_CQ_CFG1_0 0x68124 + +#define mmMME0_QM_CQ_CFG1_1 0x68128 + +#define mmMME0_QM_CQ_CFG1_2 0x6812C + +#define mmMME0_QM_CQ_CFG1_3 0x68130 + +#define mmMME0_QM_CQ_CFG1_4 0x68134 + +#define mmMME0_QM_CQ_ARUSER_31_11_0 0x68138 + +#define mmMME0_QM_CQ_ARUSER_31_11_1 0x6813C + +#define mmMME0_QM_CQ_ARUSER_31_11_2 0x68140 + +#define mmMME0_QM_CQ_ARUSER_31_11_3 0x68144 + +#define mmMME0_QM_CQ_ARUSER_31_11_4 0x68148 + +#define mmMME0_QM_CQ_STS0_0 0x6814C + +#define mmMME0_QM_CQ_STS0_1 0x68150 + +#define mmMME0_QM_CQ_STS0_2 0x68154 + +#define mmMME0_QM_CQ_STS0_3 0x68158 + +#define mmMME0_QM_CQ_STS0_4 0x6815C + +#define mmMME0_QM_CQ_STS1_0 0x68160 + +#define mmMME0_QM_CQ_STS1_1 0x68164 + +#define mmMME0_QM_CQ_STS1_2 0x68168 + +#define mmMME0_QM_CQ_STS1_3 0x6816C + +#define mmMME0_QM_CQ_STS1_4 0x68170 + +#define mmMME0_QM_CQ_PTR_LO_0 0x68174 + +#define mmMME0_QM_CQ_PTR_HI_0 0x68178 + +#define mmMME0_QM_CQ_TSIZE_0 0x6817C + +#define mmMME0_QM_CQ_CTL_0 0x68180 + +#define mmMME0_QM_CQ_PTR_LO_1 0x68184 + +#define mmMME0_QM_CQ_PTR_HI_1 0x68188 + +#define mmMME0_QM_CQ_TSIZE_1 0x6818C + +#define mmMME0_QM_CQ_CTL_1 0x68190 + +#define mmMME0_QM_CQ_PTR_LO_2 0x68194 + +#define mmMME0_QM_CQ_PTR_HI_2 0x68198 + +#define mmMME0_QM_CQ_TSIZE_2 0x6819C + +#define mmMME0_QM_CQ_CTL_2 0x681A0 + +#define mmMME0_QM_CQ_PTR_LO_3 0x681A4 + +#define mmMME0_QM_CQ_PTR_HI_3 0x681A8 + +#define mmMME0_QM_CQ_TSIZE_3 0x681AC + +#define mmMME0_QM_CQ_CTL_3 0x681B0 + +#define mmMME0_QM_CQ_PTR_LO_4 0x681B4 + +#define mmMME0_QM_CQ_PTR_HI_4 0x681B8 + +#define mmMME0_QM_CQ_TSIZE_4 0x681BC + +#define mmMME0_QM_CQ_CTL_4 0x681C0 + +#define mmMME0_QM_CQ_PTR_LO_STS_0 0x681C4 + +#define mmMME0_QM_CQ_PTR_LO_STS_1 0x681C8 + +#define mmMME0_QM_CQ_PTR_LO_STS_2 0x681CC + +#define mmMME0_QM_CQ_PTR_LO_STS_3 0x681D0 + +#define mmMME0_QM_CQ_PTR_LO_STS_4 0x681D4 + +#define mmMME0_QM_CQ_PTR_HI_STS_0 0x681D8 + +#define mmMME0_QM_CQ_PTR_HI_STS_1 0x681DC + +#define mmMME0_QM_CQ_PTR_HI_STS_2 0x681E0 + +#define mmMME0_QM_CQ_PTR_HI_STS_3 0x681E4 + +#define mmMME0_QM_CQ_PTR_HI_STS_4 0x681E8 + +#define mmMME0_QM_CQ_TSIZE_STS_0 0x681EC + +#define mmMME0_QM_CQ_TSIZE_STS_1 0x681F0 + +#define mmMME0_QM_CQ_TSIZE_STS_2 0x681F4 + +#define mmMME0_QM_CQ_TSIZE_STS_3 0x681F8 + +#define mmMME0_QM_CQ_TSIZE_STS_4 0x681FC + +#define mmMME0_QM_CQ_CTL_STS_0 0x68200 + +#define mmMME0_QM_CQ_CTL_STS_1 0x68204 + +#define mmMME0_QM_CQ_CTL_STS_2 0x68208 + +#define mmMME0_QM_CQ_CTL_STS_3 0x6820C + +#define mmMME0_QM_CQ_CTL_STS_4 0x68210 + +#define mmMME0_QM_CQ_IFIFO_CNT_0 0x68214 + +#define mmMME0_QM_CQ_IFIFO_CNT_1 0x68218 + +#define mmMME0_QM_CQ_IFIFO_CNT_2 0x6821C + +#define mmMME0_QM_CQ_IFIFO_CNT_3 0x68220 + +#define mmMME0_QM_CQ_IFIFO_CNT_4 0x68224 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 0x68228 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 0x6822C + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 0x68230 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 0x68234 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 0x68238 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 0x6823C + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 0x68240 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 0x68244 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 0x68248 + +#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 0x6824C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 0x68250 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 0x68254 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 0x68258 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 0x6825C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 0x68260 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 0x68264 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 0x68268 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 0x6826C + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 0x68270 + +#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 0x68274 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 0x68278 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 0x6827C + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 0x68280 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 0x68284 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 0x68288 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 0x6828C + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 0x68290 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 0x68294 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 0x68298 + +#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 0x6829C + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 0x682A0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 0x682A4 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 0x682A8 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 0x682AC + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 0x682B0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 0x682B4 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 0x682B8 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 0x682BC + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 0x682C0 + +#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 0x682C4 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 0x682C8 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 0x682CC + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 0x682D0 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 0x682D4 + +#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 0x682D8 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x682E0 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x682E4 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x682E8 + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x682EC + +#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x682F0 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x682F4 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x682F8 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x682FC + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x68300 + +#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x68304 + +#define mmMME0_QM_CP_FENCE0_RDATA_0 0x68308 + +#define mmMME0_QM_CP_FENCE0_RDATA_1 0x6830C + +#define mmMME0_QM_CP_FENCE0_RDATA_2 0x68310 + +#define mmMME0_QM_CP_FENCE0_RDATA_3 0x68314 + +#define mmMME0_QM_CP_FENCE0_RDATA_4 0x68318 + +#define mmMME0_QM_CP_FENCE1_RDATA_0 0x6831C + +#define mmMME0_QM_CP_FENCE1_RDATA_1 0x68320 + +#define mmMME0_QM_CP_FENCE1_RDATA_2 0x68324 + +#define mmMME0_QM_CP_FENCE1_RDATA_3 0x68328 + +#define mmMME0_QM_CP_FENCE1_RDATA_4 0x6832C + +#define mmMME0_QM_CP_FENCE2_RDATA_0 0x68330 + +#define mmMME0_QM_CP_FENCE2_RDATA_1 0x68334 + +#define mmMME0_QM_CP_FENCE2_RDATA_2 0x68338 + +#define mmMME0_QM_CP_FENCE2_RDATA_3 0x6833C + +#define mmMME0_QM_CP_FENCE2_RDATA_4 0x68340 + +#define mmMME0_QM_CP_FENCE3_RDATA_0 0x68344 + +#define mmMME0_QM_CP_FENCE3_RDATA_1 0x68348 + +#define mmMME0_QM_CP_FENCE3_RDATA_2 0x6834C + +#define mmMME0_QM_CP_FENCE3_RDATA_3 0x68350 + +#define mmMME0_QM_CP_FENCE3_RDATA_4 0x68354 + +#define mmMME0_QM_CP_FENCE0_CNT_0 0x68358 + +#define mmMME0_QM_CP_FENCE0_CNT_1 0x6835C + +#define mmMME0_QM_CP_FENCE0_CNT_2 0x68360 + +#define mmMME0_QM_CP_FENCE0_CNT_3 0x68364 + +#define mmMME0_QM_CP_FENCE0_CNT_4 0x68368 + +#define mmMME0_QM_CP_FENCE1_CNT_0 0x6836C + +#define mmMME0_QM_CP_FENCE1_CNT_1 0x68370 + +#define mmMME0_QM_CP_FENCE1_CNT_2 0x68374 + +#define mmMME0_QM_CP_FENCE1_CNT_3 0x68378 + +#define mmMME0_QM_CP_FENCE1_CNT_4 0x6837C + +#define mmMME0_QM_CP_FENCE2_CNT_0 0x68380 + +#define mmMME0_QM_CP_FENCE2_CNT_1 0x68384 + +#define mmMME0_QM_CP_FENCE2_CNT_2 0x68388 + +#define mmMME0_QM_CP_FENCE2_CNT_3 0x6838C + +#define mmMME0_QM_CP_FENCE2_CNT_4 0x68390 + +#define mmMME0_QM_CP_FENCE3_CNT_0 0x68394 + +#define mmMME0_QM_CP_FENCE3_CNT_1 0x68398 + +#define mmMME0_QM_CP_FENCE3_CNT_2 0x6839C + +#define mmMME0_QM_CP_FENCE3_CNT_3 0x683A0 + +#define mmMME0_QM_CP_FENCE3_CNT_4 0x683A4 + +#define mmMME0_QM_CP_STS_0 0x683A8 + +#define mmMME0_QM_CP_STS_1 0x683AC + +#define mmMME0_QM_CP_STS_2 0x683B0 + +#define mmMME0_QM_CP_STS_3 0x683B4 + +#define mmMME0_QM_CP_STS_4 0x683B8 + +#define mmMME0_QM_CP_CURRENT_INST_LO_0 0x683BC + +#define mmMME0_QM_CP_CURRENT_INST_LO_1 0x683C0 + +#define mmMME0_QM_CP_CURRENT_INST_LO_2 0x683C4 + +#define mmMME0_QM_CP_CURRENT_INST_LO_3 0x683C8 + +#define mmMME0_QM_CP_CURRENT_INST_LO_4 0x683CC + +#define mmMME0_QM_CP_CURRENT_INST_HI_0 0x683D0 + +#define mmMME0_QM_CP_CURRENT_INST_HI_1 0x683D4 + +#define mmMME0_QM_CP_CURRENT_INST_HI_2 0x683D8 + +#define mmMME0_QM_CP_CURRENT_INST_HI_3 0x683DC + +#define mmMME0_QM_CP_CURRENT_INST_HI_4 0x683E0 + +#define mmMME0_QM_CP_BARRIER_CFG_0 0x683F4 + +#define mmMME0_QM_CP_BARRIER_CFG_1 0x683F8 + +#define mmMME0_QM_CP_BARRIER_CFG_2 0x683FC + +#define mmMME0_QM_CP_BARRIER_CFG_3 0x68400 + +#define mmMME0_QM_CP_BARRIER_CFG_4 0x68404 + +#define mmMME0_QM_CP_DBG_0_0 0x68408 + +#define mmMME0_QM_CP_DBG_0_1 0x6840C + +#define mmMME0_QM_CP_DBG_0_2 0x68410 + +#define mmMME0_QM_CP_DBG_0_3 0x68414 + +#define mmMME0_QM_CP_DBG_0_4 0x68418 + +#define mmMME0_QM_CP_ARUSER_31_11_0 0x6841C + +#define mmMME0_QM_CP_ARUSER_31_11_1 0x68420 + +#define mmMME0_QM_CP_ARUSER_31_11_2 0x68424 + +#define mmMME0_QM_CP_ARUSER_31_11_3 0x68428 + +#define mmMME0_QM_CP_ARUSER_31_11_4 0x6842C + +#define mmMME0_QM_CP_AWUSER_31_11_0 0x68430 + +#define mmMME0_QM_CP_AWUSER_31_11_1 0x68434 + +#define mmMME0_QM_CP_AWUSER_31_11_2 0x68438 + +#define mmMME0_QM_CP_AWUSER_31_11_3 0x6843C + +#define mmMME0_QM_CP_AWUSER_31_11_4 0x68440 + +#define mmMME0_QM_ARB_CFG_0 0x68A00 + +#define mmMME0_QM_ARB_CHOISE_Q_PUSH 0x68A04 + +#define mmMME0_QM_ARB_WRR_WEIGHT_0 0x68A08 + +#define mmMME0_QM_ARB_WRR_WEIGHT_1 0x68A0C + +#define mmMME0_QM_ARB_WRR_WEIGHT_2 0x68A10 + +#define mmMME0_QM_ARB_WRR_WEIGHT_3 0x68A14 + +#define mmMME0_QM_ARB_CFG_1 0x68A18 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_0 0x68A20 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_1 0x68A24 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_2 0x68A28 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_3 0x68A2C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_4 0x68A30 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_5 0x68A34 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_6 0x68A38 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_7 0x68A3C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_8 0x68A40 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_9 0x68A44 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_10 0x68A48 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_11 0x68A4C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_12 0x68A50 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_13 0x68A54 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_14 0x68A58 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_15 0x68A5C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_16 0x68A60 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_17 0x68A64 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_18 0x68A68 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_19 0x68A6C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_20 0x68A70 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_21 0x68A74 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_22 0x68A78 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_23 0x68A7C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_24 0x68A80 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_25 0x68A84 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_26 0x68A88 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_27 0x68A8C + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_28 0x68A90 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_29 0x68A94 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_30 0x68A98 + +#define mmMME0_QM_ARB_MST_AVAIL_CRED_31 0x68A9C + +#define mmMME0_QM_ARB_MST_CRED_INC 0x68AA0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x68AA4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x68AA8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x68AAC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x68AB0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x68AB4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x68AB8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x68ABC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x68AC0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x68AC4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x68AC8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x68ACC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x68AD0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x68AD4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x68AD8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x68ADC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x68AE0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x68AE4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x68AE8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x68AEC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x68AF0 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x68AF4 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x68AF8 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x68AFC + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x68B00 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x68B04 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x68B08 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x68B0C + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x68B10 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x68B14 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x68B18 + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x68B1C + +#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x68B20 + +#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x68B28 + +#define mmMME0_QM_ARB_MST_SLAVE_EN 0x68B2C + +#define mmMME0_QM_ARB_MST_QUIET_PER 0x68B34 + +#define mmMME0_QM_ARB_SLV_CHOISE_WDT 0x68B38 + +#define mmMME0_QM_ARB_SLV_ID 0x68B3C + +#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT 0x68B44 + +#define mmMME0_QM_ARB_MSG_AWUSER_31_11 0x68B48 + +#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP 0x68B4C + +#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x68B50 + +#define mmMME0_QM_ARB_BASE_LO 0x68B54 + +#define mmMME0_QM_ARB_BASE_HI 0x68B58 + +#define mmMME0_QM_ARB_STATE_STS 0x68B80 + +#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS 0x68B84 + +#define mmMME0_QM_ARB_MSG_STS 0x68B88 + +#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD 0x68B8C + +#define mmMME0_QM_ARB_ERR_CAUSE 0x68B9C + +#define mmMME0_QM_ARB_ERR_MSG_EN 0x68BA0 + +#define mmMME0_QM_ARB_ERR_STS_DRP 0x68BA8 + +#define mmMME0_QM_ARB_MST_CRED_STS_0 0x68BB0 + +#define mmMME0_QM_ARB_MST_CRED_STS_1 0x68BB4 + +#define mmMME0_QM_ARB_MST_CRED_STS_2 0x68BB8 + +#define mmMME0_QM_ARB_MST_CRED_STS_3 0x68BBC + +#define mmMME0_QM_ARB_MST_CRED_STS_4 0x68BC0 + +#define mmMME0_QM_ARB_MST_CRED_STS_5 0x68BC4 + +#define mmMME0_QM_ARB_MST_CRED_STS_6 0x68BC8 + +#define mmMME0_QM_ARB_MST_CRED_STS_7 0x68BCC + +#define mmMME0_QM_ARB_MST_CRED_STS_8 0x68BD0 + +#define mmMME0_QM_ARB_MST_CRED_STS_9 0x68BD4 + +#define mmMME0_QM_ARB_MST_CRED_STS_10 0x68BD8 + +#define mmMME0_QM_ARB_MST_CRED_STS_11 0x68BDC + +#define mmMME0_QM_ARB_MST_CRED_STS_12 0x68BE0 + +#define mmMME0_QM_ARB_MST_CRED_STS_13 0x68BE4 + +#define mmMME0_QM_ARB_MST_CRED_STS_14 0x68BE8 + +#define mmMME0_QM_ARB_MST_CRED_STS_15 0x68BEC + +#define mmMME0_QM_ARB_MST_CRED_STS_16 0x68BF0 + +#define mmMME0_QM_ARB_MST_CRED_STS_17 0x68BF4 + +#define mmMME0_QM_ARB_MST_CRED_STS_18 0x68BF8 + +#define mmMME0_QM_ARB_MST_CRED_STS_19 0x68BFC + +#define mmMME0_QM_ARB_MST_CRED_STS_20 0x68C00 + +#define mmMME0_QM_ARB_MST_CRED_STS_21 0x68C04 + +#define mmMME0_QM_ARB_MST_CRED_STS_22 0x68C08 + +#define mmMME0_QM_ARB_MST_CRED_STS_23 0x68C0C + +#define mmMME0_QM_ARB_MST_CRED_STS_24 0x68C10 + +#define mmMME0_QM_ARB_MST_CRED_STS_25 0x68C14 + +#define mmMME0_QM_ARB_MST_CRED_STS_26 0x68C18 + +#define mmMME0_QM_ARB_MST_CRED_STS_27 0x68C1C + +#define mmMME0_QM_ARB_MST_CRED_STS_28 0x68C20 + +#define mmMME0_QM_ARB_MST_CRED_STS_29 0x68C24 + +#define mmMME0_QM_ARB_MST_CRED_STS_30 0x68C28 + +#define mmMME0_QM_ARB_MST_CRED_STS_31 0x68C2C + +#define mmMME0_QM_CGM_CFG 0x68C70 + +#define mmMME0_QM_CGM_STS 0x68C74 + +#define mmMME0_QM_CGM_CFG1 0x68C78 + +#define mmMME0_QM_LOCAL_RANGE_BASE 0x68C80 + +#define mmMME0_QM_LOCAL_RANGE_SIZE 0x68C84 + +#define mmMME0_QM_CSMR_STRICT_PRIO_CFG 0x68C90 + +#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 0x68C94 + +#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 0x68C98 + +#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 0x68C9C + +#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 0x68CA0 + +#define mmMME0_QM_GLBL_AXCACHE 0x68CA4 + +#define mmMME0_QM_IND_GW_APB_CFG 0x68CB0 + +#define mmMME0_QM_IND_GW_APB_WDATA 0x68CB4 + +#define mmMME0_QM_IND_GW_APB_RDATA 0x68CB8 + +#define mmMME0_QM_IND_GW_APB_STATUS 0x68CBC + +#define mmMME0_QM_GLBL_ERR_ADDR_LO 0x68CD0 + +#define mmMME0_QM_GLBL_ERR_ADDR_HI 0x68CD4 + +#define mmMME0_QM_GLBL_ERR_WDATA 0x68CD8 + +#define mmMME0_QM_GLBL_MEM_INIT_BUSY 0x68D00 + +#endif /* ASIC_REG_MME0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h new file mode 100644 index 000000000000..6c07f7d45490 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme1_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME1_CTRL_REGS_H_ +#define ASIC_REG_MME1_CTRL_REGS_H_ + +/* + ***************************************** + * MME1_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME1_CTRL_ARCH_STATUS 0xE0000 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_S 0xE0008 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_L 0xE000C + +#define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_O 0xE0010 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_S 0xE0014 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_L 0xE0018 + +#define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_O 0xE001C + +#define mmMME1_CTRL_ARCH_HEADER_LOW 0xE0020 + +#define mmMME1_CTRL_ARCH_HEADER_HIGH 0xE0024 + +#define mmMME1_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0xE0028 + +#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0xE002C + +#define mmMME1_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0xE0030 + +#define mmMME1_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0xE0034 + +#define mmMME1_CTRL_ARCH_OUTER_LOOP 0xE0038 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0xE003C + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0xE0040 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0xE0044 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0xE0048 + +#define mmMME1_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0xE004C + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0xE0050 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0xE0054 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0xE0058 + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0xE005C + +#define mmMME1_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0xE0060 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0xE0064 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0xE0068 + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0xE006C + +#define mmMME1_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0xE0070 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0xE0074 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0xE0078 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0xE007C + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0xE0080 + +#define mmMME1_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0084 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0xE0088 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0xE008C + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0xE0090 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0xE0094 + +#define mmMME1_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0xE0098 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_0 0xE009C + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_1 0xE00A0 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_2 0xE00A4 + +#define mmMME1_CTRL_ARCH_AGU_S_START_OFFSET_3 0xE00A8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0xE00AC + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0xE00B0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0xE00B4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0xE00B8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0xE00BC + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0xE00C0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0xE00C4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0xE00C8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0xE00CC + +#define mmMME1_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0xE00D0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0xE00D4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0xE00D8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0xE00DC + +#define mmMME1_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0xE00E0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0xE00E4 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0xE00E8 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0xE00EC + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0xE00F0 + +#define mmMME1_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE00F4 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE00F8 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE00FC + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0100 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0104 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0108 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0xE010C + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0xE0110 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0xE0114 + +#define mmMME1_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0xE0118 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE011C + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0120 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0124 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0128 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE012C + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0xE0130 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0xE0134 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0xE0138 + +#define mmMME1_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0xE013C + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0xE0140 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0xE0144 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0xE0148 + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0xE014C + +#define mmMME1_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0xE0150 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0xE0154 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0xE0158 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0xE015C + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0xE0160 + +#define mmMME1_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0xE0164 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0xE0168 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0xE016C + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0xE0170 + +#define mmMME1_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0xE0174 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0xE0178 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0xE017C + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0xE0180 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0xE0184 + +#define mmMME1_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0188 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE018C + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0190 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0194 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0198 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE019C + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0xE01A0 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0xE01A4 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0xE01A8 + +#define mmMME1_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0xE01AC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE01B0 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE01B4 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE01B8 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE01BC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE01C0 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0xE01C4 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0xE01C8 + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0xE01CC + +#define mmMME1_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0xE01D0 + +#define mmMME1_CTRL_ARCH_DESC_SB_REPEAT 0xE01D4 + +#define mmMME1_CTRL_ARCH_DESC_RATE_LIMITER 0xE01D8 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE01DC + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE01E0 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0xE01E4 + +#define mmMME1_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0xE01E8 + +#define mmMME1_CTRL_ARCH_DESC_AXI_USER_DATA 0xE01EC + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_S 0xE01F0 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0xE01F4 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0xE01F8 + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0xE01FC + +#define mmMME1_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0xE0200 + +#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_S 0xE0204 + +#define mmMME1_CTRL_ARCH_DESC_PADDING_VALUE_L 0xE0208 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_S 0xE020C + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0xE0210 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0xE0214 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0xE0218 + +#define mmMME1_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0xE021C + +#define mmMME1_CTRL_ARCH_DESC_PCU_RL_SATURATION 0xE0220 + +#define mmMME1_CTRL_ARCH_DESC_DUMMY 0xE0224 + +#define mmMME1_CTRL_CMD 0xE0280 + +#define mmMME1_CTRL_STATUS1 0xE0284 + +#define mmMME1_CTRL_RESET 0xE0288 + +#define mmMME1_CTRL_QM_STALL 0xE028C + +#define mmMME1_CTRL_SYNC_OBJECT_FIFO_TH 0xE0290 + +#define mmMME1_CTRL_EUS_ROLLUP_CNT_ADD 0xE0294 + +#define mmMME1_CTRL_INTR_CAUSE 0xE0298 + +#define mmMME1_CTRL_INTR_MASK 0xE029C + +#define mmMME1_CTRL_LOG_SHADOW 0xE02A0 + +#define mmMME1_CTRL_PCU_RL_DESC0 0xE02A4 + +#define mmMME1_CTRL_PCU_RL_TOKEN_UPDATE 0xE02A8 + +#define mmMME1_CTRL_PCU_RL_TH 0xE02AC + +#define mmMME1_CTRL_PCU_RL_MIN 0xE02B0 + +#define mmMME1_CTRL_PCU_RL_CTRL_EN 0xE02B4 + +#define mmMME1_CTRL_PCU_RL_HISTORY_LOG_SIZE 0xE02B8 + +#define mmMME1_CTRL_PCU_DUMMY_A_BF16 0xE02BC + +#define mmMME1_CTRL_PCU_DUMMY_B_BF16 0xE02C0 + +#define mmMME1_CTRL_PCU_DUMMY_A_FP32_ODD 0xE02C4 + +#define mmMME1_CTRL_PCU_DUMMY_A_FP32_EVEN 0xE02C8 + +#define mmMME1_CTRL_PCU_DUMMY_B_FP32_ODD 0xE02CC + +#define mmMME1_CTRL_PCU_DUMMY_B_FP32_EVEN 0xE02D0 + +#define mmMME1_CTRL_PROT 0xE02D4 + +#define mmMME1_CTRL_EU_POWER_SAVE_DISABLE 0xE02D8 + +#define mmMME1_CTRL_CS_DBG_BLOCK_ID 0xE02DC + +#define mmMME1_CTRL_CS_DBG_STATUS_DROP_CNT 0xE02E0 + +#define mmMME1_CTRL_TE_CLOSE_CGATE 0xE02E4 + +#define mmMME1_CTRL_AGU_SM_INFLIGHT_CNTR 0xE02E8 + +#define mmMME1_CTRL_AGU_SM_TOTAL_CNTR 0xE02EC + +#define mmMME1_CTRL_EZSYNC_OUT_CREDIT 0xE02F0 + +#define mmMME1_CTRL_PCU_RL_SAT_SEC 0xE02F4 + +#define mmMME1_CTRL_AGU_SYNC_MSG_AXI_USER 0xE02F8 + +#define mmMME1_CTRL_QM_SLV_LBW_CLK_EN 0xE02FC + +#define mmMME1_CTRL_SHADOW_0_STATUS 0xE0400 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0xE0408 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0xE040C + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0xE0410 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0xE0414 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0xE0418 + +#define mmMME1_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0xE041C + +#define mmMME1_CTRL_SHADOW_0_HEADER_LOW 0xE0420 + +#define mmMME1_CTRL_SHADOW_0_HEADER_HIGH 0xE0424 + +#define mmMME1_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0xE0428 + +#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0xE042C + +#define mmMME1_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0xE0430 + +#define mmMME1_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0xE0434 + +#define mmMME1_CTRL_SHADOW_0_OUTER_LOOP 0xE0438 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0xE043C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0xE0440 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0xE0444 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0xE0448 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0xE044C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0xE0450 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0xE0454 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0xE0458 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0xE045C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0xE0460 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0xE0464 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0xE0468 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0xE046C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0xE0470 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0xE0474 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0xE0478 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0xE047C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0xE0480 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0484 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0xE0488 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0xE048C + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0xE0490 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0xE0494 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0xE0498 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0xE049C + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0xE04A0 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0xE04A4 + +#define mmMME1_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0xE04A8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0xE04AC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0xE04B0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0xE04B4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0xE04B8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0xE04BC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0xE04C0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0xE04C4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0xE04C8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0xE04CC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0xE04D0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0xE04D4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0xE04D8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0xE04DC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0xE04E0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0xE04E4 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0xE04E8 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0xE04EC + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0xE04F0 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE04F4 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE04F8 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE04FC + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0500 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0504 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0508 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0xE050C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0xE0510 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0xE0514 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0xE0518 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE051C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0520 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0524 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0528 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE052C + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0xE0530 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0xE0534 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0xE0538 + +#define mmMME1_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0xE053C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0xE0540 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0xE0544 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0xE0548 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0xE054C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0xE0550 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0xE0554 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0xE0558 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0xE055C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0xE0560 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0xE0564 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0xE0568 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0xE056C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0xE0570 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0xE0574 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0xE0578 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0xE057C + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0xE0580 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0xE0584 + +#define mmMME1_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0588 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE058C + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0590 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0594 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0598 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE059C + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0xE05A0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0xE05A4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0xE05A8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0xE05AC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE05B0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE05B4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE05B8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE05BC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE05C0 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0xE05C4 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0xE05C8 + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0xE05CC + +#define mmMME1_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0xE05D0 + +#define mmMME1_CTRL_SHADOW_0_DESC_SB_REPEAT 0xE05D4 + +#define mmMME1_CTRL_SHADOW_0_DESC_RATE_LIMITER 0xE05D8 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE05DC + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE05E0 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0xE05E4 + +#define mmMME1_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0xE05E8 + +#define mmMME1_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0xE05EC + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_S 0xE05F0 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0xE05F4 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0xE05F8 + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0xE05FC + +#define mmMME1_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0xE0600 + +#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0xE0604 + +#define mmMME1_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0xE0608 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0xE060C + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0xE0610 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0xE0614 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0xE0618 + +#define mmMME1_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0xE061C + +#define mmMME1_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0xE0620 + +#define mmMME1_CTRL_SHADOW_0_DESC_DUMMY 0xE0624 + +#define mmMME1_CTRL_SHADOW_1_STATUS 0xE0680 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0xE0688 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0xE068C + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0xE0690 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0xE0694 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0xE0698 + +#define mmMME1_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0xE069C + +#define mmMME1_CTRL_SHADOW_1_HEADER_LOW 0xE06A0 + +#define mmMME1_CTRL_SHADOW_1_HEADER_HIGH 0xE06A4 + +#define mmMME1_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0xE06A8 + +#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0xE06AC + +#define mmMME1_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0xE06B0 + +#define mmMME1_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0xE06B4 + +#define mmMME1_CTRL_SHADOW_1_OUTER_LOOP 0xE06B8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0xE06BC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0xE06C0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0xE06C4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0xE06C8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0xE06CC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0xE06D0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0xE06D4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0xE06D8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0xE06DC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0xE06E0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0xE06E4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0xE06E8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0xE06EC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0xE06F0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0xE06F4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0xE06F8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0xE06FC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0xE0700 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0704 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0xE0708 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0xE070C + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0xE0710 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0xE0714 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0xE0718 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0xE071C + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0xE0720 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0xE0724 + +#define mmMME1_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0xE0728 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0xE072C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0xE0730 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0xE0734 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0xE0738 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0xE073C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0xE0740 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0xE0744 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0xE0748 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0xE074C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0xE0750 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0xE0754 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0xE0758 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0xE075C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0xE0760 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0xE0764 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0xE0768 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0xE076C + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0xE0770 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0774 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0778 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE077C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0780 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0784 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0788 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0xE078C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0xE0790 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0xE0794 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0xE0798 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE079C + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE07A0 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE07A4 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE07A8 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE07AC + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0xE07B0 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0xE07B4 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0xE07B8 + +#define mmMME1_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0xE07BC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0xE07C0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0xE07C4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0xE07C8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0xE07CC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0xE07D0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0xE07D4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0xE07D8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0xE07DC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0xE07E0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0xE07E4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0xE07E8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0xE07EC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0xE07F0 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0xE07F4 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0xE07F8 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0xE07FC + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0xE0800 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0xE0804 + +#define mmMME1_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0808 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE080C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0810 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0814 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0818 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE081C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0xE0820 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0xE0824 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0xE0828 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0xE082C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0830 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0834 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0838 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE083C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0840 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0xE0844 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0xE0848 + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0xE084C + +#define mmMME1_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0xE0850 + +#define mmMME1_CTRL_SHADOW_1_DESC_SB_REPEAT 0xE0854 + +#define mmMME1_CTRL_SHADOW_1_DESC_RATE_LIMITER 0xE0858 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE085C + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0860 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0864 + +#define mmMME1_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0xE0868 + +#define mmMME1_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0xE086C + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_S 0xE0870 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0xE0874 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0xE0878 + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0xE087C + +#define mmMME1_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0xE0880 + +#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0xE0884 + +#define mmMME1_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0xE0888 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0xE088C + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0xE0890 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0xE0894 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0xE0898 + +#define mmMME1_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0xE089C + +#define mmMME1_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0xE08A0 + +#define mmMME1_CTRL_SHADOW_1_DESC_DUMMY 0xE08A4 + +#define mmMME1_CTRL_SHADOW_2_STATUS 0xE0900 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0xE0908 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0xE090C + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0xE0910 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0xE0914 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0xE0918 + +#define mmMME1_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0xE091C + +#define mmMME1_CTRL_SHADOW_2_HEADER_LOW 0xE0920 + +#define mmMME1_CTRL_SHADOW_2_HEADER_HIGH 0xE0924 + +#define mmMME1_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0xE0928 + +#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0xE092C + +#define mmMME1_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0xE0930 + +#define mmMME1_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0xE0934 + +#define mmMME1_CTRL_SHADOW_2_OUTER_LOOP 0xE0938 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0xE093C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0xE0940 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0xE0944 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0xE0948 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0xE094C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0xE0950 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0xE0954 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0xE0958 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0xE095C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0xE0960 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0xE0964 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0xE0968 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0xE096C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0xE0970 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0xE0974 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0xE0978 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0xE097C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0xE0980 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0984 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0xE0988 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0xE098C + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0xE0990 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0xE0994 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0xE0998 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0xE099C + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0xE09A0 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0xE09A4 + +#define mmMME1_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0xE09A8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0xE09AC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0xE09B0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0xE09B4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0xE09B8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0xE09BC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0xE09C0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0xE09C4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0xE09C8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0xE09CC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0xE09D0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0xE09D4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0xE09D8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0xE09DC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0xE09E0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0xE09E4 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0xE09E8 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0xE09EC + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0xE09F0 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE09F4 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE09F8 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE09FC + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0A00 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0A04 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0A08 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0xE0A0C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0xE0A10 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0xE0A14 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0xE0A18 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0A1C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0A20 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0A24 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0A28 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0A2C + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0xE0A30 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0xE0A34 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0xE0A38 + +#define mmMME1_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0xE0A3C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0xE0A40 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0xE0A44 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0xE0A48 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0xE0A4C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0xE0A50 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0xE0A54 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0xE0A58 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0xE0A5C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0xE0A60 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0xE0A64 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0xE0A68 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0xE0A6C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0xE0A70 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0xE0A74 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0xE0A78 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0xE0A7C + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0xE0A80 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0xE0A84 + +#define mmMME1_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0A88 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0A8C + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0A90 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0A94 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0A98 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0A9C + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0xE0AA0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0xE0AA4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0xE0AA8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0xE0AAC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0AB0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0AB4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0AB8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0ABC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0AC0 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0xE0AC4 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0xE0AC8 + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0xE0ACC + +#define mmMME1_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0xE0AD0 + +#define mmMME1_CTRL_SHADOW_2_DESC_SB_REPEAT 0xE0AD4 + +#define mmMME1_CTRL_SHADOW_2_DESC_RATE_LIMITER 0xE0AD8 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0ADC + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0AE0 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0AE4 + +#define mmMME1_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0xE0AE8 + +#define mmMME1_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0xE0AEC + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_S 0xE0AF0 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0xE0AF4 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0xE0AF8 + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0xE0AFC + +#define mmMME1_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0xE0B00 + +#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0xE0B04 + +#define mmMME1_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0xE0B08 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0xE0B0C + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0xE0B10 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0xE0B14 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0xE0B18 + +#define mmMME1_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0xE0B1C + +#define mmMME1_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0xE0B20 + +#define mmMME1_CTRL_SHADOW_2_DESC_DUMMY 0xE0B24 + +#define mmMME1_CTRL_SHADOW_3_STATUS 0xE0B80 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0xE0B88 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0xE0B8C + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0xE0B90 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0xE0B94 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0xE0B98 + +#define mmMME1_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0xE0B9C + +#define mmMME1_CTRL_SHADOW_3_HEADER_LOW 0xE0BA0 + +#define mmMME1_CTRL_SHADOW_3_HEADER_HIGH 0xE0BA4 + +#define mmMME1_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0xE0BA8 + +#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0xE0BAC + +#define mmMME1_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0xE0BB0 + +#define mmMME1_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0xE0BB4 + +#define mmMME1_CTRL_SHADOW_3_OUTER_LOOP 0xE0BB8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0xE0BBC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0xE0BC0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0xE0BC4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0xE0BC8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0xE0BCC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0xE0BD0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0xE0BD4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0xE0BD8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0xE0BDC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0xE0BE0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0xE0BE4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0xE0BE8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0xE0BEC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0xE0BF0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0xE0BF4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0xE0BF8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0xE0BFC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0xE0C00 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0xE0C04 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0xE0C08 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0xE0C0C + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0xE0C10 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0xE0C14 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0xE0C18 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0xE0C1C + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0xE0C20 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0xE0C24 + +#define mmMME1_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0xE0C28 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0xE0C2C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0xE0C30 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0xE0C34 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0xE0C38 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0xE0C3C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0xE0C40 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0xE0C44 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0xE0C48 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0xE0C4C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0xE0C50 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0xE0C54 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0xE0C58 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0xE0C5C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0xE0C60 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0xE0C64 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0xE0C68 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0xE0C6C + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0xE0C70 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0xE0C74 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0xE0C78 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0xE0C7C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0xE0C80 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0xE0C84 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0xE0C88 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0xE0C8C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0xE0C90 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0xE0C94 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0xE0C98 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0xE0C9C + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0xE0CA0 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0xE0CA4 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0xE0CA8 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0xE0CAC + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0xE0CB0 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0xE0CB4 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0xE0CB8 + +#define mmMME1_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0xE0CBC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0xE0CC0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0xE0CC4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0xE0CC8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0xE0CCC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0xE0CD0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0xE0CD4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0xE0CD8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0xE0CDC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0xE0CE0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0xE0CE4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0xE0CE8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0xE0CEC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0xE0CF0 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0xE0CF4 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0xE0CF8 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0xE0CFC + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0xE0D00 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0xE0D04 + +#define mmMME1_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0xE0D08 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0xE0D0C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0xE0D10 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0xE0D14 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0xE0D18 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0xE0D1C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0xE0D20 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0xE0D24 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0xE0D28 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0xE0D2C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0xE0D30 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0xE0D34 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0xE0D38 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0xE0D3C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0xE0D40 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0xE0D44 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0xE0D48 + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0xE0D4C + +#define mmMME1_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0xE0D50 + +#define mmMME1_CTRL_SHADOW_3_DESC_SB_REPEAT 0xE0D54 + +#define mmMME1_CTRL_SHADOW_3_DESC_RATE_LIMITER 0xE0D58 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0xE0D5C + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0xE0D60 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0xE0D64 + +#define mmMME1_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0xE0D68 + +#define mmMME1_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0xE0D6C + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_S 0xE0D70 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0xE0D74 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0xE0D78 + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0xE0D7C + +#define mmMME1_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0xE0D80 + +#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0xE0D84 + +#define mmMME1_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0xE0D88 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0xE0D8C + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0xE0D90 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0xE0D94 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0xE0D98 + +#define mmMME1_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0xE0D9C + +#define mmMME1_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0xE0DA0 + +#define mmMME1_CTRL_SHADOW_3_DESC_DUMMY 0xE0DA4 + +#endif /* ASIC_REG_MME1_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h new file mode 100644 index 000000000000..a1f2eb8b91bd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_CTRL_REGS_H_ +#define ASIC_REG_MME2_CTRL_REGS_H_ + +/* + ***************************************** + * MME2_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME2_CTRL_ARCH_STATUS 0x160000 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_S 0x160008 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_L 0x16000C + +#define mmMME2_CTRL_ARCH_BASE_ADDR_HIGH_O 0x160010 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_S 0x160014 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_L 0x160018 + +#define mmMME2_CTRL_ARCH_BASE_ADDR_LOW_O 0x16001C + +#define mmMME2_CTRL_ARCH_HEADER_LOW 0x160020 + +#define mmMME2_CTRL_ARCH_HEADER_HIGH 0x160024 + +#define mmMME2_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x160028 + +#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x16002C + +#define mmMME2_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x160030 + +#define mmMME2_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x160034 + +#define mmMME2_CTRL_ARCH_OUTER_LOOP 0x160038 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x16003C + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x160040 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x160044 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x160048 + +#define mmMME2_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x16004C + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x160050 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x160054 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x160058 + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x16005C + +#define mmMME2_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x160060 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x160064 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x160068 + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x16006C + +#define mmMME2_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x160070 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x160074 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x160078 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x16007C + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x160080 + +#define mmMME2_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160084 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x160088 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x16008C + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x160090 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x160094 + +#define mmMME2_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x160098 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_0 0x16009C + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1600A0 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1600A4 + +#define mmMME2_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1600A8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1600AC + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1600B0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1600B4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1600B8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1600BC + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1600C0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1600C4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1600C8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1600CC + +#define mmMME2_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1600D0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1600D4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1600D8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1600DC + +#define mmMME2_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1600E0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1600E4 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1600E8 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1600EC + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1600F0 + +#define mmMME2_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1600F4 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1600F8 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1600FC + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160100 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160104 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160108 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x16010C + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x160110 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x160114 + +#define mmMME2_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x160118 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16011C + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160120 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160124 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160128 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16012C + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x160130 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x160134 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x160138 + +#define mmMME2_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x16013C + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x160140 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x160144 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x160148 + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x16014C + +#define mmMME2_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x160150 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x160154 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x160158 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x16015C + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x160160 + +#define mmMME2_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x160164 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x160168 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x16016C + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x160170 + +#define mmMME2_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x160174 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x160178 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x16017C + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x160180 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x160184 + +#define mmMME2_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160188 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16018C + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160190 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160194 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160198 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16019C + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1601A0 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1601A4 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1601A8 + +#define mmMME2_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1601AC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1601B0 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1601B4 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1601B8 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1601BC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1601C0 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1601C4 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1601C8 + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1601CC + +#define mmMME2_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1601D0 + +#define mmMME2_CTRL_ARCH_DESC_SB_REPEAT 0x1601D4 + +#define mmMME2_CTRL_ARCH_DESC_RATE_LIMITER 0x1601D8 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1601DC + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1601E0 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1601E4 + +#define mmMME2_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1601E8 + +#define mmMME2_CTRL_ARCH_DESC_AXI_USER_DATA 0x1601EC + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_S 0x1601F0 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1601F4 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1601F8 + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1601FC + +#define mmMME2_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x160200 + +#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_S 0x160204 + +#define mmMME2_CTRL_ARCH_DESC_PADDING_VALUE_L 0x160208 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_S 0x16020C + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x160210 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x160214 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x160218 + +#define mmMME2_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x16021C + +#define mmMME2_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x160220 + +#define mmMME2_CTRL_ARCH_DESC_DUMMY 0x160224 + +#define mmMME2_CTRL_CMD 0x160280 + +#define mmMME2_CTRL_STATUS1 0x160284 + +#define mmMME2_CTRL_RESET 0x160288 + +#define mmMME2_CTRL_QM_STALL 0x16028C + +#define mmMME2_CTRL_SYNC_OBJECT_FIFO_TH 0x160290 + +#define mmMME2_CTRL_EUS_ROLLUP_CNT_ADD 0x160294 + +#define mmMME2_CTRL_INTR_CAUSE 0x160298 + +#define mmMME2_CTRL_INTR_MASK 0x16029C + +#define mmMME2_CTRL_LOG_SHADOW 0x1602A0 + +#define mmMME2_CTRL_PCU_RL_DESC0 0x1602A4 + +#define mmMME2_CTRL_PCU_RL_TOKEN_UPDATE 0x1602A8 + +#define mmMME2_CTRL_PCU_RL_TH 0x1602AC + +#define mmMME2_CTRL_PCU_RL_MIN 0x1602B0 + +#define mmMME2_CTRL_PCU_RL_CTRL_EN 0x1602B4 + +#define mmMME2_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1602B8 + +#define mmMME2_CTRL_PCU_DUMMY_A_BF16 0x1602BC + +#define mmMME2_CTRL_PCU_DUMMY_B_BF16 0x1602C0 + +#define mmMME2_CTRL_PCU_DUMMY_A_FP32_ODD 0x1602C4 + +#define mmMME2_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1602C8 + +#define mmMME2_CTRL_PCU_DUMMY_B_FP32_ODD 0x1602CC + +#define mmMME2_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1602D0 + +#define mmMME2_CTRL_PROT 0x1602D4 + +#define mmMME2_CTRL_EU_POWER_SAVE_DISABLE 0x1602D8 + +#define mmMME2_CTRL_CS_DBG_BLOCK_ID 0x1602DC + +#define mmMME2_CTRL_CS_DBG_STATUS_DROP_CNT 0x1602E0 + +#define mmMME2_CTRL_TE_CLOSE_CGATE 0x1602E4 + +#define mmMME2_CTRL_AGU_SM_INFLIGHT_CNTR 0x1602E8 + +#define mmMME2_CTRL_AGU_SM_TOTAL_CNTR 0x1602EC + +#define mmMME2_CTRL_EZSYNC_OUT_CREDIT 0x1602F0 + +#define mmMME2_CTRL_PCU_RL_SAT_SEC 0x1602F4 + +#define mmMME2_CTRL_AGU_SYNC_MSG_AXI_USER 0x1602F8 + +#define mmMME2_CTRL_QM_SLV_LBW_CLK_EN 0x1602FC + +#define mmMME2_CTRL_SHADOW_0_STATUS 0x160400 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x160408 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x16040C + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x160410 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x160414 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x160418 + +#define mmMME2_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x16041C + +#define mmMME2_CTRL_SHADOW_0_HEADER_LOW 0x160420 + +#define mmMME2_CTRL_SHADOW_0_HEADER_HIGH 0x160424 + +#define mmMME2_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x160428 + +#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x16042C + +#define mmMME2_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x160430 + +#define mmMME2_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x160434 + +#define mmMME2_CTRL_SHADOW_0_OUTER_LOOP 0x160438 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x16043C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x160440 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x160444 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x160448 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x16044C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x160450 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x160454 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x160458 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x16045C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x160460 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x160464 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x160468 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x16046C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x160470 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x160474 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x160478 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x16047C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x160480 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160484 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x160488 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x16048C + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x160490 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x160494 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x160498 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x16049C + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1604A0 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1604A4 + +#define mmMME2_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1604A8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1604AC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1604B0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1604B4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1604B8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1604BC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1604C0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1604C4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1604C8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1604CC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1604D0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1604D4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1604D8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1604DC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1604E0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1604E4 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1604E8 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1604EC + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1604F0 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1604F4 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1604F8 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1604FC + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160500 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160504 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160508 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x16050C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x160510 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x160514 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x160518 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16051C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160520 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160524 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160528 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x16052C + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x160530 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x160534 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x160538 + +#define mmMME2_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x16053C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x160540 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x160544 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x160548 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x16054C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x160550 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x160554 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x160558 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x16055C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x160560 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x160564 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x160568 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x16056C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x160570 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x160574 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x160578 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x16057C + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x160580 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x160584 + +#define mmMME2_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160588 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16058C + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160590 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160594 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160598 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16059C + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1605A0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1605A4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1605A8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1605AC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1605B0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1605B4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1605B8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1605BC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1605C0 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1605C4 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1605C8 + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1605CC + +#define mmMME2_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1605D0 + +#define mmMME2_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1605D4 + +#define mmMME2_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1605D8 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1605DC + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1605E0 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1605E4 + +#define mmMME2_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1605E8 + +#define mmMME2_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1605EC + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1605F0 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1605F4 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1605F8 + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1605FC + +#define mmMME2_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x160600 + +#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x160604 + +#define mmMME2_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x160608 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x16060C + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x160610 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x160614 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x160618 + +#define mmMME2_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x16061C + +#define mmMME2_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x160620 + +#define mmMME2_CTRL_SHADOW_0_DESC_DUMMY 0x160624 + +#define mmMME2_CTRL_SHADOW_1_STATUS 0x160680 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x160688 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x16068C + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x160690 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x160694 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x160698 + +#define mmMME2_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x16069C + +#define mmMME2_CTRL_SHADOW_1_HEADER_LOW 0x1606A0 + +#define mmMME2_CTRL_SHADOW_1_HEADER_HIGH 0x1606A4 + +#define mmMME2_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1606A8 + +#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1606AC + +#define mmMME2_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1606B0 + +#define mmMME2_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1606B4 + +#define mmMME2_CTRL_SHADOW_1_OUTER_LOOP 0x1606B8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1606BC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1606C0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1606C4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1606C8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1606CC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1606D0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1606D4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1606D8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1606DC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1606E0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1606E4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1606E8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1606EC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1606F0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1606F4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1606F8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1606FC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x160700 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160704 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x160708 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x16070C + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x160710 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x160714 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x160718 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x16071C + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x160720 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x160724 + +#define mmMME2_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x160728 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x16072C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x160730 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x160734 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x160738 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x16073C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x160740 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x160744 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x160748 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x16074C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x160750 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x160754 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x160758 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x16075C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x160760 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x160764 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x160768 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x16076C + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x160770 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160774 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160778 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x16077C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160780 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160784 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160788 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x16078C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x160790 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x160794 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x160798 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x16079C + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1607A0 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1607A4 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1607A8 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1607AC + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1607B0 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1607B4 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1607B8 + +#define mmMME2_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1607BC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1607C0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1607C4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1607C8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1607CC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1607D0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1607D4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1607D8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1607DC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1607E0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1607E4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1607E8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1607EC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1607F0 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1607F4 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1607F8 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1607FC + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x160800 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x160804 + +#define mmMME2_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160808 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x16080C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160810 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160814 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160818 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x16081C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x160820 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x160824 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x160828 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x16082C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160830 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160834 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160838 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x16083C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160840 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x160844 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x160848 + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x16084C + +#define mmMME2_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x160850 + +#define mmMME2_CTRL_SHADOW_1_DESC_SB_REPEAT 0x160854 + +#define mmMME2_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x160858 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x16085C + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160860 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x160864 + +#define mmMME2_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x160868 + +#define mmMME2_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x16086C + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x160870 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x160874 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x160878 + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x16087C + +#define mmMME2_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x160880 + +#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x160884 + +#define mmMME2_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x160888 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x16088C + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x160890 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x160894 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x160898 + +#define mmMME2_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x16089C + +#define mmMME2_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1608A0 + +#define mmMME2_CTRL_SHADOW_1_DESC_DUMMY 0x1608A4 + +#define mmMME2_CTRL_SHADOW_2_STATUS 0x160900 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x160908 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x16090C + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x160910 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x160914 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x160918 + +#define mmMME2_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x16091C + +#define mmMME2_CTRL_SHADOW_2_HEADER_LOW 0x160920 + +#define mmMME2_CTRL_SHADOW_2_HEADER_HIGH 0x160924 + +#define mmMME2_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x160928 + +#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x16092C + +#define mmMME2_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x160930 + +#define mmMME2_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x160934 + +#define mmMME2_CTRL_SHADOW_2_OUTER_LOOP 0x160938 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x16093C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x160940 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x160944 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x160948 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x16094C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x160950 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x160954 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x160958 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x16095C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x160960 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x160964 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x160968 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x16096C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x160970 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x160974 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x160978 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x16097C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x160980 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160984 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x160988 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x16098C + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x160990 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x160994 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x160998 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x16099C + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1609A0 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1609A4 + +#define mmMME2_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1609A8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1609AC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1609B0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1609B4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1609B8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1609BC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1609C0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1609C4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1609C8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1609CC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1609D0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1609D4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1609D8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1609DC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1609E0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1609E4 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1609E8 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1609EC + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1609F0 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1609F4 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1609F8 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1609FC + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160A00 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160A04 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160A08 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x160A0C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x160A10 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x160A14 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x160A18 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160A1C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160A20 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160A24 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160A28 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160A2C + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x160A30 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x160A34 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x160A38 + +#define mmMME2_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x160A3C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x160A40 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x160A44 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x160A48 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x160A4C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x160A50 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x160A54 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x160A58 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x160A5C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x160A60 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x160A64 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x160A68 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x160A6C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x160A70 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x160A74 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x160A78 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x160A7C + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x160A80 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x160A84 + +#define mmMME2_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160A88 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160A8C + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160A90 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160A94 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160A98 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160A9C + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x160AA0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x160AA4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x160AA8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x160AAC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160AB0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160AB4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160AB8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160ABC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160AC0 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x160AC4 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x160AC8 + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x160ACC + +#define mmMME2_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x160AD0 + +#define mmMME2_CTRL_SHADOW_2_DESC_SB_REPEAT 0x160AD4 + +#define mmMME2_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x160AD8 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160ADC + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160AE0 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x160AE4 + +#define mmMME2_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x160AE8 + +#define mmMME2_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x160AEC + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x160AF0 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x160AF4 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x160AF8 + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x160AFC + +#define mmMME2_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x160B00 + +#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x160B04 + +#define mmMME2_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x160B08 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x160B0C + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x160B10 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x160B14 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x160B18 + +#define mmMME2_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x160B1C + +#define mmMME2_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x160B20 + +#define mmMME2_CTRL_SHADOW_2_DESC_DUMMY 0x160B24 + +#define mmMME2_CTRL_SHADOW_3_STATUS 0x160B80 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x160B88 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x160B8C + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x160B90 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x160B94 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x160B98 + +#define mmMME2_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x160B9C + +#define mmMME2_CTRL_SHADOW_3_HEADER_LOW 0x160BA0 + +#define mmMME2_CTRL_SHADOW_3_HEADER_HIGH 0x160BA4 + +#define mmMME2_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x160BA8 + +#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x160BAC + +#define mmMME2_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x160BB0 + +#define mmMME2_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x160BB4 + +#define mmMME2_CTRL_SHADOW_3_OUTER_LOOP 0x160BB8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x160BBC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x160BC0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x160BC4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x160BC8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x160BCC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x160BD0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x160BD4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x160BD8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x160BDC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x160BE0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x160BE4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x160BE8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x160BEC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x160BF0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x160BF4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x160BF8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x160BFC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x160C00 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x160C04 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x160C08 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x160C0C + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x160C10 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x160C14 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x160C18 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x160C1C + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x160C20 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x160C24 + +#define mmMME2_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x160C28 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x160C2C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x160C30 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x160C34 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x160C38 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x160C3C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x160C40 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x160C44 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x160C48 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x160C4C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x160C50 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x160C54 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x160C58 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x160C5C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x160C60 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x160C64 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x160C68 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x160C6C + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x160C70 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x160C74 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x160C78 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x160C7C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x160C80 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x160C84 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x160C88 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x160C8C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x160C90 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x160C94 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x160C98 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x160C9C + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x160CA0 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x160CA4 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x160CA8 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x160CAC + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x160CB0 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x160CB4 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x160CB8 + +#define mmMME2_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x160CBC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x160CC0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x160CC4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x160CC8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x160CCC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x160CD0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x160CD4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x160CD8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x160CDC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x160CE0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x160CE4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x160CE8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x160CEC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x160CF0 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x160CF4 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x160CF8 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x160CFC + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x160D00 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x160D04 + +#define mmMME2_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x160D08 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x160D0C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x160D10 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x160D14 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x160D18 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x160D1C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x160D20 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x160D24 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x160D28 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x160D2C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x160D30 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x160D34 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x160D38 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x160D3C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x160D40 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x160D44 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x160D48 + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x160D4C + +#define mmMME2_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x160D50 + +#define mmMME2_CTRL_SHADOW_3_DESC_SB_REPEAT 0x160D54 + +#define mmMME2_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x160D58 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x160D5C + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x160D60 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x160D64 + +#define mmMME2_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x160D68 + +#define mmMME2_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x160D6C + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x160D70 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x160D74 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x160D78 + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x160D7C + +#define mmMME2_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x160D80 + +#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x160D84 + +#define mmMME2_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x160D88 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x160D8C + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x160D90 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x160D94 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x160D98 + +#define mmMME2_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x160D9C + +#define mmMME2_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x160DA0 + +#define mmMME2_CTRL_SHADOW_3_DESC_DUMMY 0x160DA4 + +#endif /* ASIC_REG_MME2_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h new file mode 100644 index 000000000000..c1ea6a422010 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME2_QM_REGS_H_ +#define ASIC_REG_MME2_QM_REGS_H_ + +/* + ***************************************** + * MME2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmMME2_QM_GLBL_CFG0 0x168000 + +#define mmMME2_QM_GLBL_CFG1 0x168004 + +#define mmMME2_QM_GLBL_PROT 0x168008 + +#define mmMME2_QM_GLBL_ERR_CFG 0x16800C + +#define mmMME2_QM_GLBL_SECURE_PROPS_0 0x168010 + +#define mmMME2_QM_GLBL_SECURE_PROPS_1 0x168014 + +#define mmMME2_QM_GLBL_SECURE_PROPS_2 0x168018 + +#define mmMME2_QM_GLBL_SECURE_PROPS_3 0x16801C + +#define mmMME2_QM_GLBL_SECURE_PROPS_4 0x168020 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_0 0x168024 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_1 0x168028 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_2 0x16802C + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_3 0x168030 + +#define mmMME2_QM_GLBL_NON_SECURE_PROPS_4 0x168034 + +#define mmMME2_QM_GLBL_STS0 0x168038 + +#define mmMME2_QM_GLBL_STS1_0 0x168040 + +#define mmMME2_QM_GLBL_STS1_1 0x168044 + +#define mmMME2_QM_GLBL_STS1_2 0x168048 + +#define mmMME2_QM_GLBL_STS1_3 0x16804C + +#define mmMME2_QM_GLBL_STS1_4 0x168050 + +#define mmMME2_QM_GLBL_MSG_EN_0 0x168054 + +#define mmMME2_QM_GLBL_MSG_EN_1 0x168058 + +#define mmMME2_QM_GLBL_MSG_EN_2 0x16805C + +#define mmMME2_QM_GLBL_MSG_EN_3 0x168060 + +#define mmMME2_QM_GLBL_MSG_EN_4 0x168068 + +#define mmMME2_QM_PQ_BASE_LO_0 0x168070 + +#define mmMME2_QM_PQ_BASE_LO_1 0x168074 + +#define mmMME2_QM_PQ_BASE_LO_2 0x168078 + +#define mmMME2_QM_PQ_BASE_LO_3 0x16807C + +#define mmMME2_QM_PQ_BASE_HI_0 0x168080 + +#define mmMME2_QM_PQ_BASE_HI_1 0x168084 + +#define mmMME2_QM_PQ_BASE_HI_2 0x168088 + +#define mmMME2_QM_PQ_BASE_HI_3 0x16808C + +#define mmMME2_QM_PQ_SIZE_0 0x168090 + +#define mmMME2_QM_PQ_SIZE_1 0x168094 + +#define mmMME2_QM_PQ_SIZE_2 0x168098 + +#define mmMME2_QM_PQ_SIZE_3 0x16809C + +#define mmMME2_QM_PQ_PI_0 0x1680A0 + +#define mmMME2_QM_PQ_PI_1 0x1680A4 + +#define mmMME2_QM_PQ_PI_2 0x1680A8 + +#define mmMME2_QM_PQ_PI_3 0x1680AC + +#define mmMME2_QM_PQ_CI_0 0x1680B0 + +#define mmMME2_QM_PQ_CI_1 0x1680B4 + +#define mmMME2_QM_PQ_CI_2 0x1680B8 + +#define mmMME2_QM_PQ_CI_3 0x1680BC + +#define mmMME2_QM_PQ_CFG0_0 0x1680C0 + +#define mmMME2_QM_PQ_CFG0_1 0x1680C4 + +#define mmMME2_QM_PQ_CFG0_2 0x1680C8 + +#define mmMME2_QM_PQ_CFG0_3 0x1680CC + +#define mmMME2_QM_PQ_CFG1_0 0x1680D0 + +#define mmMME2_QM_PQ_CFG1_1 0x1680D4 + +#define mmMME2_QM_PQ_CFG1_2 0x1680D8 + +#define mmMME2_QM_PQ_CFG1_3 0x1680DC + +#define mmMME2_QM_PQ_ARUSER_31_11_0 0x1680E0 + +#define mmMME2_QM_PQ_ARUSER_31_11_1 0x1680E4 + +#define mmMME2_QM_PQ_ARUSER_31_11_2 0x1680E8 + +#define mmMME2_QM_PQ_ARUSER_31_11_3 0x1680EC + +#define mmMME2_QM_PQ_STS0_0 0x1680F0 + +#define mmMME2_QM_PQ_STS0_1 0x1680F4 + +#define mmMME2_QM_PQ_STS0_2 0x1680F8 + +#define mmMME2_QM_PQ_STS0_3 0x1680FC + +#define mmMME2_QM_PQ_STS1_0 0x168100 + +#define mmMME2_QM_PQ_STS1_1 0x168104 + +#define mmMME2_QM_PQ_STS1_2 0x168108 + +#define mmMME2_QM_PQ_STS1_3 0x16810C + +#define mmMME2_QM_CQ_CFG0_0 0x168110 + +#define mmMME2_QM_CQ_CFG0_1 0x168114 + +#define mmMME2_QM_CQ_CFG0_2 0x168118 + +#define mmMME2_QM_CQ_CFG0_3 0x16811C + +#define mmMME2_QM_CQ_CFG0_4 0x168120 + +#define mmMME2_QM_CQ_CFG1_0 0x168124 + +#define mmMME2_QM_CQ_CFG1_1 0x168128 + +#define mmMME2_QM_CQ_CFG1_2 0x16812C + +#define mmMME2_QM_CQ_CFG1_3 0x168130 + +#define mmMME2_QM_CQ_CFG1_4 0x168134 + +#define mmMME2_QM_CQ_ARUSER_31_11_0 0x168138 + +#define mmMME2_QM_CQ_ARUSER_31_11_1 0x16813C + +#define mmMME2_QM_CQ_ARUSER_31_11_2 0x168140 + +#define mmMME2_QM_CQ_ARUSER_31_11_3 0x168144 + +#define mmMME2_QM_CQ_ARUSER_31_11_4 0x168148 + +#define mmMME2_QM_CQ_STS0_0 0x16814C + +#define mmMME2_QM_CQ_STS0_1 0x168150 + +#define mmMME2_QM_CQ_STS0_2 0x168154 + +#define mmMME2_QM_CQ_STS0_3 0x168158 + +#define mmMME2_QM_CQ_STS0_4 0x16815C + +#define mmMME2_QM_CQ_STS1_0 0x168160 + +#define mmMME2_QM_CQ_STS1_1 0x168164 + +#define mmMME2_QM_CQ_STS1_2 0x168168 + +#define mmMME2_QM_CQ_STS1_3 0x16816C + +#define mmMME2_QM_CQ_STS1_4 0x168170 + +#define mmMME2_QM_CQ_PTR_LO_0 0x168174 + +#define mmMME2_QM_CQ_PTR_HI_0 0x168178 + +#define mmMME2_QM_CQ_TSIZE_0 0x16817C + +#define mmMME2_QM_CQ_CTL_0 0x168180 + +#define mmMME2_QM_CQ_PTR_LO_1 0x168184 + +#define mmMME2_QM_CQ_PTR_HI_1 0x168188 + +#define mmMME2_QM_CQ_TSIZE_1 0x16818C + +#define mmMME2_QM_CQ_CTL_1 0x168190 + +#define mmMME2_QM_CQ_PTR_LO_2 0x168194 + +#define mmMME2_QM_CQ_PTR_HI_2 0x168198 + +#define mmMME2_QM_CQ_TSIZE_2 0x16819C + +#define mmMME2_QM_CQ_CTL_2 0x1681A0 + +#define mmMME2_QM_CQ_PTR_LO_3 0x1681A4 + +#define mmMME2_QM_CQ_PTR_HI_3 0x1681A8 + +#define mmMME2_QM_CQ_TSIZE_3 0x1681AC + +#define mmMME2_QM_CQ_CTL_3 0x1681B0 + +#define mmMME2_QM_CQ_PTR_LO_4 0x1681B4 + +#define mmMME2_QM_CQ_PTR_HI_4 0x1681B8 + +#define mmMME2_QM_CQ_TSIZE_4 0x1681BC + +#define mmMME2_QM_CQ_CTL_4 0x1681C0 + +#define mmMME2_QM_CQ_PTR_LO_STS_0 0x1681C4 + +#define mmMME2_QM_CQ_PTR_LO_STS_1 0x1681C8 + +#define mmMME2_QM_CQ_PTR_LO_STS_2 0x1681CC + +#define mmMME2_QM_CQ_PTR_LO_STS_3 0x1681D0 + +#define mmMME2_QM_CQ_PTR_LO_STS_4 0x1681D4 + +#define mmMME2_QM_CQ_PTR_HI_STS_0 0x1681D8 + +#define mmMME2_QM_CQ_PTR_HI_STS_1 0x1681DC + +#define mmMME2_QM_CQ_PTR_HI_STS_2 0x1681E0 + +#define mmMME2_QM_CQ_PTR_HI_STS_3 0x1681E4 + +#define mmMME2_QM_CQ_PTR_HI_STS_4 0x1681E8 + +#define mmMME2_QM_CQ_TSIZE_STS_0 0x1681EC + +#define mmMME2_QM_CQ_TSIZE_STS_1 0x1681F0 + +#define mmMME2_QM_CQ_TSIZE_STS_2 0x1681F4 + +#define mmMME2_QM_CQ_TSIZE_STS_3 0x1681F8 + +#define mmMME2_QM_CQ_TSIZE_STS_4 0x1681FC + +#define mmMME2_QM_CQ_CTL_STS_0 0x168200 + +#define mmMME2_QM_CQ_CTL_STS_1 0x168204 + +#define mmMME2_QM_CQ_CTL_STS_2 0x168208 + +#define mmMME2_QM_CQ_CTL_STS_3 0x16820C + +#define mmMME2_QM_CQ_CTL_STS_4 0x168210 + +#define mmMME2_QM_CQ_IFIFO_CNT_0 0x168214 + +#define mmMME2_QM_CQ_IFIFO_CNT_1 0x168218 + +#define mmMME2_QM_CQ_IFIFO_CNT_2 0x16821C + +#define mmMME2_QM_CQ_IFIFO_CNT_3 0x168220 + +#define mmMME2_QM_CQ_IFIFO_CNT_4 0x168224 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 0x168228 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 0x16822C + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 0x168230 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 0x168234 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 0x168238 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 0x16823C + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 0x168240 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 0x168244 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 0x168248 + +#define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 0x16824C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 0x168250 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 0x168254 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 0x168258 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 0x16825C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 0x168260 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 0x168264 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 0x168268 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 0x16826C + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 0x168270 + +#define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 0x168274 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 0x168278 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 0x16827C + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 0x168280 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 0x168284 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 0x168288 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 0x16828C + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 0x168290 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 0x168294 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 0x168298 + +#define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 0x16829C + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 0x1682A0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 0x1682A4 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 0x1682A8 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 0x1682AC + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 0x1682B0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 0x1682B4 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 0x1682B8 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 0x1682BC + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 0x1682C0 + +#define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 0x1682C4 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 0x1682C8 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 0x1682CC + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 0x1682D0 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 0x1682D4 + +#define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 0x1682D8 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x1682E0 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x1682E4 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x1682E8 + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x1682EC + +#define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x1682F0 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x1682F4 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x1682F8 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x1682FC + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x168300 + +#define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x168304 + +#define mmMME2_QM_CP_FENCE0_RDATA_0 0x168308 + +#define mmMME2_QM_CP_FENCE0_RDATA_1 0x16830C + +#define mmMME2_QM_CP_FENCE0_RDATA_2 0x168310 + +#define mmMME2_QM_CP_FENCE0_RDATA_3 0x168314 + +#define mmMME2_QM_CP_FENCE0_RDATA_4 0x168318 + +#define mmMME2_QM_CP_FENCE1_RDATA_0 0x16831C + +#define mmMME2_QM_CP_FENCE1_RDATA_1 0x168320 + +#define mmMME2_QM_CP_FENCE1_RDATA_2 0x168324 + +#define mmMME2_QM_CP_FENCE1_RDATA_3 0x168328 + +#define mmMME2_QM_CP_FENCE1_RDATA_4 0x16832C + +#define mmMME2_QM_CP_FENCE2_RDATA_0 0x168330 + +#define mmMME2_QM_CP_FENCE2_RDATA_1 0x168334 + +#define mmMME2_QM_CP_FENCE2_RDATA_2 0x168338 + +#define mmMME2_QM_CP_FENCE2_RDATA_3 0x16833C + +#define mmMME2_QM_CP_FENCE2_RDATA_4 0x168340 + +#define mmMME2_QM_CP_FENCE3_RDATA_0 0x168344 + +#define mmMME2_QM_CP_FENCE3_RDATA_1 0x168348 + +#define mmMME2_QM_CP_FENCE3_RDATA_2 0x16834C + +#define mmMME2_QM_CP_FENCE3_RDATA_3 0x168350 + +#define mmMME2_QM_CP_FENCE3_RDATA_4 0x168354 + +#define mmMME2_QM_CP_FENCE0_CNT_0 0x168358 + +#define mmMME2_QM_CP_FENCE0_CNT_1 0x16835C + +#define mmMME2_QM_CP_FENCE0_CNT_2 0x168360 + +#define mmMME2_QM_CP_FENCE0_CNT_3 0x168364 + +#define mmMME2_QM_CP_FENCE0_CNT_4 0x168368 + +#define mmMME2_QM_CP_FENCE1_CNT_0 0x16836C + +#define mmMME2_QM_CP_FENCE1_CNT_1 0x168370 + +#define mmMME2_QM_CP_FENCE1_CNT_2 0x168374 + +#define mmMME2_QM_CP_FENCE1_CNT_3 0x168378 + +#define mmMME2_QM_CP_FENCE1_CNT_4 0x16837C + +#define mmMME2_QM_CP_FENCE2_CNT_0 0x168380 + +#define mmMME2_QM_CP_FENCE2_CNT_1 0x168384 + +#define mmMME2_QM_CP_FENCE2_CNT_2 0x168388 + +#define mmMME2_QM_CP_FENCE2_CNT_3 0x16838C + +#define mmMME2_QM_CP_FENCE2_CNT_4 0x168390 + +#define mmMME2_QM_CP_FENCE3_CNT_0 0x168394 + +#define mmMME2_QM_CP_FENCE3_CNT_1 0x168398 + +#define mmMME2_QM_CP_FENCE3_CNT_2 0x16839C + +#define mmMME2_QM_CP_FENCE3_CNT_3 0x1683A0 + +#define mmMME2_QM_CP_FENCE3_CNT_4 0x1683A4 + +#define mmMME2_QM_CP_STS_0 0x1683A8 + +#define mmMME2_QM_CP_STS_1 0x1683AC + +#define mmMME2_QM_CP_STS_2 0x1683B0 + +#define mmMME2_QM_CP_STS_3 0x1683B4 + +#define mmMME2_QM_CP_STS_4 0x1683B8 + +#define mmMME2_QM_CP_CURRENT_INST_LO_0 0x1683BC + +#define mmMME2_QM_CP_CURRENT_INST_LO_1 0x1683C0 + +#define mmMME2_QM_CP_CURRENT_INST_LO_2 0x1683C4 + +#define mmMME2_QM_CP_CURRENT_INST_LO_3 0x1683C8 + +#define mmMME2_QM_CP_CURRENT_INST_LO_4 0x1683CC + +#define mmMME2_QM_CP_CURRENT_INST_HI_0 0x1683D0 + +#define mmMME2_QM_CP_CURRENT_INST_HI_1 0x1683D4 + +#define mmMME2_QM_CP_CURRENT_INST_HI_2 0x1683D8 + +#define mmMME2_QM_CP_CURRENT_INST_HI_3 0x1683DC + +#define mmMME2_QM_CP_CURRENT_INST_HI_4 0x1683E0 + +#define mmMME2_QM_CP_BARRIER_CFG_0 0x1683F4 + +#define mmMME2_QM_CP_BARRIER_CFG_1 0x1683F8 + +#define mmMME2_QM_CP_BARRIER_CFG_2 0x1683FC + +#define mmMME2_QM_CP_BARRIER_CFG_3 0x168400 + +#define mmMME2_QM_CP_BARRIER_CFG_4 0x168404 + +#define mmMME2_QM_CP_DBG_0_0 0x168408 + +#define mmMME2_QM_CP_DBG_0_1 0x16840C + +#define mmMME2_QM_CP_DBG_0_2 0x168410 + +#define mmMME2_QM_CP_DBG_0_3 0x168414 + +#define mmMME2_QM_CP_DBG_0_4 0x168418 + +#define mmMME2_QM_CP_ARUSER_31_11_0 0x16841C + +#define mmMME2_QM_CP_ARUSER_31_11_1 0x168420 + +#define mmMME2_QM_CP_ARUSER_31_11_2 0x168424 + +#define mmMME2_QM_CP_ARUSER_31_11_3 0x168428 + +#define mmMME2_QM_CP_ARUSER_31_11_4 0x16842C + +#define mmMME2_QM_CP_AWUSER_31_11_0 0x168430 + +#define mmMME2_QM_CP_AWUSER_31_11_1 0x168434 + +#define mmMME2_QM_CP_AWUSER_31_11_2 0x168438 + +#define mmMME2_QM_CP_AWUSER_31_11_3 0x16843C + +#define mmMME2_QM_CP_AWUSER_31_11_4 0x168440 + +#define mmMME2_QM_ARB_CFG_0 0x168A00 + +#define mmMME2_QM_ARB_CHOISE_Q_PUSH 0x168A04 + +#define mmMME2_QM_ARB_WRR_WEIGHT_0 0x168A08 + +#define mmMME2_QM_ARB_WRR_WEIGHT_1 0x168A0C + +#define mmMME2_QM_ARB_WRR_WEIGHT_2 0x168A10 + +#define mmMME2_QM_ARB_WRR_WEIGHT_3 0x168A14 + +#define mmMME2_QM_ARB_CFG_1 0x168A18 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_0 0x168A20 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_1 0x168A24 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_2 0x168A28 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_3 0x168A2C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_4 0x168A30 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_5 0x168A34 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_6 0x168A38 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_7 0x168A3C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_8 0x168A40 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_9 0x168A44 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_10 0x168A48 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_11 0x168A4C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_12 0x168A50 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_13 0x168A54 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_14 0x168A58 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_15 0x168A5C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_16 0x168A60 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_17 0x168A64 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_18 0x168A68 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_19 0x168A6C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_20 0x168A70 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_21 0x168A74 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_22 0x168A78 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_23 0x168A7C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_24 0x168A80 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_25 0x168A84 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_26 0x168A88 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_27 0x168A8C + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_28 0x168A90 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_29 0x168A94 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_30 0x168A98 + +#define mmMME2_QM_ARB_MST_AVAIL_CRED_31 0x168A9C + +#define mmMME2_QM_ARB_MST_CRED_INC 0x168AA0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x168AA4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x168AA8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x168AAC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x168AB0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x168AB4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x168AB8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x168ABC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x168AC0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x168AC4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x168AC8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x168ACC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x168AD0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x168AD4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x168AD8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x168ADC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x168AE0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x168AE4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x168AE8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x168AEC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x168AF0 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x168AF4 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x168AF8 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x168AFC + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x168B00 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x168B04 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x168B08 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x168B0C + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x168B10 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x168B14 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x168B18 + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x168B1C + +#define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x168B20 + +#define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x168B28 + +#define mmMME2_QM_ARB_MST_SLAVE_EN 0x168B2C + +#define mmMME2_QM_ARB_MST_QUIET_PER 0x168B34 + +#define mmMME2_QM_ARB_SLV_CHOISE_WDT 0x168B38 + +#define mmMME2_QM_ARB_SLV_ID 0x168B3C + +#define mmMME2_QM_ARB_MSG_MAX_INFLIGHT 0x168B44 + +#define mmMME2_QM_ARB_MSG_AWUSER_31_11 0x168B48 + +#define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP 0x168B4C + +#define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x168B50 + +#define mmMME2_QM_ARB_BASE_LO 0x168B54 + +#define mmMME2_QM_ARB_BASE_HI 0x168B58 + +#define mmMME2_QM_ARB_STATE_STS 0x168B80 + +#define mmMME2_QM_ARB_CHOISE_FULLNESS_STS 0x168B84 + +#define mmMME2_QM_ARB_MSG_STS 0x168B88 + +#define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD 0x168B8C + +#define mmMME2_QM_ARB_ERR_CAUSE 0x168B9C + +#define mmMME2_QM_ARB_ERR_MSG_EN 0x168BA0 + +#define mmMME2_QM_ARB_ERR_STS_DRP 0x168BA8 + +#define mmMME2_QM_ARB_MST_CRED_STS_0 0x168BB0 + +#define mmMME2_QM_ARB_MST_CRED_STS_1 0x168BB4 + +#define mmMME2_QM_ARB_MST_CRED_STS_2 0x168BB8 + +#define mmMME2_QM_ARB_MST_CRED_STS_3 0x168BBC + +#define mmMME2_QM_ARB_MST_CRED_STS_4 0x168BC0 + +#define mmMME2_QM_ARB_MST_CRED_STS_5 0x168BC4 + +#define mmMME2_QM_ARB_MST_CRED_STS_6 0x168BC8 + +#define mmMME2_QM_ARB_MST_CRED_STS_7 0x168BCC + +#define mmMME2_QM_ARB_MST_CRED_STS_8 0x168BD0 + +#define mmMME2_QM_ARB_MST_CRED_STS_9 0x168BD4 + +#define mmMME2_QM_ARB_MST_CRED_STS_10 0x168BD8 + +#define mmMME2_QM_ARB_MST_CRED_STS_11 0x168BDC + +#define mmMME2_QM_ARB_MST_CRED_STS_12 0x168BE0 + +#define mmMME2_QM_ARB_MST_CRED_STS_13 0x168BE4 + +#define mmMME2_QM_ARB_MST_CRED_STS_14 0x168BE8 + +#define mmMME2_QM_ARB_MST_CRED_STS_15 0x168BEC + +#define mmMME2_QM_ARB_MST_CRED_STS_16 0x168BF0 + +#define mmMME2_QM_ARB_MST_CRED_STS_17 0x168BF4 + +#define mmMME2_QM_ARB_MST_CRED_STS_18 0x168BF8 + +#define mmMME2_QM_ARB_MST_CRED_STS_19 0x168BFC + +#define mmMME2_QM_ARB_MST_CRED_STS_20 0x168C00 + +#define mmMME2_QM_ARB_MST_CRED_STS_21 0x168C04 + +#define mmMME2_QM_ARB_MST_CRED_STS_22 0x168C08 + +#define mmMME2_QM_ARB_MST_CRED_STS_23 0x168C0C + +#define mmMME2_QM_ARB_MST_CRED_STS_24 0x168C10 + +#define mmMME2_QM_ARB_MST_CRED_STS_25 0x168C14 + +#define mmMME2_QM_ARB_MST_CRED_STS_26 0x168C18 + +#define mmMME2_QM_ARB_MST_CRED_STS_27 0x168C1C + +#define mmMME2_QM_ARB_MST_CRED_STS_28 0x168C20 + +#define mmMME2_QM_ARB_MST_CRED_STS_29 0x168C24 + +#define mmMME2_QM_ARB_MST_CRED_STS_30 0x168C28 + +#define mmMME2_QM_ARB_MST_CRED_STS_31 0x168C2C + +#define mmMME2_QM_CGM_CFG 0x168C70 + +#define mmMME2_QM_CGM_STS 0x168C74 + +#define mmMME2_QM_CGM_CFG1 0x168C78 + +#define mmMME2_QM_LOCAL_RANGE_BASE 0x168C80 + +#define mmMME2_QM_LOCAL_RANGE_SIZE 0x168C84 + +#define mmMME2_QM_CSMR_STRICT_PRIO_CFG 0x168C90 + +#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 0x168C94 + +#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 0x168C98 + +#define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 0x168C9C + +#define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 0x168CA0 + +#define mmMME2_QM_GLBL_AXCACHE 0x168CA4 + +#define mmMME2_QM_IND_GW_APB_CFG 0x168CB0 + +#define mmMME2_QM_IND_GW_APB_WDATA 0x168CB4 + +#define mmMME2_QM_IND_GW_APB_RDATA 0x168CB8 + +#define mmMME2_QM_IND_GW_APB_STATUS 0x168CBC + +#define mmMME2_QM_GLBL_ERR_ADDR_LO 0x168CD0 + +#define mmMME2_QM_GLBL_ERR_ADDR_HI 0x168CD4 + +#define mmMME2_QM_GLBL_ERR_WDATA 0x168CD8 + +#define mmMME2_QM_GLBL_MEM_INIT_BUSY 0x168D00 + +#endif /* ASIC_REG_MME2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h new file mode 100644 index 000000000000..36f6edc72e3d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mme3_ctrl_regs.h @@ -0,0 +1,1456 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MME3_CTRL_REGS_H_ +#define ASIC_REG_MME3_CTRL_REGS_H_ + +/* + ***************************************** + * MME3_CTRL (Prototype: MME) + ***************************************** + */ + +#define mmMME3_CTRL_ARCH_STATUS 0x1E0000 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_S 0x1E0008 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_L 0x1E000C + +#define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_O 0x1E0010 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_S 0x1E0014 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_L 0x1E0018 + +#define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_O 0x1E001C + +#define mmMME3_CTRL_ARCH_HEADER_LOW 0x1E0020 + +#define mmMME3_CTRL_ARCH_HEADER_HIGH 0x1E0024 + +#define mmMME3_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x1E0028 + +#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_LOW 0x1E002C + +#define mmMME3_CTRL_ARCH_CONV_ASSOCIATED_DIMS_HIGH 0x1E0030 + +#define mmMME3_CTRL_ARCH_NUM_ITERATIONS_MINUS_1 0x1E0034 + +#define mmMME3_CTRL_ARCH_OUTER_LOOP 0x1E0038 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_0 0x1E003C + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_1 0x1E0040 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_2 0x1E0044 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_3 0x1E0048 + +#define mmMME3_CTRL_ARCH_TENSOR_S_VALID_ELEMENTS_4 0x1E004C + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_0 0x1E0050 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_1 0x1E0054 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_2 0x1E0058 + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_3 0x1E005C + +#define mmMME3_CTRL_ARCH_TENSOR_S_LOOP_STRIDE_4 0x1E0060 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_0 0x1E0064 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_1 0x1E0068 + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_2 0x1E006C + +#define mmMME3_CTRL_ARCH_TENSOR_S_ROI_SIZE_3 0x1E0070 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_0 0x1E0074 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_1 0x1E0078 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_2 0x1E007C + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_STRIDES_3 0x1E0080 + +#define mmMME3_CTRL_ARCH_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0084 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_0 0x1E0088 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_1 0x1E008C + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_2 0x1E0090 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_3 0x1E0094 + +#define mmMME3_CTRL_ARCH_AGU_S_ROI_BASE_OFFSET_4 0x1E0098 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_0 0x1E009C + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_1 0x1E00A0 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_2 0x1E00A4 + +#define mmMME3_CTRL_ARCH_AGU_S_START_OFFSET_3 0x1E00A8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_0 0x1E00AC + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_1 0x1E00B0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_2 0x1E00B4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_3 0x1E00B8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_VALID_ELEMENTS_4 0x1E00BC + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_0 0x1E00C0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_1 0x1E00C4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_2 0x1E00C8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_3 0x1E00CC + +#define mmMME3_CTRL_ARCH_TENSOR_L_LOOP_STRIDE_4 0x1E00D0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_0 0x1E00D4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_1 0x1E00D8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_2 0x1E00DC + +#define mmMME3_CTRL_ARCH_TENSOR_L_ROI_SIZE_3 0x1E00E0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_0 0x1E00E4 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_1 0x1E00E8 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_2 0x1E00EC + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_STRIDES_3 0x1E00F0 + +#define mmMME3_CTRL_ARCH_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E00F4 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E00F8 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E00FC + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0100 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0104 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0108 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_0 0x1E010C + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_1 0x1E0110 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_2 0x1E0114 + +#define mmMME3_CTRL_ARCH_AGU_L_LOCAL_START_OFFSET_3 0x1E0118 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E011C + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0120 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0124 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0128 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E012C + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_0 0x1E0130 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_1 0x1E0134 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_2 0x1E0138 + +#define mmMME3_CTRL_ARCH_AGU_L_REMOTE_START_OFFSET_3 0x1E013C + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_0 0x1E0140 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_1 0x1E0144 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_2 0x1E0148 + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_3 0x1E014C + +#define mmMME3_CTRL_ARCH_TENSOR_O_VALID_ELEMENTS_4 0x1E0150 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_0 0x1E0154 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_1 0x1E0158 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_2 0x1E015C + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_3 0x1E0160 + +#define mmMME3_CTRL_ARCH_TENSOR_O_LOOP_STRIDE_4 0x1E0164 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_0 0x1E0168 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_1 0x1E016C + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_2 0x1E0170 + +#define mmMME3_CTRL_ARCH_TENSOR_O_ROI_SIZE_3 0x1E0174 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_0 0x1E0178 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_1 0x1E017C + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_2 0x1E0180 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_STRIDES_3 0x1E0184 + +#define mmMME3_CTRL_ARCH_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0188 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E018C + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0190 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0194 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0198 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E019C + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_0 0x1E01A0 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_1 0x1E01A4 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_2 0x1E01A8 + +#define mmMME3_CTRL_ARCH_AGU_O_LOCAL_START_OFFSET_3 0x1E01AC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E01B0 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E01B4 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E01B8 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E01BC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E01C0 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_0 0x1E01C4 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_1 0x1E01C8 + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_2 0x1E01CC + +#define mmMME3_CTRL_ARCH_AGU_O_REMOTE_START_OFFSET_3 0x1E01D0 + +#define mmMME3_CTRL_ARCH_DESC_SB_REPEAT 0x1E01D4 + +#define mmMME3_CTRL_ARCH_DESC_RATE_LIMITER 0x1E01D8 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E01DC + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E01E0 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E01E4 + +#define mmMME3_CTRL_ARCH_DESC_SYNC_OBJECT_DATA 0x1E01E8 + +#define mmMME3_CTRL_ARCH_DESC_AXI_USER_DATA 0x1E01EC + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_S 0x1E01F0 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_LOCAL 0x1E01F4 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_L_REMOTE 0x1E01F8 + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_LOCAL 0x1E01FC + +#define mmMME3_CTRL_ARCH_DESC_PERF_EVT_O_REMOTE 0x1E0200 + +#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_S 0x1E0204 + +#define mmMME3_CTRL_ARCH_DESC_PADDING_VALUE_L 0x1E0208 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_S 0x1E020C + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_LOCAL 0x1E0210 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_L_REMOTE 0x1E0214 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_LOCAL 0x1E0218 + +#define mmMME3_CTRL_ARCH_DESC_META_DATA_AGU_O_REMOTE 0x1E021C + +#define mmMME3_CTRL_ARCH_DESC_PCU_RL_SATURATION 0x1E0220 + +#define mmMME3_CTRL_ARCH_DESC_DUMMY 0x1E0224 + +#define mmMME3_CTRL_CMD 0x1E0280 + +#define mmMME3_CTRL_STATUS1 0x1E0284 + +#define mmMME3_CTRL_RESET 0x1E0288 + +#define mmMME3_CTRL_QM_STALL 0x1E028C + +#define mmMME3_CTRL_SYNC_OBJECT_FIFO_TH 0x1E0290 + +#define mmMME3_CTRL_EUS_ROLLUP_CNT_ADD 0x1E0294 + +#define mmMME3_CTRL_INTR_CAUSE 0x1E0298 + +#define mmMME3_CTRL_INTR_MASK 0x1E029C + +#define mmMME3_CTRL_LOG_SHADOW 0x1E02A0 + +#define mmMME3_CTRL_PCU_RL_DESC0 0x1E02A4 + +#define mmMME3_CTRL_PCU_RL_TOKEN_UPDATE 0x1E02A8 + +#define mmMME3_CTRL_PCU_RL_TH 0x1E02AC + +#define mmMME3_CTRL_PCU_RL_MIN 0x1E02B0 + +#define mmMME3_CTRL_PCU_RL_CTRL_EN 0x1E02B4 + +#define mmMME3_CTRL_PCU_RL_HISTORY_LOG_SIZE 0x1E02B8 + +#define mmMME3_CTRL_PCU_DUMMY_A_BF16 0x1E02BC + +#define mmMME3_CTRL_PCU_DUMMY_B_BF16 0x1E02C0 + +#define mmMME3_CTRL_PCU_DUMMY_A_FP32_ODD 0x1E02C4 + +#define mmMME3_CTRL_PCU_DUMMY_A_FP32_EVEN 0x1E02C8 + +#define mmMME3_CTRL_PCU_DUMMY_B_FP32_ODD 0x1E02CC + +#define mmMME3_CTRL_PCU_DUMMY_B_FP32_EVEN 0x1E02D0 + +#define mmMME3_CTRL_PROT 0x1E02D4 + +#define mmMME3_CTRL_EU_POWER_SAVE_DISABLE 0x1E02D8 + +#define mmMME3_CTRL_CS_DBG_BLOCK_ID 0x1E02DC + +#define mmMME3_CTRL_CS_DBG_STATUS_DROP_CNT 0x1E02E0 + +#define mmMME3_CTRL_TE_CLOSE_CGATE 0x1E02E4 + +#define mmMME3_CTRL_AGU_SM_INFLIGHT_CNTR 0x1E02E8 + +#define mmMME3_CTRL_AGU_SM_TOTAL_CNTR 0x1E02EC + +#define mmMME3_CTRL_EZSYNC_OUT_CREDIT 0x1E02F0 + +#define mmMME3_CTRL_PCU_RL_SAT_SEC 0x1E02F4 + +#define mmMME3_CTRL_AGU_SYNC_MSG_AXI_USER 0x1E02F8 + +#define mmMME3_CTRL_QM_SLV_LBW_CLK_EN 0x1E02FC + +#define mmMME3_CTRL_SHADOW_0_STATUS 0x1E0400 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_S 0x1E0408 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_L 0x1E040C + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_HIGH_O 0x1E0410 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_S 0x1E0414 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_L 0x1E0418 + +#define mmMME3_CTRL_SHADOW_0_BASE_ADDR_LOW_O 0x1E041C + +#define mmMME3_CTRL_SHADOW_0_HEADER_LOW 0x1E0420 + +#define mmMME3_CTRL_SHADOW_0_HEADER_HIGH 0x1E0424 + +#define mmMME3_CTRL_SHADOW_0_CONV_KERNEL_SIZE_MINUS_1 0x1E0428 + +#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_LOW 0x1E042C + +#define mmMME3_CTRL_SHADOW_0_CONV_ASSOCIATED_DIMS_HIGH 0x1E0430 + +#define mmMME3_CTRL_SHADOW_0_NUM_ITERATIONS_MINUS_1 0x1E0434 + +#define mmMME3_CTRL_SHADOW_0_OUTER_LOOP 0x1E0438 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_0 0x1E043C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_1 0x1E0440 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_2 0x1E0444 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_3 0x1E0448 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_VALID_ELEMENTS_4 0x1E044C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_0 0x1E0450 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_1 0x1E0454 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_2 0x1E0458 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_3 0x1E045C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_LOOP_STRIDE_4 0x1E0460 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_0 0x1E0464 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_1 0x1E0468 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_2 0x1E046C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_ROI_SIZE_3 0x1E0470 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_0 0x1E0474 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_1 0x1E0478 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_2 0x1E047C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_STRIDES_3 0x1E0480 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0484 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_0 0x1E0488 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_1 0x1E048C + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_2 0x1E0490 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_3 0x1E0494 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_ROI_BASE_OFFSET_4 0x1E0498 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_0 0x1E049C + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_1 0x1E04A0 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_2 0x1E04A4 + +#define mmMME3_CTRL_SHADOW_0_AGU_S_START_OFFSET_3 0x1E04A8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_0 0x1E04AC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_1 0x1E04B0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_2 0x1E04B4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_3 0x1E04B8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_VALID_ELEMENTS_4 0x1E04BC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_0 0x1E04C0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_1 0x1E04C4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_2 0x1E04C8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_3 0x1E04CC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_LOOP_STRIDE_4 0x1E04D0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_0 0x1E04D4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_1 0x1E04D8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_2 0x1E04DC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_ROI_SIZE_3 0x1E04E0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_0 0x1E04E4 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_1 0x1E04E8 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_2 0x1E04EC + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_STRIDES_3 0x1E04F0 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E04F4 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E04F8 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E04FC + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0500 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0504 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0508 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_0 0x1E050C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_1 0x1E0510 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_2 0x1E0514 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_LOCAL_START_OFFSET_3 0x1E0518 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E051C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0520 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0524 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0528 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E052C + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_0 0x1E0530 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_1 0x1E0534 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_2 0x1E0538 + +#define mmMME3_CTRL_SHADOW_0_AGU_L_REMOTE_START_OFFSET_3 0x1E053C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_0 0x1E0540 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_1 0x1E0544 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_2 0x1E0548 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_3 0x1E054C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_VALID_ELEMENTS_4 0x1E0550 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_0 0x1E0554 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_1 0x1E0558 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_2 0x1E055C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_3 0x1E0560 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_LOOP_STRIDE_4 0x1E0564 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_0 0x1E0568 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_1 0x1E056C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_2 0x1E0570 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_ROI_SIZE_3 0x1E0574 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_0 0x1E0578 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_1 0x1E057C + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_2 0x1E0580 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_STRIDES_3 0x1E0584 + +#define mmMME3_CTRL_SHADOW_0_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0588 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E058C + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0590 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0594 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0598 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E059C + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_0 0x1E05A0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_1 0x1E05A4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_2 0x1E05A8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_LOCAL_START_OFFSET_3 0x1E05AC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E05B0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E05B4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E05B8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E05BC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E05C0 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_0 0x1E05C4 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_1 0x1E05C8 + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_2 0x1E05CC + +#define mmMME3_CTRL_SHADOW_0_AGU_O_REMOTE_START_OFFSET_3 0x1E05D0 + +#define mmMME3_CTRL_SHADOW_0_DESC_SB_REPEAT 0x1E05D4 + +#define mmMME3_CTRL_SHADOW_0_DESC_RATE_LIMITER 0x1E05D8 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E05DC + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E05E0 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E05E4 + +#define mmMME3_CTRL_SHADOW_0_DESC_SYNC_OBJECT_DATA 0x1E05E8 + +#define mmMME3_CTRL_SHADOW_0_DESC_AXI_USER_DATA 0x1E05EC + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_S 0x1E05F0 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_LOCAL 0x1E05F4 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_L_REMOTE 0x1E05F8 + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_LOCAL 0x1E05FC + +#define mmMME3_CTRL_SHADOW_0_DESC_PERF_EVT_O_REMOTE 0x1E0600 + +#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_S 0x1E0604 + +#define mmMME3_CTRL_SHADOW_0_DESC_PADDING_VALUE_L 0x1E0608 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_S 0x1E060C + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_LOCAL 0x1E0610 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_L_REMOTE 0x1E0614 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_LOCAL 0x1E0618 + +#define mmMME3_CTRL_SHADOW_0_DESC_META_DATA_AGU_O_REMOTE 0x1E061C + +#define mmMME3_CTRL_SHADOW_0_DESC_PCU_RL_SATURATION 0x1E0620 + +#define mmMME3_CTRL_SHADOW_0_DESC_DUMMY 0x1E0624 + +#define mmMME3_CTRL_SHADOW_1_STATUS 0x1E0680 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_S 0x1E0688 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_L 0x1E068C + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_HIGH_O 0x1E0690 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_S 0x1E0694 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_L 0x1E0698 + +#define mmMME3_CTRL_SHADOW_1_BASE_ADDR_LOW_O 0x1E069C + +#define mmMME3_CTRL_SHADOW_1_HEADER_LOW 0x1E06A0 + +#define mmMME3_CTRL_SHADOW_1_HEADER_HIGH 0x1E06A4 + +#define mmMME3_CTRL_SHADOW_1_CONV_KERNEL_SIZE_MINUS_1 0x1E06A8 + +#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_LOW 0x1E06AC + +#define mmMME3_CTRL_SHADOW_1_CONV_ASSOCIATED_DIMS_HIGH 0x1E06B0 + +#define mmMME3_CTRL_SHADOW_1_NUM_ITERATIONS_MINUS_1 0x1E06B4 + +#define mmMME3_CTRL_SHADOW_1_OUTER_LOOP 0x1E06B8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_0 0x1E06BC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_1 0x1E06C0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_2 0x1E06C4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_3 0x1E06C8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_VALID_ELEMENTS_4 0x1E06CC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_0 0x1E06D0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_1 0x1E06D4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_2 0x1E06D8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_3 0x1E06DC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_LOOP_STRIDE_4 0x1E06E0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_0 0x1E06E4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_1 0x1E06E8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_2 0x1E06EC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_ROI_SIZE_3 0x1E06F0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_0 0x1E06F4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_1 0x1E06F8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_2 0x1E06FC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_STRIDES_3 0x1E0700 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0704 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_0 0x1E0708 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_1 0x1E070C + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_2 0x1E0710 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_3 0x1E0714 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_ROI_BASE_OFFSET_4 0x1E0718 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_0 0x1E071C + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_1 0x1E0720 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_2 0x1E0724 + +#define mmMME3_CTRL_SHADOW_1_AGU_S_START_OFFSET_3 0x1E0728 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_0 0x1E072C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_1 0x1E0730 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_2 0x1E0734 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_3 0x1E0738 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_VALID_ELEMENTS_4 0x1E073C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_0 0x1E0740 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_1 0x1E0744 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_2 0x1E0748 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_3 0x1E074C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_LOOP_STRIDE_4 0x1E0750 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_0 0x1E0754 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_1 0x1E0758 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_2 0x1E075C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_ROI_SIZE_3 0x1E0760 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_0 0x1E0764 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_1 0x1E0768 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_2 0x1E076C + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_STRIDES_3 0x1E0770 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0774 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0778 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E077C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0780 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0784 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0788 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_0 0x1E078C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_1 0x1E0790 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_2 0x1E0794 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_LOCAL_START_OFFSET_3 0x1E0798 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E079C + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E07A0 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E07A4 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E07A8 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E07AC + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_0 0x1E07B0 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_1 0x1E07B4 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_2 0x1E07B8 + +#define mmMME3_CTRL_SHADOW_1_AGU_L_REMOTE_START_OFFSET_3 0x1E07BC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_0 0x1E07C0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_1 0x1E07C4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_2 0x1E07C8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_3 0x1E07CC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_VALID_ELEMENTS_4 0x1E07D0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_0 0x1E07D4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_1 0x1E07D8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_2 0x1E07DC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_3 0x1E07E0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_LOOP_STRIDE_4 0x1E07E4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_0 0x1E07E8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_1 0x1E07EC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_2 0x1E07F0 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_ROI_SIZE_3 0x1E07F4 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_0 0x1E07F8 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_1 0x1E07FC + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_2 0x1E0800 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_STRIDES_3 0x1E0804 + +#define mmMME3_CTRL_SHADOW_1_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0808 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E080C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0810 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0814 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0818 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E081C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_0 0x1E0820 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_1 0x1E0824 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_2 0x1E0828 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_LOCAL_START_OFFSET_3 0x1E082C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0830 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0834 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0838 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E083C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0840 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_0 0x1E0844 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_1 0x1E0848 + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_2 0x1E084C + +#define mmMME3_CTRL_SHADOW_1_AGU_O_REMOTE_START_OFFSET_3 0x1E0850 + +#define mmMME3_CTRL_SHADOW_1_DESC_SB_REPEAT 0x1E0854 + +#define mmMME3_CTRL_SHADOW_1_DESC_RATE_LIMITER 0x1E0858 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E085C + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0860 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0864 + +#define mmMME3_CTRL_SHADOW_1_DESC_SYNC_OBJECT_DATA 0x1E0868 + +#define mmMME3_CTRL_SHADOW_1_DESC_AXI_USER_DATA 0x1E086C + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_S 0x1E0870 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_LOCAL 0x1E0874 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_L_REMOTE 0x1E0878 + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_LOCAL 0x1E087C + +#define mmMME3_CTRL_SHADOW_1_DESC_PERF_EVT_O_REMOTE 0x1E0880 + +#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_S 0x1E0884 + +#define mmMME3_CTRL_SHADOW_1_DESC_PADDING_VALUE_L 0x1E0888 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_S 0x1E088C + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_LOCAL 0x1E0890 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_L_REMOTE 0x1E0894 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_LOCAL 0x1E0898 + +#define mmMME3_CTRL_SHADOW_1_DESC_META_DATA_AGU_O_REMOTE 0x1E089C + +#define mmMME3_CTRL_SHADOW_1_DESC_PCU_RL_SATURATION 0x1E08A0 + +#define mmMME3_CTRL_SHADOW_1_DESC_DUMMY 0x1E08A4 + +#define mmMME3_CTRL_SHADOW_2_STATUS 0x1E0900 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_S 0x1E0908 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_L 0x1E090C + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_HIGH_O 0x1E0910 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_S 0x1E0914 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_L 0x1E0918 + +#define mmMME3_CTRL_SHADOW_2_BASE_ADDR_LOW_O 0x1E091C + +#define mmMME3_CTRL_SHADOW_2_HEADER_LOW 0x1E0920 + +#define mmMME3_CTRL_SHADOW_2_HEADER_HIGH 0x1E0924 + +#define mmMME3_CTRL_SHADOW_2_CONV_KERNEL_SIZE_MINUS_1 0x1E0928 + +#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_LOW 0x1E092C + +#define mmMME3_CTRL_SHADOW_2_CONV_ASSOCIATED_DIMS_HIGH 0x1E0930 + +#define mmMME3_CTRL_SHADOW_2_NUM_ITERATIONS_MINUS_1 0x1E0934 + +#define mmMME3_CTRL_SHADOW_2_OUTER_LOOP 0x1E0938 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_0 0x1E093C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_1 0x1E0940 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_2 0x1E0944 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_3 0x1E0948 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_VALID_ELEMENTS_4 0x1E094C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_0 0x1E0950 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_1 0x1E0954 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_2 0x1E0958 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_3 0x1E095C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_LOOP_STRIDE_4 0x1E0960 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_0 0x1E0964 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_1 0x1E0968 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_2 0x1E096C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_ROI_SIZE_3 0x1E0970 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_0 0x1E0974 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_1 0x1E0978 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_2 0x1E097C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_STRIDES_3 0x1E0980 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0984 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_0 0x1E0988 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_1 0x1E098C + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_2 0x1E0990 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_3 0x1E0994 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_ROI_BASE_OFFSET_4 0x1E0998 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_0 0x1E099C + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_1 0x1E09A0 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_2 0x1E09A4 + +#define mmMME3_CTRL_SHADOW_2_AGU_S_START_OFFSET_3 0x1E09A8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_0 0x1E09AC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_1 0x1E09B0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_2 0x1E09B4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_3 0x1E09B8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_VALID_ELEMENTS_4 0x1E09BC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_0 0x1E09C0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_1 0x1E09C4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_2 0x1E09C8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_3 0x1E09CC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_LOOP_STRIDE_4 0x1E09D0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_0 0x1E09D4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_1 0x1E09D8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_2 0x1E09DC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_ROI_SIZE_3 0x1E09E0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_0 0x1E09E4 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_1 0x1E09E8 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_2 0x1E09EC + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_STRIDES_3 0x1E09F0 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E09F4 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E09F8 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E09FC + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0A00 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0A04 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0A08 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_0 0x1E0A0C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_1 0x1E0A10 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_2 0x1E0A14 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_LOCAL_START_OFFSET_3 0x1E0A18 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0A1C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0A20 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0A24 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0A28 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0A2C + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_0 0x1E0A30 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_1 0x1E0A34 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_2 0x1E0A38 + +#define mmMME3_CTRL_SHADOW_2_AGU_L_REMOTE_START_OFFSET_3 0x1E0A3C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_0 0x1E0A40 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_1 0x1E0A44 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_2 0x1E0A48 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_3 0x1E0A4C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_VALID_ELEMENTS_4 0x1E0A50 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_0 0x1E0A54 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_1 0x1E0A58 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_2 0x1E0A5C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_3 0x1E0A60 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_LOOP_STRIDE_4 0x1E0A64 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_0 0x1E0A68 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_1 0x1E0A6C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_2 0x1E0A70 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_ROI_SIZE_3 0x1E0A74 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_0 0x1E0A78 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_1 0x1E0A7C + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_2 0x1E0A80 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_STRIDES_3 0x1E0A84 + +#define mmMME3_CTRL_SHADOW_2_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0A88 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0A8C + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0A90 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0A94 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0A98 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0A9C + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_0 0x1E0AA0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_1 0x1E0AA4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_2 0x1E0AA8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_LOCAL_START_OFFSET_3 0x1E0AAC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0AB0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0AB4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0AB8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0ABC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0AC0 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_0 0x1E0AC4 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_1 0x1E0AC8 + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_2 0x1E0ACC + +#define mmMME3_CTRL_SHADOW_2_AGU_O_REMOTE_START_OFFSET_3 0x1E0AD0 + +#define mmMME3_CTRL_SHADOW_2_DESC_SB_REPEAT 0x1E0AD4 + +#define mmMME3_CTRL_SHADOW_2_DESC_RATE_LIMITER 0x1E0AD8 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0ADC + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0AE0 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0AE4 + +#define mmMME3_CTRL_SHADOW_2_DESC_SYNC_OBJECT_DATA 0x1E0AE8 + +#define mmMME3_CTRL_SHADOW_2_DESC_AXI_USER_DATA 0x1E0AEC + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_S 0x1E0AF0 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_LOCAL 0x1E0AF4 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_L_REMOTE 0x1E0AF8 + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_LOCAL 0x1E0AFC + +#define mmMME3_CTRL_SHADOW_2_DESC_PERF_EVT_O_REMOTE 0x1E0B00 + +#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_S 0x1E0B04 + +#define mmMME3_CTRL_SHADOW_2_DESC_PADDING_VALUE_L 0x1E0B08 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_S 0x1E0B0C + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_LOCAL 0x1E0B10 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_L_REMOTE 0x1E0B14 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_LOCAL 0x1E0B18 + +#define mmMME3_CTRL_SHADOW_2_DESC_META_DATA_AGU_O_REMOTE 0x1E0B1C + +#define mmMME3_CTRL_SHADOW_2_DESC_PCU_RL_SATURATION 0x1E0B20 + +#define mmMME3_CTRL_SHADOW_2_DESC_DUMMY 0x1E0B24 + +#define mmMME3_CTRL_SHADOW_3_STATUS 0x1E0B80 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_S 0x1E0B88 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_L 0x1E0B8C + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_HIGH_O 0x1E0B90 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_S 0x1E0B94 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_L 0x1E0B98 + +#define mmMME3_CTRL_SHADOW_3_BASE_ADDR_LOW_O 0x1E0B9C + +#define mmMME3_CTRL_SHADOW_3_HEADER_LOW 0x1E0BA0 + +#define mmMME3_CTRL_SHADOW_3_HEADER_HIGH 0x1E0BA4 + +#define mmMME3_CTRL_SHADOW_3_CONV_KERNEL_SIZE_MINUS_1 0x1E0BA8 + +#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_LOW 0x1E0BAC + +#define mmMME3_CTRL_SHADOW_3_CONV_ASSOCIATED_DIMS_HIGH 0x1E0BB0 + +#define mmMME3_CTRL_SHADOW_3_NUM_ITERATIONS_MINUS_1 0x1E0BB4 + +#define mmMME3_CTRL_SHADOW_3_OUTER_LOOP 0x1E0BB8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_0 0x1E0BBC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_1 0x1E0BC0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_2 0x1E0BC4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_3 0x1E0BC8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_VALID_ELEMENTS_4 0x1E0BCC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_0 0x1E0BD0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_1 0x1E0BD4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_2 0x1E0BD8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_3 0x1E0BDC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_LOOP_STRIDE_4 0x1E0BE0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_0 0x1E0BE4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_1 0x1E0BE8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_2 0x1E0BEC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_ROI_SIZE_3 0x1E0BF0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_0 0x1E0BF4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_1 0x1E0BF8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_2 0x1E0BFC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_STRIDES_3 0x1E0C00 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_S_SPATIAL_SIZE_MINUS_1 0x1E0C04 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_0 0x1E0C08 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_1 0x1E0C0C + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_2 0x1E0C10 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_3 0x1E0C14 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_ROI_BASE_OFFSET_4 0x1E0C18 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_0 0x1E0C1C + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_1 0x1E0C20 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_2 0x1E0C24 + +#define mmMME3_CTRL_SHADOW_3_AGU_S_START_OFFSET_3 0x1E0C28 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_0 0x1E0C2C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_1 0x1E0C30 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_2 0x1E0C34 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_3 0x1E0C38 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_VALID_ELEMENTS_4 0x1E0C3C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_0 0x1E0C40 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_1 0x1E0C44 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_2 0x1E0C48 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_3 0x1E0C4C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_LOOP_STRIDE_4 0x1E0C50 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_0 0x1E0C54 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_1 0x1E0C58 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_2 0x1E0C5C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_ROI_SIZE_3 0x1E0C60 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_0 0x1E0C64 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_1 0x1E0C68 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_2 0x1E0C6C + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_STRIDES_3 0x1E0C70 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_L_SPATIAL_SIZE_MINUS_1 0x1E0C74 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_0 0x1E0C78 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_1 0x1E0C7C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_2 0x1E0C80 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_3 0x1E0C84 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_ROI_BASE_OFFSET_4 0x1E0C88 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_0 0x1E0C8C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_1 0x1E0C90 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_2 0x1E0C94 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_LOCAL_START_OFFSET_3 0x1E0C98 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_0 0x1E0C9C + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_1 0x1E0CA0 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_2 0x1E0CA4 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_3 0x1E0CA8 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_ROI_BASE_OFFSET_4 0x1E0CAC + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_0 0x1E0CB0 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_1 0x1E0CB4 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_2 0x1E0CB8 + +#define mmMME3_CTRL_SHADOW_3_AGU_L_REMOTE_START_OFFSET_3 0x1E0CBC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_0 0x1E0CC0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_1 0x1E0CC4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_2 0x1E0CC8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_3 0x1E0CCC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_VALID_ELEMENTS_4 0x1E0CD0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_0 0x1E0CD4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_1 0x1E0CD8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_2 0x1E0CDC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_3 0x1E0CE0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_LOOP_STRIDE_4 0x1E0CE4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_0 0x1E0CE8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_1 0x1E0CEC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_2 0x1E0CF0 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_ROI_SIZE_3 0x1E0CF4 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_0 0x1E0CF8 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_1 0x1E0CFC + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_2 0x1E0D00 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_STRIDES_3 0x1E0D04 + +#define mmMME3_CTRL_SHADOW_3_TENSOR_O_SPATIAL_SIZE_MINUS_1 0x1E0D08 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_0 0x1E0D0C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_1 0x1E0D10 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_2 0x1E0D14 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_3 0x1E0D18 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_ROI_BASE_OFFSET_4 0x1E0D1C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_0 0x1E0D20 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_1 0x1E0D24 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_2 0x1E0D28 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_LOCAL_START_OFFSET_3 0x1E0D2C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_0 0x1E0D30 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_1 0x1E0D34 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_2 0x1E0D38 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_3 0x1E0D3C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_ROI_BASE_OFFSET_4 0x1E0D40 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_0 0x1E0D44 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_1 0x1E0D48 + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_2 0x1E0D4C + +#define mmMME3_CTRL_SHADOW_3_AGU_O_REMOTE_START_OFFSET_3 0x1E0D50 + +#define mmMME3_CTRL_SHADOW_3_DESC_SB_REPEAT 0x1E0D54 + +#define mmMME3_CTRL_SHADOW_3_DESC_RATE_LIMITER 0x1E0D58 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_LOCAL 0x1E0D5C + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_LOW_REMOTE 0x1E0D60 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_ADDR_HIGH 0x1E0D64 + +#define mmMME3_CTRL_SHADOW_3_DESC_SYNC_OBJECT_DATA 0x1E0D68 + +#define mmMME3_CTRL_SHADOW_3_DESC_AXI_USER_DATA 0x1E0D6C + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_S 0x1E0D70 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_LOCAL 0x1E0D74 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_L_REMOTE 0x1E0D78 + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_LOCAL 0x1E0D7C + +#define mmMME3_CTRL_SHADOW_3_DESC_PERF_EVT_O_REMOTE 0x1E0D80 + +#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_S 0x1E0D84 + +#define mmMME3_CTRL_SHADOW_3_DESC_PADDING_VALUE_L 0x1E0D88 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_S 0x1E0D8C + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_LOCAL 0x1E0D90 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_L_REMOTE 0x1E0D94 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_LOCAL 0x1E0D98 + +#define mmMME3_CTRL_SHADOW_3_DESC_META_DATA_AGU_O_REMOTE 0x1E0D9C + +#define mmMME3_CTRL_SHADOW_3_DESC_PCU_RL_SATURATION 0x1E0DA0 + +#define mmMME3_CTRL_SHADOW_3_DESC_DUMMY 0x1E0DA4 + +#endif /* ASIC_REG_MME3_CTRL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h new file mode 100644 index 000000000000..61465b599850 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/mmu_up_regs.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_MMU_UP_REGS_H_ +#define ASIC_REG_MMU_UP_REGS_H_ + +/* + ***************************************** + * MMU_UP (Prototype: MMU) + ***************************************** + */ + +#define mmMMU_UP_MMU_ENABLE 0xC1100C + +#define mmMMU_UP_FORCE_ORDERING 0xC11010 + +#define mmMMU_UP_FEATURE_ENABLE 0xC11014 + +#define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018 + +#define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C + +#define mmMMU_UP_LOG2_DDR_SIZE 0xC11020 + +#define mmMMU_UP_SCRAMBLER 0xC11024 + +#define mmMMU_UP_MEM_INIT_BUSY 0xC11028 + +#define mmMMU_UP_SPI_MASK 0xC1102C + +#define mmMMU_UP_SPI_CAUSE 0xC11030 + +#define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034 + +#define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038 + +#define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C + +#define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040 + +#define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044 + +#define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048 + +#define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C + +#define mmMMU_UP_SPI_CAUSE_CLR 0xC11050 + +#define mmMMU_UP_SLICE_CREDIT 0xC11054 + +#define mmMMU_UP_PIPE_CREDIT 0xC11058 + +#define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C + +#define mmMMU_UP_RAZWI_WRITE_ID 0xC11060 + +#define mmMMU_UP_RAZWI_READ_VLD 0xC11064 + +#define mmMMU_UP_RAZWI_READ_ID 0xC11068 + +#define mmMMU_UP_MMU_BYPASS 0xC1106C + +#endif /* ASIC_REG_MMU_UP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h new file mode 100644 index 000000000000..2efa2a54deb4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_0_PERM_SEL 0x386108 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_0 0x386114 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_1 0x386118 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_2 0x38611C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_3 0x386120 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_4 0x386124 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_5 0x386128 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_6 0x38612C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_7 0x386130 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_8 0x386134 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_9 0x386138 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_10 0x38613C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_11 0x386140 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_12 0x386144 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_13 0x386148 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_14 0x38614C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_15 0x386150 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_16 0x386154 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_17 0x386158 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_18 0x38615C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_19 0x386160 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_20 0x386164 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_21 0x386168 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_22 0x38616C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_23 0x386170 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_24 0x386174 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_25 0x386178 + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_26 0x38617C + +#define mmNIF_RTR_CTRL_0_HBM_POLY_H3_27 0x386180 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x386184 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x386188 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x38618C + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x386190 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x386194 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x386198 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x38619C + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3861A0 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3861A4 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3861A8 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3861AC + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3861B0 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3861B4 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3861B8 + +#define mmNIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3861BC + +#define mmNIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x38626C + +#define mmNIF_RTR_CTRL_0_RL_HBM_EN 0x386274 + +#define mmNIF_RTR_CTRL_0_RL_HBM_SAT 0x386278 + +#define mmNIF_RTR_CTRL_0_RL_HBM_RST 0x38627C + +#define mmNIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x386280 + +#define mmNIF_RTR_CTRL_0_SCRAM_HBM_EN 0x386284 + +#define mmNIF_RTR_CTRL_0_RL_PCI_EN 0x386288 + +#define mmNIF_RTR_CTRL_0_RL_PCI_SAT 0x38628C + +#define mmNIF_RTR_CTRL_0_RL_PCI_RST 0x386290 + +#define mmNIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x386294 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_EN 0x38629C + +#define mmNIF_RTR_CTRL_0_RL_SRAM_SAT 0x3862A0 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_RST 0x3862A4 + +#define mmNIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3862AC + +#define mmNIF_RTR_CTRL_0_RL_SRAM_RED 0x3862B4 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_EN 0x3862EC + +#define mmNIF_RTR_CTRL_0_E2E_PCI_EN 0x3862F0 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3862F4 + +#define mmNIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3862F8 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x386404 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x386408 + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x38640C + +#define mmNIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x386410 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x386414 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x386418 + +#define mmNIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x38641C + +#define mmNIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x386420 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x386424 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x386428 + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x38642C + +#define mmNIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x386430 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x386434 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x386438 + +#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_0 0x386450 + +#define mmNIF_RTR_CTRL_0_NL_HBM_SEL_1 0x386454 + +#define mmNIF_RTR_CTRL_0_NON_LIN_EN 0x386480 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x386500 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x386504 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x386508 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x38650C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x386510 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x386514 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x386520 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x386524 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x386528 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x38652C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x386530 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x386534 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x386538 + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x38653C + +#define mmNIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x386540 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x386550 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x386554 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x386558 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x38655C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x386560 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x386564 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x386568 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x38656C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x386570 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x386574 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x386578 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x38657C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x386580 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x386584 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x386588 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x38658C + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x386590 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x386594 + +#define mmNIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x386598 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3865E4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3865E8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3865EC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3865F0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3865F4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3865F8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3865FC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x386600 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x386604 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x386608 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x38660C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x386610 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x386614 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x386618 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x38661C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x386620 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x386624 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x386628 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x38662C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x386630 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x386634 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x386638 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x38663C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x386640 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x386644 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x386648 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x38664C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x386650 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x386654 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x386658 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x38665C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x386660 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x386664 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x386668 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x38666C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x386670 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x386674 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x386678 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x38667C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x386680 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x386684 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x386688 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x38668C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x386690 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x386694 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x386698 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x38669C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3866A0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3866A4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3866A8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3866AC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3866B0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3866B4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3866B8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3866BC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3866C0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3866C4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3866C8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3866CC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3866D0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3866D4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3866D8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3866DC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3866E0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3866E4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3866E8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3866EC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3866F0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3866F4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3866F8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3866FC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x386700 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x386704 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x386708 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x38670C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x386710 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x386714 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x386718 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x38671C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x386720 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x386724 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x386728 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x38672C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x386730 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x386734 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x386738 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x38673C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x386740 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x386744 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x386748 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x38674C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x386750 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x386754 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x386758 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x38675C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x386760 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x386764 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x386768 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x38676C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x386770 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x386774 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x386778 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x38677C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x386780 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x386784 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x386788 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x38678C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x386790 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x386794 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x386798 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x38679C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3867A0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3867A4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3867A8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3867AC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3867B0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3867B4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3867B8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3867BC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3867C0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3867C4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3867C8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3867CC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3867D0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3867D4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3867D8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3867DC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3867E0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x386824 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x386828 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x38682C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x386830 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x386834 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x386838 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x38683C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x386840 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x386844 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x386848 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x38684C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x386850 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x386854 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x386858 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x38685C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x386860 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x386864 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x386868 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x38686C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x386870 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x386874 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x386878 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x38687C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x386880 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x386884 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x386888 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x38688C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x386890 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x386894 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x386898 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x38689C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3868A0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3868A4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3868A8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3868AC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3868B0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3868B4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3868B8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3868BC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3868C0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3868C4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3868C8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3868CC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3868D0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3868D4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3868D8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3868DC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3868E0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3868E4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3868E8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3868EC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3868F0 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3868F4 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3868F8 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3868FC + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x386900 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x386904 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x386908 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x38690C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x386910 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x386914 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x386918 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x38691C + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x386920 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x386924 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x386928 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x38692C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x386930 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x386934 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x386938 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x38693C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x386940 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x386944 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x386948 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x38694C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x386950 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x386954 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x386958 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x38695C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x386960 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x386964 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x386968 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x38696C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x386970 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x386974 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x386978 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x38697C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x386980 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x386984 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x386988 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x38698C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x386990 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x386994 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x386998 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x38699C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3869A0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3869A4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3869A8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3869AC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3869B0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3869B4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3869B8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3869BC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3869C0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3869C4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3869C8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3869CC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3869D0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3869D4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3869D8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3869DC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3869E0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3869E4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3869E8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3869EC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3869F0 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3869F4 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3869F8 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3869FC + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x386A00 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x386A04 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x386A08 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x386A0C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x386A10 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x386A14 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x386A18 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x386A1C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x386A20 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x386A64 + +#define mmNIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x386A68 + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x386A6C + +#define mmNIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x386A70 + +#define mmNIF_RTR_CTRL_0_RGL_CFG 0x386B64 + +#define mmNIF_RTR_CTRL_0_RGL_SHIFT 0x386B68 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x386B6C + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x386B70 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x386B74 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x386B78 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x386B7C + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x386B80 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x386B84 + +#define mmNIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x386B88 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_0 0x386BAC + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_1 0x386BB0 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_2 0x386BB4 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_3 0x386BB8 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_4 0x386BBC + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_5 0x386BC0 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_6 0x386BC4 + +#define mmNIF_RTR_CTRL_0_RGL_TOKEN_7 0x386BC8 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_0 0x386BEC + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_1 0x386BF0 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_2 0x386BF4 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_3 0x386BF8 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_4 0x386BFC + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_5 0x386C00 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_6 0x386C04 + +#define mmNIF_RTR_CTRL_0_RGL_BANK_ID_7 0x386C08 + +#define mmNIF_RTR_CTRL_0_RGL_WDT 0x386C2C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x386C30 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x386C34 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x386C38 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x386C3C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x386C40 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x386C44 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x386C48 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x386C4C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x386C50 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x386C54 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x386C58 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x386C5C + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x386C60 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x386C64 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x386C68 + +#define mmNIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x386C6C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x386C70 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x386C74 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x386C78 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x386C7C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x386C80 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x386C84 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x386C88 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x386C8C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x386C90 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x386C94 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x386C98 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x386C9C + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x386CA0 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x386CA4 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x386CA8 + +#define mmNIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x386CAC + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x386CB0 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x386CB4 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x386CB8 + +#define mmNIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x386CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h new file mode 100644 index 000000000000..a6047d4e2560 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_1_PERM_SEL 0x396108 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_0 0x396114 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_1 0x396118 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_2 0x39611C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_3 0x396120 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_4 0x396124 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_5 0x396128 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_6 0x39612C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_7 0x396130 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_8 0x396134 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_9 0x396138 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_10 0x39613C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_11 0x396140 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_12 0x396144 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_13 0x396148 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_14 0x39614C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_15 0x396150 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_16 0x396154 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_17 0x396158 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_18 0x39615C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_19 0x396160 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_20 0x396164 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_21 0x396168 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_22 0x39616C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_23 0x396170 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_24 0x396174 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_25 0x396178 + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_26 0x39617C + +#define mmNIF_RTR_CTRL_1_HBM_POLY_H3_27 0x396180 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x396184 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x396188 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x39618C + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x396190 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x396194 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x396198 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x39619C + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3961A0 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3961A4 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3961A8 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3961AC + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3961B0 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3961B4 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3961B8 + +#define mmNIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3961BC + +#define mmNIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x39626C + +#define mmNIF_RTR_CTRL_1_RL_HBM_EN 0x396274 + +#define mmNIF_RTR_CTRL_1_RL_HBM_SAT 0x396278 + +#define mmNIF_RTR_CTRL_1_RL_HBM_RST 0x39627C + +#define mmNIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x396280 + +#define mmNIF_RTR_CTRL_1_SCRAM_HBM_EN 0x396284 + +#define mmNIF_RTR_CTRL_1_RL_PCI_EN 0x396288 + +#define mmNIF_RTR_CTRL_1_RL_PCI_SAT 0x39628C + +#define mmNIF_RTR_CTRL_1_RL_PCI_RST 0x396290 + +#define mmNIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x396294 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_EN 0x39629C + +#define mmNIF_RTR_CTRL_1_RL_SRAM_SAT 0x3962A0 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_RST 0x3962A4 + +#define mmNIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3962AC + +#define mmNIF_RTR_CTRL_1_RL_SRAM_RED 0x3962B4 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_EN 0x3962EC + +#define mmNIF_RTR_CTRL_1_E2E_PCI_EN 0x3962F0 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3962F4 + +#define mmNIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3962F8 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x396404 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x396408 + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x39640C + +#define mmNIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x396410 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x396414 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x396418 + +#define mmNIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x39641C + +#define mmNIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x396420 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x396424 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x396428 + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x39642C + +#define mmNIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x396430 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x396434 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x396438 + +#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_0 0x396450 + +#define mmNIF_RTR_CTRL_1_NL_HBM_SEL_1 0x396454 + +#define mmNIF_RTR_CTRL_1_NON_LIN_EN 0x396480 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x396500 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x396504 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x396508 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x39650C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x396510 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x396514 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x396520 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x396524 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x396528 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x39652C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x396530 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x396534 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x396538 + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x39653C + +#define mmNIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x396540 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x396550 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x396554 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x396558 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x39655C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x396560 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x396564 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x396568 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x39656C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x396570 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x396574 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x396578 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x39657C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x396580 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x396584 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x396588 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x39658C + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x396590 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x396594 + +#define mmNIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x396598 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3965E4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3965E8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3965EC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3965F0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3965F4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3965F8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3965FC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x396600 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x396604 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x396608 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x39660C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x396610 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x396614 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x396618 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x39661C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x396620 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x396624 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x396628 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x39662C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x396630 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x396634 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x396638 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x39663C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x396640 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x396644 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x396648 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x39664C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x396650 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x396654 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x396658 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x39665C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x396660 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x396664 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x396668 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x39666C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x396670 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x396674 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x396678 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x39667C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x396680 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x396684 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x396688 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x39668C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x396690 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x396694 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x396698 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x39669C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3966A0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3966A4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3966A8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3966AC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3966B0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3966B4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3966B8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3966BC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3966C0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3966C4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3966C8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3966CC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3966D0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3966D4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3966D8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3966DC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3966E0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3966E4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3966E8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3966EC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3966F0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3966F4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3966F8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3966FC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x396700 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x396704 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x396708 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x39670C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x396710 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x396714 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x396718 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x39671C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x396720 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x396724 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x396728 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x39672C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x396730 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x396734 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x396738 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x39673C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x396740 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x396744 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x396748 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x39674C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x396750 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x396754 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x396758 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x39675C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x396760 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x396764 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x396768 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x39676C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x396770 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x396774 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x396778 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x39677C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x396780 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x396784 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x396788 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x39678C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x396790 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x396794 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x396798 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x39679C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3967A0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3967A4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3967A8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3967AC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3967B0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3967B4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3967B8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3967BC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3967C0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3967C4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3967C8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3967CC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3967D0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3967D4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3967D8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3967DC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3967E0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x396824 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x396828 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x39682C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x396830 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x396834 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x396838 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x39683C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x396840 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x396844 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x396848 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x39684C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x396850 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x396854 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x396858 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x39685C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x396860 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x396864 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x396868 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x39686C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x396870 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x396874 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x396878 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x39687C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x396880 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x396884 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x396888 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x39688C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x396890 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x396894 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x396898 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x39689C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3968A0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3968A4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3968A8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3968AC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3968B0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3968B4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3968B8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3968BC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3968C0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3968C4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3968C8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3968CC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3968D0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3968D4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3968D8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3968DC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3968E0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3968E4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3968E8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3968EC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3968F0 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3968F4 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3968F8 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3968FC + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x396900 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x396904 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x396908 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x39690C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x396910 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x396914 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x396918 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x39691C + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x396920 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x396924 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x396928 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x39692C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x396930 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x396934 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x396938 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x39693C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x396940 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x396944 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x396948 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x39694C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x396950 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x396954 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x396958 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x39695C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x396960 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x396964 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x396968 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x39696C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x396970 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x396974 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x396978 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x39697C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x396980 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x396984 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x396988 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x39698C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x396990 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x396994 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x396998 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x39699C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3969A0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3969A4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3969A8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3969AC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3969B0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3969B4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3969B8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3969BC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3969C0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3969C4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3969C8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3969CC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3969D0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3969D4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3969D8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3969DC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3969E0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3969E4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3969E8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3969EC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3969F0 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3969F4 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3969F8 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3969FC + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x396A00 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x396A04 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x396A08 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x396A0C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x396A10 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x396A14 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x396A18 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x396A1C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x396A20 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x396A64 + +#define mmNIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x396A68 + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x396A6C + +#define mmNIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x396A70 + +#define mmNIF_RTR_CTRL_1_RGL_CFG 0x396B64 + +#define mmNIF_RTR_CTRL_1_RGL_SHIFT 0x396B68 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x396B6C + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x396B70 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x396B74 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x396B78 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x396B7C + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x396B80 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x396B84 + +#define mmNIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x396B88 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_0 0x396BAC + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_1 0x396BB0 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_2 0x396BB4 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_3 0x396BB8 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_4 0x396BBC + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_5 0x396BC0 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_6 0x396BC4 + +#define mmNIF_RTR_CTRL_1_RGL_TOKEN_7 0x396BC8 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_0 0x396BEC + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_1 0x396BF0 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_2 0x396BF4 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_3 0x396BF8 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_4 0x396BFC + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_5 0x396C00 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_6 0x396C04 + +#define mmNIF_RTR_CTRL_1_RGL_BANK_ID_7 0x396C08 + +#define mmNIF_RTR_CTRL_1_RGL_WDT 0x396C2C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x396C30 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x396C34 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x396C38 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x396C3C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x396C40 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x396C44 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x396C48 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x396C4C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x396C50 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x396C54 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x396C58 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x396C5C + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x396C60 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x396C64 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x396C68 + +#define mmNIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x396C6C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x396C70 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x396C74 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x396C78 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x396C7C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x396C80 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x396C84 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x396C88 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x396C8C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x396C90 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x396C94 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x396C98 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x396C9C + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x396CA0 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x396CA4 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x396CA8 + +#define mmNIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x396CAC + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x396CB0 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x396CB4 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x396CB8 + +#define mmNIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x396CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h new file mode 100644 index 000000000000..9de8442f9bc2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_2_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_2 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_2_PERM_SEL 0x3A6108 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_0 0x3A6114 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_1 0x3A6118 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_2 0x3A611C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_3 0x3A6120 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_4 0x3A6124 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_5 0x3A6128 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_6 0x3A612C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_7 0x3A6130 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_8 0x3A6134 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_9 0x3A6138 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_10 0x3A613C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_11 0x3A6140 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_12 0x3A6144 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_13 0x3A6148 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_14 0x3A614C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_15 0x3A6150 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_16 0x3A6154 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_17 0x3A6158 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_18 0x3A615C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_19 0x3A6160 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_20 0x3A6164 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_21 0x3A6168 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_22 0x3A616C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_23 0x3A6170 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_24 0x3A6174 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_25 0x3A6178 + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_26 0x3A617C + +#define mmNIF_RTR_CTRL_2_HBM_POLY_H3_27 0x3A6180 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x3A6184 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x3A6188 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x3A618C + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x3A6190 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x3A6194 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x3A6198 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x3A619C + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3A61A0 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3A61A4 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3A61A8 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3A61AC + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3A61B0 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3A61B4 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3A61B8 + +#define mmNIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3A61BC + +#define mmNIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x3A626C + +#define mmNIF_RTR_CTRL_2_RL_HBM_EN 0x3A6274 + +#define mmNIF_RTR_CTRL_2_RL_HBM_SAT 0x3A6278 + +#define mmNIF_RTR_CTRL_2_RL_HBM_RST 0x3A627C + +#define mmNIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x3A6280 + +#define mmNIF_RTR_CTRL_2_SCRAM_HBM_EN 0x3A6284 + +#define mmNIF_RTR_CTRL_2_RL_PCI_EN 0x3A6288 + +#define mmNIF_RTR_CTRL_2_RL_PCI_SAT 0x3A628C + +#define mmNIF_RTR_CTRL_2_RL_PCI_RST 0x3A6290 + +#define mmNIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x3A6294 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_EN 0x3A629C + +#define mmNIF_RTR_CTRL_2_RL_SRAM_SAT 0x3A62A0 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_RST 0x3A62A4 + +#define mmNIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3A62AC + +#define mmNIF_RTR_CTRL_2_RL_SRAM_RED 0x3A62B4 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_EN 0x3A62EC + +#define mmNIF_RTR_CTRL_2_E2E_PCI_EN 0x3A62F0 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3A62F4 + +#define mmNIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3A62F8 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x3A6404 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x3A6408 + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x3A640C + +#define mmNIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x3A6410 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x3A6414 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x3A6418 + +#define mmNIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x3A641C + +#define mmNIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x3A6420 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x3A6424 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x3A6428 + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x3A642C + +#define mmNIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x3A6430 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x3A6434 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x3A6438 + +#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_0 0x3A6450 + +#define mmNIF_RTR_CTRL_2_NL_HBM_SEL_1 0x3A6454 + +#define mmNIF_RTR_CTRL_2_NON_LIN_EN 0x3A6480 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x3A6500 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x3A6504 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x3A6508 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x3A650C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x3A6510 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x3A6514 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x3A6520 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x3A6524 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x3A6528 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x3A652C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x3A6530 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x3A6534 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x3A6538 + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x3A653C + +#define mmNIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x3A6540 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x3A6550 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x3A6554 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x3A6558 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x3A655C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x3A6560 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x3A6564 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x3A6568 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x3A656C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x3A6570 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x3A6574 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x3A6578 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x3A657C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x3A6580 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x3A6584 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x3A6588 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x3A658C + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x3A6590 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x3A6594 + +#define mmNIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x3A6598 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3A65E4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3A65E8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3A65EC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3A65F0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3A65F4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3A65F8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3A65FC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x3A6600 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x3A6604 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x3A6608 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x3A660C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x3A6610 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x3A6614 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x3A6618 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x3A661C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x3A6620 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x3A6624 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x3A6628 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x3A662C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x3A6630 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x3A6634 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x3A6638 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x3A663C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x3A6640 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x3A6644 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x3A6648 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x3A664C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x3A6650 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x3A6654 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x3A6658 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x3A665C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x3A6660 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x3A6664 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x3A6668 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x3A666C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x3A6670 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x3A6674 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x3A6678 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x3A667C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x3A6680 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x3A6684 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x3A6688 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x3A668C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x3A6690 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x3A6694 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x3A6698 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x3A669C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3A66A0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3A66A4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3A66A8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3A66AC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3A66B0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3A66B4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3A66B8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3A66BC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3A66C0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3A66C4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3A66C8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3A66CC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3A66D0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3A66D4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3A66D8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3A66DC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3A66E0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3A66E4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3A66E8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3A66EC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3A66F0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3A66F4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3A66F8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3A66FC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x3A6700 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x3A6704 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x3A6708 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x3A670C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x3A6710 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x3A6714 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x3A6718 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x3A671C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x3A6720 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x3A6724 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x3A6728 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x3A672C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x3A6730 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x3A6734 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x3A6738 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x3A673C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x3A6740 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x3A6744 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x3A6748 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x3A674C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x3A6750 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x3A6754 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x3A6758 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x3A675C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x3A6760 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x3A6764 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x3A6768 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x3A676C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x3A6770 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x3A6774 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x3A6778 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x3A677C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x3A6780 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x3A6784 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x3A6788 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x3A678C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x3A6790 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x3A6794 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x3A6798 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x3A679C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3A67A0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3A67A4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3A67A8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3A67AC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3A67B0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3A67B4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3A67B8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3A67BC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3A67C0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3A67C4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3A67C8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3A67CC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3A67D0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3A67D4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3A67D8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3A67DC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3A67E0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x3A6824 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x3A6828 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x3A682C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x3A6830 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x3A6834 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x3A6838 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x3A683C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x3A6840 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x3A6844 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x3A6848 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x3A684C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x3A6850 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x3A6854 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x3A6858 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x3A685C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x3A6860 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x3A6864 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x3A6868 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x3A686C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x3A6870 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x3A6874 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x3A6878 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x3A687C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x3A6880 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x3A6884 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x3A6888 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x3A688C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x3A6890 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x3A6894 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x3A6898 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x3A689C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3A68A0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3A68A4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3A68A8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3A68AC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3A68B0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3A68B4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3A68B8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3A68BC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3A68C0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3A68C4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3A68C8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3A68CC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3A68D0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3A68D4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3A68D8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3A68DC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3A68E0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3A68E4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3A68E8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3A68EC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3A68F0 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3A68F4 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3A68F8 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3A68FC + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x3A6900 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x3A6904 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x3A6908 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x3A690C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x3A6910 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x3A6914 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x3A6918 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x3A691C + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x3A6920 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x3A6924 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x3A6928 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x3A692C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x3A6930 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x3A6934 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x3A6938 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x3A693C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x3A6940 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x3A6944 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x3A6948 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x3A694C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x3A6950 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x3A6954 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x3A6958 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x3A695C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x3A6960 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x3A6964 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x3A6968 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x3A696C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x3A6970 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x3A6974 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x3A6978 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x3A697C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x3A6980 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x3A6984 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x3A6988 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x3A698C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x3A6990 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x3A6994 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x3A6998 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x3A699C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3A69A0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3A69A4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3A69A8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3A69AC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3A69B0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3A69B4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3A69B8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3A69BC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3A69C0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3A69C4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3A69C8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3A69CC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3A69D0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3A69D4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3A69D8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3A69DC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3A69E0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3A69E4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3A69E8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3A69EC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3A69F0 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3A69F4 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3A69F8 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3A69FC + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x3A6A00 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x3A6A04 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x3A6A08 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x3A6A0C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x3A6A10 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x3A6A14 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x3A6A18 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x3A6A1C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x3A6A20 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x3A6A64 + +#define mmNIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x3A6A68 + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x3A6A6C + +#define mmNIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x3A6A70 + +#define mmNIF_RTR_CTRL_2_RGL_CFG 0x3A6B64 + +#define mmNIF_RTR_CTRL_2_RGL_SHIFT 0x3A6B68 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x3A6B6C + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x3A6B70 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x3A6B74 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x3A6B78 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x3A6B7C + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x3A6B80 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x3A6B84 + +#define mmNIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x3A6B88 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_0 0x3A6BAC + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_1 0x3A6BB0 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_2 0x3A6BB4 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_3 0x3A6BB8 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_4 0x3A6BBC + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_5 0x3A6BC0 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_6 0x3A6BC4 + +#define mmNIF_RTR_CTRL_2_RGL_TOKEN_7 0x3A6BC8 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_0 0x3A6BEC + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_1 0x3A6BF0 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_2 0x3A6BF4 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_3 0x3A6BF8 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_4 0x3A6BFC + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_5 0x3A6C00 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_6 0x3A6C04 + +#define mmNIF_RTR_CTRL_2_RGL_BANK_ID_7 0x3A6C08 + +#define mmNIF_RTR_CTRL_2_RGL_WDT 0x3A6C2C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x3A6C30 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x3A6C34 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x3A6C38 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x3A6C3C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x3A6C40 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x3A6C44 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x3A6C48 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x3A6C4C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x3A6C50 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x3A6C54 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x3A6C58 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x3A6C5C + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x3A6C60 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x3A6C64 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x3A6C68 + +#define mmNIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x3A6C6C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x3A6C70 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x3A6C74 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x3A6C78 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x3A6C7C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x3A6C80 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x3A6C84 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x3A6C88 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x3A6C8C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x3A6C90 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x3A6C94 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x3A6C98 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x3A6C9C + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x3A6CA0 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x3A6CA4 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x3A6CA8 + +#define mmNIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x3A6CAC + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x3A6CB0 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x3A6CB4 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x3A6CB8 + +#define mmNIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x3A6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h new file mode 100644 index 000000000000..34fd47685edd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_3_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_3 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_3_PERM_SEL 0x3B6108 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_0 0x3B6114 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_1 0x3B6118 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_2 0x3B611C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_3 0x3B6120 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_4 0x3B6124 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_5 0x3B6128 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_6 0x3B612C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_7 0x3B6130 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_8 0x3B6134 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_9 0x3B6138 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_10 0x3B613C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_11 0x3B6140 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_12 0x3B6144 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_13 0x3B6148 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_14 0x3B614C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_15 0x3B6150 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_16 0x3B6154 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_17 0x3B6158 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_18 0x3B615C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_19 0x3B6160 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_20 0x3B6164 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_21 0x3B6168 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_22 0x3B616C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_23 0x3B6170 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_24 0x3B6174 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_25 0x3B6178 + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_26 0x3B617C + +#define mmNIF_RTR_CTRL_3_HBM_POLY_H3_27 0x3B6180 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x3B6184 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x3B6188 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x3B618C + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x3B6190 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x3B6194 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x3B6198 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x3B619C + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3B61A0 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3B61A4 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3B61A8 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3B61AC + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3B61B0 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3B61B4 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3B61B8 + +#define mmNIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3B61BC + +#define mmNIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x3B626C + +#define mmNIF_RTR_CTRL_3_RL_HBM_EN 0x3B6274 + +#define mmNIF_RTR_CTRL_3_RL_HBM_SAT 0x3B6278 + +#define mmNIF_RTR_CTRL_3_RL_HBM_RST 0x3B627C + +#define mmNIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x3B6280 + +#define mmNIF_RTR_CTRL_3_SCRAM_HBM_EN 0x3B6284 + +#define mmNIF_RTR_CTRL_3_RL_PCI_EN 0x3B6288 + +#define mmNIF_RTR_CTRL_3_RL_PCI_SAT 0x3B628C + +#define mmNIF_RTR_CTRL_3_RL_PCI_RST 0x3B6290 + +#define mmNIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x3B6294 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_EN 0x3B629C + +#define mmNIF_RTR_CTRL_3_RL_SRAM_SAT 0x3B62A0 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_RST 0x3B62A4 + +#define mmNIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3B62AC + +#define mmNIF_RTR_CTRL_3_RL_SRAM_RED 0x3B62B4 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_EN 0x3B62EC + +#define mmNIF_RTR_CTRL_3_E2E_PCI_EN 0x3B62F0 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3B62F4 + +#define mmNIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3B62F8 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x3B6404 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x3B6408 + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x3B640C + +#define mmNIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x3B6410 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x3B6414 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x3B6418 + +#define mmNIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x3B641C + +#define mmNIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x3B6420 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x3B6424 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x3B6428 + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x3B642C + +#define mmNIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x3B6430 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x3B6434 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x3B6438 + +#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_0 0x3B6450 + +#define mmNIF_RTR_CTRL_3_NL_HBM_SEL_1 0x3B6454 + +#define mmNIF_RTR_CTRL_3_NON_LIN_EN 0x3B6480 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x3B6500 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x3B6504 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x3B6508 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x3B650C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x3B6510 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x3B6514 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x3B6520 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x3B6524 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x3B6528 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x3B652C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x3B6530 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x3B6534 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x3B6538 + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x3B653C + +#define mmNIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x3B6540 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x3B6550 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x3B6554 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x3B6558 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x3B655C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x3B6560 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x3B6564 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x3B6568 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x3B656C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x3B6570 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x3B6574 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x3B6578 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x3B657C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x3B6580 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x3B6584 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x3B6588 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x3B658C + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x3B6590 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x3B6594 + +#define mmNIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x3B6598 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3B65E4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3B65E8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3B65EC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3B65F0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3B65F4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3B65F8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3B65FC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x3B6600 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x3B6604 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x3B6608 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x3B660C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x3B6610 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x3B6614 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x3B6618 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x3B661C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x3B6620 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x3B6624 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x3B6628 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x3B662C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x3B6630 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x3B6634 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x3B6638 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x3B663C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x3B6640 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x3B6644 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x3B6648 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x3B664C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x3B6650 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x3B6654 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x3B6658 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x3B665C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x3B6660 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x3B6664 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x3B6668 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x3B666C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x3B6670 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x3B6674 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x3B6678 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x3B667C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x3B6680 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x3B6684 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x3B6688 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x3B668C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x3B6690 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x3B6694 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x3B6698 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x3B669C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3B66A0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3B66A4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3B66A8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3B66AC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3B66B0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3B66B4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3B66B8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3B66BC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3B66C0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3B66C4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3B66C8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3B66CC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3B66D0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3B66D4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3B66D8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3B66DC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3B66E0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3B66E4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3B66E8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3B66EC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3B66F0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3B66F4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3B66F8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3B66FC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x3B6700 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x3B6704 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x3B6708 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x3B670C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x3B6710 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x3B6714 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x3B6718 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x3B671C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x3B6720 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x3B6724 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x3B6728 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x3B672C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x3B6730 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x3B6734 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x3B6738 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x3B673C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x3B6740 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x3B6744 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x3B6748 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x3B674C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x3B6750 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x3B6754 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x3B6758 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x3B675C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x3B6760 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x3B6764 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x3B6768 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x3B676C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x3B6770 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x3B6774 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x3B6778 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x3B677C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x3B6780 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x3B6784 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x3B6788 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x3B678C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x3B6790 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x3B6794 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x3B6798 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x3B679C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3B67A0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3B67A4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3B67A8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3B67AC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3B67B0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3B67B4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3B67B8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3B67BC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3B67C0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3B67C4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3B67C8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3B67CC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3B67D0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3B67D4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3B67D8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3B67DC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3B67E0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x3B6824 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x3B6828 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x3B682C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x3B6830 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x3B6834 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x3B6838 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x3B683C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x3B6840 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x3B6844 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x3B6848 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x3B684C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x3B6850 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x3B6854 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x3B6858 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x3B685C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x3B6860 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x3B6864 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x3B6868 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x3B686C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x3B6870 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x3B6874 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x3B6878 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x3B687C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x3B6880 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x3B6884 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x3B6888 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x3B688C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x3B6890 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x3B6894 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x3B6898 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x3B689C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3B68A0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3B68A4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3B68A8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3B68AC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3B68B0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3B68B4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3B68B8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3B68BC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3B68C0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3B68C4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3B68C8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3B68CC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3B68D0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3B68D4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3B68D8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3B68DC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3B68E0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3B68E4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3B68E8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3B68EC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3B68F0 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3B68F4 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3B68F8 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3B68FC + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x3B6900 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x3B6904 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x3B6908 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x3B690C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x3B6910 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x3B6914 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x3B6918 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x3B691C + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x3B6920 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x3B6924 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x3B6928 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x3B692C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x3B6930 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x3B6934 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x3B6938 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x3B693C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x3B6940 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x3B6944 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x3B6948 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x3B694C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x3B6950 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x3B6954 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x3B6958 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x3B695C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x3B6960 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x3B6964 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x3B6968 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x3B696C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x3B6970 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x3B6974 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x3B6978 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x3B697C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x3B6980 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x3B6984 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x3B6988 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x3B698C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x3B6990 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x3B6994 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x3B6998 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x3B699C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3B69A0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3B69A4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3B69A8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3B69AC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3B69B0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3B69B4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3B69B8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3B69BC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3B69C0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3B69C4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3B69C8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3B69CC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3B69D0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3B69D4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3B69D8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3B69DC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3B69E0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3B69E4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3B69E8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3B69EC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3B69F0 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3B69F4 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3B69F8 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3B69FC + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x3B6A00 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x3B6A04 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x3B6A08 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x3B6A0C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x3B6A10 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x3B6A14 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x3B6A18 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x3B6A1C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x3B6A20 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x3B6A64 + +#define mmNIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x3B6A68 + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x3B6A6C + +#define mmNIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x3B6A70 + +#define mmNIF_RTR_CTRL_3_RGL_CFG 0x3B6B64 + +#define mmNIF_RTR_CTRL_3_RGL_SHIFT 0x3B6B68 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x3B6B6C + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x3B6B70 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x3B6B74 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x3B6B78 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x3B6B7C + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x3B6B80 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x3B6B84 + +#define mmNIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x3B6B88 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_0 0x3B6BAC + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_1 0x3B6BB0 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_2 0x3B6BB4 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_3 0x3B6BB8 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_4 0x3B6BBC + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_5 0x3B6BC0 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_6 0x3B6BC4 + +#define mmNIF_RTR_CTRL_3_RGL_TOKEN_7 0x3B6BC8 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_0 0x3B6BEC + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_1 0x3B6BF0 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_2 0x3B6BF4 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_3 0x3B6BF8 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_4 0x3B6BFC + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_5 0x3B6C00 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_6 0x3B6C04 + +#define mmNIF_RTR_CTRL_3_RGL_BANK_ID_7 0x3B6C08 + +#define mmNIF_RTR_CTRL_3_RGL_WDT 0x3B6C2C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x3B6C30 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x3B6C34 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x3B6C38 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x3B6C3C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x3B6C40 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x3B6C44 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x3B6C48 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x3B6C4C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x3B6C50 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x3B6C54 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x3B6C58 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x3B6C5C + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x3B6C60 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x3B6C64 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x3B6C68 + +#define mmNIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x3B6C6C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x3B6C70 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x3B6C74 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x3B6C78 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x3B6C7C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x3B6C80 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x3B6C84 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x3B6C88 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x3B6C8C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x3B6C90 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x3B6C94 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x3B6C98 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x3B6C9C + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x3B6CA0 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x3B6CA4 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x3B6CA8 + +#define mmNIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x3B6CAC + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x3B6CB0 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x3B6CB4 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x3B6CB8 + +#define mmNIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x3B6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h new file mode 100644 index 000000000000..543a98f81767 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_4_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_4 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_4_PERM_SEL 0x3C6108 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_0 0x3C6114 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_1 0x3C6118 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_2 0x3C611C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_3 0x3C6120 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_4 0x3C6124 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_5 0x3C6128 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_6 0x3C612C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_7 0x3C6130 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_8 0x3C6134 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_9 0x3C6138 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_10 0x3C613C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_11 0x3C6140 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_12 0x3C6144 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_13 0x3C6148 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_14 0x3C614C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_15 0x3C6150 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_16 0x3C6154 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_17 0x3C6158 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_18 0x3C615C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_19 0x3C6160 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_20 0x3C6164 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_21 0x3C6168 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_22 0x3C616C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_23 0x3C6170 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_24 0x3C6174 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_25 0x3C6178 + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_26 0x3C617C + +#define mmNIF_RTR_CTRL_4_HBM_POLY_H3_27 0x3C6180 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x3C6184 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x3C6188 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x3C618C + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x3C6190 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x3C6194 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x3C6198 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x3C619C + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3C61A0 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3C61A4 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3C61A8 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3C61AC + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3C61B0 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3C61B4 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3C61B8 + +#define mmNIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3C61BC + +#define mmNIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x3C626C + +#define mmNIF_RTR_CTRL_4_RL_HBM_EN 0x3C6274 + +#define mmNIF_RTR_CTRL_4_RL_HBM_SAT 0x3C6278 + +#define mmNIF_RTR_CTRL_4_RL_HBM_RST 0x3C627C + +#define mmNIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x3C6280 + +#define mmNIF_RTR_CTRL_4_SCRAM_HBM_EN 0x3C6284 + +#define mmNIF_RTR_CTRL_4_RL_PCI_EN 0x3C6288 + +#define mmNIF_RTR_CTRL_4_RL_PCI_SAT 0x3C628C + +#define mmNIF_RTR_CTRL_4_RL_PCI_RST 0x3C6290 + +#define mmNIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x3C6294 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_EN 0x3C629C + +#define mmNIF_RTR_CTRL_4_RL_SRAM_SAT 0x3C62A0 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_RST 0x3C62A4 + +#define mmNIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3C62AC + +#define mmNIF_RTR_CTRL_4_RL_SRAM_RED 0x3C62B4 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_EN 0x3C62EC + +#define mmNIF_RTR_CTRL_4_E2E_PCI_EN 0x3C62F0 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3C62F4 + +#define mmNIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3C62F8 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x3C6404 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x3C6408 + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x3C640C + +#define mmNIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x3C6410 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x3C6414 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x3C6418 + +#define mmNIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x3C641C + +#define mmNIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x3C6420 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x3C6424 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x3C6428 + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x3C642C + +#define mmNIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x3C6430 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x3C6434 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x3C6438 + +#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_0 0x3C6450 + +#define mmNIF_RTR_CTRL_4_NL_HBM_SEL_1 0x3C6454 + +#define mmNIF_RTR_CTRL_4_NON_LIN_EN 0x3C6480 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x3C6500 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x3C6504 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x3C6508 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x3C650C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x3C6510 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x3C6514 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x3C6520 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x3C6524 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x3C6528 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x3C652C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x3C6530 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x3C6534 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x3C6538 + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x3C653C + +#define mmNIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x3C6540 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x3C6550 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x3C6554 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x3C6558 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x3C655C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x3C6560 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x3C6564 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x3C6568 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x3C656C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x3C6570 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x3C6574 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x3C6578 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x3C657C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x3C6580 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x3C6584 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x3C6588 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x3C658C + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x3C6590 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x3C6594 + +#define mmNIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x3C6598 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3C65E4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3C65E8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3C65EC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3C65F0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3C65F4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3C65F8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3C65FC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x3C6600 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x3C6604 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x3C6608 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x3C660C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x3C6610 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x3C6614 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x3C6618 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x3C661C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x3C6620 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x3C6624 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x3C6628 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x3C662C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x3C6630 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x3C6634 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x3C6638 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x3C663C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x3C6640 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x3C6644 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x3C6648 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x3C664C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x3C6650 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x3C6654 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x3C6658 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x3C665C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x3C6660 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x3C6664 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x3C6668 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x3C666C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x3C6670 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x3C6674 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x3C6678 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x3C667C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x3C6680 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x3C6684 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x3C6688 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x3C668C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x3C6690 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x3C6694 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x3C6698 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x3C669C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3C66A0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3C66A4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3C66A8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3C66AC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3C66B0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3C66B4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3C66B8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3C66BC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3C66C0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3C66C4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3C66C8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3C66CC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3C66D0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3C66D4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3C66D8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3C66DC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3C66E0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3C66E4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3C66E8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3C66EC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3C66F0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3C66F4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3C66F8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3C66FC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x3C6700 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x3C6704 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x3C6708 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x3C670C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x3C6710 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x3C6714 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x3C6718 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x3C671C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x3C6720 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x3C6724 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x3C6728 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x3C672C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x3C6730 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x3C6734 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x3C6738 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x3C673C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x3C6740 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x3C6744 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x3C6748 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x3C674C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x3C6750 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x3C6754 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x3C6758 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x3C675C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x3C6760 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x3C6764 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x3C6768 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x3C676C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x3C6770 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x3C6774 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x3C6778 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x3C677C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x3C6780 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x3C6784 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x3C6788 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x3C678C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x3C6790 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x3C6794 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x3C6798 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x3C679C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3C67A0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3C67A4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3C67A8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3C67AC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3C67B0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3C67B4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3C67B8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3C67BC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3C67C0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3C67C4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3C67C8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3C67CC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3C67D0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3C67D4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3C67D8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3C67DC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3C67E0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x3C6824 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x3C6828 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x3C682C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x3C6830 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x3C6834 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x3C6838 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x3C683C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x3C6840 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x3C6844 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x3C6848 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x3C684C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x3C6850 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x3C6854 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x3C6858 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x3C685C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x3C6860 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x3C6864 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x3C6868 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x3C686C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x3C6870 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x3C6874 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x3C6878 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x3C687C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x3C6880 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x3C6884 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x3C6888 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x3C688C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x3C6890 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x3C6894 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x3C6898 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x3C689C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3C68A0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3C68A4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3C68A8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3C68AC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3C68B0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3C68B4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3C68B8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3C68BC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3C68C0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3C68C4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3C68C8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3C68CC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3C68D0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3C68D4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3C68D8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3C68DC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3C68E0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3C68E4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3C68E8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3C68EC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3C68F0 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3C68F4 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3C68F8 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3C68FC + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x3C6900 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x3C6904 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x3C6908 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x3C690C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x3C6910 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x3C6914 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x3C6918 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x3C691C + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x3C6920 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x3C6924 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x3C6928 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x3C692C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x3C6930 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x3C6934 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x3C6938 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x3C693C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x3C6940 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x3C6944 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x3C6948 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x3C694C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x3C6950 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x3C6954 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x3C6958 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x3C695C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x3C6960 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x3C6964 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x3C6968 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x3C696C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x3C6970 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x3C6974 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x3C6978 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x3C697C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x3C6980 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x3C6984 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x3C6988 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x3C698C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x3C6990 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x3C6994 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x3C6998 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x3C699C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3C69A0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3C69A4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3C69A8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3C69AC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3C69B0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3C69B4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3C69B8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3C69BC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3C69C0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3C69C4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3C69C8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3C69CC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3C69D0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3C69D4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3C69D8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3C69DC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3C69E0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3C69E4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3C69E8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3C69EC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3C69F0 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3C69F4 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3C69F8 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3C69FC + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x3C6A00 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x3C6A04 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x3C6A08 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x3C6A0C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x3C6A10 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x3C6A14 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x3C6A18 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x3C6A1C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x3C6A20 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x3C6A64 + +#define mmNIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x3C6A68 + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x3C6A6C + +#define mmNIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x3C6A70 + +#define mmNIF_RTR_CTRL_4_RGL_CFG 0x3C6B64 + +#define mmNIF_RTR_CTRL_4_RGL_SHIFT 0x3C6B68 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x3C6B6C + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x3C6B70 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x3C6B74 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x3C6B78 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x3C6B7C + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x3C6B80 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x3C6B84 + +#define mmNIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x3C6B88 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_0 0x3C6BAC + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_1 0x3C6BB0 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_2 0x3C6BB4 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_3 0x3C6BB8 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_4 0x3C6BBC + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_5 0x3C6BC0 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_6 0x3C6BC4 + +#define mmNIF_RTR_CTRL_4_RGL_TOKEN_7 0x3C6BC8 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_0 0x3C6BEC + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_1 0x3C6BF0 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_2 0x3C6BF4 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_3 0x3C6BF8 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_4 0x3C6BFC + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_5 0x3C6C00 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_6 0x3C6C04 + +#define mmNIF_RTR_CTRL_4_RGL_BANK_ID_7 0x3C6C08 + +#define mmNIF_RTR_CTRL_4_RGL_WDT 0x3C6C2C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x3C6C30 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x3C6C34 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x3C6C38 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x3C6C3C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x3C6C40 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x3C6C44 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x3C6C48 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x3C6C4C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x3C6C50 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x3C6C54 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x3C6C58 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x3C6C5C + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x3C6C60 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x3C6C64 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x3C6C68 + +#define mmNIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x3C6C6C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x3C6C70 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x3C6C74 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x3C6C78 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x3C6C7C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x3C6C80 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x3C6C84 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x3C6C88 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x3C6C8C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x3C6C90 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x3C6C94 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x3C6C98 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x3C6C9C + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x3C6CA0 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x3C6CA4 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x3C6CA8 + +#define mmNIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x3C6CAC + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x3C6CB0 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x3C6CB4 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x3C6CB8 + +#define mmNIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x3C6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h new file mode 100644 index 000000000000..95486b7ddf1d --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_5_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_5 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_5_PERM_SEL 0x3D6108 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_0 0x3D6114 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_1 0x3D6118 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_2 0x3D611C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_3 0x3D6120 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_4 0x3D6124 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_5 0x3D6128 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_6 0x3D612C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_7 0x3D6130 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_8 0x3D6134 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_9 0x3D6138 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_10 0x3D613C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_11 0x3D6140 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_12 0x3D6144 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_13 0x3D6148 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_14 0x3D614C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_15 0x3D6150 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_16 0x3D6154 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_17 0x3D6158 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_18 0x3D615C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_19 0x3D6160 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_20 0x3D6164 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_21 0x3D6168 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_22 0x3D616C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_23 0x3D6170 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_24 0x3D6174 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_25 0x3D6178 + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_26 0x3D617C + +#define mmNIF_RTR_CTRL_5_HBM_POLY_H3_27 0x3D6180 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x3D6184 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x3D6188 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x3D618C + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x3D6190 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x3D6194 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x3D6198 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x3D619C + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3D61A0 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3D61A4 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3D61A8 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3D61AC + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3D61B0 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3D61B4 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3D61B8 + +#define mmNIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3D61BC + +#define mmNIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x3D626C + +#define mmNIF_RTR_CTRL_5_RL_HBM_EN 0x3D6274 + +#define mmNIF_RTR_CTRL_5_RL_HBM_SAT 0x3D6278 + +#define mmNIF_RTR_CTRL_5_RL_HBM_RST 0x3D627C + +#define mmNIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x3D6280 + +#define mmNIF_RTR_CTRL_5_SCRAM_HBM_EN 0x3D6284 + +#define mmNIF_RTR_CTRL_5_RL_PCI_EN 0x3D6288 + +#define mmNIF_RTR_CTRL_5_RL_PCI_SAT 0x3D628C + +#define mmNIF_RTR_CTRL_5_RL_PCI_RST 0x3D6290 + +#define mmNIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x3D6294 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_EN 0x3D629C + +#define mmNIF_RTR_CTRL_5_RL_SRAM_SAT 0x3D62A0 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_RST 0x3D62A4 + +#define mmNIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3D62AC + +#define mmNIF_RTR_CTRL_5_RL_SRAM_RED 0x3D62B4 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_EN 0x3D62EC + +#define mmNIF_RTR_CTRL_5_E2E_PCI_EN 0x3D62F0 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3D62F4 + +#define mmNIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3D62F8 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x3D6404 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x3D6408 + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x3D640C + +#define mmNIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x3D6410 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x3D6414 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x3D6418 + +#define mmNIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x3D641C + +#define mmNIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x3D6420 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x3D6424 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x3D6428 + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x3D642C + +#define mmNIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x3D6430 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x3D6434 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x3D6438 + +#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_0 0x3D6450 + +#define mmNIF_RTR_CTRL_5_NL_HBM_SEL_1 0x3D6454 + +#define mmNIF_RTR_CTRL_5_NON_LIN_EN 0x3D6480 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x3D6500 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x3D6504 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x3D6508 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x3D650C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x3D6510 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x3D6514 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x3D6520 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x3D6524 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x3D6528 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x3D652C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x3D6530 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x3D6534 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x3D6538 + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x3D653C + +#define mmNIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x3D6540 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x3D6550 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x3D6554 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x3D6558 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x3D655C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x3D6560 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x3D6564 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x3D6568 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x3D656C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x3D6570 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x3D6574 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x3D6578 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x3D657C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x3D6580 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x3D6584 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x3D6588 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x3D658C + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x3D6590 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x3D6594 + +#define mmNIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x3D6598 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3D65E4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3D65E8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3D65EC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3D65F0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3D65F4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3D65F8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3D65FC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x3D6600 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x3D6604 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x3D6608 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x3D660C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x3D6610 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x3D6614 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x3D6618 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x3D661C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x3D6620 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x3D6624 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x3D6628 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x3D662C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x3D6630 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x3D6634 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x3D6638 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x3D663C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x3D6640 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x3D6644 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x3D6648 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x3D664C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x3D6650 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x3D6654 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x3D6658 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x3D665C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x3D6660 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x3D6664 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x3D6668 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x3D666C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x3D6670 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x3D6674 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x3D6678 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x3D667C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x3D6680 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x3D6684 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x3D6688 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x3D668C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x3D6690 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x3D6694 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x3D6698 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x3D669C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3D66A0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3D66A4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3D66A8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3D66AC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3D66B0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3D66B4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3D66B8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3D66BC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3D66C0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3D66C4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3D66C8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3D66CC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3D66D0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3D66D4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3D66D8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3D66DC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3D66E0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3D66E4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3D66E8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3D66EC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3D66F0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3D66F4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3D66F8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3D66FC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x3D6700 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x3D6704 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x3D6708 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x3D670C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x3D6710 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x3D6714 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x3D6718 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x3D671C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x3D6720 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x3D6724 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x3D6728 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x3D672C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x3D6730 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x3D6734 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x3D6738 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x3D673C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x3D6740 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x3D6744 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x3D6748 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x3D674C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x3D6750 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x3D6754 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x3D6758 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x3D675C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x3D6760 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x3D6764 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x3D6768 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x3D676C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x3D6770 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x3D6774 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x3D6778 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x3D677C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x3D6780 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x3D6784 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x3D6788 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x3D678C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x3D6790 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x3D6794 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x3D6798 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x3D679C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3D67A0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3D67A4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3D67A8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3D67AC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3D67B0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3D67B4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3D67B8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3D67BC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3D67C0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3D67C4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3D67C8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3D67CC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3D67D0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3D67D4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3D67D8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3D67DC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3D67E0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x3D6824 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x3D6828 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x3D682C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x3D6830 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x3D6834 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x3D6838 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x3D683C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x3D6840 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x3D6844 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x3D6848 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x3D684C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x3D6850 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x3D6854 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x3D6858 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x3D685C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x3D6860 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x3D6864 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x3D6868 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x3D686C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x3D6870 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x3D6874 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x3D6878 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x3D687C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x3D6880 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x3D6884 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x3D6888 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x3D688C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x3D6890 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x3D6894 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x3D6898 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x3D689C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3D68A0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3D68A4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3D68A8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3D68AC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3D68B0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3D68B4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3D68B8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3D68BC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3D68C0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3D68C4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3D68C8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3D68CC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3D68D0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3D68D4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3D68D8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3D68DC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3D68E0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3D68E4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3D68E8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3D68EC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3D68F0 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3D68F4 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3D68F8 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3D68FC + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x3D6900 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x3D6904 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x3D6908 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x3D690C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x3D6910 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x3D6914 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x3D6918 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x3D691C + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x3D6920 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x3D6924 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x3D6928 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x3D692C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x3D6930 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x3D6934 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x3D6938 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x3D693C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x3D6940 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x3D6944 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x3D6948 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x3D694C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x3D6950 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x3D6954 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x3D6958 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x3D695C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x3D6960 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x3D6964 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x3D6968 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x3D696C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x3D6970 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x3D6974 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x3D6978 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x3D697C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x3D6980 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x3D6984 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x3D6988 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x3D698C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x3D6990 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x3D6994 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x3D6998 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x3D699C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3D69A0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3D69A4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3D69A8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3D69AC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3D69B0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3D69B4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3D69B8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3D69BC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3D69C0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3D69C4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3D69C8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3D69CC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3D69D0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3D69D4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3D69D8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3D69DC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3D69E0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3D69E4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3D69E8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3D69EC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3D69F0 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3D69F4 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3D69F8 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3D69FC + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x3D6A00 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x3D6A04 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x3D6A08 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x3D6A0C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x3D6A10 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x3D6A14 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x3D6A18 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x3D6A1C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x3D6A20 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x3D6A64 + +#define mmNIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x3D6A68 + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x3D6A6C + +#define mmNIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x3D6A70 + +#define mmNIF_RTR_CTRL_5_RGL_CFG 0x3D6B64 + +#define mmNIF_RTR_CTRL_5_RGL_SHIFT 0x3D6B68 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x3D6B6C + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x3D6B70 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x3D6B74 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x3D6B78 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x3D6B7C + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x3D6B80 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x3D6B84 + +#define mmNIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x3D6B88 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_0 0x3D6BAC + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_1 0x3D6BB0 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_2 0x3D6BB4 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_3 0x3D6BB8 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_4 0x3D6BBC + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_5 0x3D6BC0 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_6 0x3D6BC4 + +#define mmNIF_RTR_CTRL_5_RGL_TOKEN_7 0x3D6BC8 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_0 0x3D6BEC + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_1 0x3D6BF0 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_2 0x3D6BF4 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_3 0x3D6BF8 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_4 0x3D6BFC + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_5 0x3D6C00 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_6 0x3D6C04 + +#define mmNIF_RTR_CTRL_5_RGL_BANK_ID_7 0x3D6C08 + +#define mmNIF_RTR_CTRL_5_RGL_WDT 0x3D6C2C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x3D6C30 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x3D6C34 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x3D6C38 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x3D6C3C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x3D6C40 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x3D6C44 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x3D6C48 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x3D6C4C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x3D6C50 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x3D6C54 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x3D6C58 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x3D6C5C + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x3D6C60 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x3D6C64 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x3D6C68 + +#define mmNIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x3D6C6C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x3D6C70 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x3D6C74 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x3D6C78 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x3D6C7C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x3D6C80 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x3D6C84 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x3D6C88 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x3D6C8C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x3D6C90 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x3D6C94 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x3D6C98 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x3D6C9C + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x3D6CA0 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x3D6CA4 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x3D6CA8 + +#define mmNIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x3D6CAC + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x3D6CB0 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x3D6CB4 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x3D6CB8 + +#define mmNIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x3D6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_5_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h new file mode 100644 index 000000000000..b79c59887b21 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_6_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_6 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_6_PERM_SEL 0x3E6108 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_0 0x3E6114 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_1 0x3E6118 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_2 0x3E611C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_3 0x3E6120 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_4 0x3E6124 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_5 0x3E6128 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_6 0x3E612C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_7 0x3E6130 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_8 0x3E6134 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_9 0x3E6138 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_10 0x3E613C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_11 0x3E6140 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_12 0x3E6144 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_13 0x3E6148 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_14 0x3E614C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_15 0x3E6150 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_16 0x3E6154 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_17 0x3E6158 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_18 0x3E615C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_19 0x3E6160 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_20 0x3E6164 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_21 0x3E6168 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_22 0x3E616C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_23 0x3E6170 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_24 0x3E6174 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_25 0x3E6178 + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_26 0x3E617C + +#define mmNIF_RTR_CTRL_6_HBM_POLY_H3_27 0x3E6180 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x3E6184 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x3E6188 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x3E618C + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x3E6190 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x3E6194 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x3E6198 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x3E619C + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3E61A0 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3E61A4 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3E61A8 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3E61AC + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3E61B0 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3E61B4 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3E61B8 + +#define mmNIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3E61BC + +#define mmNIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x3E626C + +#define mmNIF_RTR_CTRL_6_RL_HBM_EN 0x3E6274 + +#define mmNIF_RTR_CTRL_6_RL_HBM_SAT 0x3E6278 + +#define mmNIF_RTR_CTRL_6_RL_HBM_RST 0x3E627C + +#define mmNIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x3E6280 + +#define mmNIF_RTR_CTRL_6_SCRAM_HBM_EN 0x3E6284 + +#define mmNIF_RTR_CTRL_6_RL_PCI_EN 0x3E6288 + +#define mmNIF_RTR_CTRL_6_RL_PCI_SAT 0x3E628C + +#define mmNIF_RTR_CTRL_6_RL_PCI_RST 0x3E6290 + +#define mmNIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x3E6294 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_EN 0x3E629C + +#define mmNIF_RTR_CTRL_6_RL_SRAM_SAT 0x3E62A0 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_RST 0x3E62A4 + +#define mmNIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3E62AC + +#define mmNIF_RTR_CTRL_6_RL_SRAM_RED 0x3E62B4 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_EN 0x3E62EC + +#define mmNIF_RTR_CTRL_6_E2E_PCI_EN 0x3E62F0 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3E62F4 + +#define mmNIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3E62F8 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x3E6404 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x3E6408 + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x3E640C + +#define mmNIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x3E6410 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x3E6414 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x3E6418 + +#define mmNIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x3E641C + +#define mmNIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x3E6420 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x3E6424 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x3E6428 + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x3E642C + +#define mmNIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x3E6430 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x3E6434 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x3E6438 + +#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_0 0x3E6450 + +#define mmNIF_RTR_CTRL_6_NL_HBM_SEL_1 0x3E6454 + +#define mmNIF_RTR_CTRL_6_NON_LIN_EN 0x3E6480 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x3E6500 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x3E6504 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x3E6508 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x3E650C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x3E6510 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x3E6514 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x3E6520 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x3E6524 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x3E6528 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x3E652C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x3E6530 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x3E6534 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x3E6538 + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x3E653C + +#define mmNIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x3E6540 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x3E6550 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x3E6554 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x3E6558 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x3E655C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x3E6560 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x3E6564 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x3E6568 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x3E656C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x3E6570 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x3E6574 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x3E6578 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x3E657C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x3E6580 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x3E6584 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x3E6588 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x3E658C + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x3E6590 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x3E6594 + +#define mmNIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x3E6598 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3E65E4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3E65E8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3E65EC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3E65F0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3E65F4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3E65F8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3E65FC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x3E6600 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x3E6604 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x3E6608 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x3E660C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x3E6610 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x3E6614 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x3E6618 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x3E661C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x3E6620 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x3E6624 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x3E6628 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x3E662C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x3E6630 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x3E6634 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x3E6638 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x3E663C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x3E6640 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x3E6644 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x3E6648 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x3E664C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x3E6650 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x3E6654 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x3E6658 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x3E665C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x3E6660 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x3E6664 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x3E6668 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x3E666C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x3E6670 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x3E6674 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x3E6678 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x3E667C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x3E6680 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x3E6684 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x3E6688 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x3E668C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x3E6690 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x3E6694 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x3E6698 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x3E669C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3E66A0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3E66A4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3E66A8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3E66AC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3E66B0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3E66B4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3E66B8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3E66BC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3E66C0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3E66C4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3E66C8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3E66CC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3E66D0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3E66D4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3E66D8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3E66DC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3E66E0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3E66E4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3E66E8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3E66EC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3E66F0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3E66F4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3E66F8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3E66FC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x3E6700 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x3E6704 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x3E6708 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x3E670C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x3E6710 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x3E6714 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x3E6718 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x3E671C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x3E6720 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x3E6724 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x3E6728 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x3E672C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x3E6730 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x3E6734 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x3E6738 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x3E673C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x3E6740 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x3E6744 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x3E6748 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x3E674C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x3E6750 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x3E6754 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x3E6758 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x3E675C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x3E6760 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x3E6764 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x3E6768 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x3E676C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x3E6770 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x3E6774 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x3E6778 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x3E677C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x3E6780 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x3E6784 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x3E6788 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x3E678C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x3E6790 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x3E6794 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x3E6798 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x3E679C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3E67A0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3E67A4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3E67A8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3E67AC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3E67B0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3E67B4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3E67B8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3E67BC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3E67C0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3E67C4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3E67C8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3E67CC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3E67D0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3E67D4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3E67D8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3E67DC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3E67E0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x3E6824 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x3E6828 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x3E682C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x3E6830 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x3E6834 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x3E6838 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x3E683C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x3E6840 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x3E6844 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x3E6848 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x3E684C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x3E6850 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x3E6854 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x3E6858 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x3E685C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x3E6860 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x3E6864 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x3E6868 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x3E686C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x3E6870 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x3E6874 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x3E6878 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x3E687C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x3E6880 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x3E6884 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x3E6888 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x3E688C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x3E6890 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x3E6894 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x3E6898 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x3E689C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3E68A0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3E68A4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3E68A8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3E68AC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3E68B0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3E68B4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3E68B8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3E68BC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3E68C0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3E68C4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3E68C8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3E68CC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3E68D0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3E68D4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3E68D8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3E68DC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3E68E0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3E68E4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3E68E8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3E68EC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3E68F0 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3E68F4 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3E68F8 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3E68FC + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x3E6900 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x3E6904 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x3E6908 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x3E690C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x3E6910 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x3E6914 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x3E6918 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x3E691C + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x3E6920 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x3E6924 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x3E6928 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x3E692C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x3E6930 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x3E6934 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x3E6938 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x3E693C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x3E6940 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x3E6944 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x3E6948 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x3E694C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x3E6950 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x3E6954 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x3E6958 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x3E695C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x3E6960 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x3E6964 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x3E6968 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x3E696C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x3E6970 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x3E6974 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x3E6978 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x3E697C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x3E6980 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x3E6984 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x3E6988 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x3E698C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x3E6990 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x3E6994 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x3E6998 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x3E699C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3E69A0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3E69A4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3E69A8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3E69AC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3E69B0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3E69B4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3E69B8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3E69BC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3E69C0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3E69C4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3E69C8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3E69CC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3E69D0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3E69D4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3E69D8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3E69DC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3E69E0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3E69E4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3E69E8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3E69EC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3E69F0 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3E69F4 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3E69F8 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3E69FC + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x3E6A00 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x3E6A04 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x3E6A08 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x3E6A0C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x3E6A10 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x3E6A14 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x3E6A18 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x3E6A1C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x3E6A20 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x3E6A64 + +#define mmNIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x3E6A68 + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x3E6A6C + +#define mmNIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x3E6A70 + +#define mmNIF_RTR_CTRL_6_RGL_CFG 0x3E6B64 + +#define mmNIF_RTR_CTRL_6_RGL_SHIFT 0x3E6B68 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x3E6B6C + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x3E6B70 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x3E6B74 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x3E6B78 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x3E6B7C + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x3E6B80 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x3E6B84 + +#define mmNIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x3E6B88 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_0 0x3E6BAC + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_1 0x3E6BB0 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_2 0x3E6BB4 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_3 0x3E6BB8 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_4 0x3E6BBC + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_5 0x3E6BC0 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_6 0x3E6BC4 + +#define mmNIF_RTR_CTRL_6_RGL_TOKEN_7 0x3E6BC8 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_0 0x3E6BEC + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_1 0x3E6BF0 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_2 0x3E6BF4 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_3 0x3E6BF8 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_4 0x3E6BFC + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_5 0x3E6C00 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_6 0x3E6C04 + +#define mmNIF_RTR_CTRL_6_RGL_BANK_ID_7 0x3E6C08 + +#define mmNIF_RTR_CTRL_6_RGL_WDT 0x3E6C2C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x3E6C30 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x3E6C34 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x3E6C38 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x3E6C3C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x3E6C40 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x3E6C44 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x3E6C48 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x3E6C4C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x3E6C50 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x3E6C54 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x3E6C58 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x3E6C5C + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x3E6C60 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x3E6C64 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x3E6C68 + +#define mmNIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x3E6C6C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x3E6C70 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x3E6C74 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x3E6C78 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x3E6C7C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x3E6C80 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x3E6C84 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x3E6C88 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x3E6C8C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x3E6C90 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x3E6C94 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x3E6C98 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x3E6C9C + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x3E6CA0 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x3E6CA4 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x3E6CA8 + +#define mmNIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x3E6CAC + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x3E6CB0 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x3E6CB4 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x3E6CB8 + +#define mmNIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x3E6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_6_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h new file mode 100644 index 000000000000..3a6a34ba2958 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/nif_rtr_ctrl_7_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ +#define ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ + +/* + ***************************************** + * NIF_RTR_CTRL_7 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmNIF_RTR_CTRL_7_PERM_SEL 0x3F6108 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_0 0x3F6114 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_1 0x3F6118 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_2 0x3F611C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_3 0x3F6120 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_4 0x3F6124 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_5 0x3F6128 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_6 0x3F612C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_7 0x3F6130 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_8 0x3F6134 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_9 0x3F6138 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_10 0x3F613C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_11 0x3F6140 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_12 0x3F6144 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_13 0x3F6148 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_14 0x3F614C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_15 0x3F6150 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_16 0x3F6154 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_17 0x3F6158 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_18 0x3F615C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_19 0x3F6160 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_20 0x3F6164 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_21 0x3F6168 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_22 0x3F616C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_23 0x3F6170 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_24 0x3F6174 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_25 0x3F6178 + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_26 0x3F617C + +#define mmNIF_RTR_CTRL_7_HBM_POLY_H3_27 0x3F6180 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x3F6184 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x3F6188 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x3F618C + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x3F6190 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x3F6194 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x3F6198 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x3F619C + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3F61A0 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3F61A4 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3F61A8 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3F61AC + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3F61B0 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3F61B4 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3F61B8 + +#define mmNIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3F61BC + +#define mmNIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x3F626C + +#define mmNIF_RTR_CTRL_7_RL_HBM_EN 0x3F6274 + +#define mmNIF_RTR_CTRL_7_RL_HBM_SAT 0x3F6278 + +#define mmNIF_RTR_CTRL_7_RL_HBM_RST 0x3F627C + +#define mmNIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x3F6280 + +#define mmNIF_RTR_CTRL_7_SCRAM_HBM_EN 0x3F6284 + +#define mmNIF_RTR_CTRL_7_RL_PCI_EN 0x3F6288 + +#define mmNIF_RTR_CTRL_7_RL_PCI_SAT 0x3F628C + +#define mmNIF_RTR_CTRL_7_RL_PCI_RST 0x3F6290 + +#define mmNIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x3F6294 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_EN 0x3F629C + +#define mmNIF_RTR_CTRL_7_RL_SRAM_SAT 0x3F62A0 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_RST 0x3F62A4 + +#define mmNIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3F62AC + +#define mmNIF_RTR_CTRL_7_RL_SRAM_RED 0x3F62B4 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_EN 0x3F62EC + +#define mmNIF_RTR_CTRL_7_E2E_PCI_EN 0x3F62F0 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3F62F4 + +#define mmNIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3F62F8 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x3F6404 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x3F6408 + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x3F640C + +#define mmNIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x3F6410 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x3F6414 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x3F6418 + +#define mmNIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x3F641C + +#define mmNIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x3F6420 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x3F6424 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x3F6428 + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x3F642C + +#define mmNIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x3F6430 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x3F6434 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x3F6438 + +#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_0 0x3F6450 + +#define mmNIF_RTR_CTRL_7_NL_HBM_SEL_1 0x3F6454 + +#define mmNIF_RTR_CTRL_7_NON_LIN_EN 0x3F6480 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x3F6500 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x3F6504 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x3F6508 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x3F650C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x3F6510 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x3F6514 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x3F6520 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x3F6524 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x3F6528 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x3F652C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x3F6530 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x3F6534 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x3F6538 + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x3F653C + +#define mmNIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x3F6540 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x3F6550 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x3F6554 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x3F6558 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x3F655C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x3F6560 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x3F6564 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x3F6568 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x3F656C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x3F6570 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x3F6574 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x3F6578 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x3F657C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x3F6580 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x3F6584 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x3F6588 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x3F658C + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x3F6590 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x3F6594 + +#define mmNIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x3F6598 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3F65E4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3F65E8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3F65EC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3F65F0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3F65F4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3F65F8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3F65FC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x3F6600 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x3F6604 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x3F6608 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x3F660C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x3F6610 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x3F6614 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x3F6618 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x3F661C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x3F6620 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x3F6624 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x3F6628 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x3F662C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x3F6630 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x3F6634 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x3F6638 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x3F663C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x3F6640 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x3F6644 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x3F6648 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x3F664C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x3F6650 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x3F6654 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x3F6658 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x3F665C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x3F6660 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x3F6664 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x3F6668 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x3F666C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x3F6670 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x3F6674 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x3F6678 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x3F667C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x3F6680 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x3F6684 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x3F6688 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x3F668C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x3F6690 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x3F6694 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x3F6698 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x3F669C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3F66A0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3F66A4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3F66A8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3F66AC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3F66B0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3F66B4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3F66B8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3F66BC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3F66C0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3F66C4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3F66C8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3F66CC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3F66D0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3F66D4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3F66D8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3F66DC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3F66E0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3F66E4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3F66E8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3F66EC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3F66F0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3F66F4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3F66F8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3F66FC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x3F6700 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x3F6704 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x3F6708 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x3F670C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x3F6710 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x3F6714 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x3F6718 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x3F671C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x3F6720 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x3F6724 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x3F6728 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x3F672C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x3F6730 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x3F6734 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x3F6738 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x3F673C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x3F6740 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x3F6744 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x3F6748 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x3F674C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x3F6750 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x3F6754 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x3F6758 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x3F675C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x3F6760 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x3F6764 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x3F6768 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x3F676C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x3F6770 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x3F6774 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x3F6778 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x3F677C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x3F6780 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x3F6784 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x3F6788 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x3F678C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x3F6790 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x3F6794 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x3F6798 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x3F679C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3F67A0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3F67A4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3F67A8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3F67AC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3F67B0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3F67B4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3F67B8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3F67BC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3F67C0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3F67C4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3F67C8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3F67CC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3F67D0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3F67D4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3F67D8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3F67DC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3F67E0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x3F6824 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x3F6828 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x3F682C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x3F6830 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x3F6834 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x3F6838 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x3F683C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x3F6840 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x3F6844 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x3F6848 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x3F684C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x3F6850 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x3F6854 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x3F6858 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x3F685C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x3F6860 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x3F6864 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x3F6868 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x3F686C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x3F6870 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x3F6874 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x3F6878 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x3F687C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x3F6880 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x3F6884 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x3F6888 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x3F688C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x3F6890 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x3F6894 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x3F6898 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x3F689C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3F68A0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3F68A4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3F68A8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3F68AC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3F68B0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3F68B4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3F68B8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3F68BC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3F68C0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3F68C4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3F68C8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3F68CC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3F68D0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3F68D4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3F68D8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3F68DC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3F68E0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3F68E4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3F68E8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3F68EC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3F68F0 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3F68F4 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3F68F8 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3F68FC + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x3F6900 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x3F6904 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x3F6908 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x3F690C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x3F6910 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x3F6914 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x3F6918 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x3F691C + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x3F6920 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x3F6924 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x3F6928 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x3F692C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x3F6930 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x3F6934 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x3F6938 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x3F693C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x3F6940 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x3F6944 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x3F6948 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x3F694C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x3F6950 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x3F6954 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x3F6958 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x3F695C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x3F6960 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x3F6964 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x3F6968 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x3F696C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x3F6970 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x3F6974 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x3F6978 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x3F697C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x3F6980 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x3F6984 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x3F6988 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x3F698C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x3F6990 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x3F6994 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x3F6998 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x3F699C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3F69A0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3F69A4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3F69A8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3F69AC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3F69B0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3F69B4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3F69B8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3F69BC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3F69C0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3F69C4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3F69C8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3F69CC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3F69D0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3F69D4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3F69D8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3F69DC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3F69E0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3F69E4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3F69E8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3F69EC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3F69F0 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3F69F4 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3F69F8 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3F69FC + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x3F6A00 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x3F6A04 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x3F6A08 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x3F6A0C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x3F6A10 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x3F6A14 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x3F6A18 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x3F6A1C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x3F6A20 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x3F6A64 + +#define mmNIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x3F6A68 + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x3F6A6C + +#define mmNIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x3F6A70 + +#define mmNIF_RTR_CTRL_7_RGL_CFG 0x3F6B64 + +#define mmNIF_RTR_CTRL_7_RGL_SHIFT 0x3F6B68 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x3F6B6C + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x3F6B70 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x3F6B74 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x3F6B78 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x3F6B7C + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x3F6B80 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x3F6B84 + +#define mmNIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x3F6B88 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_0 0x3F6BAC + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_1 0x3F6BB0 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_2 0x3F6BB4 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_3 0x3F6BB8 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_4 0x3F6BBC + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_5 0x3F6BC0 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_6 0x3F6BC4 + +#define mmNIF_RTR_CTRL_7_RGL_TOKEN_7 0x3F6BC8 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_0 0x3F6BEC + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_1 0x3F6BF0 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_2 0x3F6BF4 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_3 0x3F6BF8 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_4 0x3F6BFC + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_5 0x3F6C00 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_6 0x3F6C04 + +#define mmNIF_RTR_CTRL_7_RGL_BANK_ID_7 0x3F6C08 + +#define mmNIF_RTR_CTRL_7_RGL_WDT 0x3F6C2C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x3F6C30 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x3F6C34 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x3F6C38 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x3F6C3C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x3F6C40 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x3F6C44 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x3F6C48 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x3F6C4C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x3F6C50 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x3F6C54 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x3F6C58 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x3F6C5C + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x3F6C60 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x3F6C64 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x3F6C68 + +#define mmNIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x3F6C6C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x3F6C70 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x3F6C74 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x3F6C78 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x3F6C7C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x3F6C80 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x3F6C84 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x3F6C88 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x3F6C8C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x3F6C90 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x3F6C94 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x3F6C98 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x3F6C9C + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x3F6CA0 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x3F6CA4 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x3F6CA8 + +#define mmNIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x3F6CAC + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x3F6CB0 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x3F6CB4 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x3F6CB8 + +#define mmNIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x3F6CBC + +#endif /* ASIC_REG_NIF_RTR_CTRL_7_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h new file mode 100644 index 000000000000..b7c33e025db5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_etr_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_ETR_REGS_H_ +#define ASIC_REG_PSOC_ETR_REGS_H_ + +/* + ***************************************** + * PSOC_ETR (Prototype: ETR) + ***************************************** + */ + +#define mmPSOC_ETR_RSZ 0x2C43004 + +#define mmPSOC_ETR_STS 0x2C4300C + +#define mmPSOC_ETR_RRD 0x2C43010 + +#define mmPSOC_ETR_RRP 0x2C43014 + +#define mmPSOC_ETR_RWP 0x2C43018 + +#define mmPSOC_ETR_TRG 0x2C4301C + +#define mmPSOC_ETR_CTL 0x2C43020 + +#define mmPSOC_ETR_RWD 0x2C43024 + +#define mmPSOC_ETR_MODE 0x2C43028 + +#define mmPSOC_ETR_LBUFLEVEL 0x2C4302C + +#define mmPSOC_ETR_CBUFLEVEL 0x2C43030 + +#define mmPSOC_ETR_BUFWM 0x2C43034 + +#define mmPSOC_ETR_RRPHI 0x2C43038 + +#define mmPSOC_ETR_RWPHI 0x2C4303C + +#define mmPSOC_ETR_AXICTL 0x2C43110 + +#define mmPSOC_ETR_DBALO 0x2C43118 + +#define mmPSOC_ETR_DBAHI 0x2C4311C + +#define mmPSOC_ETR_FFSR 0x2C43300 + +#define mmPSOC_ETR_FFCR 0x2C43304 + +#define mmPSOC_ETR_PSCR 0x2C43308 + +#define mmPSOC_ETR_ITMISCOP0 0x2C43EE0 + +#define mmPSOC_ETR_ITTRFLIN 0x2C43EE8 + +#define mmPSOC_ETR_ITATBDATA0 0x2C43EEC + +#define mmPSOC_ETR_ITATBCTR2 0x2C43EF0 + +#define mmPSOC_ETR_ITATBCTR1 0x2C43EF4 + +#define mmPSOC_ETR_ITATBCTR0 0x2C43EF8 + +#define mmPSOC_ETR_ITCTRL 0x2C43F00 + +#define mmPSOC_ETR_CLAIMSET 0x2C43FA0 + +#define mmPSOC_ETR_CLAIMCLR 0x2C43FA4 + +#define mmPSOC_ETR_LAR 0x2C43FB0 + +#define mmPSOC_ETR_LSR 0x2C43FB4 + +#define mmPSOC_ETR_AUTHSTATUS 0x2C43FB8 + +#define mmPSOC_ETR_DEVID 0x2C43FC8 + +#define mmPSOC_ETR_DEVTYPE 0x2C43FCC + +#define mmPSOC_ETR_PERIPHID4 0x2C43FD0 + +#define mmPSOC_ETR_PERIPHID5 0x2C43FD4 + +#define mmPSOC_ETR_PERIPHID6 0x2C43FD8 + +#define mmPSOC_ETR_PERIPHID7 0x2C43FDC + +#define mmPSOC_ETR_PERIPHID0 0x2C43FE0 + +#define mmPSOC_ETR_PERIPHID1 0x2C43FE4 + +#define mmPSOC_ETR_PERIPHID2 0x2C43FE8 + +#define mmPSOC_ETR_PERIPHID3 0x2C43FEC + +#define mmPSOC_ETR_COMPID0 0x2C43FF0 + +#define mmPSOC_ETR_COMPID1 0x2C43FF4 + +#define mmPSOC_ETR_COMPID2 0x2C43FF8 + +#define mmPSOC_ETR_COMPID3 0x2C43FFC + +#endif /* ASIC_REG_PSOC_ETR_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h new file mode 100644 index 000000000000..6703e678ee9f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_masks.h @@ -0,0 +1,502 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +/* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PCI_FW_FSM */ +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BTM_FSM */ +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BTM_FSM */ +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPI_MEM_EN */ +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN */ +#define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_EN */ +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */ +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SPI_IMG_STS */ +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3 +#define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PHY_STABLE */ +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_OVR */ +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4 +#define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_ETR_FLUSH */ +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */ +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */ +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */ +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RAZWI */ +#define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK 0x1 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_PROT */ +#define PSOC_GLOBAL_CONF_PROT_AR_SHIFT 0 +#define PSOC_GLOBAL_CONF_PROT_AR_MASK 0x7 +#define PSOC_GLOBAL_CONF_PROT_AW_SHIFT 4 +#define PSOC_GLOBAL_CONF_PROT_AW_MASK 0x70 + +/* PSOC_GLOBAL_CONF_ADC */ +#define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0x1 +#define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT 4 +#define PSOC_GLOBAL_CONF_ADC_MASK_MASK 0x10 + +/* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */ +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SCRATCHPAD */ +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SEMAPHORE */ +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 +#define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */ +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0 +#define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */ +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SPL_SOURCE */ +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 + +/* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 +#define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 + +/* PSOC_GLOBAL_CONF_I2C_SLV */ +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0 +#define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TRACE_ADDR */ +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0x3FF + +/* PSOC_GLOBAL_CONF_ARUSER */ +#define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_AWUSER */ +#define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_AWUSER */ +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_TRACE_ARUSER */ +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_BTL_STS */ +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 +#define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 + +/* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9 +#define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200 + +/* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 +#define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 + +/* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_TARGETID */ +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 +#define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16 +#define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 +#define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 + +/* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */ +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0x1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 1 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT 2 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK 0xC +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 4 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x10 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 5 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x20 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 6 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x40 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 7 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x80 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT 8 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK 0x1FFF00 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT 22 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK 0x400000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT 23 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK 0x800000 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT 24 +#define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK 0x1F000000 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4 +#define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10 + +/* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 +#define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 + +/* PSOC_GLOBAL_CONF_MASK_REQ */ +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_WD_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_MNL_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_SW_ALL_RST */ +#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SOFT_RST */ +#define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_L */ +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_SOFT_RST_CFG_H */ +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_UNIT_RST_N */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_UNIT_RST_N_L */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_UNIT_RST_N_H */ +#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK 0x3FFFFF + +/* PSOC_GLOBAL_CONF_BTL_IMG */ +#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PRSTN_MASK */ +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_WD_MASK */ +#define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 +#define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 + +/* PSOC_GLOBAL_CONF_RST_SRC */ +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_BOOT_STATE */ +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F + +/* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */ +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7 + +/* PSOC_GLOBAL_CONF_BNK3V3_MS */ +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */ +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */ +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES */ +#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK 0x1F + +/* PSOC_GLOBAL_CONF_ADC_TPH_CS */ +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */ +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */ +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */ +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1 + +/* PSOC_GLOBAL_CONF_ADC_CFG_DATA */ +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF + +/* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */ +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */ +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF + +/* PSOC_GLOBAL_CONF_PAD_DEFAULT */ +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF + +/* PSOC_GLOBAL_CONF_PAD_SEL */ +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 +#define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 + +/* PSOC_GLOBAL_CONF_RST_CTRL */ +#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT 0 +#define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK 0xFF + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h new file mode 100644 index 000000000000..1b5cfcc1d85f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_global_conf_regs.h @@ -0,0 +1,1062 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ +#define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ + +/* + ***************************************** + * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) + ***************************************** + */ + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0xC4B000 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0xC4B004 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0xC4B008 + +#define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0xC4B00C + +#define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0xC4B020 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0xC4B024 + +#define mmPSOC_GLOBAL_CONF_BTM_FSM 0xC4B028 + +#define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0xC4B030 + +#define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0xC4B034 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0xC4B038 + +#define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0xC4B040 + +#define mmPSOC_GLOBAL_CONF_PRSTN 0xC4B044 + +#define mmPSOC_GLOBAL_CONF_PCIE_EN 0xC4B048 + +#define mmPSOC_GLOBAL_CONF_PCIE_PRSTN_INTR 0xC4B04C + +#define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0xC4B050 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0xC4B054 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD 0xC4B058 + +#define mmPSOC_GLOBAL_CONF_PHY_STABLE 0xC4B060 + +#define mmPSOC_GLOBAL_CONF_PRSTN_OVR 0xC4B064 + +#define mmPSOC_GLOBAL_CONF_ETR_FLUSH 0xC4B068 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0 0xC4B070 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 0xC4B074 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2 0xC4B078 + +#define mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 0xC4B07C + +#define mmPSOC_GLOBAL_CONF_DIS_RAZWI_ERR 0xC4B080 + +#define mmPSOC_GLOBAL_CONF_PCIE_PHY_RST_N 0xC4B084 + +#define mmPSOC_GLOBAL_CONF_RAZWI 0xC4B088 + +#define mmPSOC_GLOBAL_CONF_PROT 0xC4B090 + +#define mmPSOC_GLOBAL_CONF_ADC 0xC4B094 + +#define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TO 0xC4B098 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0xC4B100 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0xC4B104 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0xC4B108 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0xC4B10C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0xC4B110 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0xC4B114 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0xC4B118 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0xC4B11C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0xC4B120 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0xC4B124 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0xC4B128 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0xC4B12C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0xC4B130 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0xC4B134 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0xC4B138 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0xC4B13C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0xC4B140 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0xC4B144 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0xC4B148 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0xC4B14C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0xC4B150 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0xC4B154 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0xC4B158 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0xC4B15C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0xC4B160 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0xC4B164 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0xC4B168 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0xC4B16C + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0xC4B170 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0xC4B174 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0xC4B178 + +#define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0xC4B17C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0xC4B200 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0xC4B204 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0xC4B208 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0xC4B20C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0xC4B210 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0xC4B214 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0xC4B218 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0xC4B21C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0xC4B220 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0xC4B224 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0xC4B228 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0xC4B22C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0xC4B230 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0xC4B234 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0xC4B238 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0xC4B23C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0xC4B240 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0xC4B244 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0xC4B248 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0xC4B24C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0xC4B250 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0xC4B254 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0xC4B258 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0xC4B25C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0xC4B260 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0xC4B264 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0xC4B268 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0xC4B26C + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0xC4B270 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0xC4B274 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0xC4B278 + +#define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0xC4B27C + +#define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS 0xC4B300 + +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU 0xC4B304 + +#define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0xC4B308 + +#define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0xC4B30C + +#define mmPSOC_GLOBAL_CONF_I2C_SLV 0xC4B310 + +#define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0xC4B314 + +#define mmPSOC_GLOBAL_CONF_TRACE_ADDR 0xC4B320 + +#define mmPSOC_GLOBAL_CONF_ARUSER 0xC4B330 + +#define mmPSOC_GLOBAL_CONF_AWUSER 0xC4B334 + +#define mmPSOC_GLOBAL_CONF_TRACE_AWUSER 0xC4B338 + +#define mmPSOC_GLOBAL_CONF_TRACE_ARUSER 0xC4B33C + +#define mmPSOC_GLOBAL_CONF_BTL_STS 0xC4B340 + +#define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0xC4B350 + +#define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0xC4B354 + +#define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0xC4B358 + +#define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0xC4B35C + +#define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0xC4B360 + +#define mmPSOC_GLOBAL_CONF_TARGETID 0xC4B400 + +#define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0xC4B420 + +#define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS 0xC4B430 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_DIV 0xC4B44C + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0xC4B450 + +#define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0xC4B454 + +#define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0xC4B458 + +#define mmPSOC_GLOBAL_CONF_MASK_REQ 0xC4B45C + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_L 0xC4B460 + +#define mmPSOC_GLOBAL_CONF_WD_RST_CFG_H 0xC4B464 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_L 0xC4B470 + +#define mmPSOC_GLOBAL_CONF_MNL_RST_CFG_H 0xC4B474 + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_L 0xC4B480 + +#define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG_H 0xC4B484 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L 0xC4B490 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H 0xC4B494 + +#define mmPSOC_GLOBAL_CONF_SW_ALL_RST 0xC4B498 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST 0xC4B4A0 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_L 0xC4B4A4 + +#define mmPSOC_GLOBAL_CONF_SOFT_RST_CFG_H 0xC4B4A8 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N 0xC4B4B0 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_L 0xC4B4B4 + +#define mmPSOC_GLOBAL_CONF_UNIT_RST_N_H 0xC4B4B8 + +#define mmPSOC_GLOBAL_CONF_BTL_IMG 0xC4B4E0 + +#define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0xC4B4E4 + +#define mmPSOC_GLOBAL_CONF_WD_MASK 0xC4B4E8 + +#define mmPSOC_GLOBAL_CONF_RST_SRC 0xC4B4F0 + +#define mmPSOC_GLOBAL_CONF_BOOT_STATE 0xC4B4F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0xC4B500 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0xC4B504 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0xC4B508 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0xC4B50C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0xC4B510 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0xC4B514 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0xC4B518 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0xC4B51C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0xC4B520 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0xC4B524 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0xC4B528 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0xC4B52C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0xC4B530 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0xC4B534 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0xC4B538 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0xC4B53C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0xC4B540 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0xC4B544 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0xC4B548 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0xC4B54C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0xC4B550 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0xC4B554 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0xC4B558 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0xC4B55C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0xC4B560 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0xC4B564 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0xC4B568 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0xC4B56C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0xC4B570 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0xC4B574 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0xC4B578 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0xC4B57C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0xC4B580 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0xC4B584 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0xC4B588 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0xC4B58C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0xC4B590 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0xC4B594 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0xC4B598 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0xC4B59C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0xC4B5A0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0xC4B5A4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0xC4B5A8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0xC4B5AC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0xC4B5B0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0xC4B5B4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0xC4B5B8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0xC4B5BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0xC4B5C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0xC4B5C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0xC4B5C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0xC4B5CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0xC4B5D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0xC4B5D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0xC4B5D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0xC4B5DC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0xC4B5E0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0xC4B5E4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0xC4B5E8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0xC4B5EC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0xC4B5F0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0xC4B5F4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0xC4B5F8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0xC4B5FC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0xC4B600 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0xC4B604 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0xC4B608 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0xC4B60C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0xC4B610 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_69 0xC4B614 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_70 0xC4B618 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_71 0xC4B61C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_72 0xC4B620 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_73 0xC4B624 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_74 0xC4B628 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_75 0xC4B62C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_76 0xC4B630 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_77 0xC4B634 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_78 0xC4B638 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_79 0xC4B63C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_80 0xC4B640 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_81 0xC4B644 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_82 0xC4B648 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_83 0xC4B64C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_84 0xC4B650 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_85 0xC4B654 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_86 0xC4B658 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_87 0xC4B65C + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_88 0xC4B660 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_89 0xC4B664 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0xC4B690 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0xC4B694 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0xC4B698 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0xC4B69C + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0xC4B6A0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0xC4B6A4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0xC4B6A8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0xC4B6AC + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0xC4B6B0 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0xC4B6B4 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0xC4B6B8 + +#define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0xC4B6BC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0 0xC4B6C0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1 0xC4B6C4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2 0xC4B6C8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3 0xC4B6CC + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4 0xC4B6D0 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5 0xC4B6D4 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_6 0xC4B6D8 + +#define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_7 0xC4B6DC + +#define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0xC4B710 + +#define mmPSOC_GLOBAL_CONF_ADC_CLK_FREQ 0xC4B720 + +#define mmPSOC_GLOBAL_CONF_ADC_DELAY_FROM_START 0xC4B724 + +#define mmPSOC_GLOBAL_CONF_ADC_DATA_SAMPLES 0xC4B728 + +#define mmPSOC_GLOBAL_CONF_ADC_TPH_CS 0xC4B72C + +#define mmPSOC_GLOBAL_CONF_ADC_LSB_NMSB 0xC4B730 + +#define mmPSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES 0xC4B734 + +#define mmPSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE 0xC4B738 + +#define mmPSOC_GLOBAL_CONF_ADC_CFG_DATA 0xC4B73C + +#define mmPSOC_GLOBAL_CONF_ADC_TDV_CSDO 0xC4B740 + +#define mmPSOC_GLOBAL_CONF_ADC_TSU_CSCK 0xC4B744 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0xC4B800 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0xC4B804 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0xC4B808 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0xC4B80C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0xC4B810 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0xC4B814 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0xC4B818 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0xC4B81C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0xC4B820 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0xC4B824 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0xC4B828 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0xC4B82C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0xC4B830 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0xC4B834 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0xC4B838 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0xC4B83C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0xC4B840 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0xC4B844 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0xC4B848 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0xC4B84C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0xC4B850 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0xC4B854 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0xC4B858 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0xC4B85C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0xC4B860 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0xC4B864 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0xC4B868 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0xC4B86C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0xC4B870 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0xC4B874 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0xC4B878 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0xC4B87C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0xC4B880 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0xC4B884 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0xC4B888 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0xC4B88C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0xC4B890 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0xC4B894 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0xC4B898 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0xC4B89C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0xC4B8A0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0xC4B8A4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0xC4B8A8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0xC4B8AC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0xC4B8B0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0xC4B8B4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0xC4B8B8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0xC4B8BC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0xC4B8C0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0xC4B8C4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0xC4B8C8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0xC4B8CC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0xC4B8D0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0xC4B8D4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0xC4B8D8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0xC4B8DC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0xC4B8E0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0xC4B8E4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0xC4B8E8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0xC4B8EC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0xC4B8F0 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0xC4B8F4 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0xC4B8F8 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0xC4B8FC + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0xC4B900 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0xC4B904 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0xC4B908 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0xC4B90C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0xC4B910 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0xC4B914 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0xC4B918 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0xC4B91C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0xC4B920 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0xC4B924 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0xC4B928 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0xC4B92C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0xC4B930 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0xC4B934 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0xC4B938 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0xC4B93C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0xC4B940 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0xC4B944 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_82 0xC4B948 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_83 0xC4B94C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_84 0xC4B950 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_85 0xC4B954 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_86 0xC4B958 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_87 0xC4B95C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_88 0xC4B960 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_89 0xC4B964 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_90 0xC4B968 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_91 0xC4B96C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_92 0xC4B970 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_93 0xC4B974 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_94 0xC4B978 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_95 0xC4B97C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_96 0xC4B980 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_97 0xC4B984 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_98 0xC4B988 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_99 0xC4B98C + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_100 0xC4B990 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_101 0xC4B994 + +#define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_102 0xC4B998 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0xC4BA00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0xC4BA04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0xC4BA08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0xC4BA0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0xC4BA10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0xC4BA14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0xC4BA18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0xC4BA1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0xC4BA20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0xC4BA24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0xC4BA28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0xC4BA2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0xC4BA30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0xC4BA34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0xC4BA38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0xC4BA3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0xC4BA40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0xC4BA44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0xC4BA48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0xC4BA4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0xC4BA50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0xC4BA54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0xC4BA58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0xC4BA5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0xC4BA60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0xC4BA64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0xC4BA68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0xC4BA6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0xC4BA70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0xC4BA74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0xC4BA78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0xC4BA7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0xC4BA80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0xC4BA84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0xC4BA88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0xC4BA8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0xC4BA90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0xC4BA94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0xC4BA98 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0xC4BA9C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0xC4BAA0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0xC4BAA4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0xC4BAA8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0xC4BAAC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0xC4BAB0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0xC4BAB4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0xC4BAB8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0xC4BABC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0xC4BAC0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0xC4BAC4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0xC4BAC8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0xC4BACC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0xC4BAD0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0xC4BAD4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0xC4BAD8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0xC4BADC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0xC4BAE0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0xC4BAE4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0xC4BAE8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0xC4BAEC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0xC4BAF0 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0xC4BAF4 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0xC4BAF8 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0xC4BAFC + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0xC4BB00 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0xC4BB04 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0xC4BB08 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0xC4BB0C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0xC4BB10 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0xC4BB14 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0xC4BB18 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0xC4BB1C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0xC4BB20 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0xC4BB24 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0xC4BB28 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0xC4BB2C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0xC4BB30 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0xC4BB34 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0xC4BB38 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0xC4BB3C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0xC4BB40 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0xC4BB44 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_82 0xC4BB48 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_83 0xC4BB4C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_84 0xC4BB50 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_85 0xC4BB54 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_86 0xC4BB58 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_87 0xC4BB5C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_88 0xC4BB60 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_89 0xC4BB64 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_90 0xC4BB68 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_91 0xC4BB6C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_92 0xC4BB70 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_93 0xC4BB74 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_94 0xC4BB78 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_95 0xC4BB7C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_96 0xC4BB80 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_97 0xC4BB84 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_98 0xC4BB88 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_99 0xC4BB8C + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_100 0xC4BB90 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_101 0xC4BB94 + +#define mmPSOC_GLOBAL_CONF_PAD_SEL_102 0xC4BB98 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_0 0xC4BC00 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_1 0xC4BC04 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_2 0xC4BC08 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_3 0xC4BC0C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_4 0xC4BC10 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_5 0xC4BC14 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_6 0xC4BC18 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_7 0xC4BC1C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_8 0xC4BC20 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_9 0xC4BC24 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_10 0xC4BC28 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_11 0xC4BC2C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_12 0xC4BC30 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_13 0xC4BC34 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_14 0xC4BC38 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_15 0xC4BC3C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_16 0xC4BC40 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_17 0xC4BC44 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_18 0xC4BC48 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_19 0xC4BC4C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_20 0xC4BC50 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_21 0xC4BC54 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_22 0xC4BC58 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_23 0xC4BC5C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_24 0xC4BC60 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_25 0xC4BC64 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_26 0xC4BC68 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_27 0xC4BC6C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_28 0xC4BC70 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_29 0xC4BC74 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_30 0xC4BC78 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_31 0xC4BC7C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_32 0xC4BC80 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_33 0xC4BC84 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_34 0xC4BC88 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_35 0xC4BC8C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_36 0xC4BC90 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_37 0xC4BC94 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_38 0xC4BC98 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_39 0xC4BC9C + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_40 0xC4BCA0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_41 0xC4BCA4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_42 0xC4BCA8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_43 0xC4BCAC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_44 0xC4BCB0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_45 0xC4BCB4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_46 0xC4BCB8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_47 0xC4BCBC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_48 0xC4BCC0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_49 0xC4BCC4 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_50 0xC4BCC8 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_51 0xC4BCCC + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_52 0xC4BCD0 + +#define mmPSOC_GLOBAL_CONF_RST_CTRL_53 0xC4BCD4 + +#endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_hbm_pll_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_hbm_pll_regs.h new file mode 100644 index 000000000000..687e2255cb19 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_hbm_pll_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_HBM_PLL_REGS_H_ +#define ASIC_REG_PSOC_HBM_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_HBM_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_HBM_PLL_NR 0xC74100 + +#define mmPSOC_HBM_PLL_NF 0xC74104 + +#define mmPSOC_HBM_PLL_OD 0xC74108 + +#define mmPSOC_HBM_PLL_NB 0xC7410C + +#define mmPSOC_HBM_PLL_CFG 0xC74110 + +#define mmPSOC_HBM_PLL_LOSE_MASK 0xC74120 + +#define mmPSOC_HBM_PLL_LOCK_INTR 0xC74128 + +#define mmPSOC_HBM_PLL_LOCK_BYPASS 0xC7412C + +#define mmPSOC_HBM_PLL_DATA_CHNG 0xC74130 + +#define mmPSOC_HBM_PLL_RST 0xC74134 + +#define mmPSOC_HBM_PLL_SLIP_WD_CNTR 0xC74150 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_0 0xC74200 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_1 0xC74204 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_2 0xC74208 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_3 0xC7420C + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_0 0xC74220 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_1 0xC74224 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_2 0xC74228 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_CMD_3 0xC7422C + +#define mmPSOC_HBM_PLL_DIV_SEL_0 0xC74280 + +#define mmPSOC_HBM_PLL_DIV_SEL_1 0xC74284 + +#define mmPSOC_HBM_PLL_DIV_SEL_2 0xC74288 + +#define mmPSOC_HBM_PLL_DIV_SEL_3 0xC7428C + +#define mmPSOC_HBM_PLL_DIV_EN_0 0xC742A0 + +#define mmPSOC_HBM_PLL_DIV_EN_1 0xC742A4 + +#define mmPSOC_HBM_PLL_DIV_EN_2 0xC742A8 + +#define mmPSOC_HBM_PLL_DIV_EN_3 0xC742AC + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_0 0xC742C0 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_1 0xC742C4 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_2 0xC742C8 + +#define mmPSOC_HBM_PLL_DIV_FACTOR_BUSY_3 0xC742CC + +#define mmPSOC_HBM_PLL_CLK_GATER 0xC74300 + +#define mmPSOC_HBM_PLL_CLK_RLX_0 0xC74310 + +#define mmPSOC_HBM_PLL_CLK_RLX_1 0xC74314 + +#define mmPSOC_HBM_PLL_CLK_RLX_2 0xC74318 + +#define mmPSOC_HBM_PLL_CLK_RLX_3 0xC7431C + +#define mmPSOC_HBM_PLL_REF_CNTR_PERIOD 0xC74400 + +#define mmPSOC_HBM_PLL_REF_LOW_THRESHOLD 0xC74410 + +#define mmPSOC_HBM_PLL_REF_HIGH_THRESHOLD 0xC74420 + +#define mmPSOC_HBM_PLL_PLL_NOT_STABLE 0xC74430 + +#define mmPSOC_HBM_PLL_FREQ_CALC_EN 0xC74440 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_CFG 0xC74500 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_0 0xC74510 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_1 0xC74514 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_2 0xC74518 + +#define mmPSOC_HBM_PLL_RLX_BITMAP_3 0xC7451C + +#endif /* ASIC_REG_PSOC_HBM_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_pci_pll_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_pci_pll_regs.h new file mode 100644 index 000000000000..3dc9bb4542dd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_pci_pll_regs.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_PCI_PLL_REGS_H_ +#define ASIC_REG_PSOC_PCI_PLL_REGS_H_ + +/* + ***************************************** + * PSOC_PCI_PLL (Prototype: PLL) + ***************************************** + */ + +#define mmPSOC_PCI_PLL_NR 0xC72100 + +#define mmPSOC_PCI_PLL_NF 0xC72104 + +#define mmPSOC_PCI_PLL_OD 0xC72108 + +#define mmPSOC_PCI_PLL_NB 0xC7210C + +#define mmPSOC_PCI_PLL_CFG 0xC72110 + +#define mmPSOC_PCI_PLL_LOSE_MASK 0xC72120 + +#define mmPSOC_PCI_PLL_LOCK_INTR 0xC72128 + +#define mmPSOC_PCI_PLL_LOCK_BYPASS 0xC7212C + +#define mmPSOC_PCI_PLL_DATA_CHNG 0xC72130 + +#define mmPSOC_PCI_PLL_RST 0xC72134 + +#define mmPSOC_PCI_PLL_SLIP_WD_CNTR 0xC72150 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_0 0xC72200 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_1 0xC72204 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_2 0xC72208 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_3 0xC7220C + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_0 0xC72220 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_1 0xC72224 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_2 0xC72228 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_CMD_3 0xC7222C + +#define mmPSOC_PCI_PLL_DIV_SEL_0 0xC72280 + +#define mmPSOC_PCI_PLL_DIV_SEL_1 0xC72284 + +#define mmPSOC_PCI_PLL_DIV_SEL_2 0xC72288 + +#define mmPSOC_PCI_PLL_DIV_SEL_3 0xC7228C + +#define mmPSOC_PCI_PLL_DIV_EN_0 0xC722A0 + +#define mmPSOC_PCI_PLL_DIV_EN_1 0xC722A4 + +#define mmPSOC_PCI_PLL_DIV_EN_2 0xC722A8 + +#define mmPSOC_PCI_PLL_DIV_EN_3 0xC722AC + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_0 0xC722C0 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_1 0xC722C4 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_2 0xC722C8 + +#define mmPSOC_PCI_PLL_DIV_FACTOR_BUSY_3 0xC722CC + +#define mmPSOC_PCI_PLL_CLK_GATER 0xC72300 + +#define mmPSOC_PCI_PLL_CLK_RLX_0 0xC72310 + +#define mmPSOC_PCI_PLL_CLK_RLX_1 0xC72314 + +#define mmPSOC_PCI_PLL_CLK_RLX_2 0xC72318 + +#define mmPSOC_PCI_PLL_CLK_RLX_3 0xC7231C + +#define mmPSOC_PCI_PLL_REF_CNTR_PERIOD 0xC72400 + +#define mmPSOC_PCI_PLL_REF_LOW_THRESHOLD 0xC72410 + +#define mmPSOC_PCI_PLL_REF_HIGH_THRESHOLD 0xC72420 + +#define mmPSOC_PCI_PLL_PLL_NOT_STABLE 0xC72430 + +#define mmPSOC_PCI_PLL_FREQ_CALC_EN 0xC72440 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_CFG 0xC72500 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_0 0xC72510 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_1 0xC72514 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_2 0xC72518 + +#define mmPSOC_PCI_PLL_RLX_BITMAP_3 0xC7251C + +#endif /* ASIC_REG_PSOC_PCI_PLL_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000000..9ce24597d4b0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0xC49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0xC49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0xC49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0xC4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0xC49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0xC49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0xC49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0xC49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0xC49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0xC49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0xC49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0xC49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0xC49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0xC49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0xC49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0xC49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0xC49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h new file mode 100644 index 000000000000..ddf824392cf7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_0_PERM_SEL 0x306108 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_0 0x306114 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_1 0x306118 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_2 0x30611C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_3 0x306120 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_4 0x306124 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_5 0x306128 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_6 0x30612C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_7 0x306130 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_8 0x306134 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_9 0x306138 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_10 0x30613C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_11 0x306140 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_12 0x306144 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_13 0x306148 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_14 0x30614C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_15 0x306150 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_16 0x306154 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_17 0x306158 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_18 0x30615C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_19 0x306160 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_20 0x306164 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_21 0x306168 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_22 0x30616C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_23 0x306170 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_24 0x306174 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_25 0x306178 + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_26 0x30617C + +#define mmSIF_RTR_CTRL_0_HBM_POLY_H3_27 0x306180 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x306184 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x306188 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x30618C + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x306190 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x306194 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x306198 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x30619C + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3061A0 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3061A4 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3061A8 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3061AC + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3061B0 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3061B4 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3061B8 + +#define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3061BC + +#define mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x30626C + +#define mmSIF_RTR_CTRL_0_RL_HBM_EN 0x306274 + +#define mmSIF_RTR_CTRL_0_RL_HBM_SAT 0x306278 + +#define mmSIF_RTR_CTRL_0_RL_HBM_RST 0x30627C + +#define mmSIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x306280 + +#define mmSIF_RTR_CTRL_0_SCRAM_HBM_EN 0x306284 + +#define mmSIF_RTR_CTRL_0_RL_PCI_EN 0x306288 + +#define mmSIF_RTR_CTRL_0_RL_PCI_SAT 0x30628C + +#define mmSIF_RTR_CTRL_0_RL_PCI_RST 0x306290 + +#define mmSIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x306294 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_EN 0x30629C + +#define mmSIF_RTR_CTRL_0_RL_SRAM_SAT 0x3062A0 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_RST 0x3062A4 + +#define mmSIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3062AC + +#define mmSIF_RTR_CTRL_0_RL_SRAM_RED 0x3062B4 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_EN 0x3062EC + +#define mmSIF_RTR_CTRL_0_E2E_PCI_EN 0x3062F0 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3062F4 + +#define mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3062F8 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x306404 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x306408 + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x30640C + +#define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x306410 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x306414 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x306418 + +#define mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x30641C + +#define mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x306420 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x306424 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x306428 + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x30642C + +#define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x306430 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x306434 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x306438 + +#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_0 0x306450 + +#define mmSIF_RTR_CTRL_0_NL_HBM_SEL_1 0x306454 + +#define mmSIF_RTR_CTRL_0_NON_LIN_EN 0x306480 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x306500 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x306504 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x306508 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x30650C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x306510 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x306514 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x306520 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x306524 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x306528 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x30652C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x306530 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x306534 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x306538 + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x30653C + +#define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x306540 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x306550 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x306554 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x306558 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x30655C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x306560 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x306564 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x306568 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x30656C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x306570 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x306574 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x306578 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x30657C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x306580 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x306584 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x306588 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x30658C + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x306590 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x306594 + +#define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x306598 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3065E4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3065E8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3065EC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3065F0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3065F4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3065F8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3065FC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x306600 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x306604 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x306608 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x30660C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x306610 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x306614 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x306618 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x30661C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x306620 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x306624 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x306628 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x30662C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x306630 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x306634 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x306638 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x30663C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x306640 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x306644 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x306648 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x30664C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x306650 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x306654 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x306658 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x30665C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x306660 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x306664 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x306668 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x30666C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x306670 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x306674 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x306678 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x30667C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x306680 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x306684 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x306688 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x30668C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x306690 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x306694 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x306698 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x30669C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3066A0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3066A4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3066A8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3066AC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3066B0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3066B4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3066B8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3066BC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3066C0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3066C4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3066C8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3066CC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3066D0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3066D4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3066D8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3066DC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3066E0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3066E4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3066E8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3066EC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3066F0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3066F4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3066F8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3066FC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x306700 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x306704 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x306708 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x30670C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x306710 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x306714 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x306718 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x30671C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x306720 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x306724 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x306728 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x30672C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x306730 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x306734 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x306738 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x30673C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x306740 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x306744 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x306748 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x30674C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x306750 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x306754 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x306758 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x30675C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x306760 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x306764 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x306768 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x30676C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x306770 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x306774 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x306778 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x30677C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x306780 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x306784 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x306788 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x30678C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x306790 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x306794 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x306798 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x30679C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3067A0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3067A4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3067A8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3067AC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3067B0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3067B4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3067B8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3067BC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3067C0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3067C4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3067C8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3067CC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3067D0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3067D4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3067D8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3067DC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3067E0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x306824 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x306828 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x30682C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x306830 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x306834 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x306838 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x30683C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x306840 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x306844 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x306848 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x30684C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x306850 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x306854 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x306858 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x30685C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x306860 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x306864 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x306868 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x30686C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x306870 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x306874 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x306878 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x30687C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x306880 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x306884 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x306888 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x30688C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x306890 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x306894 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x306898 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x30689C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3068A0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3068A4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3068A8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3068AC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3068B0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3068B4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3068B8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3068BC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3068C0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3068C4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3068C8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3068CC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3068D0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3068D4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3068D8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3068DC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3068E0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3068E4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3068E8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3068EC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3068F0 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3068F4 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3068F8 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3068FC + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x306900 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x306904 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x306908 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x30690C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x306910 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x306914 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x306918 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x30691C + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x306920 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x306924 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x306928 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x30692C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x306930 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x306934 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x306938 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x30693C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x306940 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x306944 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x306948 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x30694C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x306950 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x306954 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x306958 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x30695C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x306960 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x306964 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x306968 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x30696C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x306970 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x306974 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x306978 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x30697C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x306980 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x306984 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x306988 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x30698C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x306990 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x306994 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x306998 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x30699C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3069A0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3069A4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3069A8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3069AC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3069B0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3069B4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3069B8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3069BC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3069C0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3069C4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3069C8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3069CC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3069D0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3069D4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3069D8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3069DC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3069E0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3069E4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3069E8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3069EC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3069F0 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3069F4 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3069F8 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3069FC + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x306A00 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x306A04 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x306A08 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x306A0C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x306A10 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x306A14 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x306A18 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x306A1C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x306A20 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x306A64 + +#define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x306A68 + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x306A6C + +#define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x306A70 + +#define mmSIF_RTR_CTRL_0_RGL_CFG 0x306B64 + +#define mmSIF_RTR_CTRL_0_RGL_SHIFT 0x306B68 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x306B6C + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x306B70 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x306B74 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x306B78 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x306B7C + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x306B80 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x306B84 + +#define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x306B88 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_0 0x306BAC + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_1 0x306BB0 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_2 0x306BB4 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_3 0x306BB8 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_4 0x306BBC + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_5 0x306BC0 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_6 0x306BC4 + +#define mmSIF_RTR_CTRL_0_RGL_TOKEN_7 0x306BC8 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_0 0x306BEC + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_1 0x306BF0 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_2 0x306BF4 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_3 0x306BF8 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_4 0x306BFC + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_5 0x306C00 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_6 0x306C04 + +#define mmSIF_RTR_CTRL_0_RGL_BANK_ID_7 0x306C08 + +#define mmSIF_RTR_CTRL_0_RGL_WDT 0x306C2C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x306C30 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x306C34 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x306C38 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x306C3C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x306C40 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x306C44 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x306C48 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x306C4C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x306C50 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x306C54 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x306C58 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x306C5C + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x306C60 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x306C64 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x306C68 + +#define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x306C6C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x306C70 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x306C74 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x306C78 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x306C7C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x306C80 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x306C84 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x306C88 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x306C8C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x306C90 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x306C94 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x306C98 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x306C9C + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x306CA0 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x306CA4 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x306CA8 + +#define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x306CAC + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x306CB0 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x306CB4 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x306CB8 + +#define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x306CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h new file mode 100644 index 000000000000..c6d517dbbd54 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_1_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_1 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_1_PERM_SEL 0x316108 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_0 0x316114 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_1 0x316118 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_2 0x31611C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_3 0x316120 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_4 0x316124 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_5 0x316128 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_6 0x31612C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_7 0x316130 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_8 0x316134 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_9 0x316138 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_10 0x31613C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_11 0x316140 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_12 0x316144 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_13 0x316148 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_14 0x31614C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_15 0x316150 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_16 0x316154 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_17 0x316158 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_18 0x31615C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_19 0x316160 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_20 0x316164 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_21 0x316168 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_22 0x31616C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_23 0x316170 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_24 0x316174 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_25 0x316178 + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_26 0x31617C + +#define mmSIF_RTR_CTRL_1_HBM_POLY_H3_27 0x316180 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_0 0x316184 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_1 0x316188 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_2 0x31618C + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_3 0x316190 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_4 0x316194 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_5 0x316198 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_6 0x31619C + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_7 0x3161A0 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_8 0x3161A4 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_9 0x3161A8 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_10 0x3161AC + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_11 0x3161B0 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_12 0x3161B4 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_13 0x3161B8 + +#define mmSIF_RTR_CTRL_1_SRAM_POLY_H3_14 0x3161BC + +#define mmSIF_RTR_CTRL_1_SCRAM_SRAM_EN 0x31626C + +#define mmSIF_RTR_CTRL_1_RL_HBM_EN 0x316274 + +#define mmSIF_RTR_CTRL_1_RL_HBM_SAT 0x316278 + +#define mmSIF_RTR_CTRL_1_RL_HBM_RST 0x31627C + +#define mmSIF_RTR_CTRL_1_RL_HBM_TIMEOUT 0x316280 + +#define mmSIF_RTR_CTRL_1_SCRAM_HBM_EN 0x316284 + +#define mmSIF_RTR_CTRL_1_RL_PCI_EN 0x316288 + +#define mmSIF_RTR_CTRL_1_RL_PCI_SAT 0x31628C + +#define mmSIF_RTR_CTRL_1_RL_PCI_RST 0x316290 + +#define mmSIF_RTR_CTRL_1_RL_PCI_TIMEOUT 0x316294 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_EN 0x31629C + +#define mmSIF_RTR_CTRL_1_RL_SRAM_SAT 0x3162A0 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_RST 0x3162A4 + +#define mmSIF_RTR_CTRL_1_RL_SRAM_TIMEOUT 0x3162AC + +#define mmSIF_RTR_CTRL_1_RL_SRAM_RED 0x3162B4 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_EN 0x3162EC + +#define mmSIF_RTR_CTRL_1_E2E_PCI_EN 0x3162F0 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_WR_SIZE 0x3162F4 + +#define mmSIF_RTR_CTRL_1_E2E_PCI_WR_SIZE 0x3162F8 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET_EN 0x316404 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_SET 0x316408 + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_WRAP 0x31640C + +#define mmSIF_RTR_CTRL_1_E2E_AW_PCI_CTR_CNT 0x316410 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET_EN 0x316414 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM_CTR_SET 0x316418 + +#define mmSIF_RTR_CTRL_1_E2E_HBM_RD_SIZE 0x31641C + +#define mmSIF_RTR_CTRL_1_E2E_PCI_RD_SIZE 0x316420 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET_EN 0x316424 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_SET 0x316428 + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_WRAP 0x31642C + +#define mmSIF_RTR_CTRL_1_E2E_AR_PCI_CTR_CNT 0x316430 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET_EN 0x316434 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM_CTR_SET 0x316438 + +#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_0 0x316450 + +#define mmSIF_RTR_CTRL_1_NL_HBM_SEL_1 0x316454 + +#define mmSIF_RTR_CTRL_1_NON_LIN_EN 0x316480 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_0 0x316500 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_1 0x316504 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_2 0x316508 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_3 0x31650C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_BANK_4 0x316510 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_0 0x316514 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_1 0x316520 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_2 0x316524 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_3 0x316528 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_4 0x31652C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_5 0x316530 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_6 0x316534 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_7 0x316538 + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_8 0x31653C + +#define mmSIF_RTR_CTRL_1_NL_SRAM_OFFSET_9 0x316540 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_0 0x316550 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_1 0x316554 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_2 0x316558 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_3 0x31655C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_4 0x316560 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_5 0x316564 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_6 0x316568 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_7 0x31656C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_8 0x316570 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_9 0x316574 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_10 0x316578 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_11 0x31657C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_12 0x316580 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_13 0x316584 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_14 0x316588 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_15 0x31658C + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_16 0x316590 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_17 0x316594 + +#define mmSIF_RTR_CTRL_1_NL_HBM_OFFSET_18 0x316598 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_0 0x3165E4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_1 0x3165E8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_2 0x3165EC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_3 0x3165F0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_4 0x3165F4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_5 0x3165F8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_6 0x3165FC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_7 0x316600 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_8 0x316604 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_9 0x316608 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_10 0x31660C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_11 0x316610 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_12 0x316614 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_13 0x316618 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_14 0x31661C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AW_15 0x316620 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_0 0x316624 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_1 0x316628 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_2 0x31662C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_3 0x316630 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_4 0x316634 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_5 0x316638 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_6 0x31663C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_7 0x316640 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_8 0x316644 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_9 0x316648 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_10 0x31664C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_11 0x316650 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_12 0x316654 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_13 0x316658 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_14 0x31665C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AW_15 0x316660 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_0 0x316664 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_1 0x316668 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_2 0x31666C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_3 0x316670 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_4 0x316674 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_5 0x316678 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_6 0x31667C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_7 0x316680 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_8 0x316684 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_9 0x316688 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_10 0x31668C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_11 0x316690 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_12 0x316694 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_13 0x316698 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_14 0x31669C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AW_15 0x3166A0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_0 0x3166A4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_1 0x3166A8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_2 0x3166AC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_3 0x3166B0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_4 0x3166B4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_5 0x3166B8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_6 0x3166BC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_7 0x3166C0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_8 0x3166C4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_9 0x3166C8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_10 0x3166CC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_11 0x3166D0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_12 0x3166D4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_13 0x3166D8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_14 0x3166DC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AW_15 0x3166E0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_0 0x3166E4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_1 0x3166E8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_2 0x3166EC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_3 0x3166F0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_4 0x3166F4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_5 0x3166F8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_6 0x3166FC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_7 0x316700 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_8 0x316704 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_9 0x316708 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_10 0x31670C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_11 0x316710 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_12 0x316714 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_13 0x316718 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_14 0x31671C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AW_15 0x316720 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_0 0x316724 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_1 0x316728 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_2 0x31672C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_3 0x316730 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_4 0x316734 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_5 0x316738 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_6 0x31673C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_7 0x316740 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_8 0x316744 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_9 0x316748 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_10 0x31674C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_11 0x316750 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_12 0x316754 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_13 0x316758 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_14 0x31675C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AW_15 0x316760 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_0 0x316764 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_1 0x316768 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_2 0x31676C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_3 0x316770 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_4 0x316774 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_5 0x316778 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_6 0x31677C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_7 0x316780 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_8 0x316784 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_9 0x316788 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_10 0x31678C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_11 0x316790 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_12 0x316794 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_13 0x316798 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_14 0x31679C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AW_15 0x3167A0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_0 0x3167A4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_1 0x3167A8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_2 0x3167AC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_3 0x3167B0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_4 0x3167B4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_5 0x3167B8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_6 0x3167BC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_7 0x3167C0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_8 0x3167C4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_9 0x3167C8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_10 0x3167CC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_11 0x3167D0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_12 0x3167D4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_13 0x3167D8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_14 0x3167DC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AW_15 0x3167E0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_0 0x316824 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_1 0x316828 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_2 0x31682C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_3 0x316830 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_4 0x316834 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_5 0x316838 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_6 0x31683C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_7 0x316840 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_8 0x316844 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_9 0x316848 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_10 0x31684C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_11 0x316850 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_12 0x316854 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_13 0x316858 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_14 0x31685C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_LOW_AR_15 0x316860 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_0 0x316864 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_1 0x316868 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_2 0x31686C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_3 0x316870 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_4 0x316874 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_5 0x316878 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_6 0x31687C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_7 0x316880 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_8 0x316884 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_9 0x316888 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_10 0x31688C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_11 0x316890 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_12 0x316894 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_13 0x316898 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_14 0x31689C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_BASE_HIGH_AR_15 0x3168A0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_0 0x3168A4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_1 0x3168A8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_2 0x3168AC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_3 0x3168B0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_4 0x3168B4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_5 0x3168B8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_6 0x3168BC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_7 0x3168C0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_8 0x3168C4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_9 0x3168C8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_10 0x3168CC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_11 0x3168D0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_12 0x3168D4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_13 0x3168D8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_14 0x3168DC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_LOW_AR_15 0x3168E0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_0 0x3168E4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_1 0x3168E8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_2 0x3168EC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_3 0x3168F0 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_4 0x3168F4 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_5 0x3168F8 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_6 0x3168FC + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_7 0x316900 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_8 0x316904 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_9 0x316908 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_10 0x31690C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_11 0x316910 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_12 0x316914 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_13 0x316918 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_14 0x31691C + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_MASK_HIGH_AR_15 0x316920 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_0 0x316924 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_1 0x316928 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_2 0x31692C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_3 0x316930 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_4 0x316934 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_5 0x316938 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_6 0x31693C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_7 0x316940 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_8 0x316944 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_9 0x316948 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_10 0x31694C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_11 0x316950 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_12 0x316954 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_13 0x316958 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_14 0x31695C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_LOW_AR_15 0x316960 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_0 0x316964 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_1 0x316968 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_2 0x31696C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_3 0x316970 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_4 0x316974 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_5 0x316978 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_6 0x31697C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_7 0x316980 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_8 0x316984 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_9 0x316988 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_10 0x31698C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_11 0x316990 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_12 0x316994 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_13 0x316998 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_14 0x31699C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_BASE_HIGH_AR_15 0x3169A0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_0 0x3169A4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_1 0x3169A8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_2 0x3169AC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_3 0x3169B0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_4 0x3169B4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_5 0x3169B8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_6 0x3169BC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_7 0x3169C0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_8 0x3169C4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_9 0x3169C8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_10 0x3169CC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_11 0x3169D0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_12 0x3169D4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_13 0x3169D8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_14 0x3169DC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_LOW_AR_15 0x3169E0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_0 0x3169E4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_1 0x3169E8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_2 0x3169EC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_3 0x3169F0 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_4 0x3169F4 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_5 0x3169F8 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_6 0x3169FC + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_7 0x316A00 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_8 0x316A04 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_9 0x316A08 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_10 0x316A0C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_11 0x316A10 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_12 0x316A14 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_13 0x316A18 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_14 0x316A1C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_MASK_HIGH_AR_15 0x316A20 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AW 0x316A64 + +#define mmSIF_RTR_CTRL_1_RANGE_SEC_HIT_AR 0x316A68 + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AW 0x316A6C + +#define mmSIF_RTR_CTRL_1_RANGE_PRIV_HIT_AR 0x316A70 + +#define mmSIF_RTR_CTRL_1_RGL_CFG 0x316B64 + +#define mmSIF_RTR_CTRL_1_RGL_SHIFT 0x316B68 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_0 0x316B6C + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_1 0x316B70 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_2 0x316B74 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_3 0x316B78 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_4 0x316B7C + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_5 0x316B80 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_6 0x316B84 + +#define mmSIF_RTR_CTRL_1_RGL_EXPECTED_LAT_7 0x316B88 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_0 0x316BAC + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_1 0x316BB0 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_2 0x316BB4 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_3 0x316BB8 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_4 0x316BBC + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_5 0x316BC0 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_6 0x316BC4 + +#define mmSIF_RTR_CTRL_1_RGL_TOKEN_7 0x316BC8 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_0 0x316BEC + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_1 0x316BF0 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_2 0x316BF4 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_3 0x316BF8 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_4 0x316BFC + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_5 0x316C00 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_6 0x316C04 + +#define mmSIF_RTR_CTRL_1_RGL_BANK_ID_7 0x316C08 + +#define mmSIF_RTR_CTRL_1_RGL_WDT 0x316C2C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_WRAP 0x316C30 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_WRAP 0x316C34 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_WRAP 0x316C38 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_WRAP 0x316C3C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_WRAP 0x316C40 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_WRAP 0x316C44 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_WRAP 0x316C48 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_WRAP 0x316C4C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH0_CTR_CNT 0x316C50 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM0_CH1_CTR_CNT 0x316C54 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH0_CTR_CNT 0x316C58 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM1_CH1_CTR_CNT 0x316C5C + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH0_CTR_CNT 0x316C60 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM2_CH1_CTR_CNT 0x316C64 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH0_CTR_CNT 0x316C68 + +#define mmSIF_RTR_CTRL_1_E2E_AR_HBM3_CH1_CTR_CNT 0x316C6C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_WRAP 0x316C70 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_WRAP 0x316C74 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_WRAP 0x316C78 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_WRAP 0x316C7C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_WRAP 0x316C80 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_WRAP 0x316C84 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_WRAP 0x316C88 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_WRAP 0x316C8C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH0_CTR_CNT 0x316C90 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM0_CH1_CTR_CNT 0x316C94 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH0_CTR_CNT 0x316C98 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM1_CH1_CTR_CNT 0x316C9C + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH0_CTR_CNT 0x316CA0 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM2_CH1_CTR_CNT 0x316CA4 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH0_CTR_CNT 0x316CA8 + +#define mmSIF_RTR_CTRL_1_E2E_AW_HBM3_CH1_CTR_CNT 0x316CAC + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_0 0x316CB0 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_1 0x316CB4 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_2 0x316CB8 + +#define mmSIF_RTR_CTRL_1_NL_HBM_PC_SEL_3 0x316CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_1_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h new file mode 100644 index 000000000000..330e5b42d679 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_2_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_2 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_2_PERM_SEL 0x326108 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_0 0x326114 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_1 0x326118 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_2 0x32611C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_3 0x326120 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_4 0x326124 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_5 0x326128 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_6 0x32612C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_7 0x326130 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_8 0x326134 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_9 0x326138 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_10 0x32613C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_11 0x326140 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_12 0x326144 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_13 0x326148 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_14 0x32614C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_15 0x326150 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_16 0x326154 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_17 0x326158 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_18 0x32615C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_19 0x326160 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_20 0x326164 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_21 0x326168 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_22 0x32616C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_23 0x326170 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_24 0x326174 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_25 0x326178 + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_26 0x32617C + +#define mmSIF_RTR_CTRL_2_HBM_POLY_H3_27 0x326180 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_0 0x326184 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_1 0x326188 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_2 0x32618C + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_3 0x326190 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_4 0x326194 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_5 0x326198 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_6 0x32619C + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_7 0x3261A0 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_8 0x3261A4 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_9 0x3261A8 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_10 0x3261AC + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_11 0x3261B0 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_12 0x3261B4 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_13 0x3261B8 + +#define mmSIF_RTR_CTRL_2_SRAM_POLY_H3_14 0x3261BC + +#define mmSIF_RTR_CTRL_2_SCRAM_SRAM_EN 0x32626C + +#define mmSIF_RTR_CTRL_2_RL_HBM_EN 0x326274 + +#define mmSIF_RTR_CTRL_2_RL_HBM_SAT 0x326278 + +#define mmSIF_RTR_CTRL_2_RL_HBM_RST 0x32627C + +#define mmSIF_RTR_CTRL_2_RL_HBM_TIMEOUT 0x326280 + +#define mmSIF_RTR_CTRL_2_SCRAM_HBM_EN 0x326284 + +#define mmSIF_RTR_CTRL_2_RL_PCI_EN 0x326288 + +#define mmSIF_RTR_CTRL_2_RL_PCI_SAT 0x32628C + +#define mmSIF_RTR_CTRL_2_RL_PCI_RST 0x326290 + +#define mmSIF_RTR_CTRL_2_RL_PCI_TIMEOUT 0x326294 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_EN 0x32629C + +#define mmSIF_RTR_CTRL_2_RL_SRAM_SAT 0x3262A0 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_RST 0x3262A4 + +#define mmSIF_RTR_CTRL_2_RL_SRAM_TIMEOUT 0x3262AC + +#define mmSIF_RTR_CTRL_2_RL_SRAM_RED 0x3262B4 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_EN 0x3262EC + +#define mmSIF_RTR_CTRL_2_E2E_PCI_EN 0x3262F0 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_WR_SIZE 0x3262F4 + +#define mmSIF_RTR_CTRL_2_E2E_PCI_WR_SIZE 0x3262F8 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET_EN 0x326404 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_SET 0x326408 + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_WRAP 0x32640C + +#define mmSIF_RTR_CTRL_2_E2E_AW_PCI_CTR_CNT 0x326410 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET_EN 0x326414 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM_CTR_SET 0x326418 + +#define mmSIF_RTR_CTRL_2_E2E_HBM_RD_SIZE 0x32641C + +#define mmSIF_RTR_CTRL_2_E2E_PCI_RD_SIZE 0x326420 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET_EN 0x326424 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_SET 0x326428 + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_WRAP 0x32642C + +#define mmSIF_RTR_CTRL_2_E2E_AR_PCI_CTR_CNT 0x326430 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET_EN 0x326434 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM_CTR_SET 0x326438 + +#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_0 0x326450 + +#define mmSIF_RTR_CTRL_2_NL_HBM_SEL_1 0x326454 + +#define mmSIF_RTR_CTRL_2_NON_LIN_EN 0x326480 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_0 0x326500 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_1 0x326504 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_2 0x326508 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_3 0x32650C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_BANK_4 0x326510 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_0 0x326514 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_1 0x326520 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_2 0x326524 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_3 0x326528 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_4 0x32652C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_5 0x326530 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_6 0x326534 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_7 0x326538 + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_8 0x32653C + +#define mmSIF_RTR_CTRL_2_NL_SRAM_OFFSET_9 0x326540 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_0 0x326550 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_1 0x326554 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_2 0x326558 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_3 0x32655C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_4 0x326560 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_5 0x326564 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_6 0x326568 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_7 0x32656C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_8 0x326570 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_9 0x326574 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_10 0x326578 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_11 0x32657C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_12 0x326580 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_13 0x326584 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_14 0x326588 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_15 0x32658C + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_16 0x326590 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_17 0x326594 + +#define mmSIF_RTR_CTRL_2_NL_HBM_OFFSET_18 0x326598 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_0 0x3265E4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_1 0x3265E8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_2 0x3265EC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_3 0x3265F0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_4 0x3265F4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_5 0x3265F8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_6 0x3265FC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_7 0x326600 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_8 0x326604 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_9 0x326608 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_10 0x32660C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_11 0x326610 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_12 0x326614 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_13 0x326618 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_14 0x32661C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AW_15 0x326620 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_0 0x326624 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_1 0x326628 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_2 0x32662C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_3 0x326630 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_4 0x326634 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_5 0x326638 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_6 0x32663C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_7 0x326640 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_8 0x326644 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_9 0x326648 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_10 0x32664C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_11 0x326650 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_12 0x326654 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_13 0x326658 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_14 0x32665C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AW_15 0x326660 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_0 0x326664 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_1 0x326668 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_2 0x32666C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_3 0x326670 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_4 0x326674 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_5 0x326678 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_6 0x32667C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_7 0x326680 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_8 0x326684 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_9 0x326688 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_10 0x32668C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_11 0x326690 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_12 0x326694 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_13 0x326698 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_14 0x32669C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AW_15 0x3266A0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_0 0x3266A4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_1 0x3266A8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_2 0x3266AC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_3 0x3266B0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_4 0x3266B4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_5 0x3266B8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_6 0x3266BC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_7 0x3266C0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_8 0x3266C4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_9 0x3266C8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_10 0x3266CC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_11 0x3266D0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_12 0x3266D4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_13 0x3266D8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_14 0x3266DC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AW_15 0x3266E0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_0 0x3266E4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_1 0x3266E8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_2 0x3266EC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_3 0x3266F0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_4 0x3266F4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_5 0x3266F8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_6 0x3266FC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_7 0x326700 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_8 0x326704 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_9 0x326708 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_10 0x32670C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_11 0x326710 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_12 0x326714 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_13 0x326718 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_14 0x32671C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AW_15 0x326720 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_0 0x326724 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_1 0x326728 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_2 0x32672C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_3 0x326730 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_4 0x326734 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_5 0x326738 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_6 0x32673C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_7 0x326740 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_8 0x326744 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_9 0x326748 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_10 0x32674C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_11 0x326750 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_12 0x326754 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_13 0x326758 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_14 0x32675C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AW_15 0x326760 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_0 0x326764 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_1 0x326768 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_2 0x32676C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_3 0x326770 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_4 0x326774 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_5 0x326778 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_6 0x32677C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_7 0x326780 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_8 0x326784 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_9 0x326788 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_10 0x32678C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_11 0x326790 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_12 0x326794 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_13 0x326798 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_14 0x32679C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AW_15 0x3267A0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_0 0x3267A4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_1 0x3267A8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_2 0x3267AC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_3 0x3267B0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_4 0x3267B4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_5 0x3267B8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_6 0x3267BC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_7 0x3267C0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_8 0x3267C4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_9 0x3267C8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_10 0x3267CC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_11 0x3267D0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_12 0x3267D4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_13 0x3267D8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_14 0x3267DC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AW_15 0x3267E0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_0 0x326824 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_1 0x326828 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_2 0x32682C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_3 0x326830 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_4 0x326834 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_5 0x326838 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_6 0x32683C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_7 0x326840 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_8 0x326844 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_9 0x326848 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_10 0x32684C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_11 0x326850 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_12 0x326854 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_13 0x326858 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_14 0x32685C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_LOW_AR_15 0x326860 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_0 0x326864 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_1 0x326868 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_2 0x32686C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_3 0x326870 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_4 0x326874 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_5 0x326878 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_6 0x32687C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_7 0x326880 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_8 0x326884 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_9 0x326888 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_10 0x32688C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_11 0x326890 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_12 0x326894 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_13 0x326898 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_14 0x32689C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_BASE_HIGH_AR_15 0x3268A0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_0 0x3268A4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_1 0x3268A8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_2 0x3268AC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_3 0x3268B0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_4 0x3268B4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_5 0x3268B8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_6 0x3268BC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_7 0x3268C0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_8 0x3268C4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_9 0x3268C8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_10 0x3268CC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_11 0x3268D0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_12 0x3268D4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_13 0x3268D8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_14 0x3268DC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_LOW_AR_15 0x3268E0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_0 0x3268E4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_1 0x3268E8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_2 0x3268EC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_3 0x3268F0 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_4 0x3268F4 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_5 0x3268F8 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_6 0x3268FC + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_7 0x326900 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_8 0x326904 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_9 0x326908 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_10 0x32690C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_11 0x326910 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_12 0x326914 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_13 0x326918 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_14 0x32691C + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_MASK_HIGH_AR_15 0x326920 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_0 0x326924 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_1 0x326928 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_2 0x32692C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_3 0x326930 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_4 0x326934 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_5 0x326938 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_6 0x32693C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_7 0x326940 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_8 0x326944 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_9 0x326948 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_10 0x32694C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_11 0x326950 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_12 0x326954 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_13 0x326958 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_14 0x32695C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_LOW_AR_15 0x326960 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_0 0x326964 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_1 0x326968 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_2 0x32696C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_3 0x326970 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_4 0x326974 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_5 0x326978 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_6 0x32697C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_7 0x326980 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_8 0x326984 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_9 0x326988 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_10 0x32698C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_11 0x326990 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_12 0x326994 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_13 0x326998 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_14 0x32699C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_BASE_HIGH_AR_15 0x3269A0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_0 0x3269A4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_1 0x3269A8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_2 0x3269AC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_3 0x3269B0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_4 0x3269B4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_5 0x3269B8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_6 0x3269BC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_7 0x3269C0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_8 0x3269C4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_9 0x3269C8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_10 0x3269CC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_11 0x3269D0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_12 0x3269D4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_13 0x3269D8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_14 0x3269DC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_LOW_AR_15 0x3269E0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_0 0x3269E4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_1 0x3269E8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_2 0x3269EC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_3 0x3269F0 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_4 0x3269F4 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_5 0x3269F8 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_6 0x3269FC + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_7 0x326A00 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_8 0x326A04 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_9 0x326A08 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_10 0x326A0C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_11 0x326A10 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_12 0x326A14 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_13 0x326A18 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_14 0x326A1C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_MASK_HIGH_AR_15 0x326A20 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AW 0x326A64 + +#define mmSIF_RTR_CTRL_2_RANGE_SEC_HIT_AR 0x326A68 + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AW 0x326A6C + +#define mmSIF_RTR_CTRL_2_RANGE_PRIV_HIT_AR 0x326A70 + +#define mmSIF_RTR_CTRL_2_RGL_CFG 0x326B64 + +#define mmSIF_RTR_CTRL_2_RGL_SHIFT 0x326B68 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_0 0x326B6C + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_1 0x326B70 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_2 0x326B74 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_3 0x326B78 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_4 0x326B7C + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_5 0x326B80 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_6 0x326B84 + +#define mmSIF_RTR_CTRL_2_RGL_EXPECTED_LAT_7 0x326B88 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_0 0x326BAC + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_1 0x326BB0 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_2 0x326BB4 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_3 0x326BB8 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_4 0x326BBC + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_5 0x326BC0 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_6 0x326BC4 + +#define mmSIF_RTR_CTRL_2_RGL_TOKEN_7 0x326BC8 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_0 0x326BEC + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_1 0x326BF0 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_2 0x326BF4 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_3 0x326BF8 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_4 0x326BFC + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_5 0x326C00 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_6 0x326C04 + +#define mmSIF_RTR_CTRL_2_RGL_BANK_ID_7 0x326C08 + +#define mmSIF_RTR_CTRL_2_RGL_WDT 0x326C2C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_WRAP 0x326C30 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_WRAP 0x326C34 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_WRAP 0x326C38 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_WRAP 0x326C3C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_WRAP 0x326C40 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_WRAP 0x326C44 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_WRAP 0x326C48 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_WRAP 0x326C4C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH0_CTR_CNT 0x326C50 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM0_CH1_CTR_CNT 0x326C54 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH0_CTR_CNT 0x326C58 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM1_CH1_CTR_CNT 0x326C5C + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH0_CTR_CNT 0x326C60 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM2_CH1_CTR_CNT 0x326C64 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH0_CTR_CNT 0x326C68 + +#define mmSIF_RTR_CTRL_2_E2E_AR_HBM3_CH1_CTR_CNT 0x326C6C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_WRAP 0x326C70 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_WRAP 0x326C74 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_WRAP 0x326C78 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_WRAP 0x326C7C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_WRAP 0x326C80 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_WRAP 0x326C84 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_WRAP 0x326C88 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_WRAP 0x326C8C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH0_CTR_CNT 0x326C90 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM0_CH1_CTR_CNT 0x326C94 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH0_CTR_CNT 0x326C98 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM1_CH1_CTR_CNT 0x326C9C + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH0_CTR_CNT 0x326CA0 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM2_CH1_CTR_CNT 0x326CA4 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH0_CTR_CNT 0x326CA8 + +#define mmSIF_RTR_CTRL_2_E2E_AW_HBM3_CH1_CTR_CNT 0x326CAC + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_0 0x326CB0 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_1 0x326CB4 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_2 0x326CB8 + +#define mmSIF_RTR_CTRL_2_NL_HBM_PC_SEL_3 0x326CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_2_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h new file mode 100644 index 000000000000..d749f1968e5e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_3_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_3 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_3_PERM_SEL 0x336108 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_0 0x336114 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_1 0x336118 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_2 0x33611C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_3 0x336120 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_4 0x336124 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_5 0x336128 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_6 0x33612C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_7 0x336130 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_8 0x336134 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_9 0x336138 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_10 0x33613C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_11 0x336140 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_12 0x336144 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_13 0x336148 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_14 0x33614C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_15 0x336150 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_16 0x336154 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_17 0x336158 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_18 0x33615C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_19 0x336160 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_20 0x336164 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_21 0x336168 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_22 0x33616C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_23 0x336170 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_24 0x336174 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_25 0x336178 + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_26 0x33617C + +#define mmSIF_RTR_CTRL_3_HBM_POLY_H3_27 0x336180 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_0 0x336184 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_1 0x336188 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_2 0x33618C + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_3 0x336190 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_4 0x336194 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_5 0x336198 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_6 0x33619C + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_7 0x3361A0 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_8 0x3361A4 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_9 0x3361A8 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_10 0x3361AC + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_11 0x3361B0 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_12 0x3361B4 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_13 0x3361B8 + +#define mmSIF_RTR_CTRL_3_SRAM_POLY_H3_14 0x3361BC + +#define mmSIF_RTR_CTRL_3_SCRAM_SRAM_EN 0x33626C + +#define mmSIF_RTR_CTRL_3_RL_HBM_EN 0x336274 + +#define mmSIF_RTR_CTRL_3_RL_HBM_SAT 0x336278 + +#define mmSIF_RTR_CTRL_3_RL_HBM_RST 0x33627C + +#define mmSIF_RTR_CTRL_3_RL_HBM_TIMEOUT 0x336280 + +#define mmSIF_RTR_CTRL_3_SCRAM_HBM_EN 0x336284 + +#define mmSIF_RTR_CTRL_3_RL_PCI_EN 0x336288 + +#define mmSIF_RTR_CTRL_3_RL_PCI_SAT 0x33628C + +#define mmSIF_RTR_CTRL_3_RL_PCI_RST 0x336290 + +#define mmSIF_RTR_CTRL_3_RL_PCI_TIMEOUT 0x336294 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_EN 0x33629C + +#define mmSIF_RTR_CTRL_3_RL_SRAM_SAT 0x3362A0 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_RST 0x3362A4 + +#define mmSIF_RTR_CTRL_3_RL_SRAM_TIMEOUT 0x3362AC + +#define mmSIF_RTR_CTRL_3_RL_SRAM_RED 0x3362B4 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_EN 0x3362EC + +#define mmSIF_RTR_CTRL_3_E2E_PCI_EN 0x3362F0 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_WR_SIZE 0x3362F4 + +#define mmSIF_RTR_CTRL_3_E2E_PCI_WR_SIZE 0x3362F8 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET_EN 0x336404 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_SET 0x336408 + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_WRAP 0x33640C + +#define mmSIF_RTR_CTRL_3_E2E_AW_PCI_CTR_CNT 0x336410 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET_EN 0x336414 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM_CTR_SET 0x336418 + +#define mmSIF_RTR_CTRL_3_E2E_HBM_RD_SIZE 0x33641C + +#define mmSIF_RTR_CTRL_3_E2E_PCI_RD_SIZE 0x336420 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET_EN 0x336424 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_SET 0x336428 + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_WRAP 0x33642C + +#define mmSIF_RTR_CTRL_3_E2E_AR_PCI_CTR_CNT 0x336430 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET_EN 0x336434 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM_CTR_SET 0x336438 + +#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_0 0x336450 + +#define mmSIF_RTR_CTRL_3_NL_HBM_SEL_1 0x336454 + +#define mmSIF_RTR_CTRL_3_NON_LIN_EN 0x336480 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_0 0x336500 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_1 0x336504 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_2 0x336508 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_3 0x33650C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_BANK_4 0x336510 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_0 0x336514 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_1 0x336520 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_2 0x336524 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_3 0x336528 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_4 0x33652C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_5 0x336530 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_6 0x336534 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_7 0x336538 + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_8 0x33653C + +#define mmSIF_RTR_CTRL_3_NL_SRAM_OFFSET_9 0x336540 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_0 0x336550 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_1 0x336554 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_2 0x336558 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_3 0x33655C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_4 0x336560 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_5 0x336564 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_6 0x336568 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_7 0x33656C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_8 0x336570 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_9 0x336574 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_10 0x336578 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_11 0x33657C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_12 0x336580 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_13 0x336584 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_14 0x336588 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_15 0x33658C + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_16 0x336590 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_17 0x336594 + +#define mmSIF_RTR_CTRL_3_NL_HBM_OFFSET_18 0x336598 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_0 0x3365E4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_1 0x3365E8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_2 0x3365EC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_3 0x3365F0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_4 0x3365F4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_5 0x3365F8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_6 0x3365FC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_7 0x336600 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_8 0x336604 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_9 0x336608 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_10 0x33660C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_11 0x336610 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_12 0x336614 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_13 0x336618 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_14 0x33661C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AW_15 0x336620 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_0 0x336624 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_1 0x336628 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_2 0x33662C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_3 0x336630 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_4 0x336634 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_5 0x336638 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_6 0x33663C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_7 0x336640 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_8 0x336644 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_9 0x336648 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_10 0x33664C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_11 0x336650 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_12 0x336654 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_13 0x336658 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_14 0x33665C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AW_15 0x336660 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_0 0x336664 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_1 0x336668 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_2 0x33666C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_3 0x336670 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_4 0x336674 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_5 0x336678 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_6 0x33667C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_7 0x336680 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_8 0x336684 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_9 0x336688 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_10 0x33668C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_11 0x336690 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_12 0x336694 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_13 0x336698 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_14 0x33669C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AW_15 0x3366A0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_0 0x3366A4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_1 0x3366A8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_2 0x3366AC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_3 0x3366B0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_4 0x3366B4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_5 0x3366B8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_6 0x3366BC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_7 0x3366C0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_8 0x3366C4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_9 0x3366C8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_10 0x3366CC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_11 0x3366D0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_12 0x3366D4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_13 0x3366D8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_14 0x3366DC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AW_15 0x3366E0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_0 0x3366E4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_1 0x3366E8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_2 0x3366EC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_3 0x3366F0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_4 0x3366F4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_5 0x3366F8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_6 0x3366FC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_7 0x336700 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_8 0x336704 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_9 0x336708 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_10 0x33670C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_11 0x336710 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_12 0x336714 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_13 0x336718 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_14 0x33671C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AW_15 0x336720 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_0 0x336724 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_1 0x336728 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_2 0x33672C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_3 0x336730 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_4 0x336734 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_5 0x336738 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_6 0x33673C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_7 0x336740 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_8 0x336744 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_9 0x336748 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_10 0x33674C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_11 0x336750 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_12 0x336754 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_13 0x336758 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_14 0x33675C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AW_15 0x336760 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_0 0x336764 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_1 0x336768 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_2 0x33676C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_3 0x336770 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_4 0x336774 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_5 0x336778 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_6 0x33677C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_7 0x336780 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_8 0x336784 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_9 0x336788 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_10 0x33678C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_11 0x336790 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_12 0x336794 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_13 0x336798 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_14 0x33679C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AW_15 0x3367A0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_0 0x3367A4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_1 0x3367A8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_2 0x3367AC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_3 0x3367B0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_4 0x3367B4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_5 0x3367B8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_6 0x3367BC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_7 0x3367C0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_8 0x3367C4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_9 0x3367C8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_10 0x3367CC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_11 0x3367D0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_12 0x3367D4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_13 0x3367D8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_14 0x3367DC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AW_15 0x3367E0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_0 0x336824 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_1 0x336828 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_2 0x33682C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_3 0x336830 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_4 0x336834 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_5 0x336838 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_6 0x33683C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_7 0x336840 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_8 0x336844 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_9 0x336848 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_10 0x33684C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_11 0x336850 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_12 0x336854 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_13 0x336858 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_14 0x33685C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_LOW_AR_15 0x336860 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_0 0x336864 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_1 0x336868 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_2 0x33686C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_3 0x336870 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_4 0x336874 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_5 0x336878 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_6 0x33687C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_7 0x336880 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_8 0x336884 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_9 0x336888 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_10 0x33688C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_11 0x336890 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_12 0x336894 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_13 0x336898 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_14 0x33689C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_BASE_HIGH_AR_15 0x3368A0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_0 0x3368A4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_1 0x3368A8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_2 0x3368AC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_3 0x3368B0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_4 0x3368B4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_5 0x3368B8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_6 0x3368BC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_7 0x3368C0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_8 0x3368C4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_9 0x3368C8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_10 0x3368CC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_11 0x3368D0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_12 0x3368D4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_13 0x3368D8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_14 0x3368DC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_LOW_AR_15 0x3368E0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_0 0x3368E4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_1 0x3368E8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_2 0x3368EC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_3 0x3368F0 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_4 0x3368F4 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_5 0x3368F8 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_6 0x3368FC + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_7 0x336900 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_8 0x336904 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_9 0x336908 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_10 0x33690C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_11 0x336910 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_12 0x336914 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_13 0x336918 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_14 0x33691C + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_MASK_HIGH_AR_15 0x336920 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_0 0x336924 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_1 0x336928 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_2 0x33692C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_3 0x336930 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_4 0x336934 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_5 0x336938 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_6 0x33693C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_7 0x336940 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_8 0x336944 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_9 0x336948 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_10 0x33694C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_11 0x336950 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_12 0x336954 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_13 0x336958 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_14 0x33695C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_LOW_AR_15 0x336960 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_0 0x336964 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_1 0x336968 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_2 0x33696C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_3 0x336970 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_4 0x336974 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_5 0x336978 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_6 0x33697C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_7 0x336980 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_8 0x336984 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_9 0x336988 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_10 0x33698C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_11 0x336990 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_12 0x336994 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_13 0x336998 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_14 0x33699C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_BASE_HIGH_AR_15 0x3369A0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_0 0x3369A4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_1 0x3369A8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_2 0x3369AC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_3 0x3369B0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_4 0x3369B4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_5 0x3369B8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_6 0x3369BC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_7 0x3369C0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_8 0x3369C4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_9 0x3369C8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_10 0x3369CC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_11 0x3369D0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_12 0x3369D4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_13 0x3369D8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_14 0x3369DC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_LOW_AR_15 0x3369E0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_0 0x3369E4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_1 0x3369E8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_2 0x3369EC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_3 0x3369F0 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_4 0x3369F4 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_5 0x3369F8 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_6 0x3369FC + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_7 0x336A00 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_8 0x336A04 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_9 0x336A08 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_10 0x336A0C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_11 0x336A10 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_12 0x336A14 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_13 0x336A18 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_14 0x336A1C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_MASK_HIGH_AR_15 0x336A20 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AW 0x336A64 + +#define mmSIF_RTR_CTRL_3_RANGE_SEC_HIT_AR 0x336A68 + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AW 0x336A6C + +#define mmSIF_RTR_CTRL_3_RANGE_PRIV_HIT_AR 0x336A70 + +#define mmSIF_RTR_CTRL_3_RGL_CFG 0x336B64 + +#define mmSIF_RTR_CTRL_3_RGL_SHIFT 0x336B68 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_0 0x336B6C + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_1 0x336B70 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_2 0x336B74 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_3 0x336B78 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_4 0x336B7C + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_5 0x336B80 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_6 0x336B84 + +#define mmSIF_RTR_CTRL_3_RGL_EXPECTED_LAT_7 0x336B88 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_0 0x336BAC + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_1 0x336BB0 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_2 0x336BB4 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_3 0x336BB8 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_4 0x336BBC + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_5 0x336BC0 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_6 0x336BC4 + +#define mmSIF_RTR_CTRL_3_RGL_TOKEN_7 0x336BC8 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_0 0x336BEC + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_1 0x336BF0 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_2 0x336BF4 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_3 0x336BF8 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_4 0x336BFC + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_5 0x336C00 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_6 0x336C04 + +#define mmSIF_RTR_CTRL_3_RGL_BANK_ID_7 0x336C08 + +#define mmSIF_RTR_CTRL_3_RGL_WDT 0x336C2C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_WRAP 0x336C30 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_WRAP 0x336C34 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_WRAP 0x336C38 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_WRAP 0x336C3C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_WRAP 0x336C40 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_WRAP 0x336C44 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_WRAP 0x336C48 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_WRAP 0x336C4C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH0_CTR_CNT 0x336C50 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM0_CH1_CTR_CNT 0x336C54 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH0_CTR_CNT 0x336C58 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM1_CH1_CTR_CNT 0x336C5C + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH0_CTR_CNT 0x336C60 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM2_CH1_CTR_CNT 0x336C64 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH0_CTR_CNT 0x336C68 + +#define mmSIF_RTR_CTRL_3_E2E_AR_HBM3_CH1_CTR_CNT 0x336C6C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_WRAP 0x336C70 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_WRAP 0x336C74 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_WRAP 0x336C78 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_WRAP 0x336C7C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_WRAP 0x336C80 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_WRAP 0x336C84 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_WRAP 0x336C88 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_WRAP 0x336C8C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH0_CTR_CNT 0x336C90 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM0_CH1_CTR_CNT 0x336C94 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH0_CTR_CNT 0x336C98 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM1_CH1_CTR_CNT 0x336C9C + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH0_CTR_CNT 0x336CA0 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM2_CH1_CTR_CNT 0x336CA4 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH0_CTR_CNT 0x336CA8 + +#define mmSIF_RTR_CTRL_3_E2E_AW_HBM3_CH1_CTR_CNT 0x336CAC + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_0 0x336CB0 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_1 0x336CB4 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_2 0x336CB8 + +#define mmSIF_RTR_CTRL_3_NL_HBM_PC_SEL_3 0x336CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_3_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h new file mode 100644 index 000000000000..ad48773c4bbd --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_4_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_4 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_4_PERM_SEL 0x346108 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_0 0x346114 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_1 0x346118 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_2 0x34611C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_3 0x346120 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_4 0x346124 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_5 0x346128 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_6 0x34612C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_7 0x346130 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_8 0x346134 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_9 0x346138 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_10 0x34613C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_11 0x346140 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_12 0x346144 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_13 0x346148 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_14 0x34614C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_15 0x346150 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_16 0x346154 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_17 0x346158 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_18 0x34615C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_19 0x346160 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_20 0x346164 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_21 0x346168 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_22 0x34616C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_23 0x346170 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_24 0x346174 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_25 0x346178 + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_26 0x34617C + +#define mmSIF_RTR_CTRL_4_HBM_POLY_H3_27 0x346180 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_0 0x346184 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_1 0x346188 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_2 0x34618C + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_3 0x346190 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_4 0x346194 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_5 0x346198 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_6 0x34619C + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_7 0x3461A0 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_8 0x3461A4 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_9 0x3461A8 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_10 0x3461AC + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_11 0x3461B0 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_12 0x3461B4 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_13 0x3461B8 + +#define mmSIF_RTR_CTRL_4_SRAM_POLY_H3_14 0x3461BC + +#define mmSIF_RTR_CTRL_4_SCRAM_SRAM_EN 0x34626C + +#define mmSIF_RTR_CTRL_4_RL_HBM_EN 0x346274 + +#define mmSIF_RTR_CTRL_4_RL_HBM_SAT 0x346278 + +#define mmSIF_RTR_CTRL_4_RL_HBM_RST 0x34627C + +#define mmSIF_RTR_CTRL_4_RL_HBM_TIMEOUT 0x346280 + +#define mmSIF_RTR_CTRL_4_SCRAM_HBM_EN 0x346284 + +#define mmSIF_RTR_CTRL_4_RL_PCI_EN 0x346288 + +#define mmSIF_RTR_CTRL_4_RL_PCI_SAT 0x34628C + +#define mmSIF_RTR_CTRL_4_RL_PCI_RST 0x346290 + +#define mmSIF_RTR_CTRL_4_RL_PCI_TIMEOUT 0x346294 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_EN 0x34629C + +#define mmSIF_RTR_CTRL_4_RL_SRAM_SAT 0x3462A0 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_RST 0x3462A4 + +#define mmSIF_RTR_CTRL_4_RL_SRAM_TIMEOUT 0x3462AC + +#define mmSIF_RTR_CTRL_4_RL_SRAM_RED 0x3462B4 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_EN 0x3462EC + +#define mmSIF_RTR_CTRL_4_E2E_PCI_EN 0x3462F0 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_WR_SIZE 0x3462F4 + +#define mmSIF_RTR_CTRL_4_E2E_PCI_WR_SIZE 0x3462F8 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET_EN 0x346404 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_SET 0x346408 + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_WRAP 0x34640C + +#define mmSIF_RTR_CTRL_4_E2E_AW_PCI_CTR_CNT 0x346410 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET_EN 0x346414 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM_CTR_SET 0x346418 + +#define mmSIF_RTR_CTRL_4_E2E_HBM_RD_SIZE 0x34641C + +#define mmSIF_RTR_CTRL_4_E2E_PCI_RD_SIZE 0x346420 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET_EN 0x346424 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_SET 0x346428 + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_WRAP 0x34642C + +#define mmSIF_RTR_CTRL_4_E2E_AR_PCI_CTR_CNT 0x346430 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET_EN 0x346434 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM_CTR_SET 0x346438 + +#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_0 0x346450 + +#define mmSIF_RTR_CTRL_4_NL_HBM_SEL_1 0x346454 + +#define mmSIF_RTR_CTRL_4_NON_LIN_EN 0x346480 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_0 0x346500 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_1 0x346504 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_2 0x346508 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_3 0x34650C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_BANK_4 0x346510 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_0 0x346514 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_1 0x346520 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_2 0x346524 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_3 0x346528 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_4 0x34652C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_5 0x346530 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_6 0x346534 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_7 0x346538 + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_8 0x34653C + +#define mmSIF_RTR_CTRL_4_NL_SRAM_OFFSET_9 0x346540 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_0 0x346550 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_1 0x346554 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_2 0x346558 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_3 0x34655C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_4 0x346560 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_5 0x346564 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_6 0x346568 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_7 0x34656C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_8 0x346570 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_9 0x346574 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_10 0x346578 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_11 0x34657C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_12 0x346580 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_13 0x346584 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_14 0x346588 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_15 0x34658C + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_16 0x346590 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_17 0x346594 + +#define mmSIF_RTR_CTRL_4_NL_HBM_OFFSET_18 0x346598 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_0 0x3465E4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_1 0x3465E8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_2 0x3465EC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_3 0x3465F0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_4 0x3465F4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_5 0x3465F8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_6 0x3465FC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_7 0x346600 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_8 0x346604 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_9 0x346608 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_10 0x34660C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_11 0x346610 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_12 0x346614 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_13 0x346618 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_14 0x34661C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AW_15 0x346620 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_0 0x346624 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_1 0x346628 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_2 0x34662C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_3 0x346630 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_4 0x346634 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_5 0x346638 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_6 0x34663C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_7 0x346640 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_8 0x346644 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_9 0x346648 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_10 0x34664C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_11 0x346650 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_12 0x346654 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_13 0x346658 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_14 0x34665C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AW_15 0x346660 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_0 0x346664 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_1 0x346668 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_2 0x34666C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_3 0x346670 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_4 0x346674 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_5 0x346678 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_6 0x34667C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_7 0x346680 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_8 0x346684 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_9 0x346688 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_10 0x34668C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_11 0x346690 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_12 0x346694 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_13 0x346698 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_14 0x34669C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AW_15 0x3466A0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_0 0x3466A4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_1 0x3466A8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_2 0x3466AC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_3 0x3466B0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_4 0x3466B4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_5 0x3466B8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_6 0x3466BC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_7 0x3466C0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_8 0x3466C4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_9 0x3466C8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_10 0x3466CC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_11 0x3466D0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_12 0x3466D4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_13 0x3466D8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_14 0x3466DC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AW_15 0x3466E0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_0 0x3466E4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_1 0x3466E8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_2 0x3466EC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_3 0x3466F0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_4 0x3466F4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_5 0x3466F8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_6 0x3466FC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_7 0x346700 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_8 0x346704 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_9 0x346708 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_10 0x34670C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_11 0x346710 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_12 0x346714 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_13 0x346718 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_14 0x34671C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AW_15 0x346720 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_0 0x346724 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_1 0x346728 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_2 0x34672C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_3 0x346730 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_4 0x346734 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_5 0x346738 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_6 0x34673C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_7 0x346740 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_8 0x346744 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_9 0x346748 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_10 0x34674C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_11 0x346750 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_12 0x346754 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_13 0x346758 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_14 0x34675C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AW_15 0x346760 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_0 0x346764 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_1 0x346768 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_2 0x34676C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_3 0x346770 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_4 0x346774 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_5 0x346778 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_6 0x34677C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_7 0x346780 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_8 0x346784 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_9 0x346788 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_10 0x34678C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_11 0x346790 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_12 0x346794 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_13 0x346798 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_14 0x34679C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AW_15 0x3467A0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_0 0x3467A4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_1 0x3467A8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_2 0x3467AC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_3 0x3467B0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_4 0x3467B4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_5 0x3467B8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_6 0x3467BC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_7 0x3467C0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_8 0x3467C4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_9 0x3467C8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_10 0x3467CC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_11 0x3467D0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_12 0x3467D4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_13 0x3467D8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_14 0x3467DC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AW_15 0x3467E0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_0 0x346824 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_1 0x346828 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_2 0x34682C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_3 0x346830 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_4 0x346834 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_5 0x346838 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_6 0x34683C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_7 0x346840 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_8 0x346844 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_9 0x346848 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_10 0x34684C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_11 0x346850 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_12 0x346854 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_13 0x346858 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_14 0x34685C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_LOW_AR_15 0x346860 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_0 0x346864 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_1 0x346868 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_2 0x34686C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_3 0x346870 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_4 0x346874 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_5 0x346878 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_6 0x34687C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_7 0x346880 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_8 0x346884 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_9 0x346888 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_10 0x34688C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_11 0x346890 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_12 0x346894 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_13 0x346898 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_14 0x34689C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_BASE_HIGH_AR_15 0x3468A0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_0 0x3468A4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_1 0x3468A8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_2 0x3468AC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_3 0x3468B0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_4 0x3468B4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_5 0x3468B8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_6 0x3468BC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_7 0x3468C0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_8 0x3468C4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_9 0x3468C8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_10 0x3468CC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_11 0x3468D0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_12 0x3468D4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_13 0x3468D8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_14 0x3468DC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_LOW_AR_15 0x3468E0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_0 0x3468E4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_1 0x3468E8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_2 0x3468EC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_3 0x3468F0 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_4 0x3468F4 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_5 0x3468F8 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_6 0x3468FC + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_7 0x346900 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_8 0x346904 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_9 0x346908 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_10 0x34690C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_11 0x346910 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_12 0x346914 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_13 0x346918 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_14 0x34691C + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_MASK_HIGH_AR_15 0x346920 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_0 0x346924 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_1 0x346928 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_2 0x34692C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_3 0x346930 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_4 0x346934 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_5 0x346938 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_6 0x34693C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_7 0x346940 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_8 0x346944 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_9 0x346948 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_10 0x34694C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_11 0x346950 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_12 0x346954 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_13 0x346958 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_14 0x34695C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_LOW_AR_15 0x346960 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_0 0x346964 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_1 0x346968 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_2 0x34696C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_3 0x346970 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_4 0x346974 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_5 0x346978 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_6 0x34697C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_7 0x346980 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_8 0x346984 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_9 0x346988 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_10 0x34698C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_11 0x346990 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_12 0x346994 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_13 0x346998 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_14 0x34699C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_BASE_HIGH_AR_15 0x3469A0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_0 0x3469A4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_1 0x3469A8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_2 0x3469AC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_3 0x3469B0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_4 0x3469B4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_5 0x3469B8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_6 0x3469BC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_7 0x3469C0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_8 0x3469C4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_9 0x3469C8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_10 0x3469CC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_11 0x3469D0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_12 0x3469D4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_13 0x3469D8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_14 0x3469DC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_LOW_AR_15 0x3469E0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_0 0x3469E4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_1 0x3469E8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_2 0x3469EC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_3 0x3469F0 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_4 0x3469F4 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_5 0x3469F8 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_6 0x3469FC + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_7 0x346A00 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_8 0x346A04 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_9 0x346A08 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_10 0x346A0C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_11 0x346A10 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_12 0x346A14 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_13 0x346A18 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_14 0x346A1C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_MASK_HIGH_AR_15 0x346A20 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AW 0x346A64 + +#define mmSIF_RTR_CTRL_4_RANGE_SEC_HIT_AR 0x346A68 + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AW 0x346A6C + +#define mmSIF_RTR_CTRL_4_RANGE_PRIV_HIT_AR 0x346A70 + +#define mmSIF_RTR_CTRL_4_RGL_CFG 0x346B64 + +#define mmSIF_RTR_CTRL_4_RGL_SHIFT 0x346B68 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_0 0x346B6C + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_1 0x346B70 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_2 0x346B74 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_3 0x346B78 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_4 0x346B7C + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_5 0x346B80 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_6 0x346B84 + +#define mmSIF_RTR_CTRL_4_RGL_EXPECTED_LAT_7 0x346B88 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_0 0x346BAC + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_1 0x346BB0 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_2 0x346BB4 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_3 0x346BB8 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_4 0x346BBC + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_5 0x346BC0 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_6 0x346BC4 + +#define mmSIF_RTR_CTRL_4_RGL_TOKEN_7 0x346BC8 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_0 0x346BEC + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_1 0x346BF0 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_2 0x346BF4 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_3 0x346BF8 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_4 0x346BFC + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_5 0x346C00 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_6 0x346C04 + +#define mmSIF_RTR_CTRL_4_RGL_BANK_ID_7 0x346C08 + +#define mmSIF_RTR_CTRL_4_RGL_WDT 0x346C2C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_WRAP 0x346C30 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_WRAP 0x346C34 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_WRAP 0x346C38 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_WRAP 0x346C3C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_WRAP 0x346C40 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_WRAP 0x346C44 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_WRAP 0x346C48 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_WRAP 0x346C4C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH0_CTR_CNT 0x346C50 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM0_CH1_CTR_CNT 0x346C54 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH0_CTR_CNT 0x346C58 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM1_CH1_CTR_CNT 0x346C5C + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH0_CTR_CNT 0x346C60 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM2_CH1_CTR_CNT 0x346C64 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH0_CTR_CNT 0x346C68 + +#define mmSIF_RTR_CTRL_4_E2E_AR_HBM3_CH1_CTR_CNT 0x346C6C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_WRAP 0x346C70 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_WRAP 0x346C74 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_WRAP 0x346C78 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_WRAP 0x346C7C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_WRAP 0x346C80 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_WRAP 0x346C84 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_WRAP 0x346C88 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_WRAP 0x346C8C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH0_CTR_CNT 0x346C90 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM0_CH1_CTR_CNT 0x346C94 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH0_CTR_CNT 0x346C98 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM1_CH1_CTR_CNT 0x346C9C + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH0_CTR_CNT 0x346CA0 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM2_CH1_CTR_CNT 0x346CA4 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH0_CTR_CNT 0x346CA8 + +#define mmSIF_RTR_CTRL_4_E2E_AW_HBM3_CH1_CTR_CNT 0x346CAC + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_0 0x346CB0 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_1 0x346CB4 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_2 0x346CB8 + +#define mmSIF_RTR_CTRL_4_NL_HBM_PC_SEL_3 0x346CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_4_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h new file mode 100644 index 000000000000..6c27850ca3f5 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_5_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_5 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_5_PERM_SEL 0x356108 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_0 0x356114 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_1 0x356118 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_2 0x35611C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_3 0x356120 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_4 0x356124 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_5 0x356128 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_6 0x35612C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_7 0x356130 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_8 0x356134 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_9 0x356138 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_10 0x35613C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_11 0x356140 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_12 0x356144 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_13 0x356148 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_14 0x35614C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_15 0x356150 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_16 0x356154 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_17 0x356158 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_18 0x35615C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_19 0x356160 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_20 0x356164 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_21 0x356168 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_22 0x35616C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_23 0x356170 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_24 0x356174 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_25 0x356178 + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_26 0x35617C + +#define mmSIF_RTR_CTRL_5_HBM_POLY_H3_27 0x356180 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_0 0x356184 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_1 0x356188 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_2 0x35618C + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_3 0x356190 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_4 0x356194 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_5 0x356198 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_6 0x35619C + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_7 0x3561A0 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_8 0x3561A4 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_9 0x3561A8 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_10 0x3561AC + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_11 0x3561B0 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_12 0x3561B4 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_13 0x3561B8 + +#define mmSIF_RTR_CTRL_5_SRAM_POLY_H3_14 0x3561BC + +#define mmSIF_RTR_CTRL_5_SCRAM_SRAM_EN 0x35626C + +#define mmSIF_RTR_CTRL_5_RL_HBM_EN 0x356274 + +#define mmSIF_RTR_CTRL_5_RL_HBM_SAT 0x356278 + +#define mmSIF_RTR_CTRL_5_RL_HBM_RST 0x35627C + +#define mmSIF_RTR_CTRL_5_RL_HBM_TIMEOUT 0x356280 + +#define mmSIF_RTR_CTRL_5_SCRAM_HBM_EN 0x356284 + +#define mmSIF_RTR_CTRL_5_RL_PCI_EN 0x356288 + +#define mmSIF_RTR_CTRL_5_RL_PCI_SAT 0x35628C + +#define mmSIF_RTR_CTRL_5_RL_PCI_RST 0x356290 + +#define mmSIF_RTR_CTRL_5_RL_PCI_TIMEOUT 0x356294 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_EN 0x35629C + +#define mmSIF_RTR_CTRL_5_RL_SRAM_SAT 0x3562A0 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_RST 0x3562A4 + +#define mmSIF_RTR_CTRL_5_RL_SRAM_TIMEOUT 0x3562AC + +#define mmSIF_RTR_CTRL_5_RL_SRAM_RED 0x3562B4 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_EN 0x3562EC + +#define mmSIF_RTR_CTRL_5_E2E_PCI_EN 0x3562F0 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_WR_SIZE 0x3562F4 + +#define mmSIF_RTR_CTRL_5_E2E_PCI_WR_SIZE 0x3562F8 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET_EN 0x356404 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_SET 0x356408 + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_WRAP 0x35640C + +#define mmSIF_RTR_CTRL_5_E2E_AW_PCI_CTR_CNT 0x356410 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET_EN 0x356414 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM_CTR_SET 0x356418 + +#define mmSIF_RTR_CTRL_5_E2E_HBM_RD_SIZE 0x35641C + +#define mmSIF_RTR_CTRL_5_E2E_PCI_RD_SIZE 0x356420 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET_EN 0x356424 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_SET 0x356428 + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_WRAP 0x35642C + +#define mmSIF_RTR_CTRL_5_E2E_AR_PCI_CTR_CNT 0x356430 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET_EN 0x356434 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM_CTR_SET 0x356438 + +#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_0 0x356450 + +#define mmSIF_RTR_CTRL_5_NL_HBM_SEL_1 0x356454 + +#define mmSIF_RTR_CTRL_5_NON_LIN_EN 0x356480 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_0 0x356500 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_1 0x356504 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_2 0x356508 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_3 0x35650C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_BANK_4 0x356510 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_0 0x356514 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_1 0x356520 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_2 0x356524 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_3 0x356528 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_4 0x35652C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_5 0x356530 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_6 0x356534 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_7 0x356538 + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_8 0x35653C + +#define mmSIF_RTR_CTRL_5_NL_SRAM_OFFSET_9 0x356540 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_0 0x356550 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_1 0x356554 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_2 0x356558 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_3 0x35655C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_4 0x356560 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_5 0x356564 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_6 0x356568 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_7 0x35656C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_8 0x356570 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_9 0x356574 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_10 0x356578 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_11 0x35657C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_12 0x356580 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_13 0x356584 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_14 0x356588 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_15 0x35658C + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_16 0x356590 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_17 0x356594 + +#define mmSIF_RTR_CTRL_5_NL_HBM_OFFSET_18 0x356598 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_0 0x3565E4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_1 0x3565E8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_2 0x3565EC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_3 0x3565F0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_4 0x3565F4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_5 0x3565F8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_6 0x3565FC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_7 0x356600 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_8 0x356604 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_9 0x356608 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_10 0x35660C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_11 0x356610 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_12 0x356614 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_13 0x356618 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_14 0x35661C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AW_15 0x356620 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_0 0x356624 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_1 0x356628 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_2 0x35662C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_3 0x356630 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_4 0x356634 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_5 0x356638 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_6 0x35663C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_7 0x356640 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_8 0x356644 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_9 0x356648 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_10 0x35664C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_11 0x356650 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_12 0x356654 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_13 0x356658 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_14 0x35665C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AW_15 0x356660 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_0 0x356664 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_1 0x356668 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_2 0x35666C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_3 0x356670 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_4 0x356674 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_5 0x356678 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_6 0x35667C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_7 0x356680 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_8 0x356684 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_9 0x356688 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_10 0x35668C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_11 0x356690 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_12 0x356694 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_13 0x356698 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_14 0x35669C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AW_15 0x3566A0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_0 0x3566A4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_1 0x3566A8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_2 0x3566AC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_3 0x3566B0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_4 0x3566B4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_5 0x3566B8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_6 0x3566BC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_7 0x3566C0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_8 0x3566C4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_9 0x3566C8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_10 0x3566CC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_11 0x3566D0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_12 0x3566D4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_13 0x3566D8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_14 0x3566DC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AW_15 0x3566E0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_0 0x3566E4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_1 0x3566E8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_2 0x3566EC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_3 0x3566F0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_4 0x3566F4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_5 0x3566F8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_6 0x3566FC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_7 0x356700 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_8 0x356704 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_9 0x356708 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_10 0x35670C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_11 0x356710 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_12 0x356714 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_13 0x356718 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_14 0x35671C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AW_15 0x356720 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_0 0x356724 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_1 0x356728 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_2 0x35672C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_3 0x356730 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_4 0x356734 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_5 0x356738 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_6 0x35673C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_7 0x356740 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_8 0x356744 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_9 0x356748 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_10 0x35674C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_11 0x356750 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_12 0x356754 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_13 0x356758 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_14 0x35675C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AW_15 0x356760 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_0 0x356764 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_1 0x356768 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_2 0x35676C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_3 0x356770 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_4 0x356774 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_5 0x356778 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_6 0x35677C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_7 0x356780 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_8 0x356784 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_9 0x356788 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_10 0x35678C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_11 0x356790 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_12 0x356794 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_13 0x356798 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_14 0x35679C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AW_15 0x3567A0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_0 0x3567A4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_1 0x3567A8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_2 0x3567AC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_3 0x3567B0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_4 0x3567B4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_5 0x3567B8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_6 0x3567BC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_7 0x3567C0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_8 0x3567C4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_9 0x3567C8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_10 0x3567CC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_11 0x3567D0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_12 0x3567D4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_13 0x3567D8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_14 0x3567DC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AW_15 0x3567E0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_0 0x356824 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_1 0x356828 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_2 0x35682C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_3 0x356830 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_4 0x356834 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_5 0x356838 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_6 0x35683C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_7 0x356840 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_8 0x356844 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_9 0x356848 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_10 0x35684C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_11 0x356850 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_12 0x356854 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_13 0x356858 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_14 0x35685C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_LOW_AR_15 0x356860 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_0 0x356864 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_1 0x356868 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_2 0x35686C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_3 0x356870 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_4 0x356874 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_5 0x356878 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_6 0x35687C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_7 0x356880 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_8 0x356884 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_9 0x356888 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_10 0x35688C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_11 0x356890 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_12 0x356894 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_13 0x356898 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_14 0x35689C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_BASE_HIGH_AR_15 0x3568A0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_0 0x3568A4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_1 0x3568A8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_2 0x3568AC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_3 0x3568B0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_4 0x3568B4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_5 0x3568B8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_6 0x3568BC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_7 0x3568C0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_8 0x3568C4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_9 0x3568C8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_10 0x3568CC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_11 0x3568D0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_12 0x3568D4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_13 0x3568D8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_14 0x3568DC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_LOW_AR_15 0x3568E0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_0 0x3568E4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_1 0x3568E8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_2 0x3568EC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_3 0x3568F0 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_4 0x3568F4 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_5 0x3568F8 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_6 0x3568FC + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_7 0x356900 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_8 0x356904 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_9 0x356908 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_10 0x35690C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_11 0x356910 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_12 0x356914 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_13 0x356918 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_14 0x35691C + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_MASK_HIGH_AR_15 0x356920 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_0 0x356924 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_1 0x356928 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_2 0x35692C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_3 0x356930 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_4 0x356934 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_5 0x356938 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_6 0x35693C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_7 0x356940 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_8 0x356944 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_9 0x356948 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_10 0x35694C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_11 0x356950 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_12 0x356954 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_13 0x356958 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_14 0x35695C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_LOW_AR_15 0x356960 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_0 0x356964 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_1 0x356968 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_2 0x35696C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_3 0x356970 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_4 0x356974 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_5 0x356978 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_6 0x35697C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_7 0x356980 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_8 0x356984 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_9 0x356988 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_10 0x35698C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_11 0x356990 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_12 0x356994 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_13 0x356998 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_14 0x35699C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_BASE_HIGH_AR_15 0x3569A0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_0 0x3569A4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_1 0x3569A8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_2 0x3569AC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_3 0x3569B0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_4 0x3569B4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_5 0x3569B8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_6 0x3569BC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_7 0x3569C0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_8 0x3569C4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_9 0x3569C8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_10 0x3569CC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_11 0x3569D0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_12 0x3569D4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_13 0x3569D8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_14 0x3569DC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_LOW_AR_15 0x3569E0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_0 0x3569E4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_1 0x3569E8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_2 0x3569EC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_3 0x3569F0 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_4 0x3569F4 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_5 0x3569F8 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_6 0x3569FC + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_7 0x356A00 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_8 0x356A04 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_9 0x356A08 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_10 0x356A0C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_11 0x356A10 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_12 0x356A14 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_13 0x356A18 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_14 0x356A1C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_MASK_HIGH_AR_15 0x356A20 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AW 0x356A64 + +#define mmSIF_RTR_CTRL_5_RANGE_SEC_HIT_AR 0x356A68 + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AW 0x356A6C + +#define mmSIF_RTR_CTRL_5_RANGE_PRIV_HIT_AR 0x356A70 + +#define mmSIF_RTR_CTRL_5_RGL_CFG 0x356B64 + +#define mmSIF_RTR_CTRL_5_RGL_SHIFT 0x356B68 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_0 0x356B6C + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_1 0x356B70 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_2 0x356B74 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_3 0x356B78 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_4 0x356B7C + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_5 0x356B80 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_6 0x356B84 + +#define mmSIF_RTR_CTRL_5_RGL_EXPECTED_LAT_7 0x356B88 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_0 0x356BAC + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_1 0x356BB0 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_2 0x356BB4 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_3 0x356BB8 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_4 0x356BBC + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_5 0x356BC0 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_6 0x356BC4 + +#define mmSIF_RTR_CTRL_5_RGL_TOKEN_7 0x356BC8 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_0 0x356BEC + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_1 0x356BF0 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_2 0x356BF4 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_3 0x356BF8 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_4 0x356BFC + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_5 0x356C00 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_6 0x356C04 + +#define mmSIF_RTR_CTRL_5_RGL_BANK_ID_7 0x356C08 + +#define mmSIF_RTR_CTRL_5_RGL_WDT 0x356C2C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_WRAP 0x356C30 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_WRAP 0x356C34 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_WRAP 0x356C38 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_WRAP 0x356C3C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_WRAP 0x356C40 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_WRAP 0x356C44 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_WRAP 0x356C48 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_WRAP 0x356C4C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH0_CTR_CNT 0x356C50 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM0_CH1_CTR_CNT 0x356C54 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH0_CTR_CNT 0x356C58 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM1_CH1_CTR_CNT 0x356C5C + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH0_CTR_CNT 0x356C60 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM2_CH1_CTR_CNT 0x356C64 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH0_CTR_CNT 0x356C68 + +#define mmSIF_RTR_CTRL_5_E2E_AR_HBM3_CH1_CTR_CNT 0x356C6C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_WRAP 0x356C70 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_WRAP 0x356C74 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_WRAP 0x356C78 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_WRAP 0x356C7C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_WRAP 0x356C80 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_WRAP 0x356C84 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_WRAP 0x356C88 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_WRAP 0x356C8C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH0_CTR_CNT 0x356C90 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM0_CH1_CTR_CNT 0x356C94 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH0_CTR_CNT 0x356C98 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM1_CH1_CTR_CNT 0x356C9C + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH0_CTR_CNT 0x356CA0 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM2_CH1_CTR_CNT 0x356CA4 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH0_CTR_CNT 0x356CA8 + +#define mmSIF_RTR_CTRL_5_E2E_AW_HBM3_CH1_CTR_CNT 0x356CAC + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_0 0x356CB0 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_1 0x356CB4 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_2 0x356CB8 + +#define mmSIF_RTR_CTRL_5_NL_HBM_PC_SEL_3 0x356CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_5_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h new file mode 100644 index 000000000000..a9ea89aa6405 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_6_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_6 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_6_PERM_SEL 0x366108 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_0 0x366114 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_1 0x366118 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_2 0x36611C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_3 0x366120 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_4 0x366124 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_5 0x366128 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_6 0x36612C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_7 0x366130 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_8 0x366134 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_9 0x366138 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_10 0x36613C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_11 0x366140 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_12 0x366144 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_13 0x366148 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_14 0x36614C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_15 0x366150 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_16 0x366154 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_17 0x366158 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_18 0x36615C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_19 0x366160 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_20 0x366164 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_21 0x366168 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_22 0x36616C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_23 0x366170 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_24 0x366174 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_25 0x366178 + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_26 0x36617C + +#define mmSIF_RTR_CTRL_6_HBM_POLY_H3_27 0x366180 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_0 0x366184 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_1 0x366188 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_2 0x36618C + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_3 0x366190 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_4 0x366194 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_5 0x366198 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_6 0x36619C + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_7 0x3661A0 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_8 0x3661A4 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_9 0x3661A8 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_10 0x3661AC + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_11 0x3661B0 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_12 0x3661B4 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_13 0x3661B8 + +#define mmSIF_RTR_CTRL_6_SRAM_POLY_H3_14 0x3661BC + +#define mmSIF_RTR_CTRL_6_SCRAM_SRAM_EN 0x36626C + +#define mmSIF_RTR_CTRL_6_RL_HBM_EN 0x366274 + +#define mmSIF_RTR_CTRL_6_RL_HBM_SAT 0x366278 + +#define mmSIF_RTR_CTRL_6_RL_HBM_RST 0x36627C + +#define mmSIF_RTR_CTRL_6_RL_HBM_TIMEOUT 0x366280 + +#define mmSIF_RTR_CTRL_6_SCRAM_HBM_EN 0x366284 + +#define mmSIF_RTR_CTRL_6_RL_PCI_EN 0x366288 + +#define mmSIF_RTR_CTRL_6_RL_PCI_SAT 0x36628C + +#define mmSIF_RTR_CTRL_6_RL_PCI_RST 0x366290 + +#define mmSIF_RTR_CTRL_6_RL_PCI_TIMEOUT 0x366294 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_EN 0x36629C + +#define mmSIF_RTR_CTRL_6_RL_SRAM_SAT 0x3662A0 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_RST 0x3662A4 + +#define mmSIF_RTR_CTRL_6_RL_SRAM_TIMEOUT 0x3662AC + +#define mmSIF_RTR_CTRL_6_RL_SRAM_RED 0x3662B4 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_EN 0x3662EC + +#define mmSIF_RTR_CTRL_6_E2E_PCI_EN 0x3662F0 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_WR_SIZE 0x3662F4 + +#define mmSIF_RTR_CTRL_6_E2E_PCI_WR_SIZE 0x3662F8 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET_EN 0x366404 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_SET 0x366408 + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_WRAP 0x36640C + +#define mmSIF_RTR_CTRL_6_E2E_AW_PCI_CTR_CNT 0x366410 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET_EN 0x366414 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM_CTR_SET 0x366418 + +#define mmSIF_RTR_CTRL_6_E2E_HBM_RD_SIZE 0x36641C + +#define mmSIF_RTR_CTRL_6_E2E_PCI_RD_SIZE 0x366420 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET_EN 0x366424 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_SET 0x366428 + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_WRAP 0x36642C + +#define mmSIF_RTR_CTRL_6_E2E_AR_PCI_CTR_CNT 0x366430 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET_EN 0x366434 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM_CTR_SET 0x366438 + +#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_0 0x366450 + +#define mmSIF_RTR_CTRL_6_NL_HBM_SEL_1 0x366454 + +#define mmSIF_RTR_CTRL_6_NON_LIN_EN 0x366480 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_0 0x366500 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_1 0x366504 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_2 0x366508 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_3 0x36650C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_BANK_4 0x366510 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_0 0x366514 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_1 0x366520 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_2 0x366524 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_3 0x366528 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_4 0x36652C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_5 0x366530 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_6 0x366534 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_7 0x366538 + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_8 0x36653C + +#define mmSIF_RTR_CTRL_6_NL_SRAM_OFFSET_9 0x366540 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_0 0x366550 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_1 0x366554 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_2 0x366558 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_3 0x36655C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_4 0x366560 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_5 0x366564 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_6 0x366568 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_7 0x36656C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_8 0x366570 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_9 0x366574 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_10 0x366578 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_11 0x36657C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_12 0x366580 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_13 0x366584 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_14 0x366588 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_15 0x36658C + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_16 0x366590 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_17 0x366594 + +#define mmSIF_RTR_CTRL_6_NL_HBM_OFFSET_18 0x366598 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_0 0x3665E4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_1 0x3665E8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_2 0x3665EC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_3 0x3665F0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_4 0x3665F4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_5 0x3665F8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_6 0x3665FC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_7 0x366600 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_8 0x366604 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_9 0x366608 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_10 0x36660C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_11 0x366610 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_12 0x366614 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_13 0x366618 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_14 0x36661C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AW_15 0x366620 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_0 0x366624 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_1 0x366628 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_2 0x36662C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_3 0x366630 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_4 0x366634 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_5 0x366638 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_6 0x36663C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_7 0x366640 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_8 0x366644 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_9 0x366648 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_10 0x36664C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_11 0x366650 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_12 0x366654 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_13 0x366658 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_14 0x36665C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AW_15 0x366660 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_0 0x366664 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_1 0x366668 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_2 0x36666C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_3 0x366670 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_4 0x366674 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_5 0x366678 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_6 0x36667C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_7 0x366680 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_8 0x366684 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_9 0x366688 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_10 0x36668C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_11 0x366690 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_12 0x366694 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_13 0x366698 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_14 0x36669C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AW_15 0x3666A0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_0 0x3666A4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_1 0x3666A8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_2 0x3666AC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_3 0x3666B0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_4 0x3666B4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_5 0x3666B8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_6 0x3666BC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_7 0x3666C0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_8 0x3666C4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_9 0x3666C8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_10 0x3666CC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_11 0x3666D0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_12 0x3666D4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_13 0x3666D8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_14 0x3666DC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AW_15 0x3666E0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_0 0x3666E4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_1 0x3666E8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_2 0x3666EC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_3 0x3666F0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_4 0x3666F4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_5 0x3666F8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_6 0x3666FC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_7 0x366700 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_8 0x366704 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_9 0x366708 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_10 0x36670C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_11 0x366710 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_12 0x366714 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_13 0x366718 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_14 0x36671C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AW_15 0x366720 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_0 0x366724 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_1 0x366728 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_2 0x36672C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_3 0x366730 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_4 0x366734 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_5 0x366738 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_6 0x36673C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_7 0x366740 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_8 0x366744 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_9 0x366748 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_10 0x36674C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_11 0x366750 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_12 0x366754 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_13 0x366758 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_14 0x36675C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AW_15 0x366760 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_0 0x366764 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_1 0x366768 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_2 0x36676C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_3 0x366770 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_4 0x366774 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_5 0x366778 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_6 0x36677C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_7 0x366780 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_8 0x366784 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_9 0x366788 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_10 0x36678C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_11 0x366790 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_12 0x366794 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_13 0x366798 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_14 0x36679C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AW_15 0x3667A0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_0 0x3667A4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_1 0x3667A8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_2 0x3667AC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_3 0x3667B0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_4 0x3667B4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_5 0x3667B8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_6 0x3667BC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_7 0x3667C0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_8 0x3667C4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_9 0x3667C8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_10 0x3667CC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_11 0x3667D0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_12 0x3667D4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_13 0x3667D8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_14 0x3667DC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AW_15 0x3667E0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_0 0x366824 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_1 0x366828 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_2 0x36682C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_3 0x366830 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_4 0x366834 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_5 0x366838 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_6 0x36683C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_7 0x366840 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_8 0x366844 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_9 0x366848 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_10 0x36684C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_11 0x366850 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_12 0x366854 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_13 0x366858 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_14 0x36685C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_LOW_AR_15 0x366860 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_0 0x366864 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_1 0x366868 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_2 0x36686C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_3 0x366870 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_4 0x366874 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_5 0x366878 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_6 0x36687C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_7 0x366880 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_8 0x366884 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_9 0x366888 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_10 0x36688C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_11 0x366890 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_12 0x366894 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_13 0x366898 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_14 0x36689C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_BASE_HIGH_AR_15 0x3668A0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_0 0x3668A4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_1 0x3668A8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_2 0x3668AC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_3 0x3668B0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_4 0x3668B4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_5 0x3668B8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_6 0x3668BC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_7 0x3668C0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_8 0x3668C4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_9 0x3668C8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_10 0x3668CC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_11 0x3668D0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_12 0x3668D4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_13 0x3668D8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_14 0x3668DC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_LOW_AR_15 0x3668E0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_0 0x3668E4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_1 0x3668E8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_2 0x3668EC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_3 0x3668F0 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_4 0x3668F4 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_5 0x3668F8 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_6 0x3668FC + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_7 0x366900 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_8 0x366904 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_9 0x366908 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_10 0x36690C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_11 0x366910 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_12 0x366914 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_13 0x366918 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_14 0x36691C + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_MASK_HIGH_AR_15 0x366920 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_0 0x366924 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_1 0x366928 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_2 0x36692C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_3 0x366930 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_4 0x366934 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_5 0x366938 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_6 0x36693C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_7 0x366940 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_8 0x366944 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_9 0x366948 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_10 0x36694C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_11 0x366950 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_12 0x366954 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_13 0x366958 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_14 0x36695C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_LOW_AR_15 0x366960 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_0 0x366964 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_1 0x366968 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_2 0x36696C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_3 0x366970 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_4 0x366974 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_5 0x366978 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_6 0x36697C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_7 0x366980 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_8 0x366984 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_9 0x366988 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_10 0x36698C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_11 0x366990 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_12 0x366994 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_13 0x366998 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_14 0x36699C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_BASE_HIGH_AR_15 0x3669A0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_0 0x3669A4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_1 0x3669A8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_2 0x3669AC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_3 0x3669B0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_4 0x3669B4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_5 0x3669B8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_6 0x3669BC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_7 0x3669C0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_8 0x3669C4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_9 0x3669C8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_10 0x3669CC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_11 0x3669D0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_12 0x3669D4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_13 0x3669D8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_14 0x3669DC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_LOW_AR_15 0x3669E0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_0 0x3669E4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_1 0x3669E8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_2 0x3669EC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_3 0x3669F0 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_4 0x3669F4 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_5 0x3669F8 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_6 0x3669FC + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_7 0x366A00 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_8 0x366A04 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_9 0x366A08 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_10 0x366A0C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_11 0x366A10 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_12 0x366A14 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_13 0x366A18 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_14 0x366A1C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_MASK_HIGH_AR_15 0x366A20 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AW 0x366A64 + +#define mmSIF_RTR_CTRL_6_RANGE_SEC_HIT_AR 0x366A68 + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AW 0x366A6C + +#define mmSIF_RTR_CTRL_6_RANGE_PRIV_HIT_AR 0x366A70 + +#define mmSIF_RTR_CTRL_6_RGL_CFG 0x366B64 + +#define mmSIF_RTR_CTRL_6_RGL_SHIFT 0x366B68 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_0 0x366B6C + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_1 0x366B70 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_2 0x366B74 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_3 0x366B78 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_4 0x366B7C + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_5 0x366B80 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_6 0x366B84 + +#define mmSIF_RTR_CTRL_6_RGL_EXPECTED_LAT_7 0x366B88 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_0 0x366BAC + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_1 0x366BB0 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_2 0x366BB4 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_3 0x366BB8 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_4 0x366BBC + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_5 0x366BC0 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_6 0x366BC4 + +#define mmSIF_RTR_CTRL_6_RGL_TOKEN_7 0x366BC8 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_0 0x366BEC + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_1 0x366BF0 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_2 0x366BF4 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_3 0x366BF8 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_4 0x366BFC + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_5 0x366C00 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_6 0x366C04 + +#define mmSIF_RTR_CTRL_6_RGL_BANK_ID_7 0x366C08 + +#define mmSIF_RTR_CTRL_6_RGL_WDT 0x366C2C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_WRAP 0x366C30 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_WRAP 0x366C34 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_WRAP 0x366C38 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_WRAP 0x366C3C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_WRAP 0x366C40 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_WRAP 0x366C44 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_WRAP 0x366C48 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_WRAP 0x366C4C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH0_CTR_CNT 0x366C50 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM0_CH1_CTR_CNT 0x366C54 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH0_CTR_CNT 0x366C58 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM1_CH1_CTR_CNT 0x366C5C + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH0_CTR_CNT 0x366C60 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM2_CH1_CTR_CNT 0x366C64 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH0_CTR_CNT 0x366C68 + +#define mmSIF_RTR_CTRL_6_E2E_AR_HBM3_CH1_CTR_CNT 0x366C6C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_WRAP 0x366C70 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_WRAP 0x366C74 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_WRAP 0x366C78 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_WRAP 0x366C7C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_WRAP 0x366C80 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_WRAP 0x366C84 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_WRAP 0x366C88 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_WRAP 0x366C8C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH0_CTR_CNT 0x366C90 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM0_CH1_CTR_CNT 0x366C94 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH0_CTR_CNT 0x366C98 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM1_CH1_CTR_CNT 0x366C9C + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH0_CTR_CNT 0x366CA0 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM2_CH1_CTR_CNT 0x366CA4 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH0_CTR_CNT 0x366CA8 + +#define mmSIF_RTR_CTRL_6_E2E_AW_HBM3_CH1_CTR_CNT 0x366CAC + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_0 0x366CB0 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_1 0x366CB4 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_2 0x366CB8 + +#define mmSIF_RTR_CTRL_6_NL_HBM_PC_SEL_3 0x366CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_6_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h new file mode 100644 index 000000000000..a37772c531d9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/sif_rtr_ctrl_7_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ +#define ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ + +/* + ***************************************** + * SIF_RTR_CTRL_7 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmSIF_RTR_CTRL_7_PERM_SEL 0x376108 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_0 0x376114 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_1 0x376118 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_2 0x37611C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_3 0x376120 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_4 0x376124 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_5 0x376128 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_6 0x37612C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_7 0x376130 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_8 0x376134 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_9 0x376138 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_10 0x37613C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_11 0x376140 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_12 0x376144 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_13 0x376148 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_14 0x37614C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_15 0x376150 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_16 0x376154 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_17 0x376158 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_18 0x37615C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_19 0x376160 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_20 0x376164 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_21 0x376168 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_22 0x37616C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_23 0x376170 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_24 0x376174 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_25 0x376178 + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_26 0x37617C + +#define mmSIF_RTR_CTRL_7_HBM_POLY_H3_27 0x376180 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_0 0x376184 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_1 0x376188 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_2 0x37618C + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_3 0x376190 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_4 0x376194 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_5 0x376198 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_6 0x37619C + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_7 0x3761A0 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_8 0x3761A4 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_9 0x3761A8 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_10 0x3761AC + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_11 0x3761B0 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_12 0x3761B4 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_13 0x3761B8 + +#define mmSIF_RTR_CTRL_7_SRAM_POLY_H3_14 0x3761BC + +#define mmSIF_RTR_CTRL_7_SCRAM_SRAM_EN 0x37626C + +#define mmSIF_RTR_CTRL_7_RL_HBM_EN 0x376274 + +#define mmSIF_RTR_CTRL_7_RL_HBM_SAT 0x376278 + +#define mmSIF_RTR_CTRL_7_RL_HBM_RST 0x37627C + +#define mmSIF_RTR_CTRL_7_RL_HBM_TIMEOUT 0x376280 + +#define mmSIF_RTR_CTRL_7_SCRAM_HBM_EN 0x376284 + +#define mmSIF_RTR_CTRL_7_RL_PCI_EN 0x376288 + +#define mmSIF_RTR_CTRL_7_RL_PCI_SAT 0x37628C + +#define mmSIF_RTR_CTRL_7_RL_PCI_RST 0x376290 + +#define mmSIF_RTR_CTRL_7_RL_PCI_TIMEOUT 0x376294 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_EN 0x37629C + +#define mmSIF_RTR_CTRL_7_RL_SRAM_SAT 0x3762A0 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_RST 0x3762A4 + +#define mmSIF_RTR_CTRL_7_RL_SRAM_TIMEOUT 0x3762AC + +#define mmSIF_RTR_CTRL_7_RL_SRAM_RED 0x3762B4 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_EN 0x3762EC + +#define mmSIF_RTR_CTRL_7_E2E_PCI_EN 0x3762F0 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_WR_SIZE 0x3762F4 + +#define mmSIF_RTR_CTRL_7_E2E_PCI_WR_SIZE 0x3762F8 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET_EN 0x376404 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_SET 0x376408 + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_WRAP 0x37640C + +#define mmSIF_RTR_CTRL_7_E2E_AW_PCI_CTR_CNT 0x376410 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET_EN 0x376414 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM_CTR_SET 0x376418 + +#define mmSIF_RTR_CTRL_7_E2E_HBM_RD_SIZE 0x37641C + +#define mmSIF_RTR_CTRL_7_E2E_PCI_RD_SIZE 0x376420 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET_EN 0x376424 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_SET 0x376428 + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_WRAP 0x37642C + +#define mmSIF_RTR_CTRL_7_E2E_AR_PCI_CTR_CNT 0x376430 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET_EN 0x376434 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM_CTR_SET 0x376438 + +#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_0 0x376450 + +#define mmSIF_RTR_CTRL_7_NL_HBM_SEL_1 0x376454 + +#define mmSIF_RTR_CTRL_7_NON_LIN_EN 0x376480 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_0 0x376500 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_1 0x376504 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_2 0x376508 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_3 0x37650C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_BANK_4 0x376510 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_0 0x376514 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_1 0x376520 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_2 0x376524 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_3 0x376528 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_4 0x37652C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_5 0x376530 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_6 0x376534 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_7 0x376538 + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_8 0x37653C + +#define mmSIF_RTR_CTRL_7_NL_SRAM_OFFSET_9 0x376540 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_0 0x376550 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_1 0x376554 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_2 0x376558 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_3 0x37655C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_4 0x376560 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_5 0x376564 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_6 0x376568 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_7 0x37656C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_8 0x376570 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_9 0x376574 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_10 0x376578 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_11 0x37657C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_12 0x376580 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_13 0x376584 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_14 0x376588 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_15 0x37658C + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_16 0x376590 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_17 0x376594 + +#define mmSIF_RTR_CTRL_7_NL_HBM_OFFSET_18 0x376598 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_0 0x3765E4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_1 0x3765E8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_2 0x3765EC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_3 0x3765F0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_4 0x3765F4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_5 0x3765F8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_6 0x3765FC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_7 0x376600 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_8 0x376604 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_9 0x376608 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_10 0x37660C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_11 0x376610 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_12 0x376614 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_13 0x376618 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_14 0x37661C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AW_15 0x376620 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_0 0x376624 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_1 0x376628 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_2 0x37662C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_3 0x376630 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_4 0x376634 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_5 0x376638 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_6 0x37663C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_7 0x376640 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_8 0x376644 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_9 0x376648 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_10 0x37664C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_11 0x376650 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_12 0x376654 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_13 0x376658 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_14 0x37665C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AW_15 0x376660 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_0 0x376664 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_1 0x376668 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_2 0x37666C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_3 0x376670 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_4 0x376674 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_5 0x376678 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_6 0x37667C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_7 0x376680 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_8 0x376684 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_9 0x376688 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_10 0x37668C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_11 0x376690 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_12 0x376694 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_13 0x376698 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_14 0x37669C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AW_15 0x3766A0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_0 0x3766A4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_1 0x3766A8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_2 0x3766AC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_3 0x3766B0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_4 0x3766B4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_5 0x3766B8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_6 0x3766BC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_7 0x3766C0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_8 0x3766C4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_9 0x3766C8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_10 0x3766CC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_11 0x3766D0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_12 0x3766D4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_13 0x3766D8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_14 0x3766DC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AW_15 0x3766E0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_0 0x3766E4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_1 0x3766E8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_2 0x3766EC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_3 0x3766F0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_4 0x3766F4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_5 0x3766F8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_6 0x3766FC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_7 0x376700 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_8 0x376704 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_9 0x376708 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_10 0x37670C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_11 0x376710 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_12 0x376714 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_13 0x376718 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_14 0x37671C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AW_15 0x376720 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_0 0x376724 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_1 0x376728 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_2 0x37672C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_3 0x376730 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_4 0x376734 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_5 0x376738 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_6 0x37673C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_7 0x376740 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_8 0x376744 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_9 0x376748 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_10 0x37674C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_11 0x376750 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_12 0x376754 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_13 0x376758 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_14 0x37675C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AW_15 0x376760 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_0 0x376764 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_1 0x376768 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_2 0x37676C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_3 0x376770 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_4 0x376774 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_5 0x376778 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_6 0x37677C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_7 0x376780 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_8 0x376784 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_9 0x376788 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_10 0x37678C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_11 0x376790 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_12 0x376794 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_13 0x376798 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_14 0x37679C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AW_15 0x3767A0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_0 0x3767A4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_1 0x3767A8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_2 0x3767AC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_3 0x3767B0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_4 0x3767B4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_5 0x3767B8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_6 0x3767BC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_7 0x3767C0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_8 0x3767C4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_9 0x3767C8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_10 0x3767CC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_11 0x3767D0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_12 0x3767D4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_13 0x3767D8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_14 0x3767DC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AW_15 0x3767E0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_0 0x376824 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_1 0x376828 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_2 0x37682C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_3 0x376830 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_4 0x376834 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_5 0x376838 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_6 0x37683C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_7 0x376840 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_8 0x376844 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_9 0x376848 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_10 0x37684C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_11 0x376850 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_12 0x376854 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_13 0x376858 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_14 0x37685C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_LOW_AR_15 0x376860 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_0 0x376864 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_1 0x376868 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_2 0x37686C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_3 0x376870 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_4 0x376874 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_5 0x376878 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_6 0x37687C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_7 0x376880 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_8 0x376884 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_9 0x376888 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_10 0x37688C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_11 0x376890 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_12 0x376894 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_13 0x376898 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_14 0x37689C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_BASE_HIGH_AR_15 0x3768A0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_0 0x3768A4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_1 0x3768A8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_2 0x3768AC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_3 0x3768B0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_4 0x3768B4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_5 0x3768B8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_6 0x3768BC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_7 0x3768C0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_8 0x3768C4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_9 0x3768C8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_10 0x3768CC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_11 0x3768D0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_12 0x3768D4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_13 0x3768D8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_14 0x3768DC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_LOW_AR_15 0x3768E0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_0 0x3768E4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_1 0x3768E8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_2 0x3768EC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_3 0x3768F0 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_4 0x3768F4 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_5 0x3768F8 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_6 0x3768FC + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_7 0x376900 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_8 0x376904 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_9 0x376908 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_10 0x37690C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_11 0x376910 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_12 0x376914 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_13 0x376918 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_14 0x37691C + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_MASK_HIGH_AR_15 0x376920 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_0 0x376924 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_1 0x376928 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_2 0x37692C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_3 0x376930 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_4 0x376934 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_5 0x376938 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_6 0x37693C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_7 0x376940 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_8 0x376944 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_9 0x376948 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_10 0x37694C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_11 0x376950 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_12 0x376954 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_13 0x376958 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_14 0x37695C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_LOW_AR_15 0x376960 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_0 0x376964 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_1 0x376968 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_2 0x37696C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_3 0x376970 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_4 0x376974 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_5 0x376978 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_6 0x37697C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_7 0x376980 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_8 0x376984 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_9 0x376988 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_10 0x37698C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_11 0x376990 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_12 0x376994 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_13 0x376998 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_14 0x37699C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_BASE_HIGH_AR_15 0x3769A0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_0 0x3769A4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_1 0x3769A8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_2 0x3769AC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_3 0x3769B0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_4 0x3769B4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_5 0x3769B8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_6 0x3769BC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_7 0x3769C0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_8 0x3769C4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_9 0x3769C8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_10 0x3769CC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_11 0x3769D0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_12 0x3769D4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_13 0x3769D8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_14 0x3769DC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_LOW_AR_15 0x3769E0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_0 0x3769E4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_1 0x3769E8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_2 0x3769EC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_3 0x3769F0 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_4 0x3769F4 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_5 0x3769F8 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_6 0x3769FC + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_7 0x376A00 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_8 0x376A04 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_9 0x376A08 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_10 0x376A0C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_11 0x376A10 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_12 0x376A14 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_13 0x376A18 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_14 0x376A1C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_MASK_HIGH_AR_15 0x376A20 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AW 0x376A64 + +#define mmSIF_RTR_CTRL_7_RANGE_SEC_HIT_AR 0x376A68 + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AW 0x376A6C + +#define mmSIF_RTR_CTRL_7_RANGE_PRIV_HIT_AR 0x376A70 + +#define mmSIF_RTR_CTRL_7_RGL_CFG 0x376B64 + +#define mmSIF_RTR_CTRL_7_RGL_SHIFT 0x376B68 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_0 0x376B6C + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_1 0x376B70 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_2 0x376B74 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_3 0x376B78 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_4 0x376B7C + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_5 0x376B80 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_6 0x376B84 + +#define mmSIF_RTR_CTRL_7_RGL_EXPECTED_LAT_7 0x376B88 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_0 0x376BAC + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_1 0x376BB0 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_2 0x376BB4 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_3 0x376BB8 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_4 0x376BBC + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_5 0x376BC0 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_6 0x376BC4 + +#define mmSIF_RTR_CTRL_7_RGL_TOKEN_7 0x376BC8 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_0 0x376BEC + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_1 0x376BF0 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_2 0x376BF4 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_3 0x376BF8 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_4 0x376BFC + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_5 0x376C00 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_6 0x376C04 + +#define mmSIF_RTR_CTRL_7_RGL_BANK_ID_7 0x376C08 + +#define mmSIF_RTR_CTRL_7_RGL_WDT 0x376C2C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_WRAP 0x376C30 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_WRAP 0x376C34 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_WRAP 0x376C38 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_WRAP 0x376C3C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_WRAP 0x376C40 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_WRAP 0x376C44 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_WRAP 0x376C48 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_WRAP 0x376C4C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH0_CTR_CNT 0x376C50 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM0_CH1_CTR_CNT 0x376C54 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH0_CTR_CNT 0x376C58 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM1_CH1_CTR_CNT 0x376C5C + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH0_CTR_CNT 0x376C60 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM2_CH1_CTR_CNT 0x376C64 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH0_CTR_CNT 0x376C68 + +#define mmSIF_RTR_CTRL_7_E2E_AR_HBM3_CH1_CTR_CNT 0x376C6C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_WRAP 0x376C70 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_WRAP 0x376C74 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_WRAP 0x376C78 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_WRAP 0x376C7C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_WRAP 0x376C80 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_WRAP 0x376C84 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_WRAP 0x376C88 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_WRAP 0x376C8C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH0_CTR_CNT 0x376C90 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM0_CH1_CTR_CNT 0x376C94 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH0_CTR_CNT 0x376C98 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM1_CH1_CTR_CNT 0x376C9C + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH0_CTR_CNT 0x376CA0 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM2_CH1_CTR_CNT 0x376CA4 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH0_CTR_CNT 0x376CA8 + +#define mmSIF_RTR_CTRL_7_E2E_AW_HBM3_CH1_CTR_CNT 0x376CAC + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_0 0x376CB0 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_1 0x376CB4 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_2 0x376CB8 + +#define mmSIF_RTR_CTRL_7_NL_HBM_PC_SEL_3 0x376CBC + +#endif /* ASIC_REG_SIF_RTR_CTRL_7_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h new file mode 100644 index 000000000000..07d2a9000102 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/stlb_regs.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_STLB_REGS_H_ +#define ASIC_REG_STLB_REGS_H_ + +/* + ***************************************** + * STLB (Prototype: STLB) + ***************************************** + */ + +#define mmSTLB_CACHE_INV 0xC12010 + +#define mmSTLB_CACHE_INV_BASE_39_8 0xC12014 + +#define mmSTLB_CACHE_INV_BASE_49_40 0xC12018 + +#define mmSTLB_STLB_FEATURE_EN 0xC1201C + +#define mmSTLB_STLB_AXI_CACHE 0xC12020 + +#define mmSTLB_HOP_CONFIGURATION 0xC12024 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_49_32 0xC12028 + +#define mmSTLB_LINK_LIST_LOOKUP_MASK_31_0 0xC1202C + +#define mmSTLB_LINK_LIST 0xC12030 + +#define mmSTLB_INV_ALL_START 0xC12034 + +#define mmSTLB_INV_ALL_SET 0xC12038 + +#define mmSTLB_INV_PS 0xC1203C + +#define mmSTLB_INV_CONSUMER_INDEX 0xC12040 + +#define mmSTLB_INV_HIT_COUNT 0xC12044 + +#define mmSTLB_INV_SET 0xC12048 + +#define mmSTLB_SRAM_INIT 0xC1204C + +#define mmSTLB_MEM_CACHE_INVALIDATION 0xC12050 + +#define mmSTLB_MEM_CACHE_INV_STATUS 0xC12054 + +#define mmSTLB_MEM_CACHE_BASE_38_7 0xC12058 + +#define mmSTLB_MEM_CACHE_BASE_49_39 0xC1205C + +#define mmSTLB_MEM_CACHE_CONFIG 0xC12060 + +#define mmSTLB_SET_THRESHOLD_HOP4 0xC12064 + +#define mmSTLB_SET_THRESHOLD_HOP3 0xC12068 + +#define mmSTLB_SET_THRESHOLD_HOP2 0xC1206C + +#define mmSTLB_SET_THRESHOLD_HOP1 0xC12070 + +#define mmSTLB_SET_THRESHOLD_HOP0 0xC12074 + +#define mmSTLB_MULTI_HIT_INTERRUPT_CLR 0xC12078 + +#define mmSTLB_MULTI_HIT_INTERRUPT_MASK 0xC1207C + +#define mmSTLB_MEM_L0_CACHE_CFG 0xC12080 + +#define mmSTLB_MEM_READ_ARPROT 0xC12084 + +#endif /* ASIC_REG_STLB_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h new file mode 100644 index 000000000000..8f67c11c8de9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_masks.h @@ -0,0 +1,2578 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_MASKS_H_ +#define ASIC_REG_TPC0_CFG_MASKS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */ +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */ +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */ +#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */ +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */ +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +/* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */ +#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */ +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_KERNEL_KERNEL_CONFIG */ +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 + +/* TPC0_CFG_KERNEL_KERNEL_ID */ +#define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT 0 +#define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK 0xFFFF + +/* TPC0_CFG_KERNEL_SRF */ +#define TPC0_CFG_KERNEL_SRF_V_SHIFT 0 +#define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ROUND_CSR */ +#define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 +#define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 + +/* TPC0_CFG_PROT */ +#define TPC0_CFG_PROT_AWPROT_SHIFT 0 +#define TPC0_CFG_PROT_AWPROT_MASK 0x7 +#define TPC0_CFG_PROT_ARPROT_SHIFT 3 +#define TPC0_CFG_PROT_ARPROT_MASK 0x38 + +/* TPC0_CFG_SEMAPHORE */ +#define TPC0_CFG_SEMAPHORE_V_SHIFT 0 +#define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_VFLAGS */ +#define TPC0_CFG_VFLAGS_V_SHIFT 0 +#define TPC0_CFG_VFLAGS_V_MASK 0xF + +/* TPC0_CFG_SFLAGS */ +#define TPC0_CFG_SFLAGS_V_SHIFT 0 +#define TPC0_CFG_SFLAGS_V_MASK 0xF + +/* TPC0_CFG_LFSR_POLYNOM */ +#define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 +#define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_STATUS */ +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 +#define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 +#define TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 +#define TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 +#define TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 +#define TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 +#define TPC0_CFG_STATUS_QM_RDY_SHIFT 7 +#define TPC0_CFG_STATUS_QM_RDY_MASK 0x80 + +/* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_CFG_SUBTRACT_VALUE */ +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_SM_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TPC_CMD */ +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 +#define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 + +/* TPC0_CFG_TPC_EXECUTE */ +#define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 +#define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 + +/* TPC0_CFG_TPC_STALL */ +#define TPC0_CFG_TPC_STALL_V_SHIFT 0 +#define TPC0_CFG_TPC_STALL_V_MASK 0x1 + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_RD_RATE_LIMIT */ +#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 +#define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 +#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 +#define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE +#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* TPC0_CFG_WR_RATE_LIMIT */ +#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 +#define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 +#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 +#define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE +#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +/* TPC0_CFG_MSS_CONFIG */ +#define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 +#define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF +#define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 +#define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 +#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 +#define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 + +/* TPC0_CFG_TPC_INTR_CAUSE */ +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFF + +/* TPC0_CFG_TPC_INTR_MASK */ +#define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 +#define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFF + +/* TPC0_CFG_WQ_CREDITS */ +#define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 +#define TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF +#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 +#define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 + +/* TPC0_CFG_ARUSER_LO */ +#define TPC0_CFG_ARUSER_LO_V_SHIFT 0 +#define TPC0_CFG_ARUSER_LO_V_MASK 0x7FF + +/* TPC0_CFG_ARUSER_HI */ +#define TPC0_CFG_ARUSER_HI_V_SHIFT 11 +#define TPC0_CFG_ARUSER_HI_V_MASK 0x1800 +#define TPC0_CFG_ARUSER_HI_RSRV_SHIFT 13 +#define TPC0_CFG_ARUSER_HI_RSRV_MASK 0xFFFFE000 + +/* TPC0_CFG_AWUSER_LO */ +#define TPC0_CFG_AWUSER_LO_V_SHIFT 0 +#define TPC0_CFG_AWUSER_LO_V_MASK 0x7FF + +/* TPC0_CFG_AWUSER_HI */ +#define TPC0_CFG_AWUSER_HI_V_SHIFT 11 +#define TPC0_CFG_AWUSER_HI_V_MASK 0x1800 +#define TPC0_CFG_AWUSER_HI_RSRV_SHIFT 13 +#define TPC0_CFG_AWUSER_HI_RSRV_MASK 0xFFFFE000 + +/* TPC0_CFG_OPCODE_EXEC */ +#define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 +#define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F +#define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 +#define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 +#define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 +#define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 +#define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 +#define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 +#define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 +#define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 +#define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 +#define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 +#define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 +#define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 +#define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 +#define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 + +/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 +#define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_TSB_CFG_MAX_SIZE */ +#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 +#define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF +#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 +#define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 + +/* TPC0_CFG_TSB_CFG */ +#define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT 0 +#define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK 0x1 +#define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 +#define TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE + +/* TPC0_CFG_DBGMEM_ADD */ +#define TPC0_CFG_DBGMEM_ADD_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_ADD_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_DATA_WR */ +#define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_DATA_RD */ +#define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT 0 +#define TPC0_CFG_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_DBGMEM_CTRL */ +#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT 0 +#define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK 0x1 + +/* TPC0_CFG_DBGMEM_RC */ +#define TPC0_CFG_DBGMEM_RC_VALID_SHIFT 0 +#define TPC0_CFG_DBGMEM_RC_VALID_MASK 0x1 + +/* TPC0_CFG_TSB_INFLIGHT_CNTR */ +#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 +#define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_WQ_INFLIGHT_CNTR */ +#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 +#define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF +#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 +#define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0xF0000 + +/* TPC0_CFG_WQ_LBW_TOTAL_CNTR */ +#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 +#define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_WQ_HBW_TOTAL_CNTR */ +#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 +#define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_IRQ_OCCOUPY_CNTR */ +#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 +#define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_FUNC_MBIST_CNTRL */ +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 1 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x4 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF0000 + +/* TPC0_CFG_FUNC_MBIST_PAT */ +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x3 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 2 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 4 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x30 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 6 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC0 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 8 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x300 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 10 +#define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC00 + +/* TPC0_CFG_FUNC_MBIST_MEM */ +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 0 +#define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 12 +#define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x7000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 16 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF0000 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 28 +#define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x70000000 + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */ +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */ +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */ +#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */ +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 + +/* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */ +#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */ +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +/* TPC0_CFG_QM_SYNC_OBJECT_ADDR */ +#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */ +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_0 */ +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_0 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_1 */ +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_1 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_2 */ +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_2 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_3 */ +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_3 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_BASE_DIM_4 */ +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_TID_SIZE_DIM_4 */ +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 0 +#define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +/* TPC0_CFG_QM_KERNEL_CONFIG */ +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 + +/* TPC0_CFG_QM_KERNEL_ID */ +#define TPC0_CFG_QM_KERNEL_ID_V_SHIFT 0 +#define TPC0_CFG_QM_KERNEL_ID_V_MASK 0xFFFF + +/* TPC0_CFG_QM_SRF */ +#define TPC0_CFG_QM_SRF_V_SHIFT 0 +#define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF + +#endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h new file mode 100644 index 000000000000..b82a906265a8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_CFG_REGS_H_ +#define ASIC_REG_TPC0_CFG_REGS_H_ + +/* + ***************************************** + * TPC0_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE06400 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE06404 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE06408 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE0640C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE06410 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE06414 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE06418 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE0641C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE06420 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE06424 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE06428 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE0642C + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE06430 + +#define mmTPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE06434 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE06438 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE0643C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE06440 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE06444 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE06448 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE0644C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE06450 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE06454 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE06458 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE0645C + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE06460 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE06464 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE06468 + +#define mmTPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE0646C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE06470 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE06474 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE06478 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE0647C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE06480 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE06484 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE06488 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE0648C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE06490 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE06494 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE06498 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE0649C + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE064A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE064A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE064A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE064AC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE064B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE064B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE064B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE064BC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE064C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE064C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE064C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE064CC + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE064D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE064D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE064D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE064DC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE064E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE064E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE064E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE064EC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE064F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE064F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE064F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE064FC + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE06500 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE06504 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE06508 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE0650C + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE06510 + +#define mmTPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE06514 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE06518 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE0651C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE06520 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE06524 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE06528 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE0652C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE06530 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE06534 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE06538 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE0653C + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE06540 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE06544 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE06548 + +#define mmTPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE0654C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE06550 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE06554 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE06558 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE0655C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE06560 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE06564 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE06568 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE0656C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE06570 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE06574 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE06578 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE0657C + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE06580 + +#define mmTPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE06584 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE06588 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE0658C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE06590 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE06594 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE06598 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE0659C + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE065A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE065A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE065A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE065AC + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE065B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE065B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE065B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE065BC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE065C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE065C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE065C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE065CC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE065D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE065D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE065D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE065DC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE065E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE065E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE065E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE065EC + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE065F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE065F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE065F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE065FC + +#define mmTPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE06600 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE06604 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE06608 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE0660C + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE06610 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE06614 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE06618 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE0661C + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE06620 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE06624 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE06628 + +#define mmTPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE0662C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE06630 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE06634 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE06638 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE0663C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE06640 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE06644 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE06648 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE0664C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE06650 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE06654 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE06658 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE0665C + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE06660 + +#define mmTPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE06664 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE06668 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE0666C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE06670 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE06674 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE06678 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE0667C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE06680 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE06684 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE06688 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE0668C + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE06690 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE06694 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE06698 + +#define mmTPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE0669C + +#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE066A0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE066A4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE066A8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE066AC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE066B0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE066B4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE066B8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE066BC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE066C0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE066C4 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE066C8 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE066CC + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE066D0 + +#define mmTPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE066D4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE066D8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE066DC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE066E0 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE066E4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE066E8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE066EC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE066F0 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE066F4 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE066F8 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE066FC + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE06700 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE06704 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE06708 + +#define mmTPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE0670C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE06710 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE06714 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE06718 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE0671C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE06720 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE06724 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE06728 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE0672C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE06730 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE06734 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE06738 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE0673C + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE06740 + +#define mmTPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE06744 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE06748 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE0674C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE06750 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE06754 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE06758 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE0675C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE06760 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE06764 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE06768 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE0676C + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE06770 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE06774 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE06778 + +#define mmTPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE0677C + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE06780 + +#define mmTPC0_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE06784 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE06788 + +#define mmTPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE0678C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_0 0xE06790 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_0 0xE06794 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_1 0xE06798 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_1 0xE0679C + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_2 0xE067A0 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_2 0xE067A4 + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_3 0xE067A8 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_3 0xE067AC + +#define mmTPC0_CFG_KERNEL_TID_BASE_DIM_4 0xE067B0 + +#define mmTPC0_CFG_KERNEL_TID_SIZE_DIM_4 0xE067B4 + +#define mmTPC0_CFG_KERNEL_KERNEL_CONFIG 0xE067B8 + +#define mmTPC0_CFG_KERNEL_KERNEL_ID 0xE067BC + +#define mmTPC0_CFG_KERNEL_SRF_0 0xE067C0 + +#define mmTPC0_CFG_KERNEL_SRF_1 0xE067C4 + +#define mmTPC0_CFG_KERNEL_SRF_2 0xE067C8 + +#define mmTPC0_CFG_KERNEL_SRF_3 0xE067CC + +#define mmTPC0_CFG_KERNEL_SRF_4 0xE067D0 + +#define mmTPC0_CFG_KERNEL_SRF_5 0xE067D4 + +#define mmTPC0_CFG_KERNEL_SRF_6 0xE067D8 + +#define mmTPC0_CFG_KERNEL_SRF_7 0xE067DC + +#define mmTPC0_CFG_KERNEL_SRF_8 0xE067E0 + +#define mmTPC0_CFG_KERNEL_SRF_9 0xE067E4 + +#define mmTPC0_CFG_KERNEL_SRF_10 0xE067E8 + +#define mmTPC0_CFG_KERNEL_SRF_11 0xE067EC + +#define mmTPC0_CFG_KERNEL_SRF_12 0xE067F0 + +#define mmTPC0_CFG_KERNEL_SRF_13 0xE067F4 + +#define mmTPC0_CFG_KERNEL_SRF_14 0xE067F8 + +#define mmTPC0_CFG_KERNEL_SRF_15 0xE067FC + +#define mmTPC0_CFG_KERNEL_SRF_16 0xE06800 + +#define mmTPC0_CFG_KERNEL_SRF_17 0xE06804 + +#define mmTPC0_CFG_KERNEL_SRF_18 0xE06808 + +#define mmTPC0_CFG_KERNEL_SRF_19 0xE0680C + +#define mmTPC0_CFG_KERNEL_SRF_20 0xE06810 + +#define mmTPC0_CFG_KERNEL_SRF_21 0xE06814 + +#define mmTPC0_CFG_KERNEL_SRF_22 0xE06818 + +#define mmTPC0_CFG_KERNEL_SRF_23 0xE0681C + +#define mmTPC0_CFG_KERNEL_SRF_24 0xE06820 + +#define mmTPC0_CFG_KERNEL_SRF_25 0xE06824 + +#define mmTPC0_CFG_KERNEL_SRF_26 0xE06828 + +#define mmTPC0_CFG_KERNEL_SRF_27 0xE0682C + +#define mmTPC0_CFG_KERNEL_SRF_28 0xE06830 + +#define mmTPC0_CFG_KERNEL_SRF_29 0xE06834 + +#define mmTPC0_CFG_KERNEL_SRF_30 0xE06838 + +#define mmTPC0_CFG_KERNEL_SRF_31 0xE0683C + +#define mmTPC0_CFG_ROUND_CSR 0xE068FC + +#define mmTPC0_CFG_PROT 0xE06900 + +#define mmTPC0_CFG_SEMAPHORE 0xE06908 + +#define mmTPC0_CFG_VFLAGS 0xE0690C + +#define mmTPC0_CFG_SFLAGS 0xE06910 + +#define mmTPC0_CFG_LFSR_POLYNOM 0xE06918 + +#define mmTPC0_CFG_STATUS 0xE0691C + +#define mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH 0xE06920 + +#define mmTPC0_CFG_CFG_SUBTRACT_VALUE 0xE06924 + +#define mmTPC0_CFG_SM_BASE_ADDRESS_HIGH 0xE0692C + +#define mmTPC0_CFG_TPC_CMD 0xE06930 + +#define mmTPC0_CFG_TPC_EXECUTE 0xE06938 + +#define mmTPC0_CFG_TPC_STALL 0xE0693C + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_LOW 0xE06940 + +#define mmTPC0_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE06944 + +#define mmTPC0_CFG_RD_RATE_LIMIT 0xE06948 + +#define mmTPC0_CFG_WR_RATE_LIMIT 0xE06950 + +#define mmTPC0_CFG_MSS_CONFIG 0xE06954 + +#define mmTPC0_CFG_TPC_INTR_CAUSE 0xE06958 + +#define mmTPC0_CFG_TPC_INTR_MASK 0xE0695C + +#define mmTPC0_CFG_WQ_CREDITS 0xE06960 + +#define mmTPC0_CFG_ARUSER_LO 0xE06964 + +#define mmTPC0_CFG_ARUSER_HI 0xE06968 + +#define mmTPC0_CFG_AWUSER_LO 0xE0696C + +#define mmTPC0_CFG_AWUSER_HI 0xE06970 + +#define mmTPC0_CFG_OPCODE_EXEC 0xE06974 + +#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE06978 + +#define mmTPC0_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE0697C + +#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE06980 + +#define mmTPC0_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE06984 + +#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE06988 + +#define mmTPC0_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE0698C + +#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE06990 + +#define mmTPC0_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE06994 + +#define mmTPC0_CFG_TSB_CFG_MAX_SIZE 0xE06998 + +#define mmTPC0_CFG_TSB_CFG 0xE0699C + +#define mmTPC0_CFG_DBGMEM_ADD 0xE069A0 + +#define mmTPC0_CFG_DBGMEM_DATA_WR 0xE069A4 + +#define mmTPC0_CFG_DBGMEM_DATA_RD 0xE069A8 + +#define mmTPC0_CFG_DBGMEM_CTRL 0xE069AC + +#define mmTPC0_CFG_DBGMEM_RC 0xE069B0 + +#define mmTPC0_CFG_TSB_INFLIGHT_CNTR 0xE069B4 + +#define mmTPC0_CFG_WQ_INFLIGHT_CNTR 0xE069B8 + +#define mmTPC0_CFG_WQ_LBW_TOTAL_CNTR 0xE069BC + +#define mmTPC0_CFG_WQ_HBW_TOTAL_CNTR 0xE069C0 + +#define mmTPC0_CFG_IRQ_OCCOUPY_CNTR 0xE069C4 + +#define mmTPC0_CFG_FUNC_MBIST_CNTRL 0xE069D0 + +#define mmTPC0_CFG_FUNC_MBIST_PAT 0xE069D4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_0 0xE069D8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_1 0xE069DC + +#define mmTPC0_CFG_FUNC_MBIST_MEM_2 0xE069E0 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_3 0xE069E4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_4 0xE069E8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_5 0xE069EC + +#define mmTPC0_CFG_FUNC_MBIST_MEM_6 0xE069F0 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_7 0xE069F4 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_8 0xE069F8 + +#define mmTPC0_CFG_FUNC_MBIST_MEM_9 0xE069FC + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE06A00 + +#define mmTPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE06A04 + +#define mmTPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0xE06A08 + +#define mmTPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE06A0C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE06A10 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE06A14 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE06A18 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE06A1C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE06A20 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE06A24 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE06A28 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE06A2C + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE06A30 + +#define mmTPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE06A34 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE06A38 + +#define mmTPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE06A3C + +#define mmTPC0_CFG_QM_TENSOR_1_PADDING_VALUE 0xE06A40 + +#define mmTPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE06A44 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE06A48 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE06A4C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE06A50 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE06A54 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE06A58 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE06A5C + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE06A60 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE06A64 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE06A68 + +#define mmTPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE06A6C + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE06A70 + +#define mmTPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE06A74 + +#define mmTPC0_CFG_QM_TENSOR_2_PADDING_VALUE 0xE06A78 + +#define mmTPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE06A7C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE06A80 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE06A84 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE06A88 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE06A8C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE06A90 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE06A94 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE06A98 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE06A9C + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE06AA0 + +#define mmTPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE06AA4 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE06AA8 + +#define mmTPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE06AAC + +#define mmTPC0_CFG_QM_TENSOR_3_PADDING_VALUE 0xE06AB0 + +#define mmTPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE06AB4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE06AB8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE06ABC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE06AC0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE06AC4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE06AC8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE06ACC + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE06AD0 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE06AD4 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE06AD8 + +#define mmTPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE06ADC + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE06AE0 + +#define mmTPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE06AE4 + +#define mmTPC0_CFG_QM_TENSOR_4_PADDING_VALUE 0xE06AE8 + +#define mmTPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE06AEC + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE06AF0 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE06AF4 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE06AF8 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE06AFC + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE06B00 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE06B04 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE06B08 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE06B0C + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE06B10 + +#define mmTPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE06B14 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE06B18 + +#define mmTPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE06B1C + +#define mmTPC0_CFG_QM_TENSOR_5_PADDING_VALUE 0xE06B20 + +#define mmTPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE06B24 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE06B28 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE06B2C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE06B30 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE06B34 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE06B38 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE06B3C + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE06B40 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE06B44 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE06B48 + +#define mmTPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE06B4C + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE06B50 + +#define mmTPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE06B54 + +#define mmTPC0_CFG_QM_TENSOR_6_PADDING_VALUE 0xE06B58 + +#define mmTPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE06B5C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE06B60 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE06B64 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE06B68 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE06B6C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE06B70 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE06B74 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE06B78 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE06B7C + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE06B80 + +#define mmTPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE06B84 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE06B88 + +#define mmTPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE06B8C + +#define mmTPC0_CFG_QM_TENSOR_7_PADDING_VALUE 0xE06B90 + +#define mmTPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE06B94 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE06B98 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE06B9C + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE06BA0 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE06BA4 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE06BA8 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE06BAC + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE06BB0 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE06BB4 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE06BB8 + +#define mmTPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE06BBC + +#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE06BC0 + +#define mmTPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE06BC4 + +#define mmTPC0_CFG_QM_TENSOR_8_PADDING_VALUE 0xE06BC8 + +#define mmTPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE06BCC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE06BD0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE06BD4 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE06BD8 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE06BDC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE06BE0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE06BE4 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE06BE8 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE06BEC + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE06BF0 + +#define mmTPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE06BF4 + +#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE06BF8 + +#define mmTPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE06BFC + +#define mmTPC0_CFG_QM_TENSOR_9_PADDING_VALUE 0xE06C00 + +#define mmTPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE06C04 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE06C08 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE06C0C + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE06C10 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE06C14 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE06C18 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE06C1C + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE06C20 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE06C24 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE06C28 + +#define mmTPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE06C2C + +#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE06C30 + +#define mmTPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE06C34 + +#define mmTPC0_CFG_QM_TENSOR_10_PADDING_VALUE 0xE06C38 + +#define mmTPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE06C3C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE06C40 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE06C44 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE06C48 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE06C4C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE06C50 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE06C54 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE06C58 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE06C5C + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE06C60 + +#define mmTPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE06C64 + +#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE06C68 + +#define mmTPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE06C6C + +#define mmTPC0_CFG_QM_TENSOR_11_PADDING_VALUE 0xE06C70 + +#define mmTPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE06C74 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE06C78 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE06C7C + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE06C80 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE06C84 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE06C88 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE06C8C + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE06C90 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE06C94 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE06C98 + +#define mmTPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE06C9C + +#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE06CA0 + +#define mmTPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE06CA4 + +#define mmTPC0_CFG_QM_TENSOR_12_PADDING_VALUE 0xE06CA8 + +#define mmTPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE06CAC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE06CB0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE06CB4 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE06CB8 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE06CBC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE06CC0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE06CC4 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE06CC8 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE06CCC + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE06CD0 + +#define mmTPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE06CD4 + +#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE06CD8 + +#define mmTPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE06CDC + +#define mmTPC0_CFG_QM_TENSOR_13_PADDING_VALUE 0xE06CE0 + +#define mmTPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE06CE4 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE06CE8 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE06CEC + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE06CF0 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE06CF4 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE06CF8 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE06CFC + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE06D00 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE06D04 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE06D08 + +#define mmTPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE06D0C + +#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE06D10 + +#define mmTPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE06D14 + +#define mmTPC0_CFG_QM_TENSOR_14_PADDING_VALUE 0xE06D18 + +#define mmTPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE06D1C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE06D20 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE06D24 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE06D28 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE06D2C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE06D30 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE06D34 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE06D38 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE06D3C + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE06D40 + +#define mmTPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE06D44 + +#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE06D48 + +#define mmTPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE06D4C + +#define mmTPC0_CFG_QM_TENSOR_15_PADDING_VALUE 0xE06D50 + +#define mmTPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE06D54 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE06D58 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE06D5C + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE06D60 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE06D64 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE06D68 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE06D6C + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE06D70 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE06D74 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE06D78 + +#define mmTPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE06D7C + +#define mmTPC0_CFG_QM_SYNC_OBJECT_MESSAGE 0xE06D80 + +#define mmTPC0_CFG_QM_SYNC_OBJECT_ADDR 0xE06D84 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE06D88 + +#define mmTPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE06D8C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_0 0xE06D90 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_0 0xE06D94 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_1 0xE06D98 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_1 0xE06D9C + +#define mmTPC0_CFG_QM_TID_BASE_DIM_2 0xE06DA0 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_2 0xE06DA4 + +#define mmTPC0_CFG_QM_TID_BASE_DIM_3 0xE06DA8 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_3 0xE06DAC + +#define mmTPC0_CFG_QM_TID_BASE_DIM_4 0xE06DB0 + +#define mmTPC0_CFG_QM_TID_SIZE_DIM_4 0xE06DB4 + +#define mmTPC0_CFG_QM_KERNEL_CONFIG 0xE06DB8 + +#define mmTPC0_CFG_QM_KERNEL_ID 0xE06DBC + +#define mmTPC0_CFG_QM_SRF_0 0xE06DC0 + +#define mmTPC0_CFG_QM_SRF_1 0xE06DC4 + +#define mmTPC0_CFG_QM_SRF_2 0xE06DC8 + +#define mmTPC0_CFG_QM_SRF_3 0xE06DCC + +#define mmTPC0_CFG_QM_SRF_4 0xE06DD0 + +#define mmTPC0_CFG_QM_SRF_5 0xE06DD4 + +#define mmTPC0_CFG_QM_SRF_6 0xE06DD8 + +#define mmTPC0_CFG_QM_SRF_7 0xE06DDC + +#define mmTPC0_CFG_QM_SRF_8 0xE06DE0 + +#define mmTPC0_CFG_QM_SRF_9 0xE06DE4 + +#define mmTPC0_CFG_QM_SRF_10 0xE06DE8 + +#define mmTPC0_CFG_QM_SRF_11 0xE06DEC + +#define mmTPC0_CFG_QM_SRF_12 0xE06DF0 + +#define mmTPC0_CFG_QM_SRF_13 0xE06DF4 + +#define mmTPC0_CFG_QM_SRF_14 0xE06DF8 + +#define mmTPC0_CFG_QM_SRF_15 0xE06DFC + +#define mmTPC0_CFG_QM_SRF_16 0xE06E00 + +#define mmTPC0_CFG_QM_SRF_17 0xE06E04 + +#define mmTPC0_CFG_QM_SRF_18 0xE06E08 + +#define mmTPC0_CFG_QM_SRF_19 0xE06E0C + +#define mmTPC0_CFG_QM_SRF_20 0xE06E10 + +#define mmTPC0_CFG_QM_SRF_21 0xE06E14 + +#define mmTPC0_CFG_QM_SRF_22 0xE06E18 + +#define mmTPC0_CFG_QM_SRF_23 0xE06E1C + +#define mmTPC0_CFG_QM_SRF_24 0xE06E20 + +#define mmTPC0_CFG_QM_SRF_25 0xE06E24 + +#define mmTPC0_CFG_QM_SRF_26 0xE06E28 + +#define mmTPC0_CFG_QM_SRF_27 0xE06E2C + +#define mmTPC0_CFG_QM_SRF_28 0xE06E30 + +#define mmTPC0_CFG_QM_SRF_29 0xE06E34 + +#define mmTPC0_CFG_QM_SRF_30 0xE06E38 + +#define mmTPC0_CFG_QM_SRF_31 0xE06E3C + +#endif /* ASIC_REG_TPC0_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h new file mode 100644 index 000000000000..8e71532c6f36 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_masks.h @@ -0,0 +1,800 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_MASKS_H_ +#define ASIC_REG_TPC0_QM_MASKS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +/* TPC0_QM_GLBL_CFG0 */ +#define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 +#define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF +#define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 +#define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 +#define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 9 +#define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 + +/* TPC0_QM_GLBL_CFG1 */ +#define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 +#define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF +#define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 +#define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 +#define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 +#define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 +#define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 +#define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 +#define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 + +/* TPC0_QM_GLBL_PROT */ +#define TPC0_QM_GLBL_PROT_PQF_SHIFT 0 +#define TPC0_QM_GLBL_PROT_PQF_MASK 0xF +#define TPC0_QM_GLBL_PROT_CQF_SHIFT 4 +#define TPC0_QM_GLBL_PROT_CQF_MASK 0x1F0 +#define TPC0_QM_GLBL_PROT_CP_SHIFT 9 +#define TPC0_QM_GLBL_PROT_CP_MASK 0x3E00 +#define TPC0_QM_GLBL_PROT_ERR_SHIFT 14 +#define TPC0_QM_GLBL_PROT_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_PROT_ARB_SHIFT 15 +#define TPC0_QM_GLBL_PROT_ARB_MASK 0x8000 + +/* TPC0_QM_GLBL_ERR_CFG */ +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 +#define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 +#define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 +#define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 +#define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 +#define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 +#define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 +#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 +#define TPC0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 + +/* TPC0_QM_GLBL_SECURE_PROPS */ +#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_0_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_1_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_2_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_3_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_SHIFT 0 +#define TPC0_QM_GLBL_SECURE_PROPS_4_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_0_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_1_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_2_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_3_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_NON_SECURE_PROPS */ +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_SHIFT 0 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_ASID_MASK 0x3FF +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_0_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_1_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_2_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_3_MMBP_MASK 0x400 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_SHIFT 10 +#define TPC0_QM_GLBL_NON_SECURE_PROPS_4_MMBP_MASK 0x400 + +/* TPC0_QM_GLBL_STS0 */ +#define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 +#define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF +#define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 +#define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 +#define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 +#define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 +#define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 +#define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 +#define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 +#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 +#define TPC0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 + +/* TPC0_QM_GLBL_STS1 */ +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_STS1_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_STS1_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_STS1_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_STS1_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_STS1_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_STS1_4 */ +#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_STS1_4_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_STS1_4_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_STS1_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_STS1_4_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_STS1_4_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_STS1_4_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_STS1_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_MSG_EN */ +#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_SHIFT 0 +#define TPC0_QM_GLBL_MSG_EN_PQF_RD_ERR_MASK 0x1 +#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_MSG_EN_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_MSG_EN_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_MSG_EN_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_MSG_EN_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_GLBL_MSG_EN_4 */ +#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_SHIFT 1 +#define TPC0_QM_GLBL_MSG_EN_4_CQF_RD_ERR_MASK 0x2 +#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_SHIFT 2 +#define TPC0_QM_GLBL_MSG_EN_4_CP_RD_ERR_MASK 0x4 +#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 +#define TPC0_QM_GLBL_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 +#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_SHIFT 4 +#define TPC0_QM_GLBL_MSG_EN_4_CP_STOP_OP_MASK 0x10 +#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 +#define TPC0_QM_GLBL_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 +#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_SHIFT 6 +#define TPC0_QM_GLBL_MSG_EN_4_CP_WREG_ERR_MASK 0x40 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 +#define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 + +/* TPC0_QM_PQ_BASE_LO */ +#define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_BASE_HI */ +#define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_SIZE */ +#define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 +#define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_PI */ +#define TPC0_QM_PQ_PI_VAL_SHIFT 0 +#define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CI */ +#define TPC0_QM_PQ_CI_VAL_SHIFT 0 +#define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_PQ_CFG0 */ +#define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_PQ_CFG1 */ +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_ARUSER_31_11 */ +#define TPC0_QM_PQ_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_PQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_PQ_STS0 */ +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_PQ_STS1 */ +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 +#define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_CFG0 */ +#define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 +#define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 + +/* TPC0_QM_CQ_CFG1 */ +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 +#define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 +#define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_ARUSER_31_11 */ +#define TPC0_QM_CQ_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CQ_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_CQ_STS0 */ +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 +#define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_STS1 */ +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 +#define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 +#define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 +#define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 + +/* TPC0_QM_CQ_PTR_LO_0 */ +#define TPC0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_0 */ +#define TPC0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_0 */ +#define TPC0_QM_CQ_TSIZE_0_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_0 */ +#define TPC0_QM_CQ_CTL_0_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_0_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_0_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_0_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_1 */ +#define TPC0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_1 */ +#define TPC0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_1 */ +#define TPC0_QM_CQ_TSIZE_1_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_1 */ +#define TPC0_QM_CQ_CTL_1_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_1_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_1_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_1_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_2 */ +#define TPC0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_2 */ +#define TPC0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_2 */ +#define TPC0_QM_CQ_TSIZE_2_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_2 */ +#define TPC0_QM_CQ_CTL_2_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_2_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_2_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_2_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_3 */ +#define TPC0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_3 */ +#define TPC0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_3 */ +#define TPC0_QM_CQ_TSIZE_3_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_3 */ +#define TPC0_QM_CQ_CTL_3_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_3_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_3_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_3_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_4 */ +#define TPC0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_4 */ +#define TPC0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_4 */ +#define TPC0_QM_CQ_TSIZE_4_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_4 */ +#define TPC0_QM_CQ_CTL_4_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_4_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_4_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_4_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_PTR_LO_STS */ +#define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_PTR_HI_STS */ +#define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_TSIZE_STS */ +#define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 +#define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CQ_CTL_STS */ +#define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 +#define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF +#define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 +#define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 + +/* TPC0_QM_CQ_IFIFO_CNT */ +#define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 +#define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 + +/* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 +#define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_FENCE0_RDATA */ +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE1_RDATA */ +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE2_RDATA */ +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE3_RDATA */ +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF + +/* TPC0_QM_CP_FENCE0_CNT */ +#define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE1_CNT */ +#define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE2_CNT */ +#define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_FENCE3_CNT */ +#define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 +#define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF + +/* TPC0_QM_CP_STS */ +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 +#define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF +#define TPC0_QM_CP_STS_ERDY_SHIFT 16 +#define TPC0_QM_CP_STS_ERDY_MASK 0x10000 +#define TPC0_QM_CP_STS_RRDY_SHIFT 17 +#define TPC0_QM_CP_STS_RRDY_MASK 0x20000 +#define TPC0_QM_CP_STS_MRDY_SHIFT 18 +#define TPC0_QM_CP_STS_MRDY_MASK 0x40000 +#define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 +#define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 +#define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 +#define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 +#define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 + +/* TPC0_QM_CP_CURRENT_INST_LO */ +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_CURRENT_INST_HI */ +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 +#define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_CP_BARRIER_CFG */ +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 +#define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF +#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 +#define TPC0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 + +/* TPC0_QM_CP_DBG_0 */ +#define TPC0_QM_CP_DBG_0_CS_SHIFT 0 +#define TPC0_QM_CP_DBG_0_CS_MASK 0xF +#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 4 +#define TPC0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x10 +#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 5 +#define TPC0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x20 +#define TPC0_QM_CP_DBG_0_MREB_STALL_SHIFT 6 +#define TPC0_QM_CP_DBG_0_MREB_STALL_MASK 0x40 +#define TPC0_QM_CP_DBG_0_STALL_SHIFT 7 +#define TPC0_QM_CP_DBG_0_STALL_MASK 0x80 + +/* TPC0_QM_CP_ARUSER_31_11 */ +#define TPC0_QM_CP_ARUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CP_ARUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_CP_AWUSER_31_11 */ +#define TPC0_QM_CP_AWUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_CP_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_ARB_CFG_0 */ +#define TPC0_QM_ARB_CFG_0_TYPE_SHIFT 0 +#define TPC0_QM_ARB_CFG_0_TYPE_MASK 0x1 +#define TPC0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 +#define TPC0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 +#define TPC0_QM_ARB_CFG_0_EN_SHIFT 8 +#define TPC0_QM_ARB_CFG_0_EN_MASK 0x100 +#define TPC0_QM_ARB_CFG_0_MASK_SHIFT 12 +#define TPC0_QM_ARB_CFG_0_MASK_MASK 0xF000 +#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 16 +#define TPC0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x10000 + +/* TPC0_QM_ARB_CHOISE_Q_PUSH */ +#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_SHIFT 0 +#define TPC0_QM_ARB_CHOISE_Q_PUSH_VAL_MASK 0x3 + +/* TPC0_QM_ARB_WRR_WEIGHT */ +#define TPC0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 +#define TPC0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_CFG_1 */ +#define TPC0_QM_ARB_CFG_1_CLR_SHIFT 0 +#define TPC0_QM_ARB_CFG_1_CLR_MASK 0x1 + +/* TPC0_QM_ARB_MST_AVAIL_CRED */ +#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F + +/* TPC0_QM_ARB_MST_CRED_INC */ +#define TPC0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_CHOISE_PUSH_OFST */ +#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CHOISE_PUSH_OFST_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ +#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_SLAVE_EN */ +#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_MST_QUIET_PER */ +#define TPC0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_CHOISE_WDT */ +#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_CHOISE_WDT_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_SLV_ID */ +#define TPC0_QM_ARB_SLV_ID_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_ID_VAL_MASK 0x1F + +/* TPC0_QM_ARB_MSG_MAX_INFLIGHT */ +#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 +#define TPC0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F + +/* TPC0_QM_ARB_MSG_AWUSER_31_11 */ +#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_31_11_VAL_MASK 0x1FFFFF + +/* TPC0_QM_ARB_MSG_AWUSER_SEC_PROP */ +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_ASID_MASK 0x3FF +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_SHIFT 10 +#define TPC0_QM_ARB_MSG_AWUSER_SEC_PROP_MMBP_MASK 0x400 + +/* TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP */ +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_SHIFT 0 +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_ASID_MASK 0x3FF +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_SHIFT 10 +#define TPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP_MMBP_MASK 0x400 + +/* TPC0_QM_ARB_BASE_LO */ +#define TPC0_QM_ARB_BASE_LO_VAL_SHIFT 0 +#define TPC0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_BASE_HI */ +#define TPC0_QM_ARB_BASE_HI_VAL_SHIFT 0 +#define TPC0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_STATE_STS */ +#define TPC0_QM_ARB_STATE_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_ARB_CHOISE_FULLNESS_STS */ +#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_CHOISE_FULLNESS_STS_VAL_MASK 0x7F + +/* TPC0_QM_ARB_MSG_STS */ +#define TPC0_QM_ARB_MSG_STS_FULL_SHIFT 0 +#define TPC0_QM_ARB_MSG_STS_FULL_MASK 0x1 +#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 +#define TPC0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 + +/* TPC0_QM_ARB_SLV_CHOISE_Q_HEAD */ +#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_SHIFT 0 +#define TPC0_QM_ARB_SLV_CHOISE_Q_HEAD_VAL_MASK 0x3 + +/* TPC0_QM_ARB_ERR_CAUSE */ +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_SHIFT 0 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_OVF_MASK 0x1 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_SHIFT 1 +#define TPC0_QM_ARB_ERR_CAUSE_CHOISE_WDT_MASK 0x2 +#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 +#define TPC0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 + +/* TPC0_QM_ARB_ERR_MSG_EN */ +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_SHIFT 0 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_SHIFT 1 +#define TPC0_QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 +#define TPC0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +/* TPC0_QM_ARB_ERR_STS_DRP */ +#define TPC0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 +#define TPC0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 + +/* TPC0_QM_ARB_MST_CRED_STS */ +#define TPC0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 +#define TPC0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F + +/* TPC0_QM_CGM_CFG */ +#define TPC0_QM_CGM_CFG_IDLE_TH_SHIFT 0 +#define TPC0_QM_CGM_CFG_IDLE_TH_MASK 0xFFF +#define TPC0_QM_CGM_CFG_G2F_TH_SHIFT 16 +#define TPC0_QM_CGM_CFG_G2F_TH_MASK 0xFF0000 +#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT 24 +#define TPC0_QM_CGM_CFG_CP_IDLE_MASK_MASK 0x1F000000 +#define TPC0_QM_CGM_CFG_EN_SHIFT 31 +#define TPC0_QM_CGM_CFG_EN_MASK 0x80000000 + +/* TPC0_QM_CGM_STS */ +#define TPC0_QM_CGM_STS_ST_SHIFT 0 +#define TPC0_QM_CGM_STS_ST_MASK 0x3 +#define TPC0_QM_CGM_STS_CG_SHIFT 4 +#define TPC0_QM_CGM_STS_CG_MASK 0x10 +#define TPC0_QM_CGM_STS_AGENT_IDLE_SHIFT 8 +#define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 +#define TPC0_QM_CGM_STS_AXI_IDLE_SHIFT 9 +#define TPC0_QM_CGM_STS_AXI_IDLE_MASK 0x200 +#define TPC0_QM_CGM_STS_CP_IDLE_SHIFT 10 +#define TPC0_QM_CGM_STS_CP_IDLE_MASK 0x400 + +/* TPC0_QM_CGM_CFG1 */ +#define TPC0_QM_CGM_CFG1_MASK_TH_SHIFT 0 +#define TPC0_QM_CGM_CFG1_MASK_TH_MASK 0xFF + +/* TPC0_QM_LOCAL_RANGE_BASE */ +#define TPC0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 +#define TPC0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF + +/* TPC0_QM_LOCAL_RANGE_SIZE */ +#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 +#define TPC0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF + +/* TPC0_QM_CSMR_STRICT_PRIO_CFG */ +#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_SHIFT 0 +#define TPC0_QM_CSMR_STRICT_PRIO_CFG_TYPE_MASK 0x1 + +/* TPC0_QM_HBW_RD_RATE_LIM_CFG_1 */ +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* TPC0_QM_LBW_WR_RATE_LIM_CFG_0 */ +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* TPC0_QM_LBW_WR_RATE_LIM_CFG_1 */ +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 +#define TPC0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 + +/* TPC0_QM_HBW_RD_RATE_LIM_CFG_0 */ +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 +#define TPC0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 + +/* TPC0_QM_GLBL_AXCACHE */ +#define TPC0_QM_GLBL_AXCACHE_AR_SHIFT 0 +#define TPC0_QM_GLBL_AXCACHE_AR_MASK 0xF +#define TPC0_QM_GLBL_AXCACHE_AW_SHIFT 16 +#define TPC0_QM_GLBL_AXCACHE_AW_MASK 0xF0000 + +/* TPC0_QM_IND_GW_APB_CFG */ +#define TPC0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 +#define TPC0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF +#define TPC0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 +#define TPC0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 + +/* TPC0_QM_IND_GW_APB_WDATA */ +#define TPC0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 +#define TPC0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_IND_GW_APB_RDATA */ +#define TPC0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 +#define TPC0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_IND_GW_APB_STATUS */ +#define TPC0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 +#define TPC0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 +#define TPC0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 +#define TPC0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 + +/* TPC0_QM_GLBL_ERR_ADDR_LO */ +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_ADDR_HI */ +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_ERR_WDATA */ +#define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 +#define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF + +/* TPC0_QM_GLBL_MEM_INIT_BUSY */ +#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_SHIFT 0 +#define TPC0_QM_GLBL_MEM_INIT_BUSY_RBUF_MASK 0xF + +#endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h new file mode 100644 index 000000000000..f9e310ab6df2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC0_QM_REGS_H_ +#define ASIC_REG_TPC0_QM_REGS_H_ + +/* + ***************************************** + * TPC0_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC0_QM_GLBL_CFG0 0xE08000 + +#define mmTPC0_QM_GLBL_CFG1 0xE08004 + +#define mmTPC0_QM_GLBL_PROT 0xE08008 + +#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_0 0xE08010 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_1 0xE08014 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_2 0xE08018 + +#define mmTPC0_QM_GLBL_SECURE_PROPS_3 0xE0801C + +#define mmTPC0_QM_GLBL_SECURE_PROPS_4 0xE08020 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 0xE08024 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 0xE08028 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 0xE0802C + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 0xE08030 + +#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 0xE08034 + +#define mmTPC0_QM_GLBL_STS0 0xE08038 + +#define mmTPC0_QM_GLBL_STS1_0 0xE08040 + +#define mmTPC0_QM_GLBL_STS1_1 0xE08044 + +#define mmTPC0_QM_GLBL_STS1_2 0xE08048 + +#define mmTPC0_QM_GLBL_STS1_3 0xE0804C + +#define mmTPC0_QM_GLBL_STS1_4 0xE08050 + +#define mmTPC0_QM_GLBL_MSG_EN_0 0xE08054 + +#define mmTPC0_QM_GLBL_MSG_EN_1 0xE08058 + +#define mmTPC0_QM_GLBL_MSG_EN_2 0xE0805C + +#define mmTPC0_QM_GLBL_MSG_EN_3 0xE08060 + +#define mmTPC0_QM_GLBL_MSG_EN_4 0xE08068 + +#define mmTPC0_QM_PQ_BASE_LO_0 0xE08070 + +#define mmTPC0_QM_PQ_BASE_LO_1 0xE08074 + +#define mmTPC0_QM_PQ_BASE_LO_2 0xE08078 + +#define mmTPC0_QM_PQ_BASE_LO_3 0xE0807C + +#define mmTPC0_QM_PQ_BASE_HI_0 0xE08080 + +#define mmTPC0_QM_PQ_BASE_HI_1 0xE08084 + +#define mmTPC0_QM_PQ_BASE_HI_2 0xE08088 + +#define mmTPC0_QM_PQ_BASE_HI_3 0xE0808C + +#define mmTPC0_QM_PQ_SIZE_0 0xE08090 + +#define mmTPC0_QM_PQ_SIZE_1 0xE08094 + +#define mmTPC0_QM_PQ_SIZE_2 0xE08098 + +#define mmTPC0_QM_PQ_SIZE_3 0xE0809C + +#define mmTPC0_QM_PQ_PI_0 0xE080A0 + +#define mmTPC0_QM_PQ_PI_1 0xE080A4 + +#define mmTPC0_QM_PQ_PI_2 0xE080A8 + +#define mmTPC0_QM_PQ_PI_3 0xE080AC + +#define mmTPC0_QM_PQ_CI_0 0xE080B0 + +#define mmTPC0_QM_PQ_CI_1 0xE080B4 + +#define mmTPC0_QM_PQ_CI_2 0xE080B8 + +#define mmTPC0_QM_PQ_CI_3 0xE080BC + +#define mmTPC0_QM_PQ_CFG0_0 0xE080C0 + +#define mmTPC0_QM_PQ_CFG0_1 0xE080C4 + +#define mmTPC0_QM_PQ_CFG0_2 0xE080C8 + +#define mmTPC0_QM_PQ_CFG0_3 0xE080CC + +#define mmTPC0_QM_PQ_CFG1_0 0xE080D0 + +#define mmTPC0_QM_PQ_CFG1_1 0xE080D4 + +#define mmTPC0_QM_PQ_CFG1_2 0xE080D8 + +#define mmTPC0_QM_PQ_CFG1_3 0xE080DC + +#define mmTPC0_QM_PQ_ARUSER_31_11_0 0xE080E0 + +#define mmTPC0_QM_PQ_ARUSER_31_11_1 0xE080E4 + +#define mmTPC0_QM_PQ_ARUSER_31_11_2 0xE080E8 + +#define mmTPC0_QM_PQ_ARUSER_31_11_3 0xE080EC + +#define mmTPC0_QM_PQ_STS0_0 0xE080F0 + +#define mmTPC0_QM_PQ_STS0_1 0xE080F4 + +#define mmTPC0_QM_PQ_STS0_2 0xE080F8 + +#define mmTPC0_QM_PQ_STS0_3 0xE080FC + +#define mmTPC0_QM_PQ_STS1_0 0xE08100 + +#define mmTPC0_QM_PQ_STS1_1 0xE08104 + +#define mmTPC0_QM_PQ_STS1_2 0xE08108 + +#define mmTPC0_QM_PQ_STS1_3 0xE0810C + +#define mmTPC0_QM_CQ_CFG0_0 0xE08110 + +#define mmTPC0_QM_CQ_CFG0_1 0xE08114 + +#define mmTPC0_QM_CQ_CFG0_2 0xE08118 + +#define mmTPC0_QM_CQ_CFG0_3 0xE0811C + +#define mmTPC0_QM_CQ_CFG0_4 0xE08120 + +#define mmTPC0_QM_CQ_CFG1_0 0xE08124 + +#define mmTPC0_QM_CQ_CFG1_1 0xE08128 + +#define mmTPC0_QM_CQ_CFG1_2 0xE0812C + +#define mmTPC0_QM_CQ_CFG1_3 0xE08130 + +#define mmTPC0_QM_CQ_CFG1_4 0xE08134 + +#define mmTPC0_QM_CQ_ARUSER_31_11_0 0xE08138 + +#define mmTPC0_QM_CQ_ARUSER_31_11_1 0xE0813C + +#define mmTPC0_QM_CQ_ARUSER_31_11_2 0xE08140 + +#define mmTPC0_QM_CQ_ARUSER_31_11_3 0xE08144 + +#define mmTPC0_QM_CQ_ARUSER_31_11_4 0xE08148 + +#define mmTPC0_QM_CQ_STS0_0 0xE0814C + +#define mmTPC0_QM_CQ_STS0_1 0xE08150 + +#define mmTPC0_QM_CQ_STS0_2 0xE08154 + +#define mmTPC0_QM_CQ_STS0_3 0xE08158 + +#define mmTPC0_QM_CQ_STS0_4 0xE0815C + +#define mmTPC0_QM_CQ_STS1_0 0xE08160 + +#define mmTPC0_QM_CQ_STS1_1 0xE08164 + +#define mmTPC0_QM_CQ_STS1_2 0xE08168 + +#define mmTPC0_QM_CQ_STS1_3 0xE0816C + +#define mmTPC0_QM_CQ_STS1_4 0xE08170 + +#define mmTPC0_QM_CQ_PTR_LO_0 0xE08174 + +#define mmTPC0_QM_CQ_PTR_HI_0 0xE08178 + +#define mmTPC0_QM_CQ_TSIZE_0 0xE0817C + +#define mmTPC0_QM_CQ_CTL_0 0xE08180 + +#define mmTPC0_QM_CQ_PTR_LO_1 0xE08184 + +#define mmTPC0_QM_CQ_PTR_HI_1 0xE08188 + +#define mmTPC0_QM_CQ_TSIZE_1 0xE0818C + +#define mmTPC0_QM_CQ_CTL_1 0xE08190 + +#define mmTPC0_QM_CQ_PTR_LO_2 0xE08194 + +#define mmTPC0_QM_CQ_PTR_HI_2 0xE08198 + +#define mmTPC0_QM_CQ_TSIZE_2 0xE0819C + +#define mmTPC0_QM_CQ_CTL_2 0xE081A0 + +#define mmTPC0_QM_CQ_PTR_LO_3 0xE081A4 + +#define mmTPC0_QM_CQ_PTR_HI_3 0xE081A8 + +#define mmTPC0_QM_CQ_TSIZE_3 0xE081AC + +#define mmTPC0_QM_CQ_CTL_3 0xE081B0 + +#define mmTPC0_QM_CQ_PTR_LO_4 0xE081B4 + +#define mmTPC0_QM_CQ_PTR_HI_4 0xE081B8 + +#define mmTPC0_QM_CQ_TSIZE_4 0xE081BC + +#define mmTPC0_QM_CQ_CTL_4 0xE081C0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_0 0xE081C4 + +#define mmTPC0_QM_CQ_PTR_LO_STS_1 0xE081C8 + +#define mmTPC0_QM_CQ_PTR_LO_STS_2 0xE081CC + +#define mmTPC0_QM_CQ_PTR_LO_STS_3 0xE081D0 + +#define mmTPC0_QM_CQ_PTR_LO_STS_4 0xE081D4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_0 0xE081D8 + +#define mmTPC0_QM_CQ_PTR_HI_STS_1 0xE081DC + +#define mmTPC0_QM_CQ_PTR_HI_STS_2 0xE081E0 + +#define mmTPC0_QM_CQ_PTR_HI_STS_3 0xE081E4 + +#define mmTPC0_QM_CQ_PTR_HI_STS_4 0xE081E8 + +#define mmTPC0_QM_CQ_TSIZE_STS_0 0xE081EC + +#define mmTPC0_QM_CQ_TSIZE_STS_1 0xE081F0 + +#define mmTPC0_QM_CQ_TSIZE_STS_2 0xE081F4 + +#define mmTPC0_QM_CQ_TSIZE_STS_3 0xE081F8 + +#define mmTPC0_QM_CQ_TSIZE_STS_4 0xE081FC + +#define mmTPC0_QM_CQ_CTL_STS_0 0xE08200 + +#define mmTPC0_QM_CQ_CTL_STS_1 0xE08204 + +#define mmTPC0_QM_CQ_CTL_STS_2 0xE08208 + +#define mmTPC0_QM_CQ_CTL_STS_3 0xE0820C + +#define mmTPC0_QM_CQ_CTL_STS_4 0xE08210 + +#define mmTPC0_QM_CQ_IFIFO_CNT_0 0xE08214 + +#define mmTPC0_QM_CQ_IFIFO_CNT_1 0xE08218 + +#define mmTPC0_QM_CQ_IFIFO_CNT_2 0xE0821C + +#define mmTPC0_QM_CQ_IFIFO_CNT_3 0xE08220 + +#define mmTPC0_QM_CQ_IFIFO_CNT_4 0xE08224 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0xE08228 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0xE0822C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0xE08230 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0xE08234 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0xE08238 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0xE0823C + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0xE08240 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0xE08244 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0xE08248 + +#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0xE0824C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0xE08250 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0xE08254 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0xE08258 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0xE0825C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0xE08260 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0xE08264 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0xE08268 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0xE0826C + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0xE08270 + +#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0xE08274 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0xE08278 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0xE0827C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0xE08280 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0xE08284 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0xE08288 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0xE0828C + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0xE08290 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0xE08294 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0xE08298 + +#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0xE0829C + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0xE082A0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0xE082A4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0xE082A8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0xE082AC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0xE082B0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0xE082B4 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0xE082B8 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0xE082BC + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0xE082C0 + +#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0xE082C4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 0xE082C8 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 0xE082CC + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 0xE082D0 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 0xE082D4 + +#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 0xE082D8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE082E0 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE082E4 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE082E8 + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE082EC + +#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE082F0 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE082F4 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE082F8 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE082FC + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE08300 + +#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE08304 + +#define mmTPC0_QM_CP_FENCE0_RDATA_0 0xE08308 + +#define mmTPC0_QM_CP_FENCE0_RDATA_1 0xE0830C + +#define mmTPC0_QM_CP_FENCE0_RDATA_2 0xE08310 + +#define mmTPC0_QM_CP_FENCE0_RDATA_3 0xE08314 + +#define mmTPC0_QM_CP_FENCE0_RDATA_4 0xE08318 + +#define mmTPC0_QM_CP_FENCE1_RDATA_0 0xE0831C + +#define mmTPC0_QM_CP_FENCE1_RDATA_1 0xE08320 + +#define mmTPC0_QM_CP_FENCE1_RDATA_2 0xE08324 + +#define mmTPC0_QM_CP_FENCE1_RDATA_3 0xE08328 + +#define mmTPC0_QM_CP_FENCE1_RDATA_4 0xE0832C + +#define mmTPC0_QM_CP_FENCE2_RDATA_0 0xE08330 + +#define mmTPC0_QM_CP_FENCE2_RDATA_1 0xE08334 + +#define mmTPC0_QM_CP_FENCE2_RDATA_2 0xE08338 + +#define mmTPC0_QM_CP_FENCE2_RDATA_3 0xE0833C + +#define mmTPC0_QM_CP_FENCE2_RDATA_4 0xE08340 + +#define mmTPC0_QM_CP_FENCE3_RDATA_0 0xE08344 + +#define mmTPC0_QM_CP_FENCE3_RDATA_1 0xE08348 + +#define mmTPC0_QM_CP_FENCE3_RDATA_2 0xE0834C + +#define mmTPC0_QM_CP_FENCE3_RDATA_3 0xE08350 + +#define mmTPC0_QM_CP_FENCE3_RDATA_4 0xE08354 + +#define mmTPC0_QM_CP_FENCE0_CNT_0 0xE08358 + +#define mmTPC0_QM_CP_FENCE0_CNT_1 0xE0835C + +#define mmTPC0_QM_CP_FENCE0_CNT_2 0xE08360 + +#define mmTPC0_QM_CP_FENCE0_CNT_3 0xE08364 + +#define mmTPC0_QM_CP_FENCE0_CNT_4 0xE08368 + +#define mmTPC0_QM_CP_FENCE1_CNT_0 0xE0836C + +#define mmTPC0_QM_CP_FENCE1_CNT_1 0xE08370 + +#define mmTPC0_QM_CP_FENCE1_CNT_2 0xE08374 + +#define mmTPC0_QM_CP_FENCE1_CNT_3 0xE08378 + +#define mmTPC0_QM_CP_FENCE1_CNT_4 0xE0837C + +#define mmTPC0_QM_CP_FENCE2_CNT_0 0xE08380 + +#define mmTPC0_QM_CP_FENCE2_CNT_1 0xE08384 + +#define mmTPC0_QM_CP_FENCE2_CNT_2 0xE08388 + +#define mmTPC0_QM_CP_FENCE2_CNT_3 0xE0838C + +#define mmTPC0_QM_CP_FENCE2_CNT_4 0xE08390 + +#define mmTPC0_QM_CP_FENCE3_CNT_0 0xE08394 + +#define mmTPC0_QM_CP_FENCE3_CNT_1 0xE08398 + +#define mmTPC0_QM_CP_FENCE3_CNT_2 0xE0839C + +#define mmTPC0_QM_CP_FENCE3_CNT_3 0xE083A0 + +#define mmTPC0_QM_CP_FENCE3_CNT_4 0xE083A4 + +#define mmTPC0_QM_CP_STS_0 0xE083A8 + +#define mmTPC0_QM_CP_STS_1 0xE083AC + +#define mmTPC0_QM_CP_STS_2 0xE083B0 + +#define mmTPC0_QM_CP_STS_3 0xE083B4 + +#define mmTPC0_QM_CP_STS_4 0xE083B8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_0 0xE083BC + +#define mmTPC0_QM_CP_CURRENT_INST_LO_1 0xE083C0 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_2 0xE083C4 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_3 0xE083C8 + +#define mmTPC0_QM_CP_CURRENT_INST_LO_4 0xE083CC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_0 0xE083D0 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_1 0xE083D4 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_2 0xE083D8 + +#define mmTPC0_QM_CP_CURRENT_INST_HI_3 0xE083DC + +#define mmTPC0_QM_CP_CURRENT_INST_HI_4 0xE083E0 + +#define mmTPC0_QM_CP_BARRIER_CFG_0 0xE083F4 + +#define mmTPC0_QM_CP_BARRIER_CFG_1 0xE083F8 + +#define mmTPC0_QM_CP_BARRIER_CFG_2 0xE083FC + +#define mmTPC0_QM_CP_BARRIER_CFG_3 0xE08400 + +#define mmTPC0_QM_CP_BARRIER_CFG_4 0xE08404 + +#define mmTPC0_QM_CP_DBG_0_0 0xE08408 + +#define mmTPC0_QM_CP_DBG_0_1 0xE0840C + +#define mmTPC0_QM_CP_DBG_0_2 0xE08410 + +#define mmTPC0_QM_CP_DBG_0_3 0xE08414 + +#define mmTPC0_QM_CP_DBG_0_4 0xE08418 + +#define mmTPC0_QM_CP_ARUSER_31_11_0 0xE0841C + +#define mmTPC0_QM_CP_ARUSER_31_11_1 0xE08420 + +#define mmTPC0_QM_CP_ARUSER_31_11_2 0xE08424 + +#define mmTPC0_QM_CP_ARUSER_31_11_3 0xE08428 + +#define mmTPC0_QM_CP_ARUSER_31_11_4 0xE0842C + +#define mmTPC0_QM_CP_AWUSER_31_11_0 0xE08430 + +#define mmTPC0_QM_CP_AWUSER_31_11_1 0xE08434 + +#define mmTPC0_QM_CP_AWUSER_31_11_2 0xE08438 + +#define mmTPC0_QM_CP_AWUSER_31_11_3 0xE0843C + +#define mmTPC0_QM_CP_AWUSER_31_11_4 0xE08440 + +#define mmTPC0_QM_ARB_CFG_0 0xE08A00 + +#define mmTPC0_QM_ARB_CHOISE_Q_PUSH 0xE08A04 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_0 0xE08A08 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_1 0xE08A0C + +#define mmTPC0_QM_ARB_WRR_WEIGHT_2 0xE08A10 + +#define mmTPC0_QM_ARB_WRR_WEIGHT_3 0xE08A14 + +#define mmTPC0_QM_ARB_CFG_1 0xE08A18 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0 0xE08A20 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1 0xE08A24 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2 0xE08A28 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3 0xE08A2C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4 0xE08A30 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5 0xE08A34 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6 0xE08A38 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7 0xE08A3C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8 0xE08A40 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9 0xE08A44 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10 0xE08A48 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11 0xE08A4C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12 0xE08A50 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13 0xE08A54 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14 0xE08A58 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15 0xE08A5C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16 0xE08A60 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17 0xE08A64 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18 0xE08A68 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19 0xE08A6C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20 0xE08A70 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21 0xE08A74 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22 0xE08A78 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23 0xE08A7C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24 0xE08A80 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25 0xE08A84 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26 0xE08A88 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27 0xE08A8C + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28 0xE08A90 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29 0xE08A94 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30 0xE08A98 + +#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31 0xE08A9C + +#define mmTPC0_QM_ARB_MST_CRED_INC 0xE08AA0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE08AA4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE08AA8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE08AAC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE08AB0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE08AB4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE08AB8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE08ABC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE08AC0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE08AC4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE08AC8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE08ACC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE08AD0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE08AD4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE08AD8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE08ADC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE08AE0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE08AE4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE08AE8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE08AEC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE08AF0 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE08AF4 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE08AF8 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE08AFC + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE08B00 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE08B04 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE08B08 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE08B0C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE08B10 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE08B14 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE08B18 + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE08B1C + +#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE08B20 + +#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE08B28 + +#define mmTPC0_QM_ARB_MST_SLAVE_EN 0xE08B2C + +#define mmTPC0_QM_ARB_MST_QUIET_PER 0xE08B34 + +#define mmTPC0_QM_ARB_SLV_CHOISE_WDT 0xE08B38 + +#define mmTPC0_QM_ARB_SLV_ID 0xE08B3C + +#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT 0xE08B44 + +#define mmTPC0_QM_ARB_MSG_AWUSER_31_11 0xE08B48 + +#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP 0xE08B4C + +#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE08B50 + +#define mmTPC0_QM_ARB_BASE_LO 0xE08B54 + +#define mmTPC0_QM_ARB_BASE_HI 0xE08B58 + +#define mmTPC0_QM_ARB_STATE_STS 0xE08B80 + +#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS 0xE08B84 + +#define mmTPC0_QM_ARB_MSG_STS 0xE08B88 + +#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD 0xE08B8C + +#define mmTPC0_QM_ARB_ERR_CAUSE 0xE08B9C + +#define mmTPC0_QM_ARB_ERR_MSG_EN 0xE08BA0 + +#define mmTPC0_QM_ARB_ERR_STS_DRP 0xE08BA8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_0 0xE08BB0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_1 0xE08BB4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_2 0xE08BB8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_3 0xE08BBC + +#define mmTPC0_QM_ARB_MST_CRED_STS_4 0xE08BC0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_5 0xE08BC4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_6 0xE08BC8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_7 0xE08BCC + +#define mmTPC0_QM_ARB_MST_CRED_STS_8 0xE08BD0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_9 0xE08BD4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_10 0xE08BD8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_11 0xE08BDC + +#define mmTPC0_QM_ARB_MST_CRED_STS_12 0xE08BE0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_13 0xE08BE4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_14 0xE08BE8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_15 0xE08BEC + +#define mmTPC0_QM_ARB_MST_CRED_STS_16 0xE08BF0 + +#define mmTPC0_QM_ARB_MST_CRED_STS_17 0xE08BF4 + +#define mmTPC0_QM_ARB_MST_CRED_STS_18 0xE08BF8 + +#define mmTPC0_QM_ARB_MST_CRED_STS_19 0xE08BFC + +#define mmTPC0_QM_ARB_MST_CRED_STS_20 0xE08C00 + +#define mmTPC0_QM_ARB_MST_CRED_STS_21 0xE08C04 + +#define mmTPC0_QM_ARB_MST_CRED_STS_22 0xE08C08 + +#define mmTPC0_QM_ARB_MST_CRED_STS_23 0xE08C0C + +#define mmTPC0_QM_ARB_MST_CRED_STS_24 0xE08C10 + +#define mmTPC0_QM_ARB_MST_CRED_STS_25 0xE08C14 + +#define mmTPC0_QM_ARB_MST_CRED_STS_26 0xE08C18 + +#define mmTPC0_QM_ARB_MST_CRED_STS_27 0xE08C1C + +#define mmTPC0_QM_ARB_MST_CRED_STS_28 0xE08C20 + +#define mmTPC0_QM_ARB_MST_CRED_STS_29 0xE08C24 + +#define mmTPC0_QM_ARB_MST_CRED_STS_30 0xE08C28 + +#define mmTPC0_QM_ARB_MST_CRED_STS_31 0xE08C2C + +#define mmTPC0_QM_CGM_CFG 0xE08C70 + +#define mmTPC0_QM_CGM_STS 0xE08C74 + +#define mmTPC0_QM_CGM_CFG1 0xE08C78 + +#define mmTPC0_QM_LOCAL_RANGE_BASE 0xE08C80 + +#define mmTPC0_QM_LOCAL_RANGE_SIZE 0xE08C84 + +#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG 0xE08C90 + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 0xE08C94 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 0xE08C98 + +#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 0xE08C9C + +#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 0xE08CA0 + +#define mmTPC0_QM_GLBL_AXCACHE 0xE08CA4 + +#define mmTPC0_QM_IND_GW_APB_CFG 0xE08CB0 + +#define mmTPC0_QM_IND_GW_APB_WDATA 0xE08CB4 + +#define mmTPC0_QM_IND_GW_APB_RDATA 0xE08CB8 + +#define mmTPC0_QM_IND_GW_APB_STATUS 0xE08CBC + +#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08CD0 + +#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08CD4 + +#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08CD8 + +#define mmTPC0_QM_GLBL_MEM_INIT_BUSY 0xE08D00 + +#endif /* ASIC_REG_TPC0_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h new file mode 100644 index 000000000000..6736c476d979 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_CFG_REGS_H_ +#define ASIC_REG_TPC1_CFG_REGS_H_ + +/* + ***************************************** + * TPC1_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE46400 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE46404 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE46408 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE4640C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE46410 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE46414 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE46418 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE4641C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE46420 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE46424 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE46428 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE4642C + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE46430 + +#define mmTPC1_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE46434 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE46438 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE4643C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE46440 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE46444 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE46448 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE4644C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE46450 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE46454 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE46458 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE4645C + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE46460 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE46464 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE46468 + +#define mmTPC1_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE4646C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE46470 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE46474 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE46478 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE4647C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE46480 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE46484 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE46488 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE4648C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE46490 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE46494 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE46498 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE4649C + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE464A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE464A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE464A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE464AC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE464B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE464B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE464B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE464BC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE464C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE464C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE464C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE464CC + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE464D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE464D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE464D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE464DC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE464E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE464E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE464E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE464EC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE464F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE464F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE464F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE464FC + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE46500 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE46504 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE46508 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE4650C + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE46510 + +#define mmTPC1_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE46514 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE46518 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE4651C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE46520 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE46524 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE46528 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE4652C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE46530 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE46534 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE46538 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE4653C + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE46540 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE46544 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE46548 + +#define mmTPC1_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE4654C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE46550 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE46554 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE46558 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE4655C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE46560 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE46564 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE46568 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE4656C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE46570 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE46574 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE46578 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE4657C + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE46580 + +#define mmTPC1_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE46584 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE46588 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE4658C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE46590 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE46594 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE46598 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE4659C + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE465A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE465A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE465A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE465AC + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE465B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE465B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE465B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE465BC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE465C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE465C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE465C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE465CC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE465D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE465D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE465D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE465DC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE465E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE465E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE465E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE465EC + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE465F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE465F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE465F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE465FC + +#define mmTPC1_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE46600 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE46604 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE46608 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE4660C + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE46610 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE46614 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE46618 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE4661C + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE46620 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE46624 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE46628 + +#define mmTPC1_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE4662C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE46630 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE46634 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE46638 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE4663C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE46640 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE46644 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE46648 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE4664C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE46650 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE46654 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE46658 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE4665C + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE46660 + +#define mmTPC1_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE46664 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE46668 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE4666C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE46670 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE46674 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE46678 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE4667C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE46680 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE46684 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE46688 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE4668C + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE46690 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE46694 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE46698 + +#define mmTPC1_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE4669C + +#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE466A0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE466A4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE466A8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE466AC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE466B0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE466B4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE466B8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE466BC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE466C0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE466C4 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE466C8 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE466CC + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE466D0 + +#define mmTPC1_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE466D4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE466D8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE466DC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE466E0 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE466E4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE466E8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE466EC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE466F0 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE466F4 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE466F8 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE466FC + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE46700 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE46704 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE46708 + +#define mmTPC1_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE4670C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE46710 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE46714 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE46718 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE4671C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE46720 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE46724 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE46728 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE4672C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE46730 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE46734 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE46738 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE4673C + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE46740 + +#define mmTPC1_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE46744 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE46748 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE4674C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE46750 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE46754 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE46758 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE4675C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE46760 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE46764 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE46768 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE4676C + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE46770 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE46774 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE46778 + +#define mmTPC1_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE4677C + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE46780 + +#define mmTPC1_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE46784 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE46788 + +#define mmTPC1_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE4678C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_0 0xE46790 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_0 0xE46794 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_1 0xE46798 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_1 0xE4679C + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_2 0xE467A0 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_2 0xE467A4 + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_3 0xE467A8 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_3 0xE467AC + +#define mmTPC1_CFG_KERNEL_TID_BASE_DIM_4 0xE467B0 + +#define mmTPC1_CFG_KERNEL_TID_SIZE_DIM_4 0xE467B4 + +#define mmTPC1_CFG_KERNEL_KERNEL_CONFIG 0xE467B8 + +#define mmTPC1_CFG_KERNEL_KERNEL_ID 0xE467BC + +#define mmTPC1_CFG_KERNEL_SRF_0 0xE467C0 + +#define mmTPC1_CFG_KERNEL_SRF_1 0xE467C4 + +#define mmTPC1_CFG_KERNEL_SRF_2 0xE467C8 + +#define mmTPC1_CFG_KERNEL_SRF_3 0xE467CC + +#define mmTPC1_CFG_KERNEL_SRF_4 0xE467D0 + +#define mmTPC1_CFG_KERNEL_SRF_5 0xE467D4 + +#define mmTPC1_CFG_KERNEL_SRF_6 0xE467D8 + +#define mmTPC1_CFG_KERNEL_SRF_7 0xE467DC + +#define mmTPC1_CFG_KERNEL_SRF_8 0xE467E0 + +#define mmTPC1_CFG_KERNEL_SRF_9 0xE467E4 + +#define mmTPC1_CFG_KERNEL_SRF_10 0xE467E8 + +#define mmTPC1_CFG_KERNEL_SRF_11 0xE467EC + +#define mmTPC1_CFG_KERNEL_SRF_12 0xE467F0 + +#define mmTPC1_CFG_KERNEL_SRF_13 0xE467F4 + +#define mmTPC1_CFG_KERNEL_SRF_14 0xE467F8 + +#define mmTPC1_CFG_KERNEL_SRF_15 0xE467FC + +#define mmTPC1_CFG_KERNEL_SRF_16 0xE46800 + +#define mmTPC1_CFG_KERNEL_SRF_17 0xE46804 + +#define mmTPC1_CFG_KERNEL_SRF_18 0xE46808 + +#define mmTPC1_CFG_KERNEL_SRF_19 0xE4680C + +#define mmTPC1_CFG_KERNEL_SRF_20 0xE46810 + +#define mmTPC1_CFG_KERNEL_SRF_21 0xE46814 + +#define mmTPC1_CFG_KERNEL_SRF_22 0xE46818 + +#define mmTPC1_CFG_KERNEL_SRF_23 0xE4681C + +#define mmTPC1_CFG_KERNEL_SRF_24 0xE46820 + +#define mmTPC1_CFG_KERNEL_SRF_25 0xE46824 + +#define mmTPC1_CFG_KERNEL_SRF_26 0xE46828 + +#define mmTPC1_CFG_KERNEL_SRF_27 0xE4682C + +#define mmTPC1_CFG_KERNEL_SRF_28 0xE46830 + +#define mmTPC1_CFG_KERNEL_SRF_29 0xE46834 + +#define mmTPC1_CFG_KERNEL_SRF_30 0xE46838 + +#define mmTPC1_CFG_KERNEL_SRF_31 0xE4683C + +#define mmTPC1_CFG_ROUND_CSR 0xE468FC + +#define mmTPC1_CFG_PROT 0xE46900 + +#define mmTPC1_CFG_SEMAPHORE 0xE46908 + +#define mmTPC1_CFG_VFLAGS 0xE4690C + +#define mmTPC1_CFG_SFLAGS 0xE46910 + +#define mmTPC1_CFG_LFSR_POLYNOM 0xE46918 + +#define mmTPC1_CFG_STATUS 0xE4691C + +#define mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH 0xE46920 + +#define mmTPC1_CFG_CFG_SUBTRACT_VALUE 0xE46924 + +#define mmTPC1_CFG_SM_BASE_ADDRESS_HIGH 0xE4692C + +#define mmTPC1_CFG_TPC_CMD 0xE46930 + +#define mmTPC1_CFG_TPC_EXECUTE 0xE46938 + +#define mmTPC1_CFG_TPC_STALL 0xE4693C + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_LOW 0xE46940 + +#define mmTPC1_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE46944 + +#define mmTPC1_CFG_RD_RATE_LIMIT 0xE46948 + +#define mmTPC1_CFG_WR_RATE_LIMIT 0xE46950 + +#define mmTPC1_CFG_MSS_CONFIG 0xE46954 + +#define mmTPC1_CFG_TPC_INTR_CAUSE 0xE46958 + +#define mmTPC1_CFG_TPC_INTR_MASK 0xE4695C + +#define mmTPC1_CFG_WQ_CREDITS 0xE46960 + +#define mmTPC1_CFG_ARUSER_LO 0xE46964 + +#define mmTPC1_CFG_ARUSER_HI 0xE46968 + +#define mmTPC1_CFG_AWUSER_LO 0xE4696C + +#define mmTPC1_CFG_AWUSER_HI 0xE46970 + +#define mmTPC1_CFG_OPCODE_EXEC 0xE46974 + +#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE46978 + +#define mmTPC1_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE4697C + +#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE46980 + +#define mmTPC1_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE46984 + +#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE46988 + +#define mmTPC1_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE4698C + +#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE46990 + +#define mmTPC1_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE46994 + +#define mmTPC1_CFG_TSB_CFG_MAX_SIZE 0xE46998 + +#define mmTPC1_CFG_TSB_CFG 0xE4699C + +#define mmTPC1_CFG_DBGMEM_ADD 0xE469A0 + +#define mmTPC1_CFG_DBGMEM_DATA_WR 0xE469A4 + +#define mmTPC1_CFG_DBGMEM_DATA_RD 0xE469A8 + +#define mmTPC1_CFG_DBGMEM_CTRL 0xE469AC + +#define mmTPC1_CFG_DBGMEM_RC 0xE469B0 + +#define mmTPC1_CFG_TSB_INFLIGHT_CNTR 0xE469B4 + +#define mmTPC1_CFG_WQ_INFLIGHT_CNTR 0xE469B8 + +#define mmTPC1_CFG_WQ_LBW_TOTAL_CNTR 0xE469BC + +#define mmTPC1_CFG_WQ_HBW_TOTAL_CNTR 0xE469C0 + +#define mmTPC1_CFG_IRQ_OCCOUPY_CNTR 0xE469C4 + +#define mmTPC1_CFG_FUNC_MBIST_CNTRL 0xE469D0 + +#define mmTPC1_CFG_FUNC_MBIST_PAT 0xE469D4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_0 0xE469D8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_1 0xE469DC + +#define mmTPC1_CFG_FUNC_MBIST_MEM_2 0xE469E0 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_3 0xE469E4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_4 0xE469E8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_5 0xE469EC + +#define mmTPC1_CFG_FUNC_MBIST_MEM_6 0xE469F0 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_7 0xE469F4 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_8 0xE469F8 + +#define mmTPC1_CFG_FUNC_MBIST_MEM_9 0xE469FC + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE46A00 + +#define mmTPC1_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE46A04 + +#define mmTPC1_CFG_QM_TENSOR_0_PADDING_VALUE 0xE46A08 + +#define mmTPC1_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE46A0C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE46A10 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE46A14 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE46A18 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE46A1C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE46A20 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE46A24 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE46A28 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE46A2C + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE46A30 + +#define mmTPC1_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE46A34 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE46A38 + +#define mmTPC1_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE46A3C + +#define mmTPC1_CFG_QM_TENSOR_1_PADDING_VALUE 0xE46A40 + +#define mmTPC1_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE46A44 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE46A48 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE46A4C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE46A50 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE46A54 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE46A58 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE46A5C + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE46A60 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE46A64 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE46A68 + +#define mmTPC1_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE46A6C + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE46A70 + +#define mmTPC1_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE46A74 + +#define mmTPC1_CFG_QM_TENSOR_2_PADDING_VALUE 0xE46A78 + +#define mmTPC1_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE46A7C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE46A80 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE46A84 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE46A88 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE46A8C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE46A90 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE46A94 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE46A98 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE46A9C + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE46AA0 + +#define mmTPC1_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE46AA4 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE46AA8 + +#define mmTPC1_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE46AAC + +#define mmTPC1_CFG_QM_TENSOR_3_PADDING_VALUE 0xE46AB0 + +#define mmTPC1_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE46AB4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE46AB8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE46ABC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE46AC0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE46AC4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE46AC8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE46ACC + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE46AD0 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE46AD4 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE46AD8 + +#define mmTPC1_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE46ADC + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE46AE0 + +#define mmTPC1_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE46AE4 + +#define mmTPC1_CFG_QM_TENSOR_4_PADDING_VALUE 0xE46AE8 + +#define mmTPC1_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE46AEC + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE46AF0 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE46AF4 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE46AF8 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE46AFC + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE46B00 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE46B04 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE46B08 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE46B0C + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE46B10 + +#define mmTPC1_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE46B14 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE46B18 + +#define mmTPC1_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE46B1C + +#define mmTPC1_CFG_QM_TENSOR_5_PADDING_VALUE 0xE46B20 + +#define mmTPC1_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE46B24 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE46B28 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE46B2C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE46B30 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE46B34 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE46B38 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE46B3C + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE46B40 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE46B44 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE46B48 + +#define mmTPC1_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE46B4C + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE46B50 + +#define mmTPC1_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE46B54 + +#define mmTPC1_CFG_QM_TENSOR_6_PADDING_VALUE 0xE46B58 + +#define mmTPC1_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE46B5C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE46B60 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE46B64 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE46B68 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE46B6C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE46B70 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE46B74 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE46B78 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE46B7C + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE46B80 + +#define mmTPC1_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE46B84 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE46B88 + +#define mmTPC1_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE46B8C + +#define mmTPC1_CFG_QM_TENSOR_7_PADDING_VALUE 0xE46B90 + +#define mmTPC1_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE46B94 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE46B98 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE46B9C + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE46BA0 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE46BA4 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE46BA8 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE46BAC + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE46BB0 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE46BB4 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE46BB8 + +#define mmTPC1_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE46BBC + +#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE46BC0 + +#define mmTPC1_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE46BC4 + +#define mmTPC1_CFG_QM_TENSOR_8_PADDING_VALUE 0xE46BC8 + +#define mmTPC1_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE46BCC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE46BD0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE46BD4 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE46BD8 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE46BDC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE46BE0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE46BE4 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE46BE8 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE46BEC + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE46BF0 + +#define mmTPC1_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE46BF4 + +#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE46BF8 + +#define mmTPC1_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE46BFC + +#define mmTPC1_CFG_QM_TENSOR_9_PADDING_VALUE 0xE46C00 + +#define mmTPC1_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE46C04 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE46C08 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE46C0C + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE46C10 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE46C14 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE46C18 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE46C1C + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE46C20 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE46C24 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE46C28 + +#define mmTPC1_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE46C2C + +#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE46C30 + +#define mmTPC1_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE46C34 + +#define mmTPC1_CFG_QM_TENSOR_10_PADDING_VALUE 0xE46C38 + +#define mmTPC1_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE46C3C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE46C40 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE46C44 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE46C48 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE46C4C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE46C50 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE46C54 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE46C58 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE46C5C + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE46C60 + +#define mmTPC1_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE46C64 + +#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE46C68 + +#define mmTPC1_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE46C6C + +#define mmTPC1_CFG_QM_TENSOR_11_PADDING_VALUE 0xE46C70 + +#define mmTPC1_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE46C74 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE46C78 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE46C7C + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE46C80 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE46C84 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE46C88 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE46C8C + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE46C90 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE46C94 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE46C98 + +#define mmTPC1_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE46C9C + +#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE46CA0 + +#define mmTPC1_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE46CA4 + +#define mmTPC1_CFG_QM_TENSOR_12_PADDING_VALUE 0xE46CA8 + +#define mmTPC1_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE46CAC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE46CB0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE46CB4 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE46CB8 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE46CBC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE46CC0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE46CC4 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE46CC8 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE46CCC + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE46CD0 + +#define mmTPC1_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE46CD4 + +#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE46CD8 + +#define mmTPC1_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE46CDC + +#define mmTPC1_CFG_QM_TENSOR_13_PADDING_VALUE 0xE46CE0 + +#define mmTPC1_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE46CE4 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE46CE8 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE46CEC + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE46CF0 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE46CF4 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE46CF8 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE46CFC + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE46D00 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE46D04 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE46D08 + +#define mmTPC1_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE46D0C + +#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE46D10 + +#define mmTPC1_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE46D14 + +#define mmTPC1_CFG_QM_TENSOR_14_PADDING_VALUE 0xE46D18 + +#define mmTPC1_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE46D1C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE46D20 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE46D24 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE46D28 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE46D2C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE46D30 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE46D34 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE46D38 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE46D3C + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE46D40 + +#define mmTPC1_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE46D44 + +#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE46D48 + +#define mmTPC1_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE46D4C + +#define mmTPC1_CFG_QM_TENSOR_15_PADDING_VALUE 0xE46D50 + +#define mmTPC1_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE46D54 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE46D58 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE46D5C + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE46D60 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE46D64 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE46D68 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE46D6C + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE46D70 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE46D74 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE46D78 + +#define mmTPC1_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE46D7C + +#define mmTPC1_CFG_QM_SYNC_OBJECT_MESSAGE 0xE46D80 + +#define mmTPC1_CFG_QM_SYNC_OBJECT_ADDR 0xE46D84 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE46D88 + +#define mmTPC1_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE46D8C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_0 0xE46D90 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_0 0xE46D94 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_1 0xE46D98 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_1 0xE46D9C + +#define mmTPC1_CFG_QM_TID_BASE_DIM_2 0xE46DA0 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_2 0xE46DA4 + +#define mmTPC1_CFG_QM_TID_BASE_DIM_3 0xE46DA8 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_3 0xE46DAC + +#define mmTPC1_CFG_QM_TID_BASE_DIM_4 0xE46DB0 + +#define mmTPC1_CFG_QM_TID_SIZE_DIM_4 0xE46DB4 + +#define mmTPC1_CFG_QM_KERNEL_CONFIG 0xE46DB8 + +#define mmTPC1_CFG_QM_KERNEL_ID 0xE46DBC + +#define mmTPC1_CFG_QM_SRF_0 0xE46DC0 + +#define mmTPC1_CFG_QM_SRF_1 0xE46DC4 + +#define mmTPC1_CFG_QM_SRF_2 0xE46DC8 + +#define mmTPC1_CFG_QM_SRF_3 0xE46DCC + +#define mmTPC1_CFG_QM_SRF_4 0xE46DD0 + +#define mmTPC1_CFG_QM_SRF_5 0xE46DD4 + +#define mmTPC1_CFG_QM_SRF_6 0xE46DD8 + +#define mmTPC1_CFG_QM_SRF_7 0xE46DDC + +#define mmTPC1_CFG_QM_SRF_8 0xE46DE0 + +#define mmTPC1_CFG_QM_SRF_9 0xE46DE4 + +#define mmTPC1_CFG_QM_SRF_10 0xE46DE8 + +#define mmTPC1_CFG_QM_SRF_11 0xE46DEC + +#define mmTPC1_CFG_QM_SRF_12 0xE46DF0 + +#define mmTPC1_CFG_QM_SRF_13 0xE46DF4 + +#define mmTPC1_CFG_QM_SRF_14 0xE46DF8 + +#define mmTPC1_CFG_QM_SRF_15 0xE46DFC + +#define mmTPC1_CFG_QM_SRF_16 0xE46E00 + +#define mmTPC1_CFG_QM_SRF_17 0xE46E04 + +#define mmTPC1_CFG_QM_SRF_18 0xE46E08 + +#define mmTPC1_CFG_QM_SRF_19 0xE46E0C + +#define mmTPC1_CFG_QM_SRF_20 0xE46E10 + +#define mmTPC1_CFG_QM_SRF_21 0xE46E14 + +#define mmTPC1_CFG_QM_SRF_22 0xE46E18 + +#define mmTPC1_CFG_QM_SRF_23 0xE46E1C + +#define mmTPC1_CFG_QM_SRF_24 0xE46E20 + +#define mmTPC1_CFG_QM_SRF_25 0xE46E24 + +#define mmTPC1_CFG_QM_SRF_26 0xE46E28 + +#define mmTPC1_CFG_QM_SRF_27 0xE46E2C + +#define mmTPC1_CFG_QM_SRF_28 0xE46E30 + +#define mmTPC1_CFG_QM_SRF_29 0xE46E34 + +#define mmTPC1_CFG_QM_SRF_30 0xE46E38 + +#define mmTPC1_CFG_QM_SRF_31 0xE46E3C + +#endif /* ASIC_REG_TPC1_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h new file mode 100644 index 000000000000..af10ef7a87d9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc1_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC1_QM_REGS_H_ +#define ASIC_REG_TPC1_QM_REGS_H_ + +/* + ***************************************** + * TPC1_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC1_QM_GLBL_CFG0 0xE48000 + +#define mmTPC1_QM_GLBL_CFG1 0xE48004 + +#define mmTPC1_QM_GLBL_PROT 0xE48008 + +#define mmTPC1_QM_GLBL_ERR_CFG 0xE4800C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_0 0xE48010 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_1 0xE48014 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_2 0xE48018 + +#define mmTPC1_QM_GLBL_SECURE_PROPS_3 0xE4801C + +#define mmTPC1_QM_GLBL_SECURE_PROPS_4 0xE48020 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_0 0xE48024 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_1 0xE48028 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_2 0xE4802C + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_3 0xE48030 + +#define mmTPC1_QM_GLBL_NON_SECURE_PROPS_4 0xE48034 + +#define mmTPC1_QM_GLBL_STS0 0xE48038 + +#define mmTPC1_QM_GLBL_STS1_0 0xE48040 + +#define mmTPC1_QM_GLBL_STS1_1 0xE48044 + +#define mmTPC1_QM_GLBL_STS1_2 0xE48048 + +#define mmTPC1_QM_GLBL_STS1_3 0xE4804C + +#define mmTPC1_QM_GLBL_STS1_4 0xE48050 + +#define mmTPC1_QM_GLBL_MSG_EN_0 0xE48054 + +#define mmTPC1_QM_GLBL_MSG_EN_1 0xE48058 + +#define mmTPC1_QM_GLBL_MSG_EN_2 0xE4805C + +#define mmTPC1_QM_GLBL_MSG_EN_3 0xE48060 + +#define mmTPC1_QM_GLBL_MSG_EN_4 0xE48068 + +#define mmTPC1_QM_PQ_BASE_LO_0 0xE48070 + +#define mmTPC1_QM_PQ_BASE_LO_1 0xE48074 + +#define mmTPC1_QM_PQ_BASE_LO_2 0xE48078 + +#define mmTPC1_QM_PQ_BASE_LO_3 0xE4807C + +#define mmTPC1_QM_PQ_BASE_HI_0 0xE48080 + +#define mmTPC1_QM_PQ_BASE_HI_1 0xE48084 + +#define mmTPC1_QM_PQ_BASE_HI_2 0xE48088 + +#define mmTPC1_QM_PQ_BASE_HI_3 0xE4808C + +#define mmTPC1_QM_PQ_SIZE_0 0xE48090 + +#define mmTPC1_QM_PQ_SIZE_1 0xE48094 + +#define mmTPC1_QM_PQ_SIZE_2 0xE48098 + +#define mmTPC1_QM_PQ_SIZE_3 0xE4809C + +#define mmTPC1_QM_PQ_PI_0 0xE480A0 + +#define mmTPC1_QM_PQ_PI_1 0xE480A4 + +#define mmTPC1_QM_PQ_PI_2 0xE480A8 + +#define mmTPC1_QM_PQ_PI_3 0xE480AC + +#define mmTPC1_QM_PQ_CI_0 0xE480B0 + +#define mmTPC1_QM_PQ_CI_1 0xE480B4 + +#define mmTPC1_QM_PQ_CI_2 0xE480B8 + +#define mmTPC1_QM_PQ_CI_3 0xE480BC + +#define mmTPC1_QM_PQ_CFG0_0 0xE480C0 + +#define mmTPC1_QM_PQ_CFG0_1 0xE480C4 + +#define mmTPC1_QM_PQ_CFG0_2 0xE480C8 + +#define mmTPC1_QM_PQ_CFG0_3 0xE480CC + +#define mmTPC1_QM_PQ_CFG1_0 0xE480D0 + +#define mmTPC1_QM_PQ_CFG1_1 0xE480D4 + +#define mmTPC1_QM_PQ_CFG1_2 0xE480D8 + +#define mmTPC1_QM_PQ_CFG1_3 0xE480DC + +#define mmTPC1_QM_PQ_ARUSER_31_11_0 0xE480E0 + +#define mmTPC1_QM_PQ_ARUSER_31_11_1 0xE480E4 + +#define mmTPC1_QM_PQ_ARUSER_31_11_2 0xE480E8 + +#define mmTPC1_QM_PQ_ARUSER_31_11_3 0xE480EC + +#define mmTPC1_QM_PQ_STS0_0 0xE480F0 + +#define mmTPC1_QM_PQ_STS0_1 0xE480F4 + +#define mmTPC1_QM_PQ_STS0_2 0xE480F8 + +#define mmTPC1_QM_PQ_STS0_3 0xE480FC + +#define mmTPC1_QM_PQ_STS1_0 0xE48100 + +#define mmTPC1_QM_PQ_STS1_1 0xE48104 + +#define mmTPC1_QM_PQ_STS1_2 0xE48108 + +#define mmTPC1_QM_PQ_STS1_3 0xE4810C + +#define mmTPC1_QM_CQ_CFG0_0 0xE48110 + +#define mmTPC1_QM_CQ_CFG0_1 0xE48114 + +#define mmTPC1_QM_CQ_CFG0_2 0xE48118 + +#define mmTPC1_QM_CQ_CFG0_3 0xE4811C + +#define mmTPC1_QM_CQ_CFG0_4 0xE48120 + +#define mmTPC1_QM_CQ_CFG1_0 0xE48124 + +#define mmTPC1_QM_CQ_CFG1_1 0xE48128 + +#define mmTPC1_QM_CQ_CFG1_2 0xE4812C + +#define mmTPC1_QM_CQ_CFG1_3 0xE48130 + +#define mmTPC1_QM_CQ_CFG1_4 0xE48134 + +#define mmTPC1_QM_CQ_ARUSER_31_11_0 0xE48138 + +#define mmTPC1_QM_CQ_ARUSER_31_11_1 0xE4813C + +#define mmTPC1_QM_CQ_ARUSER_31_11_2 0xE48140 + +#define mmTPC1_QM_CQ_ARUSER_31_11_3 0xE48144 + +#define mmTPC1_QM_CQ_ARUSER_31_11_4 0xE48148 + +#define mmTPC1_QM_CQ_STS0_0 0xE4814C + +#define mmTPC1_QM_CQ_STS0_1 0xE48150 + +#define mmTPC1_QM_CQ_STS0_2 0xE48154 + +#define mmTPC1_QM_CQ_STS0_3 0xE48158 + +#define mmTPC1_QM_CQ_STS0_4 0xE4815C + +#define mmTPC1_QM_CQ_STS1_0 0xE48160 + +#define mmTPC1_QM_CQ_STS1_1 0xE48164 + +#define mmTPC1_QM_CQ_STS1_2 0xE48168 + +#define mmTPC1_QM_CQ_STS1_3 0xE4816C + +#define mmTPC1_QM_CQ_STS1_4 0xE48170 + +#define mmTPC1_QM_CQ_PTR_LO_0 0xE48174 + +#define mmTPC1_QM_CQ_PTR_HI_0 0xE48178 + +#define mmTPC1_QM_CQ_TSIZE_0 0xE4817C + +#define mmTPC1_QM_CQ_CTL_0 0xE48180 + +#define mmTPC1_QM_CQ_PTR_LO_1 0xE48184 + +#define mmTPC1_QM_CQ_PTR_HI_1 0xE48188 + +#define mmTPC1_QM_CQ_TSIZE_1 0xE4818C + +#define mmTPC1_QM_CQ_CTL_1 0xE48190 + +#define mmTPC1_QM_CQ_PTR_LO_2 0xE48194 + +#define mmTPC1_QM_CQ_PTR_HI_2 0xE48198 + +#define mmTPC1_QM_CQ_TSIZE_2 0xE4819C + +#define mmTPC1_QM_CQ_CTL_2 0xE481A0 + +#define mmTPC1_QM_CQ_PTR_LO_3 0xE481A4 + +#define mmTPC1_QM_CQ_PTR_HI_3 0xE481A8 + +#define mmTPC1_QM_CQ_TSIZE_3 0xE481AC + +#define mmTPC1_QM_CQ_CTL_3 0xE481B0 + +#define mmTPC1_QM_CQ_PTR_LO_4 0xE481B4 + +#define mmTPC1_QM_CQ_PTR_HI_4 0xE481B8 + +#define mmTPC1_QM_CQ_TSIZE_4 0xE481BC + +#define mmTPC1_QM_CQ_CTL_4 0xE481C0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_0 0xE481C4 + +#define mmTPC1_QM_CQ_PTR_LO_STS_1 0xE481C8 + +#define mmTPC1_QM_CQ_PTR_LO_STS_2 0xE481CC + +#define mmTPC1_QM_CQ_PTR_LO_STS_3 0xE481D0 + +#define mmTPC1_QM_CQ_PTR_LO_STS_4 0xE481D4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_0 0xE481D8 + +#define mmTPC1_QM_CQ_PTR_HI_STS_1 0xE481DC + +#define mmTPC1_QM_CQ_PTR_HI_STS_2 0xE481E0 + +#define mmTPC1_QM_CQ_PTR_HI_STS_3 0xE481E4 + +#define mmTPC1_QM_CQ_PTR_HI_STS_4 0xE481E8 + +#define mmTPC1_QM_CQ_TSIZE_STS_0 0xE481EC + +#define mmTPC1_QM_CQ_TSIZE_STS_1 0xE481F0 + +#define mmTPC1_QM_CQ_TSIZE_STS_2 0xE481F4 + +#define mmTPC1_QM_CQ_TSIZE_STS_3 0xE481F8 + +#define mmTPC1_QM_CQ_TSIZE_STS_4 0xE481FC + +#define mmTPC1_QM_CQ_CTL_STS_0 0xE48200 + +#define mmTPC1_QM_CQ_CTL_STS_1 0xE48204 + +#define mmTPC1_QM_CQ_CTL_STS_2 0xE48208 + +#define mmTPC1_QM_CQ_CTL_STS_3 0xE4820C + +#define mmTPC1_QM_CQ_CTL_STS_4 0xE48210 + +#define mmTPC1_QM_CQ_IFIFO_CNT_0 0xE48214 + +#define mmTPC1_QM_CQ_IFIFO_CNT_1 0xE48218 + +#define mmTPC1_QM_CQ_IFIFO_CNT_2 0xE4821C + +#define mmTPC1_QM_CQ_IFIFO_CNT_3 0xE48220 + +#define mmTPC1_QM_CQ_IFIFO_CNT_4 0xE48224 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_0 0xE48228 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_1 0xE4822C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_2 0xE48230 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_3 0xE48234 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_LO_4 0xE48238 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_0 0xE4823C + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_1 0xE48240 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_2 0xE48244 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_3 0xE48248 + +#define mmTPC1_QM_CP_MSG_BASE0_ADDR_HI_4 0xE4824C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_0 0xE48250 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_1 0xE48254 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_2 0xE48258 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_3 0xE4825C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_LO_4 0xE48260 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_0 0xE48264 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_1 0xE48268 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_2 0xE4826C + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_3 0xE48270 + +#define mmTPC1_QM_CP_MSG_BASE1_ADDR_HI_4 0xE48274 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_0 0xE48278 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_1 0xE4827C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_2 0xE48280 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_3 0xE48284 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_LO_4 0xE48288 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_0 0xE4828C + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_1 0xE48290 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_2 0xE48294 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_3 0xE48298 + +#define mmTPC1_QM_CP_MSG_BASE2_ADDR_HI_4 0xE4829C + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_0 0xE482A0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_1 0xE482A4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_2 0xE482A8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_3 0xE482AC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_LO_4 0xE482B0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_0 0xE482B4 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_1 0xE482B8 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_2 0xE482BC + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_3 0xE482C0 + +#define mmTPC1_QM_CP_MSG_BASE3_ADDR_HI_4 0xE482C4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_0 0xE482C8 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_1 0xE482CC + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_2 0xE482D0 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_3 0xE482D4 + +#define mmTPC1_QM_CP_LDMA_TSIZE_OFFSET_4 0xE482D8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE482E0 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE482E4 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE482E8 + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE482EC + +#define mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE482F0 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE482F4 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE482F8 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE482FC + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE48300 + +#define mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE48304 + +#define mmTPC1_QM_CP_FENCE0_RDATA_0 0xE48308 + +#define mmTPC1_QM_CP_FENCE0_RDATA_1 0xE4830C + +#define mmTPC1_QM_CP_FENCE0_RDATA_2 0xE48310 + +#define mmTPC1_QM_CP_FENCE0_RDATA_3 0xE48314 + +#define mmTPC1_QM_CP_FENCE0_RDATA_4 0xE48318 + +#define mmTPC1_QM_CP_FENCE1_RDATA_0 0xE4831C + +#define mmTPC1_QM_CP_FENCE1_RDATA_1 0xE48320 + +#define mmTPC1_QM_CP_FENCE1_RDATA_2 0xE48324 + +#define mmTPC1_QM_CP_FENCE1_RDATA_3 0xE48328 + +#define mmTPC1_QM_CP_FENCE1_RDATA_4 0xE4832C + +#define mmTPC1_QM_CP_FENCE2_RDATA_0 0xE48330 + +#define mmTPC1_QM_CP_FENCE2_RDATA_1 0xE48334 + +#define mmTPC1_QM_CP_FENCE2_RDATA_2 0xE48338 + +#define mmTPC1_QM_CP_FENCE2_RDATA_3 0xE4833C + +#define mmTPC1_QM_CP_FENCE2_RDATA_4 0xE48340 + +#define mmTPC1_QM_CP_FENCE3_RDATA_0 0xE48344 + +#define mmTPC1_QM_CP_FENCE3_RDATA_1 0xE48348 + +#define mmTPC1_QM_CP_FENCE3_RDATA_2 0xE4834C + +#define mmTPC1_QM_CP_FENCE3_RDATA_3 0xE48350 + +#define mmTPC1_QM_CP_FENCE3_RDATA_4 0xE48354 + +#define mmTPC1_QM_CP_FENCE0_CNT_0 0xE48358 + +#define mmTPC1_QM_CP_FENCE0_CNT_1 0xE4835C + +#define mmTPC1_QM_CP_FENCE0_CNT_2 0xE48360 + +#define mmTPC1_QM_CP_FENCE0_CNT_3 0xE48364 + +#define mmTPC1_QM_CP_FENCE0_CNT_4 0xE48368 + +#define mmTPC1_QM_CP_FENCE1_CNT_0 0xE4836C + +#define mmTPC1_QM_CP_FENCE1_CNT_1 0xE48370 + +#define mmTPC1_QM_CP_FENCE1_CNT_2 0xE48374 + +#define mmTPC1_QM_CP_FENCE1_CNT_3 0xE48378 + +#define mmTPC1_QM_CP_FENCE1_CNT_4 0xE4837C + +#define mmTPC1_QM_CP_FENCE2_CNT_0 0xE48380 + +#define mmTPC1_QM_CP_FENCE2_CNT_1 0xE48384 + +#define mmTPC1_QM_CP_FENCE2_CNT_2 0xE48388 + +#define mmTPC1_QM_CP_FENCE2_CNT_3 0xE4838C + +#define mmTPC1_QM_CP_FENCE2_CNT_4 0xE48390 + +#define mmTPC1_QM_CP_FENCE3_CNT_0 0xE48394 + +#define mmTPC1_QM_CP_FENCE3_CNT_1 0xE48398 + +#define mmTPC1_QM_CP_FENCE3_CNT_2 0xE4839C + +#define mmTPC1_QM_CP_FENCE3_CNT_3 0xE483A0 + +#define mmTPC1_QM_CP_FENCE3_CNT_4 0xE483A4 + +#define mmTPC1_QM_CP_STS_0 0xE483A8 + +#define mmTPC1_QM_CP_STS_1 0xE483AC + +#define mmTPC1_QM_CP_STS_2 0xE483B0 + +#define mmTPC1_QM_CP_STS_3 0xE483B4 + +#define mmTPC1_QM_CP_STS_4 0xE483B8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_0 0xE483BC + +#define mmTPC1_QM_CP_CURRENT_INST_LO_1 0xE483C0 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_2 0xE483C4 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_3 0xE483C8 + +#define mmTPC1_QM_CP_CURRENT_INST_LO_4 0xE483CC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_0 0xE483D0 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_1 0xE483D4 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_2 0xE483D8 + +#define mmTPC1_QM_CP_CURRENT_INST_HI_3 0xE483DC + +#define mmTPC1_QM_CP_CURRENT_INST_HI_4 0xE483E0 + +#define mmTPC1_QM_CP_BARRIER_CFG_0 0xE483F4 + +#define mmTPC1_QM_CP_BARRIER_CFG_1 0xE483F8 + +#define mmTPC1_QM_CP_BARRIER_CFG_2 0xE483FC + +#define mmTPC1_QM_CP_BARRIER_CFG_3 0xE48400 + +#define mmTPC1_QM_CP_BARRIER_CFG_4 0xE48404 + +#define mmTPC1_QM_CP_DBG_0_0 0xE48408 + +#define mmTPC1_QM_CP_DBG_0_1 0xE4840C + +#define mmTPC1_QM_CP_DBG_0_2 0xE48410 + +#define mmTPC1_QM_CP_DBG_0_3 0xE48414 + +#define mmTPC1_QM_CP_DBG_0_4 0xE48418 + +#define mmTPC1_QM_CP_ARUSER_31_11_0 0xE4841C + +#define mmTPC1_QM_CP_ARUSER_31_11_1 0xE48420 + +#define mmTPC1_QM_CP_ARUSER_31_11_2 0xE48424 + +#define mmTPC1_QM_CP_ARUSER_31_11_3 0xE48428 + +#define mmTPC1_QM_CP_ARUSER_31_11_4 0xE4842C + +#define mmTPC1_QM_CP_AWUSER_31_11_0 0xE48430 + +#define mmTPC1_QM_CP_AWUSER_31_11_1 0xE48434 + +#define mmTPC1_QM_CP_AWUSER_31_11_2 0xE48438 + +#define mmTPC1_QM_CP_AWUSER_31_11_3 0xE4843C + +#define mmTPC1_QM_CP_AWUSER_31_11_4 0xE48440 + +#define mmTPC1_QM_ARB_CFG_0 0xE48A00 + +#define mmTPC1_QM_ARB_CHOISE_Q_PUSH 0xE48A04 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_0 0xE48A08 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_1 0xE48A0C + +#define mmTPC1_QM_ARB_WRR_WEIGHT_2 0xE48A10 + +#define mmTPC1_QM_ARB_WRR_WEIGHT_3 0xE48A14 + +#define mmTPC1_QM_ARB_CFG_1 0xE48A18 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_0 0xE48A20 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_1 0xE48A24 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_2 0xE48A28 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_3 0xE48A2C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_4 0xE48A30 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_5 0xE48A34 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_6 0xE48A38 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_7 0xE48A3C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_8 0xE48A40 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_9 0xE48A44 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_10 0xE48A48 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_11 0xE48A4C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_12 0xE48A50 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_13 0xE48A54 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_14 0xE48A58 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_15 0xE48A5C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_16 0xE48A60 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_17 0xE48A64 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_18 0xE48A68 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_19 0xE48A6C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_20 0xE48A70 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_21 0xE48A74 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_22 0xE48A78 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_23 0xE48A7C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_24 0xE48A80 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_25 0xE48A84 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_26 0xE48A88 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_27 0xE48A8C + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_28 0xE48A90 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_29 0xE48A94 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_30 0xE48A98 + +#define mmTPC1_QM_ARB_MST_AVAIL_CRED_31 0xE48A9C + +#define mmTPC1_QM_ARB_MST_CRED_INC 0xE48AA0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE48AA4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE48AA8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE48AAC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE48AB0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE48AB4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE48AB8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE48ABC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE48AC0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE48AC4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE48AC8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE48ACC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE48AD0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE48AD4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE48AD8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE48ADC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE48AE0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE48AE4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE48AE8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE48AEC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE48AF0 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE48AF4 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE48AF8 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE48AFC + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE48B00 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE48B04 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE48B08 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE48B0C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE48B10 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE48B14 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE48B18 + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE48B1C + +#define mmTPC1_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE48B20 + +#define mmTPC1_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE48B28 + +#define mmTPC1_QM_ARB_MST_SLAVE_EN 0xE48B2C + +#define mmTPC1_QM_ARB_MST_QUIET_PER 0xE48B34 + +#define mmTPC1_QM_ARB_SLV_CHOISE_WDT 0xE48B38 + +#define mmTPC1_QM_ARB_SLV_ID 0xE48B3C + +#define mmTPC1_QM_ARB_MSG_MAX_INFLIGHT 0xE48B44 + +#define mmTPC1_QM_ARB_MSG_AWUSER_31_11 0xE48B48 + +#define mmTPC1_QM_ARB_MSG_AWUSER_SEC_PROP 0xE48B4C + +#define mmTPC1_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE48B50 + +#define mmTPC1_QM_ARB_BASE_LO 0xE48B54 + +#define mmTPC1_QM_ARB_BASE_HI 0xE48B58 + +#define mmTPC1_QM_ARB_STATE_STS 0xE48B80 + +#define mmTPC1_QM_ARB_CHOISE_FULLNESS_STS 0xE48B84 + +#define mmTPC1_QM_ARB_MSG_STS 0xE48B88 + +#define mmTPC1_QM_ARB_SLV_CHOISE_Q_HEAD 0xE48B8C + +#define mmTPC1_QM_ARB_ERR_CAUSE 0xE48B9C + +#define mmTPC1_QM_ARB_ERR_MSG_EN 0xE48BA0 + +#define mmTPC1_QM_ARB_ERR_STS_DRP 0xE48BA8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_0 0xE48BB0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_1 0xE48BB4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_2 0xE48BB8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_3 0xE48BBC + +#define mmTPC1_QM_ARB_MST_CRED_STS_4 0xE48BC0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_5 0xE48BC4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_6 0xE48BC8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_7 0xE48BCC + +#define mmTPC1_QM_ARB_MST_CRED_STS_8 0xE48BD0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_9 0xE48BD4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_10 0xE48BD8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_11 0xE48BDC + +#define mmTPC1_QM_ARB_MST_CRED_STS_12 0xE48BE0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_13 0xE48BE4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_14 0xE48BE8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_15 0xE48BEC + +#define mmTPC1_QM_ARB_MST_CRED_STS_16 0xE48BF0 + +#define mmTPC1_QM_ARB_MST_CRED_STS_17 0xE48BF4 + +#define mmTPC1_QM_ARB_MST_CRED_STS_18 0xE48BF8 + +#define mmTPC1_QM_ARB_MST_CRED_STS_19 0xE48BFC + +#define mmTPC1_QM_ARB_MST_CRED_STS_20 0xE48C00 + +#define mmTPC1_QM_ARB_MST_CRED_STS_21 0xE48C04 + +#define mmTPC1_QM_ARB_MST_CRED_STS_22 0xE48C08 + +#define mmTPC1_QM_ARB_MST_CRED_STS_23 0xE48C0C + +#define mmTPC1_QM_ARB_MST_CRED_STS_24 0xE48C10 + +#define mmTPC1_QM_ARB_MST_CRED_STS_25 0xE48C14 + +#define mmTPC1_QM_ARB_MST_CRED_STS_26 0xE48C18 + +#define mmTPC1_QM_ARB_MST_CRED_STS_27 0xE48C1C + +#define mmTPC1_QM_ARB_MST_CRED_STS_28 0xE48C20 + +#define mmTPC1_QM_ARB_MST_CRED_STS_29 0xE48C24 + +#define mmTPC1_QM_ARB_MST_CRED_STS_30 0xE48C28 + +#define mmTPC1_QM_ARB_MST_CRED_STS_31 0xE48C2C + +#define mmTPC1_QM_CGM_CFG 0xE48C70 + +#define mmTPC1_QM_CGM_STS 0xE48C74 + +#define mmTPC1_QM_CGM_CFG1 0xE48C78 + +#define mmTPC1_QM_LOCAL_RANGE_BASE 0xE48C80 + +#define mmTPC1_QM_LOCAL_RANGE_SIZE 0xE48C84 + +#define mmTPC1_QM_CSMR_STRICT_PRIO_CFG 0xE48C90 + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_1 0xE48C94 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_0 0xE48C98 + +#define mmTPC1_QM_LBW_WR_RATE_LIM_CFG_1 0xE48C9C + +#define mmTPC1_QM_HBW_RD_RATE_LIM_CFG_0 0xE48CA0 + +#define mmTPC1_QM_GLBL_AXCACHE 0xE48CA4 + +#define mmTPC1_QM_IND_GW_APB_CFG 0xE48CB0 + +#define mmTPC1_QM_IND_GW_APB_WDATA 0xE48CB4 + +#define mmTPC1_QM_IND_GW_APB_RDATA 0xE48CB8 + +#define mmTPC1_QM_IND_GW_APB_STATUS 0xE48CBC + +#define mmTPC1_QM_GLBL_ERR_ADDR_LO 0xE48CD0 + +#define mmTPC1_QM_GLBL_ERR_ADDR_HI 0xE48CD4 + +#define mmTPC1_QM_GLBL_ERR_WDATA 0xE48CD8 + +#define mmTPC1_QM_GLBL_MEM_INIT_BUSY 0xE48D00 + +#endif /* ASIC_REG_TPC1_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h new file mode 100644 index 000000000000..3e77c37952bc --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_CFG_REGS_H_ +#define ASIC_REG_TPC2_CFG_REGS_H_ + +/* + ***************************************** + * TPC2_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xE86400 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xE86404 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xE86408 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xE8640C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xE86410 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xE86414 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xE86418 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xE8641C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xE86420 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xE86424 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xE86428 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xE8642C + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xE86430 + +#define mmTPC2_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xE86434 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xE86438 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xE8643C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xE86440 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xE86444 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xE86448 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xE8644C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xE86450 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xE86454 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xE86458 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xE8645C + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xE86460 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xE86464 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xE86468 + +#define mmTPC2_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xE8646C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xE86470 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xE86474 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xE86478 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xE8647C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xE86480 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xE86484 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xE86488 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xE8648C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xE86490 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xE86494 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xE86498 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xE8649C + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xE864A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xE864A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xE864A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xE864AC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xE864B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xE864B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xE864B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xE864BC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xE864C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xE864C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xE864C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xE864CC + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xE864D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xE864D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xE864D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xE864DC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xE864E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xE864E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xE864E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xE864EC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xE864F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xE864F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xE864F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xE864FC + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xE86500 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xE86504 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xE86508 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xE8650C + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xE86510 + +#define mmTPC2_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xE86514 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xE86518 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xE8651C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xE86520 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xE86524 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xE86528 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xE8652C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xE86530 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xE86534 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xE86538 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xE8653C + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xE86540 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xE86544 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xE86548 + +#define mmTPC2_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xE8654C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xE86550 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xE86554 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xE86558 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xE8655C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xE86560 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xE86564 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xE86568 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xE8656C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xE86570 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xE86574 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xE86578 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xE8657C + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xE86580 + +#define mmTPC2_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xE86584 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xE86588 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xE8658C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xE86590 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xE86594 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xE86598 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xE8659C + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xE865A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xE865A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xE865A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xE865AC + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xE865B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xE865B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xE865B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xE865BC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xE865C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xE865C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xE865C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xE865CC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xE865D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xE865D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xE865D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xE865DC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xE865E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xE865E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xE865E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xE865EC + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xE865F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xE865F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xE865F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xE865FC + +#define mmTPC2_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xE86600 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xE86604 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xE86608 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xE8660C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xE86610 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xE86614 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xE86618 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xE8661C + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xE86620 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xE86624 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xE86628 + +#define mmTPC2_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xE8662C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xE86630 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xE86634 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xE86638 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xE8663C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xE86640 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xE86644 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xE86648 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xE8664C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xE86650 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xE86654 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xE86658 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xE8665C + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xE86660 + +#define mmTPC2_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xE86664 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xE86668 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xE8666C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xE86670 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xE86674 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xE86678 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xE8667C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xE86680 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xE86684 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xE86688 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xE8668C + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xE86690 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xE86694 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xE86698 + +#define mmTPC2_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xE8669C + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xE866A0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xE866A4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xE866A8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xE866AC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xE866B0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xE866B4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xE866B8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xE866BC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xE866C0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xE866C4 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xE866C8 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xE866CC + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xE866D0 + +#define mmTPC2_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xE866D4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xE866D8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xE866DC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xE866E0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xE866E4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xE866E8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xE866EC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xE866F0 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xE866F4 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xE866F8 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xE866FC + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xE86700 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xE86704 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xE86708 + +#define mmTPC2_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xE8670C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xE86710 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xE86714 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xE86718 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xE8671C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xE86720 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xE86724 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xE86728 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xE8672C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xE86730 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xE86734 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xE86738 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xE8673C + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xE86740 + +#define mmTPC2_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xE86744 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xE86748 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xE8674C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xE86750 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xE86754 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xE86758 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xE8675C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xE86760 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xE86764 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xE86768 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xE8676C + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xE86770 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xE86774 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xE86778 + +#define mmTPC2_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xE8677C + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xE86780 + +#define mmTPC2_CFG_KERNEL_SYNC_OBJECT_ADDR 0xE86784 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xE86788 + +#define mmTPC2_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xE8678C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_0 0xE86790 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_0 0xE86794 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_1 0xE86798 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_1 0xE8679C + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_2 0xE867A0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_2 0xE867A4 + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_3 0xE867A8 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_3 0xE867AC + +#define mmTPC2_CFG_KERNEL_TID_BASE_DIM_4 0xE867B0 + +#define mmTPC2_CFG_KERNEL_TID_SIZE_DIM_4 0xE867B4 + +#define mmTPC2_CFG_KERNEL_KERNEL_CONFIG 0xE867B8 + +#define mmTPC2_CFG_KERNEL_KERNEL_ID 0xE867BC + +#define mmTPC2_CFG_KERNEL_SRF_0 0xE867C0 + +#define mmTPC2_CFG_KERNEL_SRF_1 0xE867C4 + +#define mmTPC2_CFG_KERNEL_SRF_2 0xE867C8 + +#define mmTPC2_CFG_KERNEL_SRF_3 0xE867CC + +#define mmTPC2_CFG_KERNEL_SRF_4 0xE867D0 + +#define mmTPC2_CFG_KERNEL_SRF_5 0xE867D4 + +#define mmTPC2_CFG_KERNEL_SRF_6 0xE867D8 + +#define mmTPC2_CFG_KERNEL_SRF_7 0xE867DC + +#define mmTPC2_CFG_KERNEL_SRF_8 0xE867E0 + +#define mmTPC2_CFG_KERNEL_SRF_9 0xE867E4 + +#define mmTPC2_CFG_KERNEL_SRF_10 0xE867E8 + +#define mmTPC2_CFG_KERNEL_SRF_11 0xE867EC + +#define mmTPC2_CFG_KERNEL_SRF_12 0xE867F0 + +#define mmTPC2_CFG_KERNEL_SRF_13 0xE867F4 + +#define mmTPC2_CFG_KERNEL_SRF_14 0xE867F8 + +#define mmTPC2_CFG_KERNEL_SRF_15 0xE867FC + +#define mmTPC2_CFG_KERNEL_SRF_16 0xE86800 + +#define mmTPC2_CFG_KERNEL_SRF_17 0xE86804 + +#define mmTPC2_CFG_KERNEL_SRF_18 0xE86808 + +#define mmTPC2_CFG_KERNEL_SRF_19 0xE8680C + +#define mmTPC2_CFG_KERNEL_SRF_20 0xE86810 + +#define mmTPC2_CFG_KERNEL_SRF_21 0xE86814 + +#define mmTPC2_CFG_KERNEL_SRF_22 0xE86818 + +#define mmTPC2_CFG_KERNEL_SRF_23 0xE8681C + +#define mmTPC2_CFG_KERNEL_SRF_24 0xE86820 + +#define mmTPC2_CFG_KERNEL_SRF_25 0xE86824 + +#define mmTPC2_CFG_KERNEL_SRF_26 0xE86828 + +#define mmTPC2_CFG_KERNEL_SRF_27 0xE8682C + +#define mmTPC2_CFG_KERNEL_SRF_28 0xE86830 + +#define mmTPC2_CFG_KERNEL_SRF_29 0xE86834 + +#define mmTPC2_CFG_KERNEL_SRF_30 0xE86838 + +#define mmTPC2_CFG_KERNEL_SRF_31 0xE8683C + +#define mmTPC2_CFG_ROUND_CSR 0xE868FC + +#define mmTPC2_CFG_PROT 0xE86900 + +#define mmTPC2_CFG_SEMAPHORE 0xE86908 + +#define mmTPC2_CFG_VFLAGS 0xE8690C + +#define mmTPC2_CFG_SFLAGS 0xE86910 + +#define mmTPC2_CFG_LFSR_POLYNOM 0xE86918 + +#define mmTPC2_CFG_STATUS 0xE8691C + +#define mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH 0xE86920 + +#define mmTPC2_CFG_CFG_SUBTRACT_VALUE 0xE86924 + +#define mmTPC2_CFG_SM_BASE_ADDRESS_HIGH 0xE8692C + +#define mmTPC2_CFG_TPC_CMD 0xE86930 + +#define mmTPC2_CFG_TPC_EXECUTE 0xE86938 + +#define mmTPC2_CFG_TPC_STALL 0xE8693C + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_LOW 0xE86940 + +#define mmTPC2_CFG_ICACHE_BASE_ADDERESS_HIGH 0xE86944 + +#define mmTPC2_CFG_RD_RATE_LIMIT 0xE86948 + +#define mmTPC2_CFG_WR_RATE_LIMIT 0xE86950 + +#define mmTPC2_CFG_MSS_CONFIG 0xE86954 + +#define mmTPC2_CFG_TPC_INTR_CAUSE 0xE86958 + +#define mmTPC2_CFG_TPC_INTR_MASK 0xE8695C + +#define mmTPC2_CFG_WQ_CREDITS 0xE86960 + +#define mmTPC2_CFG_ARUSER_LO 0xE86964 + +#define mmTPC2_CFG_ARUSER_HI 0xE86968 + +#define mmTPC2_CFG_AWUSER_LO 0xE8696C + +#define mmTPC2_CFG_AWUSER_HI 0xE86970 + +#define mmTPC2_CFG_OPCODE_EXEC 0xE86974 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_LO 0xE86978 + +#define mmTPC2_CFG_LUT_FUNC32_BASE_ADDR_HI 0xE8697C + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_LO 0xE86980 + +#define mmTPC2_CFG_LUT_FUNC64_BASE_ADDR_HI 0xE86984 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_LO 0xE86988 + +#define mmTPC2_CFG_LUT_FUNC128_BASE_ADDR_HI 0xE8698C + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_LO 0xE86990 + +#define mmTPC2_CFG_LUT_FUNC256_BASE_ADDR_HI 0xE86994 + +#define mmTPC2_CFG_TSB_CFG_MAX_SIZE 0xE86998 + +#define mmTPC2_CFG_TSB_CFG 0xE8699C + +#define mmTPC2_CFG_DBGMEM_ADD 0xE869A0 + +#define mmTPC2_CFG_DBGMEM_DATA_WR 0xE869A4 + +#define mmTPC2_CFG_DBGMEM_DATA_RD 0xE869A8 + +#define mmTPC2_CFG_DBGMEM_CTRL 0xE869AC + +#define mmTPC2_CFG_DBGMEM_RC 0xE869B0 + +#define mmTPC2_CFG_TSB_INFLIGHT_CNTR 0xE869B4 + +#define mmTPC2_CFG_WQ_INFLIGHT_CNTR 0xE869B8 + +#define mmTPC2_CFG_WQ_LBW_TOTAL_CNTR 0xE869BC + +#define mmTPC2_CFG_WQ_HBW_TOTAL_CNTR 0xE869C0 + +#define mmTPC2_CFG_IRQ_OCCOUPY_CNTR 0xE869C4 + +#define mmTPC2_CFG_FUNC_MBIST_CNTRL 0xE869D0 + +#define mmTPC2_CFG_FUNC_MBIST_PAT 0xE869D4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_0 0xE869D8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_1 0xE869DC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_2 0xE869E0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_3 0xE869E4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_4 0xE869E8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_5 0xE869EC + +#define mmTPC2_CFG_FUNC_MBIST_MEM_6 0xE869F0 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_7 0xE869F4 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_8 0xE869F8 + +#define mmTPC2_CFG_FUNC_MBIST_MEM_9 0xE869FC + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xE86A00 + +#define mmTPC2_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xE86A04 + +#define mmTPC2_CFG_QM_TENSOR_0_PADDING_VALUE 0xE86A08 + +#define mmTPC2_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xE86A0C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_SIZE 0xE86A10 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xE86A14 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_SIZE 0xE86A18 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xE86A1C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_SIZE 0xE86A20 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xE86A24 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_SIZE 0xE86A28 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xE86A2C + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_SIZE 0xE86A30 + +#define mmTPC2_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xE86A34 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xE86A38 + +#define mmTPC2_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xE86A3C + +#define mmTPC2_CFG_QM_TENSOR_1_PADDING_VALUE 0xE86A40 + +#define mmTPC2_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xE86A44 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_SIZE 0xE86A48 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xE86A4C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_SIZE 0xE86A50 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xE86A54 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_SIZE 0xE86A58 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xE86A5C + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_SIZE 0xE86A60 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xE86A64 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_SIZE 0xE86A68 + +#define mmTPC2_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xE86A6C + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xE86A70 + +#define mmTPC2_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xE86A74 + +#define mmTPC2_CFG_QM_TENSOR_2_PADDING_VALUE 0xE86A78 + +#define mmTPC2_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xE86A7C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_SIZE 0xE86A80 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xE86A84 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_SIZE 0xE86A88 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xE86A8C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_SIZE 0xE86A90 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xE86A94 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_SIZE 0xE86A98 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xE86A9C + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_SIZE 0xE86AA0 + +#define mmTPC2_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xE86AA4 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xE86AA8 + +#define mmTPC2_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xE86AAC + +#define mmTPC2_CFG_QM_TENSOR_3_PADDING_VALUE 0xE86AB0 + +#define mmTPC2_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xE86AB4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_SIZE 0xE86AB8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xE86ABC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_SIZE 0xE86AC0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xE86AC4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_SIZE 0xE86AC8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xE86ACC + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_SIZE 0xE86AD0 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xE86AD4 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_SIZE 0xE86AD8 + +#define mmTPC2_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xE86ADC + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xE86AE0 + +#define mmTPC2_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xE86AE4 + +#define mmTPC2_CFG_QM_TENSOR_4_PADDING_VALUE 0xE86AE8 + +#define mmTPC2_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xE86AEC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_SIZE 0xE86AF0 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xE86AF4 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_SIZE 0xE86AF8 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xE86AFC + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_SIZE 0xE86B00 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xE86B04 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_SIZE 0xE86B08 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xE86B0C + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_SIZE 0xE86B10 + +#define mmTPC2_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xE86B14 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xE86B18 + +#define mmTPC2_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xE86B1C + +#define mmTPC2_CFG_QM_TENSOR_5_PADDING_VALUE 0xE86B20 + +#define mmTPC2_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xE86B24 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_SIZE 0xE86B28 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xE86B2C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_SIZE 0xE86B30 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xE86B34 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_SIZE 0xE86B38 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xE86B3C + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_SIZE 0xE86B40 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xE86B44 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_SIZE 0xE86B48 + +#define mmTPC2_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xE86B4C + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xE86B50 + +#define mmTPC2_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xE86B54 + +#define mmTPC2_CFG_QM_TENSOR_6_PADDING_VALUE 0xE86B58 + +#define mmTPC2_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xE86B5C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_SIZE 0xE86B60 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xE86B64 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_SIZE 0xE86B68 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xE86B6C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_SIZE 0xE86B70 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xE86B74 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_SIZE 0xE86B78 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xE86B7C + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_SIZE 0xE86B80 + +#define mmTPC2_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xE86B84 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xE86B88 + +#define mmTPC2_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xE86B8C + +#define mmTPC2_CFG_QM_TENSOR_7_PADDING_VALUE 0xE86B90 + +#define mmTPC2_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xE86B94 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_SIZE 0xE86B98 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xE86B9C + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_SIZE 0xE86BA0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xE86BA4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_SIZE 0xE86BA8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xE86BAC + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_SIZE 0xE86BB0 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xE86BB4 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_SIZE 0xE86BB8 + +#define mmTPC2_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xE86BBC + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xE86BC0 + +#define mmTPC2_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xE86BC4 + +#define mmTPC2_CFG_QM_TENSOR_8_PADDING_VALUE 0xE86BC8 + +#define mmTPC2_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xE86BCC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_SIZE 0xE86BD0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xE86BD4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_SIZE 0xE86BD8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xE86BDC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_SIZE 0xE86BE0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xE86BE4 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_SIZE 0xE86BE8 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xE86BEC + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_SIZE 0xE86BF0 + +#define mmTPC2_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xE86BF4 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xE86BF8 + +#define mmTPC2_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xE86BFC + +#define mmTPC2_CFG_QM_TENSOR_9_PADDING_VALUE 0xE86C00 + +#define mmTPC2_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xE86C04 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_SIZE 0xE86C08 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xE86C0C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_SIZE 0xE86C10 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xE86C14 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_SIZE 0xE86C18 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xE86C1C + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_SIZE 0xE86C20 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xE86C24 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_SIZE 0xE86C28 + +#define mmTPC2_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xE86C2C + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xE86C30 + +#define mmTPC2_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xE86C34 + +#define mmTPC2_CFG_QM_TENSOR_10_PADDING_VALUE 0xE86C38 + +#define mmTPC2_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xE86C3C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_SIZE 0xE86C40 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xE86C44 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_SIZE 0xE86C48 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xE86C4C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_SIZE 0xE86C50 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xE86C54 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_SIZE 0xE86C58 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xE86C5C + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_SIZE 0xE86C60 + +#define mmTPC2_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xE86C64 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xE86C68 + +#define mmTPC2_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xE86C6C + +#define mmTPC2_CFG_QM_TENSOR_11_PADDING_VALUE 0xE86C70 + +#define mmTPC2_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xE86C74 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_SIZE 0xE86C78 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xE86C7C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_SIZE 0xE86C80 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xE86C84 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_SIZE 0xE86C88 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xE86C8C + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_SIZE 0xE86C90 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xE86C94 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_SIZE 0xE86C98 + +#define mmTPC2_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xE86C9C + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xE86CA0 + +#define mmTPC2_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xE86CA4 + +#define mmTPC2_CFG_QM_TENSOR_12_PADDING_VALUE 0xE86CA8 + +#define mmTPC2_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xE86CAC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_SIZE 0xE86CB0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xE86CB4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_SIZE 0xE86CB8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xE86CBC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_SIZE 0xE86CC0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xE86CC4 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_SIZE 0xE86CC8 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xE86CCC + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_SIZE 0xE86CD0 + +#define mmTPC2_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xE86CD4 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xE86CD8 + +#define mmTPC2_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xE86CDC + +#define mmTPC2_CFG_QM_TENSOR_13_PADDING_VALUE 0xE86CE0 + +#define mmTPC2_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xE86CE4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_SIZE 0xE86CE8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xE86CEC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_SIZE 0xE86CF0 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xE86CF4 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_SIZE 0xE86CF8 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xE86CFC + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_SIZE 0xE86D00 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xE86D04 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_SIZE 0xE86D08 + +#define mmTPC2_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xE86D0C + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xE86D10 + +#define mmTPC2_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xE86D14 + +#define mmTPC2_CFG_QM_TENSOR_14_PADDING_VALUE 0xE86D18 + +#define mmTPC2_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xE86D1C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_SIZE 0xE86D20 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xE86D24 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_SIZE 0xE86D28 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xE86D2C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_SIZE 0xE86D30 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xE86D34 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_SIZE 0xE86D38 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xE86D3C + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_SIZE 0xE86D40 + +#define mmTPC2_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xE86D44 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xE86D48 + +#define mmTPC2_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xE86D4C + +#define mmTPC2_CFG_QM_TENSOR_15_PADDING_VALUE 0xE86D50 + +#define mmTPC2_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xE86D54 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_SIZE 0xE86D58 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xE86D5C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_SIZE 0xE86D60 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xE86D64 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_SIZE 0xE86D68 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xE86D6C + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_SIZE 0xE86D70 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xE86D74 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_SIZE 0xE86D78 + +#define mmTPC2_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xE86D7C + +#define mmTPC2_CFG_QM_SYNC_OBJECT_MESSAGE 0xE86D80 + +#define mmTPC2_CFG_QM_SYNC_OBJECT_ADDR 0xE86D84 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xE86D88 + +#define mmTPC2_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xE86D8C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_0 0xE86D90 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_0 0xE86D94 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_1 0xE86D98 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_1 0xE86D9C + +#define mmTPC2_CFG_QM_TID_BASE_DIM_2 0xE86DA0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_2 0xE86DA4 + +#define mmTPC2_CFG_QM_TID_BASE_DIM_3 0xE86DA8 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_3 0xE86DAC + +#define mmTPC2_CFG_QM_TID_BASE_DIM_4 0xE86DB0 + +#define mmTPC2_CFG_QM_TID_SIZE_DIM_4 0xE86DB4 + +#define mmTPC2_CFG_QM_KERNEL_CONFIG 0xE86DB8 + +#define mmTPC2_CFG_QM_KERNEL_ID 0xE86DBC + +#define mmTPC2_CFG_QM_SRF_0 0xE86DC0 + +#define mmTPC2_CFG_QM_SRF_1 0xE86DC4 + +#define mmTPC2_CFG_QM_SRF_2 0xE86DC8 + +#define mmTPC2_CFG_QM_SRF_3 0xE86DCC + +#define mmTPC2_CFG_QM_SRF_4 0xE86DD0 + +#define mmTPC2_CFG_QM_SRF_5 0xE86DD4 + +#define mmTPC2_CFG_QM_SRF_6 0xE86DD8 + +#define mmTPC2_CFG_QM_SRF_7 0xE86DDC + +#define mmTPC2_CFG_QM_SRF_8 0xE86DE0 + +#define mmTPC2_CFG_QM_SRF_9 0xE86DE4 + +#define mmTPC2_CFG_QM_SRF_10 0xE86DE8 + +#define mmTPC2_CFG_QM_SRF_11 0xE86DEC + +#define mmTPC2_CFG_QM_SRF_12 0xE86DF0 + +#define mmTPC2_CFG_QM_SRF_13 0xE86DF4 + +#define mmTPC2_CFG_QM_SRF_14 0xE86DF8 + +#define mmTPC2_CFG_QM_SRF_15 0xE86DFC + +#define mmTPC2_CFG_QM_SRF_16 0xE86E00 + +#define mmTPC2_CFG_QM_SRF_17 0xE86E04 + +#define mmTPC2_CFG_QM_SRF_18 0xE86E08 + +#define mmTPC2_CFG_QM_SRF_19 0xE86E0C + +#define mmTPC2_CFG_QM_SRF_20 0xE86E10 + +#define mmTPC2_CFG_QM_SRF_21 0xE86E14 + +#define mmTPC2_CFG_QM_SRF_22 0xE86E18 + +#define mmTPC2_CFG_QM_SRF_23 0xE86E1C + +#define mmTPC2_CFG_QM_SRF_24 0xE86E20 + +#define mmTPC2_CFG_QM_SRF_25 0xE86E24 + +#define mmTPC2_CFG_QM_SRF_26 0xE86E28 + +#define mmTPC2_CFG_QM_SRF_27 0xE86E2C + +#define mmTPC2_CFG_QM_SRF_28 0xE86E30 + +#define mmTPC2_CFG_QM_SRF_29 0xE86E34 + +#define mmTPC2_CFG_QM_SRF_30 0xE86E38 + +#define mmTPC2_CFG_QM_SRF_31 0xE86E3C + +#endif /* ASIC_REG_TPC2_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h new file mode 100644 index 000000000000..2919e2fa58f8 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc2_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC2_QM_REGS_H_ +#define ASIC_REG_TPC2_QM_REGS_H_ + +/* + ***************************************** + * TPC2_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC2_QM_GLBL_CFG0 0xE88000 + +#define mmTPC2_QM_GLBL_CFG1 0xE88004 + +#define mmTPC2_QM_GLBL_PROT 0xE88008 + +#define mmTPC2_QM_GLBL_ERR_CFG 0xE8800C + +#define mmTPC2_QM_GLBL_SECURE_PROPS_0 0xE88010 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_1 0xE88014 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_2 0xE88018 + +#define mmTPC2_QM_GLBL_SECURE_PROPS_3 0xE8801C + +#define mmTPC2_QM_GLBL_SECURE_PROPS_4 0xE88020 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_0 0xE88024 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_1 0xE88028 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_2 0xE8802C + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_3 0xE88030 + +#define mmTPC2_QM_GLBL_NON_SECURE_PROPS_4 0xE88034 + +#define mmTPC2_QM_GLBL_STS0 0xE88038 + +#define mmTPC2_QM_GLBL_STS1_0 0xE88040 + +#define mmTPC2_QM_GLBL_STS1_1 0xE88044 + +#define mmTPC2_QM_GLBL_STS1_2 0xE88048 + +#define mmTPC2_QM_GLBL_STS1_3 0xE8804C + +#define mmTPC2_QM_GLBL_STS1_4 0xE88050 + +#define mmTPC2_QM_GLBL_MSG_EN_0 0xE88054 + +#define mmTPC2_QM_GLBL_MSG_EN_1 0xE88058 + +#define mmTPC2_QM_GLBL_MSG_EN_2 0xE8805C + +#define mmTPC2_QM_GLBL_MSG_EN_3 0xE88060 + +#define mmTPC2_QM_GLBL_MSG_EN_4 0xE88068 + +#define mmTPC2_QM_PQ_BASE_LO_0 0xE88070 + +#define mmTPC2_QM_PQ_BASE_LO_1 0xE88074 + +#define mmTPC2_QM_PQ_BASE_LO_2 0xE88078 + +#define mmTPC2_QM_PQ_BASE_LO_3 0xE8807C + +#define mmTPC2_QM_PQ_BASE_HI_0 0xE88080 + +#define mmTPC2_QM_PQ_BASE_HI_1 0xE88084 + +#define mmTPC2_QM_PQ_BASE_HI_2 0xE88088 + +#define mmTPC2_QM_PQ_BASE_HI_3 0xE8808C + +#define mmTPC2_QM_PQ_SIZE_0 0xE88090 + +#define mmTPC2_QM_PQ_SIZE_1 0xE88094 + +#define mmTPC2_QM_PQ_SIZE_2 0xE88098 + +#define mmTPC2_QM_PQ_SIZE_3 0xE8809C + +#define mmTPC2_QM_PQ_PI_0 0xE880A0 + +#define mmTPC2_QM_PQ_PI_1 0xE880A4 + +#define mmTPC2_QM_PQ_PI_2 0xE880A8 + +#define mmTPC2_QM_PQ_PI_3 0xE880AC + +#define mmTPC2_QM_PQ_CI_0 0xE880B0 + +#define mmTPC2_QM_PQ_CI_1 0xE880B4 + +#define mmTPC2_QM_PQ_CI_2 0xE880B8 + +#define mmTPC2_QM_PQ_CI_3 0xE880BC + +#define mmTPC2_QM_PQ_CFG0_0 0xE880C0 + +#define mmTPC2_QM_PQ_CFG0_1 0xE880C4 + +#define mmTPC2_QM_PQ_CFG0_2 0xE880C8 + +#define mmTPC2_QM_PQ_CFG0_3 0xE880CC + +#define mmTPC2_QM_PQ_CFG1_0 0xE880D0 + +#define mmTPC2_QM_PQ_CFG1_1 0xE880D4 + +#define mmTPC2_QM_PQ_CFG1_2 0xE880D8 + +#define mmTPC2_QM_PQ_CFG1_3 0xE880DC + +#define mmTPC2_QM_PQ_ARUSER_31_11_0 0xE880E0 + +#define mmTPC2_QM_PQ_ARUSER_31_11_1 0xE880E4 + +#define mmTPC2_QM_PQ_ARUSER_31_11_2 0xE880E8 + +#define mmTPC2_QM_PQ_ARUSER_31_11_3 0xE880EC + +#define mmTPC2_QM_PQ_STS0_0 0xE880F0 + +#define mmTPC2_QM_PQ_STS0_1 0xE880F4 + +#define mmTPC2_QM_PQ_STS0_2 0xE880F8 + +#define mmTPC2_QM_PQ_STS0_3 0xE880FC + +#define mmTPC2_QM_PQ_STS1_0 0xE88100 + +#define mmTPC2_QM_PQ_STS1_1 0xE88104 + +#define mmTPC2_QM_PQ_STS1_2 0xE88108 + +#define mmTPC2_QM_PQ_STS1_3 0xE8810C + +#define mmTPC2_QM_CQ_CFG0_0 0xE88110 + +#define mmTPC2_QM_CQ_CFG0_1 0xE88114 + +#define mmTPC2_QM_CQ_CFG0_2 0xE88118 + +#define mmTPC2_QM_CQ_CFG0_3 0xE8811C + +#define mmTPC2_QM_CQ_CFG0_4 0xE88120 + +#define mmTPC2_QM_CQ_CFG1_0 0xE88124 + +#define mmTPC2_QM_CQ_CFG1_1 0xE88128 + +#define mmTPC2_QM_CQ_CFG1_2 0xE8812C + +#define mmTPC2_QM_CQ_CFG1_3 0xE88130 + +#define mmTPC2_QM_CQ_CFG1_4 0xE88134 + +#define mmTPC2_QM_CQ_ARUSER_31_11_0 0xE88138 + +#define mmTPC2_QM_CQ_ARUSER_31_11_1 0xE8813C + +#define mmTPC2_QM_CQ_ARUSER_31_11_2 0xE88140 + +#define mmTPC2_QM_CQ_ARUSER_31_11_3 0xE88144 + +#define mmTPC2_QM_CQ_ARUSER_31_11_4 0xE88148 + +#define mmTPC2_QM_CQ_STS0_0 0xE8814C + +#define mmTPC2_QM_CQ_STS0_1 0xE88150 + +#define mmTPC2_QM_CQ_STS0_2 0xE88154 + +#define mmTPC2_QM_CQ_STS0_3 0xE88158 + +#define mmTPC2_QM_CQ_STS0_4 0xE8815C + +#define mmTPC2_QM_CQ_STS1_0 0xE88160 + +#define mmTPC2_QM_CQ_STS1_1 0xE88164 + +#define mmTPC2_QM_CQ_STS1_2 0xE88168 + +#define mmTPC2_QM_CQ_STS1_3 0xE8816C + +#define mmTPC2_QM_CQ_STS1_4 0xE88170 + +#define mmTPC2_QM_CQ_PTR_LO_0 0xE88174 + +#define mmTPC2_QM_CQ_PTR_HI_0 0xE88178 + +#define mmTPC2_QM_CQ_TSIZE_0 0xE8817C + +#define mmTPC2_QM_CQ_CTL_0 0xE88180 + +#define mmTPC2_QM_CQ_PTR_LO_1 0xE88184 + +#define mmTPC2_QM_CQ_PTR_HI_1 0xE88188 + +#define mmTPC2_QM_CQ_TSIZE_1 0xE8818C + +#define mmTPC2_QM_CQ_CTL_1 0xE88190 + +#define mmTPC2_QM_CQ_PTR_LO_2 0xE88194 + +#define mmTPC2_QM_CQ_PTR_HI_2 0xE88198 + +#define mmTPC2_QM_CQ_TSIZE_2 0xE8819C + +#define mmTPC2_QM_CQ_CTL_2 0xE881A0 + +#define mmTPC2_QM_CQ_PTR_LO_3 0xE881A4 + +#define mmTPC2_QM_CQ_PTR_HI_3 0xE881A8 + +#define mmTPC2_QM_CQ_TSIZE_3 0xE881AC + +#define mmTPC2_QM_CQ_CTL_3 0xE881B0 + +#define mmTPC2_QM_CQ_PTR_LO_4 0xE881B4 + +#define mmTPC2_QM_CQ_PTR_HI_4 0xE881B8 + +#define mmTPC2_QM_CQ_TSIZE_4 0xE881BC + +#define mmTPC2_QM_CQ_CTL_4 0xE881C0 + +#define mmTPC2_QM_CQ_PTR_LO_STS_0 0xE881C4 + +#define mmTPC2_QM_CQ_PTR_LO_STS_1 0xE881C8 + +#define mmTPC2_QM_CQ_PTR_LO_STS_2 0xE881CC + +#define mmTPC2_QM_CQ_PTR_LO_STS_3 0xE881D0 + +#define mmTPC2_QM_CQ_PTR_LO_STS_4 0xE881D4 + +#define mmTPC2_QM_CQ_PTR_HI_STS_0 0xE881D8 + +#define mmTPC2_QM_CQ_PTR_HI_STS_1 0xE881DC + +#define mmTPC2_QM_CQ_PTR_HI_STS_2 0xE881E0 + +#define mmTPC2_QM_CQ_PTR_HI_STS_3 0xE881E4 + +#define mmTPC2_QM_CQ_PTR_HI_STS_4 0xE881E8 + +#define mmTPC2_QM_CQ_TSIZE_STS_0 0xE881EC + +#define mmTPC2_QM_CQ_TSIZE_STS_1 0xE881F0 + +#define mmTPC2_QM_CQ_TSIZE_STS_2 0xE881F4 + +#define mmTPC2_QM_CQ_TSIZE_STS_3 0xE881F8 + +#define mmTPC2_QM_CQ_TSIZE_STS_4 0xE881FC + +#define mmTPC2_QM_CQ_CTL_STS_0 0xE88200 + +#define mmTPC2_QM_CQ_CTL_STS_1 0xE88204 + +#define mmTPC2_QM_CQ_CTL_STS_2 0xE88208 + +#define mmTPC2_QM_CQ_CTL_STS_3 0xE8820C + +#define mmTPC2_QM_CQ_CTL_STS_4 0xE88210 + +#define mmTPC2_QM_CQ_IFIFO_CNT_0 0xE88214 + +#define mmTPC2_QM_CQ_IFIFO_CNT_1 0xE88218 + +#define mmTPC2_QM_CQ_IFIFO_CNT_2 0xE8821C + +#define mmTPC2_QM_CQ_IFIFO_CNT_3 0xE88220 + +#define mmTPC2_QM_CQ_IFIFO_CNT_4 0xE88224 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_0 0xE88228 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_1 0xE8822C + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_2 0xE88230 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_3 0xE88234 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_LO_4 0xE88238 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_0 0xE8823C + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_1 0xE88240 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_2 0xE88244 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_3 0xE88248 + +#define mmTPC2_QM_CP_MSG_BASE0_ADDR_HI_4 0xE8824C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_0 0xE88250 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_1 0xE88254 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_2 0xE88258 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_3 0xE8825C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_LO_4 0xE88260 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_0 0xE88264 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_1 0xE88268 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_2 0xE8826C + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_3 0xE88270 + +#define mmTPC2_QM_CP_MSG_BASE1_ADDR_HI_4 0xE88274 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_0 0xE88278 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_1 0xE8827C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_2 0xE88280 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_3 0xE88284 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_LO_4 0xE88288 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_0 0xE8828C + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_1 0xE88290 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_2 0xE88294 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_3 0xE88298 + +#define mmTPC2_QM_CP_MSG_BASE2_ADDR_HI_4 0xE8829C + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_0 0xE882A0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_1 0xE882A4 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_2 0xE882A8 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_3 0xE882AC + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_LO_4 0xE882B0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_0 0xE882B4 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_1 0xE882B8 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_2 0xE882BC + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_3 0xE882C0 + +#define mmTPC2_QM_CP_MSG_BASE3_ADDR_HI_4 0xE882C4 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_0 0xE882C8 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_1 0xE882CC + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_2 0xE882D0 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_3 0xE882D4 + +#define mmTPC2_QM_CP_LDMA_TSIZE_OFFSET_4 0xE882D8 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE882E0 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE882E4 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE882E8 + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE882EC + +#define mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE882F0 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE882F4 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE882F8 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE882FC + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE88300 + +#define mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE88304 + +#define mmTPC2_QM_CP_FENCE0_RDATA_0 0xE88308 + +#define mmTPC2_QM_CP_FENCE0_RDATA_1 0xE8830C + +#define mmTPC2_QM_CP_FENCE0_RDATA_2 0xE88310 + +#define mmTPC2_QM_CP_FENCE0_RDATA_3 0xE88314 + +#define mmTPC2_QM_CP_FENCE0_RDATA_4 0xE88318 + +#define mmTPC2_QM_CP_FENCE1_RDATA_0 0xE8831C + +#define mmTPC2_QM_CP_FENCE1_RDATA_1 0xE88320 + +#define mmTPC2_QM_CP_FENCE1_RDATA_2 0xE88324 + +#define mmTPC2_QM_CP_FENCE1_RDATA_3 0xE88328 + +#define mmTPC2_QM_CP_FENCE1_RDATA_4 0xE8832C + +#define mmTPC2_QM_CP_FENCE2_RDATA_0 0xE88330 + +#define mmTPC2_QM_CP_FENCE2_RDATA_1 0xE88334 + +#define mmTPC2_QM_CP_FENCE2_RDATA_2 0xE88338 + +#define mmTPC2_QM_CP_FENCE2_RDATA_3 0xE8833C + +#define mmTPC2_QM_CP_FENCE2_RDATA_4 0xE88340 + +#define mmTPC2_QM_CP_FENCE3_RDATA_0 0xE88344 + +#define mmTPC2_QM_CP_FENCE3_RDATA_1 0xE88348 + +#define mmTPC2_QM_CP_FENCE3_RDATA_2 0xE8834C + +#define mmTPC2_QM_CP_FENCE3_RDATA_3 0xE88350 + +#define mmTPC2_QM_CP_FENCE3_RDATA_4 0xE88354 + +#define mmTPC2_QM_CP_FENCE0_CNT_0 0xE88358 + +#define mmTPC2_QM_CP_FENCE0_CNT_1 0xE8835C + +#define mmTPC2_QM_CP_FENCE0_CNT_2 0xE88360 + +#define mmTPC2_QM_CP_FENCE0_CNT_3 0xE88364 + +#define mmTPC2_QM_CP_FENCE0_CNT_4 0xE88368 + +#define mmTPC2_QM_CP_FENCE1_CNT_0 0xE8836C + +#define mmTPC2_QM_CP_FENCE1_CNT_1 0xE88370 + +#define mmTPC2_QM_CP_FENCE1_CNT_2 0xE88374 + +#define mmTPC2_QM_CP_FENCE1_CNT_3 0xE88378 + +#define mmTPC2_QM_CP_FENCE1_CNT_4 0xE8837C + +#define mmTPC2_QM_CP_FENCE2_CNT_0 0xE88380 + +#define mmTPC2_QM_CP_FENCE2_CNT_1 0xE88384 + +#define mmTPC2_QM_CP_FENCE2_CNT_2 0xE88388 + +#define mmTPC2_QM_CP_FENCE2_CNT_3 0xE8838C + +#define mmTPC2_QM_CP_FENCE2_CNT_4 0xE88390 + +#define mmTPC2_QM_CP_FENCE3_CNT_0 0xE88394 + +#define mmTPC2_QM_CP_FENCE3_CNT_1 0xE88398 + +#define mmTPC2_QM_CP_FENCE3_CNT_2 0xE8839C + +#define mmTPC2_QM_CP_FENCE3_CNT_3 0xE883A0 + +#define mmTPC2_QM_CP_FENCE3_CNT_4 0xE883A4 + +#define mmTPC2_QM_CP_STS_0 0xE883A8 + +#define mmTPC2_QM_CP_STS_1 0xE883AC + +#define mmTPC2_QM_CP_STS_2 0xE883B0 + +#define mmTPC2_QM_CP_STS_3 0xE883B4 + +#define mmTPC2_QM_CP_STS_4 0xE883B8 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_0 0xE883BC + +#define mmTPC2_QM_CP_CURRENT_INST_LO_1 0xE883C0 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_2 0xE883C4 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_3 0xE883C8 + +#define mmTPC2_QM_CP_CURRENT_INST_LO_4 0xE883CC + +#define mmTPC2_QM_CP_CURRENT_INST_HI_0 0xE883D0 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_1 0xE883D4 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_2 0xE883D8 + +#define mmTPC2_QM_CP_CURRENT_INST_HI_3 0xE883DC + +#define mmTPC2_QM_CP_CURRENT_INST_HI_4 0xE883E0 + +#define mmTPC2_QM_CP_BARRIER_CFG_0 0xE883F4 + +#define mmTPC2_QM_CP_BARRIER_CFG_1 0xE883F8 + +#define mmTPC2_QM_CP_BARRIER_CFG_2 0xE883FC + +#define mmTPC2_QM_CP_BARRIER_CFG_3 0xE88400 + +#define mmTPC2_QM_CP_BARRIER_CFG_4 0xE88404 + +#define mmTPC2_QM_CP_DBG_0_0 0xE88408 + +#define mmTPC2_QM_CP_DBG_0_1 0xE8840C + +#define mmTPC2_QM_CP_DBG_0_2 0xE88410 + +#define mmTPC2_QM_CP_DBG_0_3 0xE88414 + +#define mmTPC2_QM_CP_DBG_0_4 0xE88418 + +#define mmTPC2_QM_CP_ARUSER_31_11_0 0xE8841C + +#define mmTPC2_QM_CP_ARUSER_31_11_1 0xE88420 + +#define mmTPC2_QM_CP_ARUSER_31_11_2 0xE88424 + +#define mmTPC2_QM_CP_ARUSER_31_11_3 0xE88428 + +#define mmTPC2_QM_CP_ARUSER_31_11_4 0xE8842C + +#define mmTPC2_QM_CP_AWUSER_31_11_0 0xE88430 + +#define mmTPC2_QM_CP_AWUSER_31_11_1 0xE88434 + +#define mmTPC2_QM_CP_AWUSER_31_11_2 0xE88438 + +#define mmTPC2_QM_CP_AWUSER_31_11_3 0xE8843C + +#define mmTPC2_QM_CP_AWUSER_31_11_4 0xE88440 + +#define mmTPC2_QM_ARB_CFG_0 0xE88A00 + +#define mmTPC2_QM_ARB_CHOISE_Q_PUSH 0xE88A04 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_0 0xE88A08 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_1 0xE88A0C + +#define mmTPC2_QM_ARB_WRR_WEIGHT_2 0xE88A10 + +#define mmTPC2_QM_ARB_WRR_WEIGHT_3 0xE88A14 + +#define mmTPC2_QM_ARB_CFG_1 0xE88A18 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_0 0xE88A20 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_1 0xE88A24 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_2 0xE88A28 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_3 0xE88A2C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_4 0xE88A30 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_5 0xE88A34 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_6 0xE88A38 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_7 0xE88A3C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_8 0xE88A40 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_9 0xE88A44 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_10 0xE88A48 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_11 0xE88A4C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_12 0xE88A50 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_13 0xE88A54 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_14 0xE88A58 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_15 0xE88A5C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_16 0xE88A60 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_17 0xE88A64 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_18 0xE88A68 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_19 0xE88A6C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_20 0xE88A70 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_21 0xE88A74 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_22 0xE88A78 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_23 0xE88A7C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_24 0xE88A80 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_25 0xE88A84 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_26 0xE88A88 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_27 0xE88A8C + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_28 0xE88A90 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_29 0xE88A94 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_30 0xE88A98 + +#define mmTPC2_QM_ARB_MST_AVAIL_CRED_31 0xE88A9C + +#define mmTPC2_QM_ARB_MST_CRED_INC 0xE88AA0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE88AA4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE88AA8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE88AAC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE88AB0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE88AB4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE88AB8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE88ABC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE88AC0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE88AC4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE88AC8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE88ACC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE88AD0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE88AD4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE88AD8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE88ADC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE88AE0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE88AE4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE88AE8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE88AEC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE88AF0 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE88AF4 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE88AF8 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE88AFC + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE88B00 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE88B04 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE88B08 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE88B0C + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE88B10 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE88B14 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE88B18 + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE88B1C + +#define mmTPC2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE88B20 + +#define mmTPC2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE88B28 + +#define mmTPC2_QM_ARB_MST_SLAVE_EN 0xE88B2C + +#define mmTPC2_QM_ARB_MST_QUIET_PER 0xE88B34 + +#define mmTPC2_QM_ARB_SLV_CHOISE_WDT 0xE88B38 + +#define mmTPC2_QM_ARB_SLV_ID 0xE88B3C + +#define mmTPC2_QM_ARB_MSG_MAX_INFLIGHT 0xE88B44 + +#define mmTPC2_QM_ARB_MSG_AWUSER_31_11 0xE88B48 + +#define mmTPC2_QM_ARB_MSG_AWUSER_SEC_PROP 0xE88B4C + +#define mmTPC2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE88B50 + +#define mmTPC2_QM_ARB_BASE_LO 0xE88B54 + +#define mmTPC2_QM_ARB_BASE_HI 0xE88B58 + +#define mmTPC2_QM_ARB_STATE_STS 0xE88B80 + +#define mmTPC2_QM_ARB_CHOISE_FULLNESS_STS 0xE88B84 + +#define mmTPC2_QM_ARB_MSG_STS 0xE88B88 + +#define mmTPC2_QM_ARB_SLV_CHOISE_Q_HEAD 0xE88B8C + +#define mmTPC2_QM_ARB_ERR_CAUSE 0xE88B9C + +#define mmTPC2_QM_ARB_ERR_MSG_EN 0xE88BA0 + +#define mmTPC2_QM_ARB_ERR_STS_DRP 0xE88BA8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_0 0xE88BB0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_1 0xE88BB4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_2 0xE88BB8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_3 0xE88BBC + +#define mmTPC2_QM_ARB_MST_CRED_STS_4 0xE88BC0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_5 0xE88BC4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_6 0xE88BC8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_7 0xE88BCC + +#define mmTPC2_QM_ARB_MST_CRED_STS_8 0xE88BD0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_9 0xE88BD4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_10 0xE88BD8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_11 0xE88BDC + +#define mmTPC2_QM_ARB_MST_CRED_STS_12 0xE88BE0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_13 0xE88BE4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_14 0xE88BE8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_15 0xE88BEC + +#define mmTPC2_QM_ARB_MST_CRED_STS_16 0xE88BF0 + +#define mmTPC2_QM_ARB_MST_CRED_STS_17 0xE88BF4 + +#define mmTPC2_QM_ARB_MST_CRED_STS_18 0xE88BF8 + +#define mmTPC2_QM_ARB_MST_CRED_STS_19 0xE88BFC + +#define mmTPC2_QM_ARB_MST_CRED_STS_20 0xE88C00 + +#define mmTPC2_QM_ARB_MST_CRED_STS_21 0xE88C04 + +#define mmTPC2_QM_ARB_MST_CRED_STS_22 0xE88C08 + +#define mmTPC2_QM_ARB_MST_CRED_STS_23 0xE88C0C + +#define mmTPC2_QM_ARB_MST_CRED_STS_24 0xE88C10 + +#define mmTPC2_QM_ARB_MST_CRED_STS_25 0xE88C14 + +#define mmTPC2_QM_ARB_MST_CRED_STS_26 0xE88C18 + +#define mmTPC2_QM_ARB_MST_CRED_STS_27 0xE88C1C + +#define mmTPC2_QM_ARB_MST_CRED_STS_28 0xE88C20 + +#define mmTPC2_QM_ARB_MST_CRED_STS_29 0xE88C24 + +#define mmTPC2_QM_ARB_MST_CRED_STS_30 0xE88C28 + +#define mmTPC2_QM_ARB_MST_CRED_STS_31 0xE88C2C + +#define mmTPC2_QM_CGM_CFG 0xE88C70 + +#define mmTPC2_QM_CGM_STS 0xE88C74 + +#define mmTPC2_QM_CGM_CFG1 0xE88C78 + +#define mmTPC2_QM_LOCAL_RANGE_BASE 0xE88C80 + +#define mmTPC2_QM_LOCAL_RANGE_SIZE 0xE88C84 + +#define mmTPC2_QM_CSMR_STRICT_PRIO_CFG 0xE88C90 + +#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_1 0xE88C94 + +#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_0 0xE88C98 + +#define mmTPC2_QM_LBW_WR_RATE_LIM_CFG_1 0xE88C9C + +#define mmTPC2_QM_HBW_RD_RATE_LIM_CFG_0 0xE88CA0 + +#define mmTPC2_QM_GLBL_AXCACHE 0xE88CA4 + +#define mmTPC2_QM_IND_GW_APB_CFG 0xE88CB0 + +#define mmTPC2_QM_IND_GW_APB_WDATA 0xE88CB4 + +#define mmTPC2_QM_IND_GW_APB_RDATA 0xE88CB8 + +#define mmTPC2_QM_IND_GW_APB_STATUS 0xE88CBC + +#define mmTPC2_QM_GLBL_ERR_ADDR_LO 0xE88CD0 + +#define mmTPC2_QM_GLBL_ERR_ADDR_HI 0xE88CD4 + +#define mmTPC2_QM_GLBL_ERR_WDATA 0xE88CD8 + +#define mmTPC2_QM_GLBL_MEM_INIT_BUSY 0xE88D00 + +#endif /* ASIC_REG_TPC2_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h new file mode 100644 index 000000000000..6d42469659f1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_CFG_REGS_H_ +#define ASIC_REG_TPC3_CFG_REGS_H_ + +/* + ***************************************** + * TPC3_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC6418 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC641C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6420 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC6424 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6428 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC642C + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6430 + +#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6434 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC6438 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC643C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6440 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6444 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC6448 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC644C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6450 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC6454 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6458 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC645C + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6460 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6464 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC6468 + +#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC646C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6470 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC6474 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC6478 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC647C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC6480 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC6484 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC6488 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC648C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC6490 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC6494 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC6498 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC649C + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64AC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64BC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC64C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC64C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC64C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC64CC + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC64D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC64D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC64D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC64DC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC64E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC64E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC64E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC64EC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC64F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC64F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC64F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC64FC + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6500 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC6504 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6508 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC650C + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6510 + +#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6514 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC6518 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC651C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6520 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6524 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC6528 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC652C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6530 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC6534 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC6538 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC653C + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC6540 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC6544 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC6548 + +#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC654C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC6550 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC6554 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC6558 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC655C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC6560 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC6564 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC6568 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC656C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC6570 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC6574 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC6578 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC657C + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6580 + +#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC6584 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6588 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC658C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC6590 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6594 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6598 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC659C + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC65A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC65A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC65A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC65AC + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC65B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC65B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC65B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC65BC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xEC65C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xEC65C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xEC65C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xEC65CC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xEC65D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xEC65D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xEC65D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xEC65DC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xEC65E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xEC65E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xEC65E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xEC65EC + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xEC65F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xEC65F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xEC65F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xEC65FC + +#define mmTPC3_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xEC6600 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xEC6604 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xEC6608 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xEC660C + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xEC6610 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xEC6614 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xEC6618 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xEC661C + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xEC6620 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xEC6624 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xEC6628 + +#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xEC662C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xEC6630 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xEC6634 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xEC6638 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xEC663C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xEC6640 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xEC6644 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xEC6648 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xEC664C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xEC6650 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xEC6654 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xEC6658 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xEC665C + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xEC6660 + +#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xEC6664 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xEC6668 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xEC666C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xEC6670 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xEC6674 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xEC6678 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xEC667C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xEC6680 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xEC6684 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xEC6688 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xEC668C + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xEC6690 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xEC6694 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xEC6698 + +#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xEC669C + +#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xEC66A0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xEC66A4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xEC66A8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xEC66AC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xEC66B0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xEC66B4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xEC66B8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xEC66BC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xEC66C0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xEC66C4 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xEC66C8 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xEC66CC + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xEC66D0 + +#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xEC66D4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xEC66D8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xEC66DC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xEC66E0 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xEC66E4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xEC66E8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xEC66EC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xEC66F0 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xEC66F4 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xEC66F8 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xEC66FC + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xEC6700 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xEC6704 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xEC6708 + +#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xEC670C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xEC6710 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xEC6714 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xEC6718 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xEC671C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xEC6720 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xEC6724 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xEC6728 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xEC672C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xEC6730 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xEC6734 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xEC6738 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xEC673C + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xEC6740 + +#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xEC6744 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xEC6748 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xEC674C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xEC6750 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xEC6754 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xEC6758 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xEC675C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xEC6760 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xEC6764 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xEC6768 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xEC676C + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xEC6770 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xEC6774 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xEC6778 + +#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xEC677C + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6780 + +#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_ADDR 0xEC6784 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6788 + +#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC678C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6790 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC6794 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6798 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC679C + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC67A0 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC67A4 + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC67A8 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC67AC + +#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC67B0 + +#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC67B4 + +#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC67B8 + +#define mmTPC3_CFG_KERNEL_KERNEL_ID 0xEC67BC + +#define mmTPC3_CFG_KERNEL_SRF_0 0xEC67C0 + +#define mmTPC3_CFG_KERNEL_SRF_1 0xEC67C4 + +#define mmTPC3_CFG_KERNEL_SRF_2 0xEC67C8 + +#define mmTPC3_CFG_KERNEL_SRF_3 0xEC67CC + +#define mmTPC3_CFG_KERNEL_SRF_4 0xEC67D0 + +#define mmTPC3_CFG_KERNEL_SRF_5 0xEC67D4 + +#define mmTPC3_CFG_KERNEL_SRF_6 0xEC67D8 + +#define mmTPC3_CFG_KERNEL_SRF_7 0xEC67DC + +#define mmTPC3_CFG_KERNEL_SRF_8 0xEC67E0 + +#define mmTPC3_CFG_KERNEL_SRF_9 0xEC67E4 + +#define mmTPC3_CFG_KERNEL_SRF_10 0xEC67E8 + +#define mmTPC3_CFG_KERNEL_SRF_11 0xEC67EC + +#define mmTPC3_CFG_KERNEL_SRF_12 0xEC67F0 + +#define mmTPC3_CFG_KERNEL_SRF_13 0xEC67F4 + +#define mmTPC3_CFG_KERNEL_SRF_14 0xEC67F8 + +#define mmTPC3_CFG_KERNEL_SRF_15 0xEC67FC + +#define mmTPC3_CFG_KERNEL_SRF_16 0xEC6800 + +#define mmTPC3_CFG_KERNEL_SRF_17 0xEC6804 + +#define mmTPC3_CFG_KERNEL_SRF_18 0xEC6808 + +#define mmTPC3_CFG_KERNEL_SRF_19 0xEC680C + +#define mmTPC3_CFG_KERNEL_SRF_20 0xEC6810 + +#define mmTPC3_CFG_KERNEL_SRF_21 0xEC6814 + +#define mmTPC3_CFG_KERNEL_SRF_22 0xEC6818 + +#define mmTPC3_CFG_KERNEL_SRF_23 0xEC681C + +#define mmTPC3_CFG_KERNEL_SRF_24 0xEC6820 + +#define mmTPC3_CFG_KERNEL_SRF_25 0xEC6824 + +#define mmTPC3_CFG_KERNEL_SRF_26 0xEC6828 + +#define mmTPC3_CFG_KERNEL_SRF_27 0xEC682C + +#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6830 + +#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6834 + +#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6838 + +#define mmTPC3_CFG_KERNEL_SRF_31 0xEC683C + +#define mmTPC3_CFG_ROUND_CSR 0xEC68FC + +#define mmTPC3_CFG_PROT 0xEC6900 + +#define mmTPC3_CFG_SEMAPHORE 0xEC6908 + +#define mmTPC3_CFG_VFLAGS 0xEC690C + +#define mmTPC3_CFG_SFLAGS 0xEC6910 + +#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6918 + +#define mmTPC3_CFG_STATUS 0xEC691C + +#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6920 + +#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6924 + +#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC692C + +#define mmTPC3_CFG_TPC_CMD 0xEC6930 + +#define mmTPC3_CFG_TPC_EXECUTE 0xEC6938 + +#define mmTPC3_CFG_TPC_STALL 0xEC693C + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6940 + +#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6944 + +#define mmTPC3_CFG_RD_RATE_LIMIT 0xEC6948 + +#define mmTPC3_CFG_WR_RATE_LIMIT 0xEC6950 + +#define mmTPC3_CFG_MSS_CONFIG 0xEC6954 + +#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6958 + +#define mmTPC3_CFG_TPC_INTR_MASK 0xEC695C + +#define mmTPC3_CFG_WQ_CREDITS 0xEC6960 + +#define mmTPC3_CFG_ARUSER_LO 0xEC6964 + +#define mmTPC3_CFG_ARUSER_HI 0xEC6968 + +#define mmTPC3_CFG_AWUSER_LO 0xEC696C + +#define mmTPC3_CFG_AWUSER_HI 0xEC6970 + +#define mmTPC3_CFG_OPCODE_EXEC 0xEC6974 + +#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_LO 0xEC6978 + +#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_HI 0xEC697C + +#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_LO 0xEC6980 + +#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_HI 0xEC6984 + +#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_LO 0xEC6988 + +#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_HI 0xEC698C + +#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_LO 0xEC6990 + +#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_HI 0xEC6994 + +#define mmTPC3_CFG_TSB_CFG_MAX_SIZE 0xEC6998 + +#define mmTPC3_CFG_TSB_CFG 0xEC699C + +#define mmTPC3_CFG_DBGMEM_ADD 0xEC69A0 + +#define mmTPC3_CFG_DBGMEM_DATA_WR 0xEC69A4 + +#define mmTPC3_CFG_DBGMEM_DATA_RD 0xEC69A8 + +#define mmTPC3_CFG_DBGMEM_CTRL 0xEC69AC + +#define mmTPC3_CFG_DBGMEM_RC 0xEC69B0 + +#define mmTPC3_CFG_TSB_INFLIGHT_CNTR 0xEC69B4 + +#define mmTPC3_CFG_WQ_INFLIGHT_CNTR 0xEC69B8 + +#define mmTPC3_CFG_WQ_LBW_TOTAL_CNTR 0xEC69BC + +#define mmTPC3_CFG_WQ_HBW_TOTAL_CNTR 0xEC69C0 + +#define mmTPC3_CFG_IRQ_OCCOUPY_CNTR 0xEC69C4 + +#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC69D0 + +#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC69D4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC69D8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC69DC + +#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC69E0 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC69E4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC69E8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC69EC + +#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC69F0 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC69F4 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC69F8 + +#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC69FC + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00 + +#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04 + +#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08 + +#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A18 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A1C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A20 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A24 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A28 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A2C + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A30 + +#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A34 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A38 + +#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A3C + +#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A40 + +#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A44 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A48 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A4C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A50 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A54 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A58 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A5C + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A60 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A64 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A68 + +#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A6C + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A70 + +#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A74 + +#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6A78 + +#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6A7C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6A80 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6A84 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6A88 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6A8C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6A90 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6A94 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6A98 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6A9C + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AA0 + +#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6AA4 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AA8 + +#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AAC + +#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AB0 + +#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AB4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AB8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6ABC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6AC0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6AC4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6AC8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6ACC + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6AD0 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6AD4 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6AD8 + +#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6ADC + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6AE0 + +#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6AE4 + +#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6AE8 + +#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6AEC + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6AF0 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6AF4 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6AF8 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6AFC + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B00 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B04 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B08 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B0C + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B10 + +#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B14 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B18 + +#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B1C + +#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B20 + +#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B24 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B28 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B2C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B30 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B34 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6B38 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6B3C + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6B40 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6B44 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6B48 + +#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6B4C + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6B50 + +#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6B54 + +#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6B58 + +#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6B5C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6B60 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6B64 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6B68 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6B6C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6B70 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6B74 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6B78 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6B7C + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6B80 + +#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6B84 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6B88 + +#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6B8C + +#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6B90 + +#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6B94 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6B98 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6B9C + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6BA0 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6BA4 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6BA8 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6BAC + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6BB0 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6BB4 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6BB8 + +#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6BBC + +#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xEC6BC0 + +#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xEC6BC4 + +#define mmTPC3_CFG_QM_TENSOR_8_PADDING_VALUE 0xEC6BC8 + +#define mmTPC3_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xEC6BCC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_SIZE 0xEC6BD0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xEC6BD4 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_SIZE 0xEC6BD8 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xEC6BDC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_SIZE 0xEC6BE0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xEC6BE4 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_SIZE 0xEC6BE8 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xEC6BEC + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_SIZE 0xEC6BF0 + +#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xEC6BF4 + +#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xEC6BF8 + +#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xEC6BFC + +#define mmTPC3_CFG_QM_TENSOR_9_PADDING_VALUE 0xEC6C00 + +#define mmTPC3_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xEC6C04 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_SIZE 0xEC6C08 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xEC6C0C + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_SIZE 0xEC6C10 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xEC6C14 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_SIZE 0xEC6C18 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xEC6C1C + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_SIZE 0xEC6C20 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xEC6C24 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_SIZE 0xEC6C28 + +#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xEC6C2C + +#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xEC6C30 + +#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xEC6C34 + +#define mmTPC3_CFG_QM_TENSOR_10_PADDING_VALUE 0xEC6C38 + +#define mmTPC3_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xEC6C3C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_SIZE 0xEC6C40 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xEC6C44 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_SIZE 0xEC6C48 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xEC6C4C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_SIZE 0xEC6C50 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xEC6C54 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_SIZE 0xEC6C58 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xEC6C5C + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_SIZE 0xEC6C60 + +#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xEC6C64 + +#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xEC6C68 + +#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xEC6C6C + +#define mmTPC3_CFG_QM_TENSOR_11_PADDING_VALUE 0xEC6C70 + +#define mmTPC3_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xEC6C74 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_SIZE 0xEC6C78 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xEC6C7C + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_SIZE 0xEC6C80 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xEC6C84 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_SIZE 0xEC6C88 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xEC6C8C + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_SIZE 0xEC6C90 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xEC6C94 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_SIZE 0xEC6C98 + +#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xEC6C9C + +#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xEC6CA0 + +#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xEC6CA4 + +#define mmTPC3_CFG_QM_TENSOR_12_PADDING_VALUE 0xEC6CA8 + +#define mmTPC3_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xEC6CAC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_SIZE 0xEC6CB0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xEC6CB4 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_SIZE 0xEC6CB8 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xEC6CBC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_SIZE 0xEC6CC0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xEC6CC4 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_SIZE 0xEC6CC8 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xEC6CCC + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_SIZE 0xEC6CD0 + +#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xEC6CD4 + +#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xEC6CD8 + +#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xEC6CDC + +#define mmTPC3_CFG_QM_TENSOR_13_PADDING_VALUE 0xEC6CE0 + +#define mmTPC3_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xEC6CE4 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_SIZE 0xEC6CE8 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xEC6CEC + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_SIZE 0xEC6CF0 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xEC6CF4 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_SIZE 0xEC6CF8 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xEC6CFC + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_SIZE 0xEC6D00 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xEC6D04 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_SIZE 0xEC6D08 + +#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xEC6D0C + +#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xEC6D10 + +#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xEC6D14 + +#define mmTPC3_CFG_QM_TENSOR_14_PADDING_VALUE 0xEC6D18 + +#define mmTPC3_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xEC6D1C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_SIZE 0xEC6D20 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xEC6D24 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_SIZE 0xEC6D28 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xEC6D2C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_SIZE 0xEC6D30 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xEC6D34 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_SIZE 0xEC6D38 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xEC6D3C + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_SIZE 0xEC6D40 + +#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xEC6D44 + +#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xEC6D48 + +#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xEC6D4C + +#define mmTPC3_CFG_QM_TENSOR_15_PADDING_VALUE 0xEC6D50 + +#define mmTPC3_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xEC6D54 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_SIZE 0xEC6D58 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xEC6D5C + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_SIZE 0xEC6D60 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xEC6D64 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_SIZE 0xEC6D68 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xEC6D6C + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_SIZE 0xEC6D70 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xEC6D74 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_SIZE 0xEC6D78 + +#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xEC6D7C + +#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D80 + +#define mmTPC3_CFG_QM_SYNC_OBJECT_ADDR 0xEC6D84 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6D88 + +#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6D8C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6D90 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6D94 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6D98 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6D9C + +#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6DA0 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6DA4 + +#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6DA8 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6DAC + +#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6DB0 + +#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6DB4 + +#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6DB8 + +#define mmTPC3_CFG_QM_KERNEL_ID 0xEC6DBC + +#define mmTPC3_CFG_QM_SRF_0 0xEC6DC0 + +#define mmTPC3_CFG_QM_SRF_1 0xEC6DC4 + +#define mmTPC3_CFG_QM_SRF_2 0xEC6DC8 + +#define mmTPC3_CFG_QM_SRF_3 0xEC6DCC + +#define mmTPC3_CFG_QM_SRF_4 0xEC6DD0 + +#define mmTPC3_CFG_QM_SRF_5 0xEC6DD4 + +#define mmTPC3_CFG_QM_SRF_6 0xEC6DD8 + +#define mmTPC3_CFG_QM_SRF_7 0xEC6DDC + +#define mmTPC3_CFG_QM_SRF_8 0xEC6DE0 + +#define mmTPC3_CFG_QM_SRF_9 0xEC6DE4 + +#define mmTPC3_CFG_QM_SRF_10 0xEC6DE8 + +#define mmTPC3_CFG_QM_SRF_11 0xEC6DEC + +#define mmTPC3_CFG_QM_SRF_12 0xEC6DF0 + +#define mmTPC3_CFG_QM_SRF_13 0xEC6DF4 + +#define mmTPC3_CFG_QM_SRF_14 0xEC6DF8 + +#define mmTPC3_CFG_QM_SRF_15 0xEC6DFC + +#define mmTPC3_CFG_QM_SRF_16 0xEC6E00 + +#define mmTPC3_CFG_QM_SRF_17 0xEC6E04 + +#define mmTPC3_CFG_QM_SRF_18 0xEC6E08 + +#define mmTPC3_CFG_QM_SRF_19 0xEC6E0C + +#define mmTPC3_CFG_QM_SRF_20 0xEC6E10 + +#define mmTPC3_CFG_QM_SRF_21 0xEC6E14 + +#define mmTPC3_CFG_QM_SRF_22 0xEC6E18 + +#define mmTPC3_CFG_QM_SRF_23 0xEC6E1C + +#define mmTPC3_CFG_QM_SRF_24 0xEC6E20 + +#define mmTPC3_CFG_QM_SRF_25 0xEC6E24 + +#define mmTPC3_CFG_QM_SRF_26 0xEC6E28 + +#define mmTPC3_CFG_QM_SRF_27 0xEC6E2C + +#define mmTPC3_CFG_QM_SRF_28 0xEC6E30 + +#define mmTPC3_CFG_QM_SRF_29 0xEC6E34 + +#define mmTPC3_CFG_QM_SRF_30 0xEC6E38 + +#define mmTPC3_CFG_QM_SRF_31 0xEC6E3C + +#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h new file mode 100644 index 000000000000..5f2a0fd86c9e --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc3_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC3_QM_REGS_H_ +#define ASIC_REG_TPC3_QM_REGS_H_ + +/* + ***************************************** + * TPC3_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC3_QM_GLBL_CFG0 0xEC8000 + +#define mmTPC3_QM_GLBL_CFG1 0xEC8004 + +#define mmTPC3_QM_GLBL_PROT 0xEC8008 + +#define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C + +#define mmTPC3_QM_GLBL_SECURE_PROPS_0 0xEC8010 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_1 0xEC8014 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_2 0xEC8018 + +#define mmTPC3_QM_GLBL_SECURE_PROPS_3 0xEC801C + +#define mmTPC3_QM_GLBL_SECURE_PROPS_4 0xEC8020 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_0 0xEC8024 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_1 0xEC8028 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_2 0xEC802C + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_3 0xEC8030 + +#define mmTPC3_QM_GLBL_NON_SECURE_PROPS_4 0xEC8034 + +#define mmTPC3_QM_GLBL_STS0 0xEC8038 + +#define mmTPC3_QM_GLBL_STS1_0 0xEC8040 + +#define mmTPC3_QM_GLBL_STS1_1 0xEC8044 + +#define mmTPC3_QM_GLBL_STS1_2 0xEC8048 + +#define mmTPC3_QM_GLBL_STS1_3 0xEC804C + +#define mmTPC3_QM_GLBL_STS1_4 0xEC8050 + +#define mmTPC3_QM_GLBL_MSG_EN_0 0xEC8054 + +#define mmTPC3_QM_GLBL_MSG_EN_1 0xEC8058 + +#define mmTPC3_QM_GLBL_MSG_EN_2 0xEC805C + +#define mmTPC3_QM_GLBL_MSG_EN_3 0xEC8060 + +#define mmTPC3_QM_GLBL_MSG_EN_4 0xEC8068 + +#define mmTPC3_QM_PQ_BASE_LO_0 0xEC8070 + +#define mmTPC3_QM_PQ_BASE_LO_1 0xEC8074 + +#define mmTPC3_QM_PQ_BASE_LO_2 0xEC8078 + +#define mmTPC3_QM_PQ_BASE_LO_3 0xEC807C + +#define mmTPC3_QM_PQ_BASE_HI_0 0xEC8080 + +#define mmTPC3_QM_PQ_BASE_HI_1 0xEC8084 + +#define mmTPC3_QM_PQ_BASE_HI_2 0xEC8088 + +#define mmTPC3_QM_PQ_BASE_HI_3 0xEC808C + +#define mmTPC3_QM_PQ_SIZE_0 0xEC8090 + +#define mmTPC3_QM_PQ_SIZE_1 0xEC8094 + +#define mmTPC3_QM_PQ_SIZE_2 0xEC8098 + +#define mmTPC3_QM_PQ_SIZE_3 0xEC809C + +#define mmTPC3_QM_PQ_PI_0 0xEC80A0 + +#define mmTPC3_QM_PQ_PI_1 0xEC80A4 + +#define mmTPC3_QM_PQ_PI_2 0xEC80A8 + +#define mmTPC3_QM_PQ_PI_3 0xEC80AC + +#define mmTPC3_QM_PQ_CI_0 0xEC80B0 + +#define mmTPC3_QM_PQ_CI_1 0xEC80B4 + +#define mmTPC3_QM_PQ_CI_2 0xEC80B8 + +#define mmTPC3_QM_PQ_CI_3 0xEC80BC + +#define mmTPC3_QM_PQ_CFG0_0 0xEC80C0 + +#define mmTPC3_QM_PQ_CFG0_1 0xEC80C4 + +#define mmTPC3_QM_PQ_CFG0_2 0xEC80C8 + +#define mmTPC3_QM_PQ_CFG0_3 0xEC80CC + +#define mmTPC3_QM_PQ_CFG1_0 0xEC80D0 + +#define mmTPC3_QM_PQ_CFG1_1 0xEC80D4 + +#define mmTPC3_QM_PQ_CFG1_2 0xEC80D8 + +#define mmTPC3_QM_PQ_CFG1_3 0xEC80DC + +#define mmTPC3_QM_PQ_ARUSER_31_11_0 0xEC80E0 + +#define mmTPC3_QM_PQ_ARUSER_31_11_1 0xEC80E4 + +#define mmTPC3_QM_PQ_ARUSER_31_11_2 0xEC80E8 + +#define mmTPC3_QM_PQ_ARUSER_31_11_3 0xEC80EC + +#define mmTPC3_QM_PQ_STS0_0 0xEC80F0 + +#define mmTPC3_QM_PQ_STS0_1 0xEC80F4 + +#define mmTPC3_QM_PQ_STS0_2 0xEC80F8 + +#define mmTPC3_QM_PQ_STS0_3 0xEC80FC + +#define mmTPC3_QM_PQ_STS1_0 0xEC8100 + +#define mmTPC3_QM_PQ_STS1_1 0xEC8104 + +#define mmTPC3_QM_PQ_STS1_2 0xEC8108 + +#define mmTPC3_QM_PQ_STS1_3 0xEC810C + +#define mmTPC3_QM_CQ_CFG0_0 0xEC8110 + +#define mmTPC3_QM_CQ_CFG0_1 0xEC8114 + +#define mmTPC3_QM_CQ_CFG0_2 0xEC8118 + +#define mmTPC3_QM_CQ_CFG0_3 0xEC811C + +#define mmTPC3_QM_CQ_CFG0_4 0xEC8120 + +#define mmTPC3_QM_CQ_CFG1_0 0xEC8124 + +#define mmTPC3_QM_CQ_CFG1_1 0xEC8128 + +#define mmTPC3_QM_CQ_CFG1_2 0xEC812C + +#define mmTPC3_QM_CQ_CFG1_3 0xEC8130 + +#define mmTPC3_QM_CQ_CFG1_4 0xEC8134 + +#define mmTPC3_QM_CQ_ARUSER_31_11_0 0xEC8138 + +#define mmTPC3_QM_CQ_ARUSER_31_11_1 0xEC813C + +#define mmTPC3_QM_CQ_ARUSER_31_11_2 0xEC8140 + +#define mmTPC3_QM_CQ_ARUSER_31_11_3 0xEC8144 + +#define mmTPC3_QM_CQ_ARUSER_31_11_4 0xEC8148 + +#define mmTPC3_QM_CQ_STS0_0 0xEC814C + +#define mmTPC3_QM_CQ_STS0_1 0xEC8150 + +#define mmTPC3_QM_CQ_STS0_2 0xEC8154 + +#define mmTPC3_QM_CQ_STS0_3 0xEC8158 + +#define mmTPC3_QM_CQ_STS0_4 0xEC815C + +#define mmTPC3_QM_CQ_STS1_0 0xEC8160 + +#define mmTPC3_QM_CQ_STS1_1 0xEC8164 + +#define mmTPC3_QM_CQ_STS1_2 0xEC8168 + +#define mmTPC3_QM_CQ_STS1_3 0xEC816C + +#define mmTPC3_QM_CQ_STS1_4 0xEC8170 + +#define mmTPC3_QM_CQ_PTR_LO_0 0xEC8174 + +#define mmTPC3_QM_CQ_PTR_HI_0 0xEC8178 + +#define mmTPC3_QM_CQ_TSIZE_0 0xEC817C + +#define mmTPC3_QM_CQ_CTL_0 0xEC8180 + +#define mmTPC3_QM_CQ_PTR_LO_1 0xEC8184 + +#define mmTPC3_QM_CQ_PTR_HI_1 0xEC8188 + +#define mmTPC3_QM_CQ_TSIZE_1 0xEC818C + +#define mmTPC3_QM_CQ_CTL_1 0xEC8190 + +#define mmTPC3_QM_CQ_PTR_LO_2 0xEC8194 + +#define mmTPC3_QM_CQ_PTR_HI_2 0xEC8198 + +#define mmTPC3_QM_CQ_TSIZE_2 0xEC819C + +#define mmTPC3_QM_CQ_CTL_2 0xEC81A0 + +#define mmTPC3_QM_CQ_PTR_LO_3 0xEC81A4 + +#define mmTPC3_QM_CQ_PTR_HI_3 0xEC81A8 + +#define mmTPC3_QM_CQ_TSIZE_3 0xEC81AC + +#define mmTPC3_QM_CQ_CTL_3 0xEC81B0 + +#define mmTPC3_QM_CQ_PTR_LO_4 0xEC81B4 + +#define mmTPC3_QM_CQ_PTR_HI_4 0xEC81B8 + +#define mmTPC3_QM_CQ_TSIZE_4 0xEC81BC + +#define mmTPC3_QM_CQ_CTL_4 0xEC81C0 + +#define mmTPC3_QM_CQ_PTR_LO_STS_0 0xEC81C4 + +#define mmTPC3_QM_CQ_PTR_LO_STS_1 0xEC81C8 + +#define mmTPC3_QM_CQ_PTR_LO_STS_2 0xEC81CC + +#define mmTPC3_QM_CQ_PTR_LO_STS_3 0xEC81D0 + +#define mmTPC3_QM_CQ_PTR_LO_STS_4 0xEC81D4 + +#define mmTPC3_QM_CQ_PTR_HI_STS_0 0xEC81D8 + +#define mmTPC3_QM_CQ_PTR_HI_STS_1 0xEC81DC + +#define mmTPC3_QM_CQ_PTR_HI_STS_2 0xEC81E0 + +#define mmTPC3_QM_CQ_PTR_HI_STS_3 0xEC81E4 + +#define mmTPC3_QM_CQ_PTR_HI_STS_4 0xEC81E8 + +#define mmTPC3_QM_CQ_TSIZE_STS_0 0xEC81EC + +#define mmTPC3_QM_CQ_TSIZE_STS_1 0xEC81F0 + +#define mmTPC3_QM_CQ_TSIZE_STS_2 0xEC81F4 + +#define mmTPC3_QM_CQ_TSIZE_STS_3 0xEC81F8 + +#define mmTPC3_QM_CQ_TSIZE_STS_4 0xEC81FC + +#define mmTPC3_QM_CQ_CTL_STS_0 0xEC8200 + +#define mmTPC3_QM_CQ_CTL_STS_1 0xEC8204 + +#define mmTPC3_QM_CQ_CTL_STS_2 0xEC8208 + +#define mmTPC3_QM_CQ_CTL_STS_3 0xEC820C + +#define mmTPC3_QM_CQ_CTL_STS_4 0xEC8210 + +#define mmTPC3_QM_CQ_IFIFO_CNT_0 0xEC8214 + +#define mmTPC3_QM_CQ_IFIFO_CNT_1 0xEC8218 + +#define mmTPC3_QM_CQ_IFIFO_CNT_2 0xEC821C + +#define mmTPC3_QM_CQ_IFIFO_CNT_3 0xEC8220 + +#define mmTPC3_QM_CQ_IFIFO_CNT_4 0xEC8224 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_0 0xEC8228 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_1 0xEC822C + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_2 0xEC8230 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_3 0xEC8234 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO_4 0xEC8238 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_0 0xEC823C + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_1 0xEC8240 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_2 0xEC8244 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_3 0xEC8248 + +#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI_4 0xEC824C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_0 0xEC8250 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_1 0xEC8254 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_2 0xEC8258 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_3 0xEC825C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO_4 0xEC8260 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_0 0xEC8264 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_1 0xEC8268 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_2 0xEC826C + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_3 0xEC8270 + +#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI_4 0xEC8274 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_0 0xEC8278 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_1 0xEC827C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_2 0xEC8280 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_3 0xEC8284 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO_4 0xEC8288 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_0 0xEC828C + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_1 0xEC8290 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_2 0xEC8294 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_3 0xEC8298 + +#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI_4 0xEC829C + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_0 0xEC82A0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_1 0xEC82A4 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_2 0xEC82A8 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_3 0xEC82AC + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO_4 0xEC82B0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_0 0xEC82B4 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_1 0xEC82B8 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_2 0xEC82BC + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_3 0xEC82C0 + +#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI_4 0xEC82C4 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_0 0xEC82C8 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_1 0xEC82CC + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_2 0xEC82D0 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_3 0xEC82D4 + +#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET_4 0xEC82D8 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xEC82E0 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xEC82E4 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xEC82E8 + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xEC82EC + +#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xEC82F0 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xEC82F4 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xEC82F8 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xEC82FC + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xEC8300 + +#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xEC8304 + +#define mmTPC3_QM_CP_FENCE0_RDATA_0 0xEC8308 + +#define mmTPC3_QM_CP_FENCE0_RDATA_1 0xEC830C + +#define mmTPC3_QM_CP_FENCE0_RDATA_2 0xEC8310 + +#define mmTPC3_QM_CP_FENCE0_RDATA_3 0xEC8314 + +#define mmTPC3_QM_CP_FENCE0_RDATA_4 0xEC8318 + +#define mmTPC3_QM_CP_FENCE1_RDATA_0 0xEC831C + +#define mmTPC3_QM_CP_FENCE1_RDATA_1 0xEC8320 + +#define mmTPC3_QM_CP_FENCE1_RDATA_2 0xEC8324 + +#define mmTPC3_QM_CP_FENCE1_RDATA_3 0xEC8328 + +#define mmTPC3_QM_CP_FENCE1_RDATA_4 0xEC832C + +#define mmTPC3_QM_CP_FENCE2_RDATA_0 0xEC8330 + +#define mmTPC3_QM_CP_FENCE2_RDATA_1 0xEC8334 + +#define mmTPC3_QM_CP_FENCE2_RDATA_2 0xEC8338 + +#define mmTPC3_QM_CP_FENCE2_RDATA_3 0xEC833C + +#define mmTPC3_QM_CP_FENCE2_RDATA_4 0xEC8340 + +#define mmTPC3_QM_CP_FENCE3_RDATA_0 0xEC8344 + +#define mmTPC3_QM_CP_FENCE3_RDATA_1 0xEC8348 + +#define mmTPC3_QM_CP_FENCE3_RDATA_2 0xEC834C + +#define mmTPC3_QM_CP_FENCE3_RDATA_3 0xEC8350 + +#define mmTPC3_QM_CP_FENCE3_RDATA_4 0xEC8354 + +#define mmTPC3_QM_CP_FENCE0_CNT_0 0xEC8358 + +#define mmTPC3_QM_CP_FENCE0_CNT_1 0xEC835C + +#define mmTPC3_QM_CP_FENCE0_CNT_2 0xEC8360 + +#define mmTPC3_QM_CP_FENCE0_CNT_3 0xEC8364 + +#define mmTPC3_QM_CP_FENCE0_CNT_4 0xEC8368 + +#define mmTPC3_QM_CP_FENCE1_CNT_0 0xEC836C + +#define mmTPC3_QM_CP_FENCE1_CNT_1 0xEC8370 + +#define mmTPC3_QM_CP_FENCE1_CNT_2 0xEC8374 + +#define mmTPC3_QM_CP_FENCE1_CNT_3 0xEC8378 + +#define mmTPC3_QM_CP_FENCE1_CNT_4 0xEC837C + +#define mmTPC3_QM_CP_FENCE2_CNT_0 0xEC8380 + +#define mmTPC3_QM_CP_FENCE2_CNT_1 0xEC8384 + +#define mmTPC3_QM_CP_FENCE2_CNT_2 0xEC8388 + +#define mmTPC3_QM_CP_FENCE2_CNT_3 0xEC838C + +#define mmTPC3_QM_CP_FENCE2_CNT_4 0xEC8390 + +#define mmTPC3_QM_CP_FENCE3_CNT_0 0xEC8394 + +#define mmTPC3_QM_CP_FENCE3_CNT_1 0xEC8398 + +#define mmTPC3_QM_CP_FENCE3_CNT_2 0xEC839C + +#define mmTPC3_QM_CP_FENCE3_CNT_3 0xEC83A0 + +#define mmTPC3_QM_CP_FENCE3_CNT_4 0xEC83A4 + +#define mmTPC3_QM_CP_STS_0 0xEC83A8 + +#define mmTPC3_QM_CP_STS_1 0xEC83AC + +#define mmTPC3_QM_CP_STS_2 0xEC83B0 + +#define mmTPC3_QM_CP_STS_3 0xEC83B4 + +#define mmTPC3_QM_CP_STS_4 0xEC83B8 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_0 0xEC83BC + +#define mmTPC3_QM_CP_CURRENT_INST_LO_1 0xEC83C0 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_2 0xEC83C4 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_3 0xEC83C8 + +#define mmTPC3_QM_CP_CURRENT_INST_LO_4 0xEC83CC + +#define mmTPC3_QM_CP_CURRENT_INST_HI_0 0xEC83D0 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_1 0xEC83D4 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_2 0xEC83D8 + +#define mmTPC3_QM_CP_CURRENT_INST_HI_3 0xEC83DC + +#define mmTPC3_QM_CP_CURRENT_INST_HI_4 0xEC83E0 + +#define mmTPC3_QM_CP_BARRIER_CFG_0 0xEC83F4 + +#define mmTPC3_QM_CP_BARRIER_CFG_1 0xEC83F8 + +#define mmTPC3_QM_CP_BARRIER_CFG_2 0xEC83FC + +#define mmTPC3_QM_CP_BARRIER_CFG_3 0xEC8400 + +#define mmTPC3_QM_CP_BARRIER_CFG_4 0xEC8404 + +#define mmTPC3_QM_CP_DBG_0_0 0xEC8408 + +#define mmTPC3_QM_CP_DBG_0_1 0xEC840C + +#define mmTPC3_QM_CP_DBG_0_2 0xEC8410 + +#define mmTPC3_QM_CP_DBG_0_3 0xEC8414 + +#define mmTPC3_QM_CP_DBG_0_4 0xEC8418 + +#define mmTPC3_QM_CP_ARUSER_31_11_0 0xEC841C + +#define mmTPC3_QM_CP_ARUSER_31_11_1 0xEC8420 + +#define mmTPC3_QM_CP_ARUSER_31_11_2 0xEC8424 + +#define mmTPC3_QM_CP_ARUSER_31_11_3 0xEC8428 + +#define mmTPC3_QM_CP_ARUSER_31_11_4 0xEC842C + +#define mmTPC3_QM_CP_AWUSER_31_11_0 0xEC8430 + +#define mmTPC3_QM_CP_AWUSER_31_11_1 0xEC8434 + +#define mmTPC3_QM_CP_AWUSER_31_11_2 0xEC8438 + +#define mmTPC3_QM_CP_AWUSER_31_11_3 0xEC843C + +#define mmTPC3_QM_CP_AWUSER_31_11_4 0xEC8440 + +#define mmTPC3_QM_ARB_CFG_0 0xEC8A00 + +#define mmTPC3_QM_ARB_CHOISE_Q_PUSH 0xEC8A04 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_0 0xEC8A08 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_1 0xEC8A0C + +#define mmTPC3_QM_ARB_WRR_WEIGHT_2 0xEC8A10 + +#define mmTPC3_QM_ARB_WRR_WEIGHT_3 0xEC8A14 + +#define mmTPC3_QM_ARB_CFG_1 0xEC8A18 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_0 0xEC8A20 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_1 0xEC8A24 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_2 0xEC8A28 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_3 0xEC8A2C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_4 0xEC8A30 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_5 0xEC8A34 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_6 0xEC8A38 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_7 0xEC8A3C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_8 0xEC8A40 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_9 0xEC8A44 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_10 0xEC8A48 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_11 0xEC8A4C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_12 0xEC8A50 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_13 0xEC8A54 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_14 0xEC8A58 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_15 0xEC8A5C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_16 0xEC8A60 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_17 0xEC8A64 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_18 0xEC8A68 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_19 0xEC8A6C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_20 0xEC8A70 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_21 0xEC8A74 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_22 0xEC8A78 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_23 0xEC8A7C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_24 0xEC8A80 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_25 0xEC8A84 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_26 0xEC8A88 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_27 0xEC8A8C + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_28 0xEC8A90 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_29 0xEC8A94 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_30 0xEC8A98 + +#define mmTPC3_QM_ARB_MST_AVAIL_CRED_31 0xEC8A9C + +#define mmTPC3_QM_ARB_MST_CRED_INC 0xEC8AA0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xEC8AA4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xEC8AA8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xEC8AAC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xEC8AB0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xEC8AB4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xEC8AB8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xEC8ABC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xEC8AC0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xEC8AC4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xEC8AC8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xEC8ACC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xEC8AD0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xEC8AD4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xEC8AD8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xEC8ADC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xEC8AE0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xEC8AE4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xEC8AE8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xEC8AEC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xEC8AF0 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xEC8AF4 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xEC8AF8 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xEC8AFC + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xEC8B00 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xEC8B04 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xEC8B08 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xEC8B0C + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xEC8B10 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xEC8B14 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xEC8B18 + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xEC8B1C + +#define mmTPC3_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xEC8B20 + +#define mmTPC3_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xEC8B28 + +#define mmTPC3_QM_ARB_MST_SLAVE_EN 0xEC8B2C + +#define mmTPC3_QM_ARB_MST_QUIET_PER 0xEC8B34 + +#define mmTPC3_QM_ARB_SLV_CHOISE_WDT 0xEC8B38 + +#define mmTPC3_QM_ARB_SLV_ID 0xEC8B3C + +#define mmTPC3_QM_ARB_MSG_MAX_INFLIGHT 0xEC8B44 + +#define mmTPC3_QM_ARB_MSG_AWUSER_31_11 0xEC8B48 + +#define mmTPC3_QM_ARB_MSG_AWUSER_SEC_PROP 0xEC8B4C + +#define mmTPC3_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xEC8B50 + +#define mmTPC3_QM_ARB_BASE_LO 0xEC8B54 + +#define mmTPC3_QM_ARB_BASE_HI 0xEC8B58 + +#define mmTPC3_QM_ARB_STATE_STS 0xEC8B80 + +#define mmTPC3_QM_ARB_CHOISE_FULLNESS_STS 0xEC8B84 + +#define mmTPC3_QM_ARB_MSG_STS 0xEC8B88 + +#define mmTPC3_QM_ARB_SLV_CHOISE_Q_HEAD 0xEC8B8C + +#define mmTPC3_QM_ARB_ERR_CAUSE 0xEC8B9C + +#define mmTPC3_QM_ARB_ERR_MSG_EN 0xEC8BA0 + +#define mmTPC3_QM_ARB_ERR_STS_DRP 0xEC8BA8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_0 0xEC8BB0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_1 0xEC8BB4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_2 0xEC8BB8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_3 0xEC8BBC + +#define mmTPC3_QM_ARB_MST_CRED_STS_4 0xEC8BC0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_5 0xEC8BC4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_6 0xEC8BC8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_7 0xEC8BCC + +#define mmTPC3_QM_ARB_MST_CRED_STS_8 0xEC8BD0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_9 0xEC8BD4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_10 0xEC8BD8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_11 0xEC8BDC + +#define mmTPC3_QM_ARB_MST_CRED_STS_12 0xEC8BE0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_13 0xEC8BE4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_14 0xEC8BE8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_15 0xEC8BEC + +#define mmTPC3_QM_ARB_MST_CRED_STS_16 0xEC8BF0 + +#define mmTPC3_QM_ARB_MST_CRED_STS_17 0xEC8BF4 + +#define mmTPC3_QM_ARB_MST_CRED_STS_18 0xEC8BF8 + +#define mmTPC3_QM_ARB_MST_CRED_STS_19 0xEC8BFC + +#define mmTPC3_QM_ARB_MST_CRED_STS_20 0xEC8C00 + +#define mmTPC3_QM_ARB_MST_CRED_STS_21 0xEC8C04 + +#define mmTPC3_QM_ARB_MST_CRED_STS_22 0xEC8C08 + +#define mmTPC3_QM_ARB_MST_CRED_STS_23 0xEC8C0C + +#define mmTPC3_QM_ARB_MST_CRED_STS_24 0xEC8C10 + +#define mmTPC3_QM_ARB_MST_CRED_STS_25 0xEC8C14 + +#define mmTPC3_QM_ARB_MST_CRED_STS_26 0xEC8C18 + +#define mmTPC3_QM_ARB_MST_CRED_STS_27 0xEC8C1C + +#define mmTPC3_QM_ARB_MST_CRED_STS_28 0xEC8C20 + +#define mmTPC3_QM_ARB_MST_CRED_STS_29 0xEC8C24 + +#define mmTPC3_QM_ARB_MST_CRED_STS_30 0xEC8C28 + +#define mmTPC3_QM_ARB_MST_CRED_STS_31 0xEC8C2C + +#define mmTPC3_QM_CGM_CFG 0xEC8C70 + +#define mmTPC3_QM_CGM_STS 0xEC8C74 + +#define mmTPC3_QM_CGM_CFG1 0xEC8C78 + +#define mmTPC3_QM_LOCAL_RANGE_BASE 0xEC8C80 + +#define mmTPC3_QM_LOCAL_RANGE_SIZE 0xEC8C84 + +#define mmTPC3_QM_CSMR_STRICT_PRIO_CFG 0xEC8C90 + +#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_1 0xEC8C94 + +#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_0 0xEC8C98 + +#define mmTPC3_QM_LBW_WR_RATE_LIM_CFG_1 0xEC8C9C + +#define mmTPC3_QM_HBW_RD_RATE_LIM_CFG_0 0xEC8CA0 + +#define mmTPC3_QM_GLBL_AXCACHE 0xEC8CA4 + +#define mmTPC3_QM_IND_GW_APB_CFG 0xEC8CB0 + +#define mmTPC3_QM_IND_GW_APB_WDATA 0xEC8CB4 + +#define mmTPC3_QM_IND_GW_APB_RDATA 0xEC8CB8 + +#define mmTPC3_QM_IND_GW_APB_STATUS 0xEC8CBC + +#define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8CD0 + +#define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8CD4 + +#define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8CD8 + +#define mmTPC3_QM_GLBL_MEM_INIT_BUSY 0xEC8D00 + +#endif /* ASIC_REG_TPC3_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h new file mode 100644 index 000000000000..7a9447f39a74 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_CFG_REGS_H_ +#define ASIC_REG_TPC4_CFG_REGS_H_ + +/* + ***************************************** + * TPC4_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF06418 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF0641C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06420 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF06424 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06428 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF0642C + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06430 + +#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06434 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF06438 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF0643C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06440 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06444 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF06448 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF0644C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06450 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF06454 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06458 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF0645C + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06460 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06464 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF06468 + +#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF0646C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06470 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF06474 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF06478 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF0647C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF06480 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF06484 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF06488 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF0648C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF06490 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF06494 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF06498 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF0649C + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064AC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064BC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF064C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF064C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF064C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF064CC + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF064D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF064D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF064D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF064DC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF064E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF064E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF064E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF064EC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF064F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF064F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF064F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF064FC + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06500 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF06504 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06508 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF0650C + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06510 + +#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06514 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF06518 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF0651C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06520 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06524 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF06528 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF0652C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06530 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF06534 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF06538 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF0653C + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF06540 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF06544 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF06548 + +#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF0654C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF06550 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF06554 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF06558 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF0655C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF06560 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF06564 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF06568 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF0656C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF06570 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF06574 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF06578 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF0657C + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06580 + +#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF06584 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06588 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF0658C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF06590 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06594 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06598 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF0659C + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF065A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF065A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF065A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF065AC + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF065B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF065B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF065B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF065BC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF065C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF065C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF065C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF065CC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF065D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF065D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF065D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF065DC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF065E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF065E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF065E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF065EC + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF065F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF065F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF065F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF065FC + +#define mmTPC4_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF06600 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF06604 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF06608 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF0660C + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF06610 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF06614 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF06618 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF0661C + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF06620 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF06624 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF06628 + +#define mmTPC4_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF0662C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF06630 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF06634 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF06638 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF0663C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF06640 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF06644 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF06648 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF0664C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF06650 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF06654 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF06658 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF0665C + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF06660 + +#define mmTPC4_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF06664 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF06668 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF0666C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF06670 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF06674 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF06678 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF0667C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF06680 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF06684 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF06688 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF0668C + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF06690 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF06694 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF06698 + +#define mmTPC4_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF0669C + +#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF066A0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF066A4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF066A8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF066AC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF066B0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF066B4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF066B8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF066BC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF066C0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF066C4 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF066C8 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF066CC + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF066D0 + +#define mmTPC4_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF066D4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF066D8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF066DC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF066E0 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF066E4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF066E8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF066EC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF066F0 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF066F4 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF066F8 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF066FC + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF06700 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF06704 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF06708 + +#define mmTPC4_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF0670C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF06710 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF06714 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF06718 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF0671C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF06720 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF06724 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF06728 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF0672C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF06730 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF06734 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF06738 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF0673C + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF06740 + +#define mmTPC4_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF06744 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF06748 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF0674C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF06750 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF06754 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF06758 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF0675C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF06760 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF06764 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF06768 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF0676C + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF06770 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF06774 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF06778 + +#define mmTPC4_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF0677C + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06780 + +#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF06784 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06788 + +#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF0678C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06790 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF06794 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06798 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF0679C + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF067A0 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF067A4 + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF067A8 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF067AC + +#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF067B0 + +#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF067B4 + +#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF067B8 + +#define mmTPC4_CFG_KERNEL_KERNEL_ID 0xF067BC + +#define mmTPC4_CFG_KERNEL_SRF_0 0xF067C0 + +#define mmTPC4_CFG_KERNEL_SRF_1 0xF067C4 + +#define mmTPC4_CFG_KERNEL_SRF_2 0xF067C8 + +#define mmTPC4_CFG_KERNEL_SRF_3 0xF067CC + +#define mmTPC4_CFG_KERNEL_SRF_4 0xF067D0 + +#define mmTPC4_CFG_KERNEL_SRF_5 0xF067D4 + +#define mmTPC4_CFG_KERNEL_SRF_6 0xF067D8 + +#define mmTPC4_CFG_KERNEL_SRF_7 0xF067DC + +#define mmTPC4_CFG_KERNEL_SRF_8 0xF067E0 + +#define mmTPC4_CFG_KERNEL_SRF_9 0xF067E4 + +#define mmTPC4_CFG_KERNEL_SRF_10 0xF067E8 + +#define mmTPC4_CFG_KERNEL_SRF_11 0xF067EC + +#define mmTPC4_CFG_KERNEL_SRF_12 0xF067F0 + +#define mmTPC4_CFG_KERNEL_SRF_13 0xF067F4 + +#define mmTPC4_CFG_KERNEL_SRF_14 0xF067F8 + +#define mmTPC4_CFG_KERNEL_SRF_15 0xF067FC + +#define mmTPC4_CFG_KERNEL_SRF_16 0xF06800 + +#define mmTPC4_CFG_KERNEL_SRF_17 0xF06804 + +#define mmTPC4_CFG_KERNEL_SRF_18 0xF06808 + +#define mmTPC4_CFG_KERNEL_SRF_19 0xF0680C + +#define mmTPC4_CFG_KERNEL_SRF_20 0xF06810 + +#define mmTPC4_CFG_KERNEL_SRF_21 0xF06814 + +#define mmTPC4_CFG_KERNEL_SRF_22 0xF06818 + +#define mmTPC4_CFG_KERNEL_SRF_23 0xF0681C + +#define mmTPC4_CFG_KERNEL_SRF_24 0xF06820 + +#define mmTPC4_CFG_KERNEL_SRF_25 0xF06824 + +#define mmTPC4_CFG_KERNEL_SRF_26 0xF06828 + +#define mmTPC4_CFG_KERNEL_SRF_27 0xF0682C + +#define mmTPC4_CFG_KERNEL_SRF_28 0xF06830 + +#define mmTPC4_CFG_KERNEL_SRF_29 0xF06834 + +#define mmTPC4_CFG_KERNEL_SRF_30 0xF06838 + +#define mmTPC4_CFG_KERNEL_SRF_31 0xF0683C + +#define mmTPC4_CFG_ROUND_CSR 0xF068FC + +#define mmTPC4_CFG_PROT 0xF06900 + +#define mmTPC4_CFG_SEMAPHORE 0xF06908 + +#define mmTPC4_CFG_VFLAGS 0xF0690C + +#define mmTPC4_CFG_SFLAGS 0xF06910 + +#define mmTPC4_CFG_LFSR_POLYNOM 0xF06918 + +#define mmTPC4_CFG_STATUS 0xF0691C + +#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06920 + +#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06924 + +#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0692C + +#define mmTPC4_CFG_TPC_CMD 0xF06930 + +#define mmTPC4_CFG_TPC_EXECUTE 0xF06938 + +#define mmTPC4_CFG_TPC_STALL 0xF0693C + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06940 + +#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06944 + +#define mmTPC4_CFG_RD_RATE_LIMIT 0xF06948 + +#define mmTPC4_CFG_WR_RATE_LIMIT 0xF06950 + +#define mmTPC4_CFG_MSS_CONFIG 0xF06954 + +#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06958 + +#define mmTPC4_CFG_TPC_INTR_MASK 0xF0695C + +#define mmTPC4_CFG_WQ_CREDITS 0xF06960 + +#define mmTPC4_CFG_ARUSER_LO 0xF06964 + +#define mmTPC4_CFG_ARUSER_HI 0xF06968 + +#define mmTPC4_CFG_AWUSER_LO 0xF0696C + +#define mmTPC4_CFG_AWUSER_HI 0xF06970 + +#define mmTPC4_CFG_OPCODE_EXEC 0xF06974 + +#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF06978 + +#define mmTPC4_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF0697C + +#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF06980 + +#define mmTPC4_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF06984 + +#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF06988 + +#define mmTPC4_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF0698C + +#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF06990 + +#define mmTPC4_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF06994 + +#define mmTPC4_CFG_TSB_CFG_MAX_SIZE 0xF06998 + +#define mmTPC4_CFG_TSB_CFG 0xF0699C + +#define mmTPC4_CFG_DBGMEM_ADD 0xF069A0 + +#define mmTPC4_CFG_DBGMEM_DATA_WR 0xF069A4 + +#define mmTPC4_CFG_DBGMEM_DATA_RD 0xF069A8 + +#define mmTPC4_CFG_DBGMEM_CTRL 0xF069AC + +#define mmTPC4_CFG_DBGMEM_RC 0xF069B0 + +#define mmTPC4_CFG_TSB_INFLIGHT_CNTR 0xF069B4 + +#define mmTPC4_CFG_WQ_INFLIGHT_CNTR 0xF069B8 + +#define mmTPC4_CFG_WQ_LBW_TOTAL_CNTR 0xF069BC + +#define mmTPC4_CFG_WQ_HBW_TOTAL_CNTR 0xF069C0 + +#define mmTPC4_CFG_IRQ_OCCOUPY_CNTR 0xF069C4 + +#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF069D0 + +#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF069D4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF069D8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF069DC + +#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF069E0 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF069E4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF069E8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF069EC + +#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF069F0 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF069F4 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF069F8 + +#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF069FC + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 + +#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 + +#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 + +#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A18 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A1C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A20 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A24 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A28 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A2C + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A30 + +#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A34 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A38 + +#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A3C + +#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A40 + +#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A44 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A48 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A4C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A50 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A54 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A58 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A5C + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A60 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A64 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A68 + +#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A6C + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A70 + +#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A74 + +#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06A78 + +#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06A7C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06A80 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06A84 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06A88 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06A8C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06A90 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06A94 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06A98 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06A9C + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AA0 + +#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06AA4 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AA8 + +#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AAC + +#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AB0 + +#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AB4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AB8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06ABC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06AC0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06AC4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06AC8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06ACC + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06AD0 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06AD4 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06AD8 + +#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06ADC + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06AE0 + +#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06AE4 + +#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06AE8 + +#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06AEC + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06AF0 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06AF4 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06AF8 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06AFC + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B00 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B04 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B08 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B0C + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B10 + +#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B14 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B18 + +#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B1C + +#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B20 + +#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B24 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B28 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B2C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B30 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B34 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06B38 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06B3C + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06B40 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06B44 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06B48 + +#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06B4C + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06B50 + +#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06B54 + +#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06B58 + +#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06B5C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06B60 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06B64 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06B68 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06B6C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06B70 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06B74 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06B78 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06B7C + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06B80 + +#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06B84 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06B88 + +#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06B8C + +#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06B90 + +#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06B94 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06B98 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06B9C + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06BA0 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06BA4 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06BA8 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06BAC + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06BB0 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06BB4 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06BB8 + +#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06BBC + +#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF06BC0 + +#define mmTPC4_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF06BC4 + +#define mmTPC4_CFG_QM_TENSOR_8_PADDING_VALUE 0xF06BC8 + +#define mmTPC4_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF06BCC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF06BD0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF06BD4 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF06BD8 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF06BDC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF06BE0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF06BE4 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF06BE8 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF06BEC + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF06BF0 + +#define mmTPC4_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF06BF4 + +#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF06BF8 + +#define mmTPC4_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF06BFC + +#define mmTPC4_CFG_QM_TENSOR_9_PADDING_VALUE 0xF06C00 + +#define mmTPC4_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF06C04 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF06C08 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF06C0C + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF06C10 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF06C14 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF06C18 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF06C1C + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF06C20 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF06C24 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF06C28 + +#define mmTPC4_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF06C2C + +#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF06C30 + +#define mmTPC4_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF06C34 + +#define mmTPC4_CFG_QM_TENSOR_10_PADDING_VALUE 0xF06C38 + +#define mmTPC4_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF06C3C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF06C40 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF06C44 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF06C48 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF06C4C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF06C50 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF06C54 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF06C58 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF06C5C + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF06C60 + +#define mmTPC4_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF06C64 + +#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF06C68 + +#define mmTPC4_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF06C6C + +#define mmTPC4_CFG_QM_TENSOR_11_PADDING_VALUE 0xF06C70 + +#define mmTPC4_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF06C74 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF06C78 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF06C7C + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF06C80 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF06C84 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF06C88 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF06C8C + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF06C90 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF06C94 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF06C98 + +#define mmTPC4_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF06C9C + +#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF06CA0 + +#define mmTPC4_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF06CA4 + +#define mmTPC4_CFG_QM_TENSOR_12_PADDING_VALUE 0xF06CA8 + +#define mmTPC4_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF06CAC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF06CB0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF06CB4 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF06CB8 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF06CBC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF06CC0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF06CC4 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF06CC8 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF06CCC + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF06CD0 + +#define mmTPC4_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF06CD4 + +#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF06CD8 + +#define mmTPC4_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF06CDC + +#define mmTPC4_CFG_QM_TENSOR_13_PADDING_VALUE 0xF06CE0 + +#define mmTPC4_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF06CE4 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF06CE8 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF06CEC + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF06CF0 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF06CF4 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF06CF8 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF06CFC + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF06D00 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF06D04 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF06D08 + +#define mmTPC4_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF06D0C + +#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF06D10 + +#define mmTPC4_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF06D14 + +#define mmTPC4_CFG_QM_TENSOR_14_PADDING_VALUE 0xF06D18 + +#define mmTPC4_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF06D1C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF06D20 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF06D24 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF06D28 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF06D2C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF06D30 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF06D34 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF06D38 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF06D3C + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF06D40 + +#define mmTPC4_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF06D44 + +#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF06D48 + +#define mmTPC4_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF06D4C + +#define mmTPC4_CFG_QM_TENSOR_15_PADDING_VALUE 0xF06D50 + +#define mmTPC4_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF06D54 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF06D58 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF06D5C + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF06D60 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF06D64 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF06D68 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF06D6C + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF06D70 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF06D74 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF06D78 + +#define mmTPC4_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF06D7C + +#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D80 + +#define mmTPC4_CFG_QM_SYNC_OBJECT_ADDR 0xF06D84 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06D88 + +#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06D8C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06D90 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06D94 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06D98 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06D9C + +#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06DA0 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06DA4 + +#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06DA8 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06DAC + +#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06DB0 + +#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06DB4 + +#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06DB8 + +#define mmTPC4_CFG_QM_KERNEL_ID 0xF06DBC + +#define mmTPC4_CFG_QM_SRF_0 0xF06DC0 + +#define mmTPC4_CFG_QM_SRF_1 0xF06DC4 + +#define mmTPC4_CFG_QM_SRF_2 0xF06DC8 + +#define mmTPC4_CFG_QM_SRF_3 0xF06DCC + +#define mmTPC4_CFG_QM_SRF_4 0xF06DD0 + +#define mmTPC4_CFG_QM_SRF_5 0xF06DD4 + +#define mmTPC4_CFG_QM_SRF_6 0xF06DD8 + +#define mmTPC4_CFG_QM_SRF_7 0xF06DDC + +#define mmTPC4_CFG_QM_SRF_8 0xF06DE0 + +#define mmTPC4_CFG_QM_SRF_9 0xF06DE4 + +#define mmTPC4_CFG_QM_SRF_10 0xF06DE8 + +#define mmTPC4_CFG_QM_SRF_11 0xF06DEC + +#define mmTPC4_CFG_QM_SRF_12 0xF06DF0 + +#define mmTPC4_CFG_QM_SRF_13 0xF06DF4 + +#define mmTPC4_CFG_QM_SRF_14 0xF06DF8 + +#define mmTPC4_CFG_QM_SRF_15 0xF06DFC + +#define mmTPC4_CFG_QM_SRF_16 0xF06E00 + +#define mmTPC4_CFG_QM_SRF_17 0xF06E04 + +#define mmTPC4_CFG_QM_SRF_18 0xF06E08 + +#define mmTPC4_CFG_QM_SRF_19 0xF06E0C + +#define mmTPC4_CFG_QM_SRF_20 0xF06E10 + +#define mmTPC4_CFG_QM_SRF_21 0xF06E14 + +#define mmTPC4_CFG_QM_SRF_22 0xF06E18 + +#define mmTPC4_CFG_QM_SRF_23 0xF06E1C + +#define mmTPC4_CFG_QM_SRF_24 0xF06E20 + +#define mmTPC4_CFG_QM_SRF_25 0xF06E24 + +#define mmTPC4_CFG_QM_SRF_26 0xF06E28 + +#define mmTPC4_CFG_QM_SRF_27 0xF06E2C + +#define mmTPC4_CFG_QM_SRF_28 0xF06E30 + +#define mmTPC4_CFG_QM_SRF_29 0xF06E34 + +#define mmTPC4_CFG_QM_SRF_30 0xF06E38 + +#define mmTPC4_CFG_QM_SRF_31 0xF06E3C + +#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h new file mode 100644 index 000000000000..80e63402f6e0 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc4_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC4_QM_REGS_H_ +#define ASIC_REG_TPC4_QM_REGS_H_ + +/* + ***************************************** + * TPC4_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC4_QM_GLBL_CFG0 0xF08000 + +#define mmTPC4_QM_GLBL_CFG1 0xF08004 + +#define mmTPC4_QM_GLBL_PROT 0xF08008 + +#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C + +#define mmTPC4_QM_GLBL_SECURE_PROPS_0 0xF08010 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_1 0xF08014 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_2 0xF08018 + +#define mmTPC4_QM_GLBL_SECURE_PROPS_3 0xF0801C + +#define mmTPC4_QM_GLBL_SECURE_PROPS_4 0xF08020 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 0xF08024 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 0xF08028 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 0xF0802C + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 0xF08030 + +#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 0xF08034 + +#define mmTPC4_QM_GLBL_STS0 0xF08038 + +#define mmTPC4_QM_GLBL_STS1_0 0xF08040 + +#define mmTPC4_QM_GLBL_STS1_1 0xF08044 + +#define mmTPC4_QM_GLBL_STS1_2 0xF08048 + +#define mmTPC4_QM_GLBL_STS1_3 0xF0804C + +#define mmTPC4_QM_GLBL_STS1_4 0xF08050 + +#define mmTPC4_QM_GLBL_MSG_EN_0 0xF08054 + +#define mmTPC4_QM_GLBL_MSG_EN_1 0xF08058 + +#define mmTPC4_QM_GLBL_MSG_EN_2 0xF0805C + +#define mmTPC4_QM_GLBL_MSG_EN_3 0xF08060 + +#define mmTPC4_QM_GLBL_MSG_EN_4 0xF08068 + +#define mmTPC4_QM_PQ_BASE_LO_0 0xF08070 + +#define mmTPC4_QM_PQ_BASE_LO_1 0xF08074 + +#define mmTPC4_QM_PQ_BASE_LO_2 0xF08078 + +#define mmTPC4_QM_PQ_BASE_LO_3 0xF0807C + +#define mmTPC4_QM_PQ_BASE_HI_0 0xF08080 + +#define mmTPC4_QM_PQ_BASE_HI_1 0xF08084 + +#define mmTPC4_QM_PQ_BASE_HI_2 0xF08088 + +#define mmTPC4_QM_PQ_BASE_HI_3 0xF0808C + +#define mmTPC4_QM_PQ_SIZE_0 0xF08090 + +#define mmTPC4_QM_PQ_SIZE_1 0xF08094 + +#define mmTPC4_QM_PQ_SIZE_2 0xF08098 + +#define mmTPC4_QM_PQ_SIZE_3 0xF0809C + +#define mmTPC4_QM_PQ_PI_0 0xF080A0 + +#define mmTPC4_QM_PQ_PI_1 0xF080A4 + +#define mmTPC4_QM_PQ_PI_2 0xF080A8 + +#define mmTPC4_QM_PQ_PI_3 0xF080AC + +#define mmTPC4_QM_PQ_CI_0 0xF080B0 + +#define mmTPC4_QM_PQ_CI_1 0xF080B4 + +#define mmTPC4_QM_PQ_CI_2 0xF080B8 + +#define mmTPC4_QM_PQ_CI_3 0xF080BC + +#define mmTPC4_QM_PQ_CFG0_0 0xF080C0 + +#define mmTPC4_QM_PQ_CFG0_1 0xF080C4 + +#define mmTPC4_QM_PQ_CFG0_2 0xF080C8 + +#define mmTPC4_QM_PQ_CFG0_3 0xF080CC + +#define mmTPC4_QM_PQ_CFG1_0 0xF080D0 + +#define mmTPC4_QM_PQ_CFG1_1 0xF080D4 + +#define mmTPC4_QM_PQ_CFG1_2 0xF080D8 + +#define mmTPC4_QM_PQ_CFG1_3 0xF080DC + +#define mmTPC4_QM_PQ_ARUSER_31_11_0 0xF080E0 + +#define mmTPC4_QM_PQ_ARUSER_31_11_1 0xF080E4 + +#define mmTPC4_QM_PQ_ARUSER_31_11_2 0xF080E8 + +#define mmTPC4_QM_PQ_ARUSER_31_11_3 0xF080EC + +#define mmTPC4_QM_PQ_STS0_0 0xF080F0 + +#define mmTPC4_QM_PQ_STS0_1 0xF080F4 + +#define mmTPC4_QM_PQ_STS0_2 0xF080F8 + +#define mmTPC4_QM_PQ_STS0_3 0xF080FC + +#define mmTPC4_QM_PQ_STS1_0 0xF08100 + +#define mmTPC4_QM_PQ_STS1_1 0xF08104 + +#define mmTPC4_QM_PQ_STS1_2 0xF08108 + +#define mmTPC4_QM_PQ_STS1_3 0xF0810C + +#define mmTPC4_QM_CQ_CFG0_0 0xF08110 + +#define mmTPC4_QM_CQ_CFG0_1 0xF08114 + +#define mmTPC4_QM_CQ_CFG0_2 0xF08118 + +#define mmTPC4_QM_CQ_CFG0_3 0xF0811C + +#define mmTPC4_QM_CQ_CFG0_4 0xF08120 + +#define mmTPC4_QM_CQ_CFG1_0 0xF08124 + +#define mmTPC4_QM_CQ_CFG1_1 0xF08128 + +#define mmTPC4_QM_CQ_CFG1_2 0xF0812C + +#define mmTPC4_QM_CQ_CFG1_3 0xF08130 + +#define mmTPC4_QM_CQ_CFG1_4 0xF08134 + +#define mmTPC4_QM_CQ_ARUSER_31_11_0 0xF08138 + +#define mmTPC4_QM_CQ_ARUSER_31_11_1 0xF0813C + +#define mmTPC4_QM_CQ_ARUSER_31_11_2 0xF08140 + +#define mmTPC4_QM_CQ_ARUSER_31_11_3 0xF08144 + +#define mmTPC4_QM_CQ_ARUSER_31_11_4 0xF08148 + +#define mmTPC4_QM_CQ_STS0_0 0xF0814C + +#define mmTPC4_QM_CQ_STS0_1 0xF08150 + +#define mmTPC4_QM_CQ_STS0_2 0xF08154 + +#define mmTPC4_QM_CQ_STS0_3 0xF08158 + +#define mmTPC4_QM_CQ_STS0_4 0xF0815C + +#define mmTPC4_QM_CQ_STS1_0 0xF08160 + +#define mmTPC4_QM_CQ_STS1_1 0xF08164 + +#define mmTPC4_QM_CQ_STS1_2 0xF08168 + +#define mmTPC4_QM_CQ_STS1_3 0xF0816C + +#define mmTPC4_QM_CQ_STS1_4 0xF08170 + +#define mmTPC4_QM_CQ_PTR_LO_0 0xF08174 + +#define mmTPC4_QM_CQ_PTR_HI_0 0xF08178 + +#define mmTPC4_QM_CQ_TSIZE_0 0xF0817C + +#define mmTPC4_QM_CQ_CTL_0 0xF08180 + +#define mmTPC4_QM_CQ_PTR_LO_1 0xF08184 + +#define mmTPC4_QM_CQ_PTR_HI_1 0xF08188 + +#define mmTPC4_QM_CQ_TSIZE_1 0xF0818C + +#define mmTPC4_QM_CQ_CTL_1 0xF08190 + +#define mmTPC4_QM_CQ_PTR_LO_2 0xF08194 + +#define mmTPC4_QM_CQ_PTR_HI_2 0xF08198 + +#define mmTPC4_QM_CQ_TSIZE_2 0xF0819C + +#define mmTPC4_QM_CQ_CTL_2 0xF081A0 + +#define mmTPC4_QM_CQ_PTR_LO_3 0xF081A4 + +#define mmTPC4_QM_CQ_PTR_HI_3 0xF081A8 + +#define mmTPC4_QM_CQ_TSIZE_3 0xF081AC + +#define mmTPC4_QM_CQ_CTL_3 0xF081B0 + +#define mmTPC4_QM_CQ_PTR_LO_4 0xF081B4 + +#define mmTPC4_QM_CQ_PTR_HI_4 0xF081B8 + +#define mmTPC4_QM_CQ_TSIZE_4 0xF081BC + +#define mmTPC4_QM_CQ_CTL_4 0xF081C0 + +#define mmTPC4_QM_CQ_PTR_LO_STS_0 0xF081C4 + +#define mmTPC4_QM_CQ_PTR_LO_STS_1 0xF081C8 + +#define mmTPC4_QM_CQ_PTR_LO_STS_2 0xF081CC + +#define mmTPC4_QM_CQ_PTR_LO_STS_3 0xF081D0 + +#define mmTPC4_QM_CQ_PTR_LO_STS_4 0xF081D4 + +#define mmTPC4_QM_CQ_PTR_HI_STS_0 0xF081D8 + +#define mmTPC4_QM_CQ_PTR_HI_STS_1 0xF081DC + +#define mmTPC4_QM_CQ_PTR_HI_STS_2 0xF081E0 + +#define mmTPC4_QM_CQ_PTR_HI_STS_3 0xF081E4 + +#define mmTPC4_QM_CQ_PTR_HI_STS_4 0xF081E8 + +#define mmTPC4_QM_CQ_TSIZE_STS_0 0xF081EC + +#define mmTPC4_QM_CQ_TSIZE_STS_1 0xF081F0 + +#define mmTPC4_QM_CQ_TSIZE_STS_2 0xF081F4 + +#define mmTPC4_QM_CQ_TSIZE_STS_3 0xF081F8 + +#define mmTPC4_QM_CQ_TSIZE_STS_4 0xF081FC + +#define mmTPC4_QM_CQ_CTL_STS_0 0xF08200 + +#define mmTPC4_QM_CQ_CTL_STS_1 0xF08204 + +#define mmTPC4_QM_CQ_CTL_STS_2 0xF08208 + +#define mmTPC4_QM_CQ_CTL_STS_3 0xF0820C + +#define mmTPC4_QM_CQ_CTL_STS_4 0xF08210 + +#define mmTPC4_QM_CQ_IFIFO_CNT_0 0xF08214 + +#define mmTPC4_QM_CQ_IFIFO_CNT_1 0xF08218 + +#define mmTPC4_QM_CQ_IFIFO_CNT_2 0xF0821C + +#define mmTPC4_QM_CQ_IFIFO_CNT_3 0xF08220 + +#define mmTPC4_QM_CQ_IFIFO_CNT_4 0xF08224 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 0xF08228 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 0xF0822C + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 0xF08230 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 0xF08234 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 0xF08238 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 0xF0823C + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 0xF08240 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 0xF08244 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 0xF08248 + +#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 0xF0824C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 0xF08250 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 0xF08254 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 0xF08258 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 0xF0825C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 0xF08260 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 0xF08264 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 0xF08268 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 0xF0826C + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 0xF08270 + +#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 0xF08274 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 0xF08278 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 0xF0827C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 0xF08280 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 0xF08284 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 0xF08288 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 0xF0828C + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 0xF08290 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 0xF08294 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 0xF08298 + +#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 0xF0829C + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 0xF082A0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 0xF082A4 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 0xF082A8 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 0xF082AC + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 0xF082B0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 0xF082B4 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 0xF082B8 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 0xF082BC + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 0xF082C0 + +#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 0xF082C4 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 0xF082C8 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 0xF082CC + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 0xF082D0 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 0xF082D4 + +#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 0xF082D8 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF082E0 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF082E4 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF082E8 + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF082EC + +#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF082F0 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF082F4 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF082F8 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF082FC + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF08300 + +#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF08304 + +#define mmTPC4_QM_CP_FENCE0_RDATA_0 0xF08308 + +#define mmTPC4_QM_CP_FENCE0_RDATA_1 0xF0830C + +#define mmTPC4_QM_CP_FENCE0_RDATA_2 0xF08310 + +#define mmTPC4_QM_CP_FENCE0_RDATA_3 0xF08314 + +#define mmTPC4_QM_CP_FENCE0_RDATA_4 0xF08318 + +#define mmTPC4_QM_CP_FENCE1_RDATA_0 0xF0831C + +#define mmTPC4_QM_CP_FENCE1_RDATA_1 0xF08320 + +#define mmTPC4_QM_CP_FENCE1_RDATA_2 0xF08324 + +#define mmTPC4_QM_CP_FENCE1_RDATA_3 0xF08328 + +#define mmTPC4_QM_CP_FENCE1_RDATA_4 0xF0832C + +#define mmTPC4_QM_CP_FENCE2_RDATA_0 0xF08330 + +#define mmTPC4_QM_CP_FENCE2_RDATA_1 0xF08334 + +#define mmTPC4_QM_CP_FENCE2_RDATA_2 0xF08338 + +#define mmTPC4_QM_CP_FENCE2_RDATA_3 0xF0833C + +#define mmTPC4_QM_CP_FENCE2_RDATA_4 0xF08340 + +#define mmTPC4_QM_CP_FENCE3_RDATA_0 0xF08344 + +#define mmTPC4_QM_CP_FENCE3_RDATA_1 0xF08348 + +#define mmTPC4_QM_CP_FENCE3_RDATA_2 0xF0834C + +#define mmTPC4_QM_CP_FENCE3_RDATA_3 0xF08350 + +#define mmTPC4_QM_CP_FENCE3_RDATA_4 0xF08354 + +#define mmTPC4_QM_CP_FENCE0_CNT_0 0xF08358 + +#define mmTPC4_QM_CP_FENCE0_CNT_1 0xF0835C + +#define mmTPC4_QM_CP_FENCE0_CNT_2 0xF08360 + +#define mmTPC4_QM_CP_FENCE0_CNT_3 0xF08364 + +#define mmTPC4_QM_CP_FENCE0_CNT_4 0xF08368 + +#define mmTPC4_QM_CP_FENCE1_CNT_0 0xF0836C + +#define mmTPC4_QM_CP_FENCE1_CNT_1 0xF08370 + +#define mmTPC4_QM_CP_FENCE1_CNT_2 0xF08374 + +#define mmTPC4_QM_CP_FENCE1_CNT_3 0xF08378 + +#define mmTPC4_QM_CP_FENCE1_CNT_4 0xF0837C + +#define mmTPC4_QM_CP_FENCE2_CNT_0 0xF08380 + +#define mmTPC4_QM_CP_FENCE2_CNT_1 0xF08384 + +#define mmTPC4_QM_CP_FENCE2_CNT_2 0xF08388 + +#define mmTPC4_QM_CP_FENCE2_CNT_3 0xF0838C + +#define mmTPC4_QM_CP_FENCE2_CNT_4 0xF08390 + +#define mmTPC4_QM_CP_FENCE3_CNT_0 0xF08394 + +#define mmTPC4_QM_CP_FENCE3_CNT_1 0xF08398 + +#define mmTPC4_QM_CP_FENCE3_CNT_2 0xF0839C + +#define mmTPC4_QM_CP_FENCE3_CNT_3 0xF083A0 + +#define mmTPC4_QM_CP_FENCE3_CNT_4 0xF083A4 + +#define mmTPC4_QM_CP_STS_0 0xF083A8 + +#define mmTPC4_QM_CP_STS_1 0xF083AC + +#define mmTPC4_QM_CP_STS_2 0xF083B0 + +#define mmTPC4_QM_CP_STS_3 0xF083B4 + +#define mmTPC4_QM_CP_STS_4 0xF083B8 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_0 0xF083BC + +#define mmTPC4_QM_CP_CURRENT_INST_LO_1 0xF083C0 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_2 0xF083C4 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_3 0xF083C8 + +#define mmTPC4_QM_CP_CURRENT_INST_LO_4 0xF083CC + +#define mmTPC4_QM_CP_CURRENT_INST_HI_0 0xF083D0 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_1 0xF083D4 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_2 0xF083D8 + +#define mmTPC4_QM_CP_CURRENT_INST_HI_3 0xF083DC + +#define mmTPC4_QM_CP_CURRENT_INST_HI_4 0xF083E0 + +#define mmTPC4_QM_CP_BARRIER_CFG_0 0xF083F4 + +#define mmTPC4_QM_CP_BARRIER_CFG_1 0xF083F8 + +#define mmTPC4_QM_CP_BARRIER_CFG_2 0xF083FC + +#define mmTPC4_QM_CP_BARRIER_CFG_3 0xF08400 + +#define mmTPC4_QM_CP_BARRIER_CFG_4 0xF08404 + +#define mmTPC4_QM_CP_DBG_0_0 0xF08408 + +#define mmTPC4_QM_CP_DBG_0_1 0xF0840C + +#define mmTPC4_QM_CP_DBG_0_2 0xF08410 + +#define mmTPC4_QM_CP_DBG_0_3 0xF08414 + +#define mmTPC4_QM_CP_DBG_0_4 0xF08418 + +#define mmTPC4_QM_CP_ARUSER_31_11_0 0xF0841C + +#define mmTPC4_QM_CP_ARUSER_31_11_1 0xF08420 + +#define mmTPC4_QM_CP_ARUSER_31_11_2 0xF08424 + +#define mmTPC4_QM_CP_ARUSER_31_11_3 0xF08428 + +#define mmTPC4_QM_CP_ARUSER_31_11_4 0xF0842C + +#define mmTPC4_QM_CP_AWUSER_31_11_0 0xF08430 + +#define mmTPC4_QM_CP_AWUSER_31_11_1 0xF08434 + +#define mmTPC4_QM_CP_AWUSER_31_11_2 0xF08438 + +#define mmTPC4_QM_CP_AWUSER_31_11_3 0xF0843C + +#define mmTPC4_QM_CP_AWUSER_31_11_4 0xF08440 + +#define mmTPC4_QM_ARB_CFG_0 0xF08A00 + +#define mmTPC4_QM_ARB_CHOISE_Q_PUSH 0xF08A04 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_0 0xF08A08 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_1 0xF08A0C + +#define mmTPC4_QM_ARB_WRR_WEIGHT_2 0xF08A10 + +#define mmTPC4_QM_ARB_WRR_WEIGHT_3 0xF08A14 + +#define mmTPC4_QM_ARB_CFG_1 0xF08A18 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_0 0xF08A20 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_1 0xF08A24 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_2 0xF08A28 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_3 0xF08A2C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_4 0xF08A30 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_5 0xF08A34 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_6 0xF08A38 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_7 0xF08A3C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_8 0xF08A40 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_9 0xF08A44 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_10 0xF08A48 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_11 0xF08A4C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_12 0xF08A50 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_13 0xF08A54 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_14 0xF08A58 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_15 0xF08A5C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_16 0xF08A60 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_17 0xF08A64 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_18 0xF08A68 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_19 0xF08A6C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_20 0xF08A70 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_21 0xF08A74 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_22 0xF08A78 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_23 0xF08A7C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_24 0xF08A80 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_25 0xF08A84 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_26 0xF08A88 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_27 0xF08A8C + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_28 0xF08A90 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_29 0xF08A94 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_30 0xF08A98 + +#define mmTPC4_QM_ARB_MST_AVAIL_CRED_31 0xF08A9C + +#define mmTPC4_QM_ARB_MST_CRED_INC 0xF08AA0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF08AA4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF08AA8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF08AAC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF08AB0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF08AB4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF08AB8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF08ABC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF08AC0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF08AC4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF08AC8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF08ACC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF08AD0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF08AD4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF08AD8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF08ADC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF08AE0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF08AE4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF08AE8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF08AEC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF08AF0 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF08AF4 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF08AF8 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF08AFC + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF08B00 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF08B04 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF08B08 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF08B0C + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF08B10 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF08B14 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF08B18 + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF08B1C + +#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF08B20 + +#define mmTPC4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF08B28 + +#define mmTPC4_QM_ARB_MST_SLAVE_EN 0xF08B2C + +#define mmTPC4_QM_ARB_MST_QUIET_PER 0xF08B34 + +#define mmTPC4_QM_ARB_SLV_CHOISE_WDT 0xF08B38 + +#define mmTPC4_QM_ARB_SLV_ID 0xF08B3C + +#define mmTPC4_QM_ARB_MSG_MAX_INFLIGHT 0xF08B44 + +#define mmTPC4_QM_ARB_MSG_AWUSER_31_11 0xF08B48 + +#define mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP 0xF08B4C + +#define mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF08B50 + +#define mmTPC4_QM_ARB_BASE_LO 0xF08B54 + +#define mmTPC4_QM_ARB_BASE_HI 0xF08B58 + +#define mmTPC4_QM_ARB_STATE_STS 0xF08B80 + +#define mmTPC4_QM_ARB_CHOISE_FULLNESS_STS 0xF08B84 + +#define mmTPC4_QM_ARB_MSG_STS 0xF08B88 + +#define mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD 0xF08B8C + +#define mmTPC4_QM_ARB_ERR_CAUSE 0xF08B9C + +#define mmTPC4_QM_ARB_ERR_MSG_EN 0xF08BA0 + +#define mmTPC4_QM_ARB_ERR_STS_DRP 0xF08BA8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_0 0xF08BB0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_1 0xF08BB4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_2 0xF08BB8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_3 0xF08BBC + +#define mmTPC4_QM_ARB_MST_CRED_STS_4 0xF08BC0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_5 0xF08BC4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_6 0xF08BC8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_7 0xF08BCC + +#define mmTPC4_QM_ARB_MST_CRED_STS_8 0xF08BD0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_9 0xF08BD4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_10 0xF08BD8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_11 0xF08BDC + +#define mmTPC4_QM_ARB_MST_CRED_STS_12 0xF08BE0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_13 0xF08BE4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_14 0xF08BE8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_15 0xF08BEC + +#define mmTPC4_QM_ARB_MST_CRED_STS_16 0xF08BF0 + +#define mmTPC4_QM_ARB_MST_CRED_STS_17 0xF08BF4 + +#define mmTPC4_QM_ARB_MST_CRED_STS_18 0xF08BF8 + +#define mmTPC4_QM_ARB_MST_CRED_STS_19 0xF08BFC + +#define mmTPC4_QM_ARB_MST_CRED_STS_20 0xF08C00 + +#define mmTPC4_QM_ARB_MST_CRED_STS_21 0xF08C04 + +#define mmTPC4_QM_ARB_MST_CRED_STS_22 0xF08C08 + +#define mmTPC4_QM_ARB_MST_CRED_STS_23 0xF08C0C + +#define mmTPC4_QM_ARB_MST_CRED_STS_24 0xF08C10 + +#define mmTPC4_QM_ARB_MST_CRED_STS_25 0xF08C14 + +#define mmTPC4_QM_ARB_MST_CRED_STS_26 0xF08C18 + +#define mmTPC4_QM_ARB_MST_CRED_STS_27 0xF08C1C + +#define mmTPC4_QM_ARB_MST_CRED_STS_28 0xF08C20 + +#define mmTPC4_QM_ARB_MST_CRED_STS_29 0xF08C24 + +#define mmTPC4_QM_ARB_MST_CRED_STS_30 0xF08C28 + +#define mmTPC4_QM_ARB_MST_CRED_STS_31 0xF08C2C + +#define mmTPC4_QM_CGM_CFG 0xF08C70 + +#define mmTPC4_QM_CGM_STS 0xF08C74 + +#define mmTPC4_QM_CGM_CFG1 0xF08C78 + +#define mmTPC4_QM_LOCAL_RANGE_BASE 0xF08C80 + +#define mmTPC4_QM_LOCAL_RANGE_SIZE 0xF08C84 + +#define mmTPC4_QM_CSMR_STRICT_PRIO_CFG 0xF08C90 + +#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 0xF08C94 + +#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 0xF08C98 + +#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 0xF08C9C + +#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 0xF08CA0 + +#define mmTPC4_QM_GLBL_AXCACHE 0xF08CA4 + +#define mmTPC4_QM_IND_GW_APB_CFG 0xF08CB0 + +#define mmTPC4_QM_IND_GW_APB_WDATA 0xF08CB4 + +#define mmTPC4_QM_IND_GW_APB_RDATA 0xF08CB8 + +#define mmTPC4_QM_IND_GW_APB_STATUS 0xF08CBC + +#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08CD0 + +#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08CD4 + +#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08CD8 + +#define mmTPC4_QM_GLBL_MEM_INIT_BUSY 0xF08D00 + +#endif /* ASIC_REG_TPC4_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h new file mode 100644 index 000000000000..f428f891935a --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_CFG_REGS_H_ +#define ASIC_REG_TPC5_CFG_REGS_H_ + +/* + ***************************************** + * TPC5_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF46400 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF46404 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF46408 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF4640C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF46410 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF46414 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF46418 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF4641C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF46420 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF46424 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF46428 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF4642C + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF46430 + +#define mmTPC5_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF46434 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF46438 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF4643C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF46440 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF46444 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF46448 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF4644C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF46450 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF46454 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF46458 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF4645C + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF46460 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF46464 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF46468 + +#define mmTPC5_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF4646C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF46470 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF46474 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF46478 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF4647C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF46480 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF46484 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF46488 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF4648C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF46490 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF46494 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF46498 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF4649C + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF464A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF464A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF464A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF464AC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF464B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF464B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF464B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF464BC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF464C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF464C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF464C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF464CC + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF464D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF464D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF464D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF464DC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF464E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF464E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF464E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF464EC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF464F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF464F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF464F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF464FC + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF46500 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF46504 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF46508 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF4650C + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF46510 + +#define mmTPC5_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF46514 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF46518 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF4651C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF46520 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF46524 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF46528 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF4652C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF46530 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF46534 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF46538 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF4653C + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF46540 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF46544 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF46548 + +#define mmTPC5_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF4654C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF46550 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF46554 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF46558 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF4655C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF46560 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF46564 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF46568 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF4656C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF46570 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF46574 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF46578 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF4657C + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF46580 + +#define mmTPC5_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF46584 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF46588 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF4658C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF46590 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF46594 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF46598 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF4659C + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF465A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF465A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF465A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF465AC + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF465B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF465B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF465B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF465BC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF465C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF465C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF465C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF465CC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF465D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF465D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF465D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF465DC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF465E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF465E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF465E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF465EC + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF465F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF465F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF465F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF465FC + +#define mmTPC5_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF46600 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF46604 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF46608 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF4660C + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF46610 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF46614 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF46618 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF4661C + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF46620 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF46624 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF46628 + +#define mmTPC5_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF4662C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF46630 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF46634 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF46638 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF4663C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF46640 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF46644 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF46648 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF4664C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF46650 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF46654 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF46658 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF4665C + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF46660 + +#define mmTPC5_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF46664 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF46668 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF4666C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF46670 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF46674 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF46678 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF4667C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF46680 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF46684 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF46688 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF4668C + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF46690 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF46694 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF46698 + +#define mmTPC5_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF4669C + +#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF466A0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF466A4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF466A8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF466AC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF466B0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF466B4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF466B8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF466BC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF466C0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF466C4 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF466C8 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF466CC + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF466D0 + +#define mmTPC5_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF466D4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF466D8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF466DC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF466E0 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF466E4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF466E8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF466EC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF466F0 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF466F4 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF466F8 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF466FC + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF46700 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF46704 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF46708 + +#define mmTPC5_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF4670C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF46710 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF46714 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF46718 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF4671C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF46720 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF46724 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF46728 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF4672C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF46730 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF46734 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF46738 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF4673C + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF46740 + +#define mmTPC5_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF46744 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF46748 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF4674C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF46750 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF46754 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF46758 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF4675C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF46760 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF46764 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF46768 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF4676C + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF46770 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF46774 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF46778 + +#define mmTPC5_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF4677C + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF46780 + +#define mmTPC5_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF46784 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF46788 + +#define mmTPC5_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF4678C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_0 0xF46790 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_0 0xF46794 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_1 0xF46798 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_1 0xF4679C + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_2 0xF467A0 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_2 0xF467A4 + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_3 0xF467A8 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_3 0xF467AC + +#define mmTPC5_CFG_KERNEL_TID_BASE_DIM_4 0xF467B0 + +#define mmTPC5_CFG_KERNEL_TID_SIZE_DIM_4 0xF467B4 + +#define mmTPC5_CFG_KERNEL_KERNEL_CONFIG 0xF467B8 + +#define mmTPC5_CFG_KERNEL_KERNEL_ID 0xF467BC + +#define mmTPC5_CFG_KERNEL_SRF_0 0xF467C0 + +#define mmTPC5_CFG_KERNEL_SRF_1 0xF467C4 + +#define mmTPC5_CFG_KERNEL_SRF_2 0xF467C8 + +#define mmTPC5_CFG_KERNEL_SRF_3 0xF467CC + +#define mmTPC5_CFG_KERNEL_SRF_4 0xF467D0 + +#define mmTPC5_CFG_KERNEL_SRF_5 0xF467D4 + +#define mmTPC5_CFG_KERNEL_SRF_6 0xF467D8 + +#define mmTPC5_CFG_KERNEL_SRF_7 0xF467DC + +#define mmTPC5_CFG_KERNEL_SRF_8 0xF467E0 + +#define mmTPC5_CFG_KERNEL_SRF_9 0xF467E4 + +#define mmTPC5_CFG_KERNEL_SRF_10 0xF467E8 + +#define mmTPC5_CFG_KERNEL_SRF_11 0xF467EC + +#define mmTPC5_CFG_KERNEL_SRF_12 0xF467F0 + +#define mmTPC5_CFG_KERNEL_SRF_13 0xF467F4 + +#define mmTPC5_CFG_KERNEL_SRF_14 0xF467F8 + +#define mmTPC5_CFG_KERNEL_SRF_15 0xF467FC + +#define mmTPC5_CFG_KERNEL_SRF_16 0xF46800 + +#define mmTPC5_CFG_KERNEL_SRF_17 0xF46804 + +#define mmTPC5_CFG_KERNEL_SRF_18 0xF46808 + +#define mmTPC5_CFG_KERNEL_SRF_19 0xF4680C + +#define mmTPC5_CFG_KERNEL_SRF_20 0xF46810 + +#define mmTPC5_CFG_KERNEL_SRF_21 0xF46814 + +#define mmTPC5_CFG_KERNEL_SRF_22 0xF46818 + +#define mmTPC5_CFG_KERNEL_SRF_23 0xF4681C + +#define mmTPC5_CFG_KERNEL_SRF_24 0xF46820 + +#define mmTPC5_CFG_KERNEL_SRF_25 0xF46824 + +#define mmTPC5_CFG_KERNEL_SRF_26 0xF46828 + +#define mmTPC5_CFG_KERNEL_SRF_27 0xF4682C + +#define mmTPC5_CFG_KERNEL_SRF_28 0xF46830 + +#define mmTPC5_CFG_KERNEL_SRF_29 0xF46834 + +#define mmTPC5_CFG_KERNEL_SRF_30 0xF46838 + +#define mmTPC5_CFG_KERNEL_SRF_31 0xF4683C + +#define mmTPC5_CFG_ROUND_CSR 0xF468FC + +#define mmTPC5_CFG_PROT 0xF46900 + +#define mmTPC5_CFG_SEMAPHORE 0xF46908 + +#define mmTPC5_CFG_VFLAGS 0xF4690C + +#define mmTPC5_CFG_SFLAGS 0xF46910 + +#define mmTPC5_CFG_LFSR_POLYNOM 0xF46918 + +#define mmTPC5_CFG_STATUS 0xF4691C + +#define mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH 0xF46920 + +#define mmTPC5_CFG_CFG_SUBTRACT_VALUE 0xF46924 + +#define mmTPC5_CFG_SM_BASE_ADDRESS_HIGH 0xF4692C + +#define mmTPC5_CFG_TPC_CMD 0xF46930 + +#define mmTPC5_CFG_TPC_EXECUTE 0xF46938 + +#define mmTPC5_CFG_TPC_STALL 0xF4693C + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_LOW 0xF46940 + +#define mmTPC5_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF46944 + +#define mmTPC5_CFG_RD_RATE_LIMIT 0xF46948 + +#define mmTPC5_CFG_WR_RATE_LIMIT 0xF46950 + +#define mmTPC5_CFG_MSS_CONFIG 0xF46954 + +#define mmTPC5_CFG_TPC_INTR_CAUSE 0xF46958 + +#define mmTPC5_CFG_TPC_INTR_MASK 0xF4695C + +#define mmTPC5_CFG_WQ_CREDITS 0xF46960 + +#define mmTPC5_CFG_ARUSER_LO 0xF46964 + +#define mmTPC5_CFG_ARUSER_HI 0xF46968 + +#define mmTPC5_CFG_AWUSER_LO 0xF4696C + +#define mmTPC5_CFG_AWUSER_HI 0xF46970 + +#define mmTPC5_CFG_OPCODE_EXEC 0xF46974 + +#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF46978 + +#define mmTPC5_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF4697C + +#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF46980 + +#define mmTPC5_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF46984 + +#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF46988 + +#define mmTPC5_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF4698C + +#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF46990 + +#define mmTPC5_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF46994 + +#define mmTPC5_CFG_TSB_CFG_MAX_SIZE 0xF46998 + +#define mmTPC5_CFG_TSB_CFG 0xF4699C + +#define mmTPC5_CFG_DBGMEM_ADD 0xF469A0 + +#define mmTPC5_CFG_DBGMEM_DATA_WR 0xF469A4 + +#define mmTPC5_CFG_DBGMEM_DATA_RD 0xF469A8 + +#define mmTPC5_CFG_DBGMEM_CTRL 0xF469AC + +#define mmTPC5_CFG_DBGMEM_RC 0xF469B0 + +#define mmTPC5_CFG_TSB_INFLIGHT_CNTR 0xF469B4 + +#define mmTPC5_CFG_WQ_INFLIGHT_CNTR 0xF469B8 + +#define mmTPC5_CFG_WQ_LBW_TOTAL_CNTR 0xF469BC + +#define mmTPC5_CFG_WQ_HBW_TOTAL_CNTR 0xF469C0 + +#define mmTPC5_CFG_IRQ_OCCOUPY_CNTR 0xF469C4 + +#define mmTPC5_CFG_FUNC_MBIST_CNTRL 0xF469D0 + +#define mmTPC5_CFG_FUNC_MBIST_PAT 0xF469D4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_0 0xF469D8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_1 0xF469DC + +#define mmTPC5_CFG_FUNC_MBIST_MEM_2 0xF469E0 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_3 0xF469E4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_4 0xF469E8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_5 0xF469EC + +#define mmTPC5_CFG_FUNC_MBIST_MEM_6 0xF469F0 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_7 0xF469F4 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_8 0xF469F8 + +#define mmTPC5_CFG_FUNC_MBIST_MEM_9 0xF469FC + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF46A00 + +#define mmTPC5_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF46A04 + +#define mmTPC5_CFG_QM_TENSOR_0_PADDING_VALUE 0xF46A08 + +#define mmTPC5_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF46A0C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF46A10 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF46A14 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF46A18 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF46A1C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF46A20 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF46A24 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF46A28 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF46A2C + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF46A30 + +#define mmTPC5_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF46A34 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF46A38 + +#define mmTPC5_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF46A3C + +#define mmTPC5_CFG_QM_TENSOR_1_PADDING_VALUE 0xF46A40 + +#define mmTPC5_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF46A44 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF46A48 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF46A4C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF46A50 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF46A54 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF46A58 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF46A5C + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF46A60 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF46A64 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF46A68 + +#define mmTPC5_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF46A6C + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF46A70 + +#define mmTPC5_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF46A74 + +#define mmTPC5_CFG_QM_TENSOR_2_PADDING_VALUE 0xF46A78 + +#define mmTPC5_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF46A7C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF46A80 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF46A84 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF46A88 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF46A8C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF46A90 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF46A94 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF46A98 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF46A9C + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF46AA0 + +#define mmTPC5_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF46AA4 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF46AA8 + +#define mmTPC5_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF46AAC + +#define mmTPC5_CFG_QM_TENSOR_3_PADDING_VALUE 0xF46AB0 + +#define mmTPC5_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF46AB4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF46AB8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF46ABC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF46AC0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF46AC4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF46AC8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF46ACC + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF46AD0 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF46AD4 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF46AD8 + +#define mmTPC5_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF46ADC + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF46AE0 + +#define mmTPC5_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF46AE4 + +#define mmTPC5_CFG_QM_TENSOR_4_PADDING_VALUE 0xF46AE8 + +#define mmTPC5_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF46AEC + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF46AF0 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF46AF4 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF46AF8 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF46AFC + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF46B00 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF46B04 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF46B08 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF46B0C + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF46B10 + +#define mmTPC5_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF46B14 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF46B18 + +#define mmTPC5_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF46B1C + +#define mmTPC5_CFG_QM_TENSOR_5_PADDING_VALUE 0xF46B20 + +#define mmTPC5_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF46B24 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF46B28 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF46B2C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF46B30 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF46B34 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF46B38 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF46B3C + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF46B40 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF46B44 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF46B48 + +#define mmTPC5_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF46B4C + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF46B50 + +#define mmTPC5_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF46B54 + +#define mmTPC5_CFG_QM_TENSOR_6_PADDING_VALUE 0xF46B58 + +#define mmTPC5_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF46B5C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF46B60 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF46B64 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF46B68 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF46B6C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF46B70 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF46B74 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF46B78 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF46B7C + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF46B80 + +#define mmTPC5_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF46B84 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF46B88 + +#define mmTPC5_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF46B8C + +#define mmTPC5_CFG_QM_TENSOR_7_PADDING_VALUE 0xF46B90 + +#define mmTPC5_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF46B94 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF46B98 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF46B9C + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF46BA0 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF46BA4 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF46BA8 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF46BAC + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF46BB0 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF46BB4 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF46BB8 + +#define mmTPC5_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF46BBC + +#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF46BC0 + +#define mmTPC5_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF46BC4 + +#define mmTPC5_CFG_QM_TENSOR_8_PADDING_VALUE 0xF46BC8 + +#define mmTPC5_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF46BCC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF46BD0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF46BD4 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF46BD8 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF46BDC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF46BE0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF46BE4 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF46BE8 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF46BEC + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF46BF0 + +#define mmTPC5_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF46BF4 + +#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF46BF8 + +#define mmTPC5_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF46BFC + +#define mmTPC5_CFG_QM_TENSOR_9_PADDING_VALUE 0xF46C00 + +#define mmTPC5_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF46C04 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF46C08 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF46C0C + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF46C10 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF46C14 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF46C18 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF46C1C + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF46C20 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF46C24 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF46C28 + +#define mmTPC5_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF46C2C + +#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF46C30 + +#define mmTPC5_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF46C34 + +#define mmTPC5_CFG_QM_TENSOR_10_PADDING_VALUE 0xF46C38 + +#define mmTPC5_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF46C3C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF46C40 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF46C44 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF46C48 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF46C4C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF46C50 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF46C54 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF46C58 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF46C5C + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF46C60 + +#define mmTPC5_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF46C64 + +#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF46C68 + +#define mmTPC5_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF46C6C + +#define mmTPC5_CFG_QM_TENSOR_11_PADDING_VALUE 0xF46C70 + +#define mmTPC5_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF46C74 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF46C78 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF46C7C + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF46C80 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF46C84 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF46C88 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF46C8C + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF46C90 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF46C94 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF46C98 + +#define mmTPC5_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF46C9C + +#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF46CA0 + +#define mmTPC5_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF46CA4 + +#define mmTPC5_CFG_QM_TENSOR_12_PADDING_VALUE 0xF46CA8 + +#define mmTPC5_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF46CAC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF46CB0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF46CB4 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF46CB8 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF46CBC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF46CC0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF46CC4 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF46CC8 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF46CCC + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF46CD0 + +#define mmTPC5_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF46CD4 + +#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF46CD8 + +#define mmTPC5_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF46CDC + +#define mmTPC5_CFG_QM_TENSOR_13_PADDING_VALUE 0xF46CE0 + +#define mmTPC5_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF46CE4 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF46CE8 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF46CEC + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF46CF0 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF46CF4 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF46CF8 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF46CFC + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF46D00 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF46D04 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF46D08 + +#define mmTPC5_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF46D0C + +#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF46D10 + +#define mmTPC5_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF46D14 + +#define mmTPC5_CFG_QM_TENSOR_14_PADDING_VALUE 0xF46D18 + +#define mmTPC5_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF46D1C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF46D20 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF46D24 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF46D28 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF46D2C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF46D30 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF46D34 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF46D38 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF46D3C + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF46D40 + +#define mmTPC5_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF46D44 + +#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF46D48 + +#define mmTPC5_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF46D4C + +#define mmTPC5_CFG_QM_TENSOR_15_PADDING_VALUE 0xF46D50 + +#define mmTPC5_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF46D54 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF46D58 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF46D5C + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF46D60 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF46D64 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF46D68 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF46D6C + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF46D70 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF46D74 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF46D78 + +#define mmTPC5_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF46D7C + +#define mmTPC5_CFG_QM_SYNC_OBJECT_MESSAGE 0xF46D80 + +#define mmTPC5_CFG_QM_SYNC_OBJECT_ADDR 0xF46D84 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF46D88 + +#define mmTPC5_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF46D8C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_0 0xF46D90 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_0 0xF46D94 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_1 0xF46D98 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_1 0xF46D9C + +#define mmTPC5_CFG_QM_TID_BASE_DIM_2 0xF46DA0 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_2 0xF46DA4 + +#define mmTPC5_CFG_QM_TID_BASE_DIM_3 0xF46DA8 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_3 0xF46DAC + +#define mmTPC5_CFG_QM_TID_BASE_DIM_4 0xF46DB0 + +#define mmTPC5_CFG_QM_TID_SIZE_DIM_4 0xF46DB4 + +#define mmTPC5_CFG_QM_KERNEL_CONFIG 0xF46DB8 + +#define mmTPC5_CFG_QM_KERNEL_ID 0xF46DBC + +#define mmTPC5_CFG_QM_SRF_0 0xF46DC0 + +#define mmTPC5_CFG_QM_SRF_1 0xF46DC4 + +#define mmTPC5_CFG_QM_SRF_2 0xF46DC8 + +#define mmTPC5_CFG_QM_SRF_3 0xF46DCC + +#define mmTPC5_CFG_QM_SRF_4 0xF46DD0 + +#define mmTPC5_CFG_QM_SRF_5 0xF46DD4 + +#define mmTPC5_CFG_QM_SRF_6 0xF46DD8 + +#define mmTPC5_CFG_QM_SRF_7 0xF46DDC + +#define mmTPC5_CFG_QM_SRF_8 0xF46DE0 + +#define mmTPC5_CFG_QM_SRF_9 0xF46DE4 + +#define mmTPC5_CFG_QM_SRF_10 0xF46DE8 + +#define mmTPC5_CFG_QM_SRF_11 0xF46DEC + +#define mmTPC5_CFG_QM_SRF_12 0xF46DF0 + +#define mmTPC5_CFG_QM_SRF_13 0xF46DF4 + +#define mmTPC5_CFG_QM_SRF_14 0xF46DF8 + +#define mmTPC5_CFG_QM_SRF_15 0xF46DFC + +#define mmTPC5_CFG_QM_SRF_16 0xF46E00 + +#define mmTPC5_CFG_QM_SRF_17 0xF46E04 + +#define mmTPC5_CFG_QM_SRF_18 0xF46E08 + +#define mmTPC5_CFG_QM_SRF_19 0xF46E0C + +#define mmTPC5_CFG_QM_SRF_20 0xF46E10 + +#define mmTPC5_CFG_QM_SRF_21 0xF46E14 + +#define mmTPC5_CFG_QM_SRF_22 0xF46E18 + +#define mmTPC5_CFG_QM_SRF_23 0xF46E1C + +#define mmTPC5_CFG_QM_SRF_24 0xF46E20 + +#define mmTPC5_CFG_QM_SRF_25 0xF46E24 + +#define mmTPC5_CFG_QM_SRF_26 0xF46E28 + +#define mmTPC5_CFG_QM_SRF_27 0xF46E2C + +#define mmTPC5_CFG_QM_SRF_28 0xF46E30 + +#define mmTPC5_CFG_QM_SRF_29 0xF46E34 + +#define mmTPC5_CFG_QM_SRF_30 0xF46E38 + +#define mmTPC5_CFG_QM_SRF_31 0xF46E3C + +#endif /* ASIC_REG_TPC5_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h new file mode 100644 index 000000000000..cd3a810ff4c4 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc5_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC5_QM_REGS_H_ +#define ASIC_REG_TPC5_QM_REGS_H_ + +/* + ***************************************** + * TPC5_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC5_QM_GLBL_CFG0 0xF48000 + +#define mmTPC5_QM_GLBL_CFG1 0xF48004 + +#define mmTPC5_QM_GLBL_PROT 0xF48008 + +#define mmTPC5_QM_GLBL_ERR_CFG 0xF4800C + +#define mmTPC5_QM_GLBL_SECURE_PROPS_0 0xF48010 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_1 0xF48014 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_2 0xF48018 + +#define mmTPC5_QM_GLBL_SECURE_PROPS_3 0xF4801C + +#define mmTPC5_QM_GLBL_SECURE_PROPS_4 0xF48020 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_0 0xF48024 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_1 0xF48028 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_2 0xF4802C + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_3 0xF48030 + +#define mmTPC5_QM_GLBL_NON_SECURE_PROPS_4 0xF48034 + +#define mmTPC5_QM_GLBL_STS0 0xF48038 + +#define mmTPC5_QM_GLBL_STS1_0 0xF48040 + +#define mmTPC5_QM_GLBL_STS1_1 0xF48044 + +#define mmTPC5_QM_GLBL_STS1_2 0xF48048 + +#define mmTPC5_QM_GLBL_STS1_3 0xF4804C + +#define mmTPC5_QM_GLBL_STS1_4 0xF48050 + +#define mmTPC5_QM_GLBL_MSG_EN_0 0xF48054 + +#define mmTPC5_QM_GLBL_MSG_EN_1 0xF48058 + +#define mmTPC5_QM_GLBL_MSG_EN_2 0xF4805C + +#define mmTPC5_QM_GLBL_MSG_EN_3 0xF48060 + +#define mmTPC5_QM_GLBL_MSG_EN_4 0xF48068 + +#define mmTPC5_QM_PQ_BASE_LO_0 0xF48070 + +#define mmTPC5_QM_PQ_BASE_LO_1 0xF48074 + +#define mmTPC5_QM_PQ_BASE_LO_2 0xF48078 + +#define mmTPC5_QM_PQ_BASE_LO_3 0xF4807C + +#define mmTPC5_QM_PQ_BASE_HI_0 0xF48080 + +#define mmTPC5_QM_PQ_BASE_HI_1 0xF48084 + +#define mmTPC5_QM_PQ_BASE_HI_2 0xF48088 + +#define mmTPC5_QM_PQ_BASE_HI_3 0xF4808C + +#define mmTPC5_QM_PQ_SIZE_0 0xF48090 + +#define mmTPC5_QM_PQ_SIZE_1 0xF48094 + +#define mmTPC5_QM_PQ_SIZE_2 0xF48098 + +#define mmTPC5_QM_PQ_SIZE_3 0xF4809C + +#define mmTPC5_QM_PQ_PI_0 0xF480A0 + +#define mmTPC5_QM_PQ_PI_1 0xF480A4 + +#define mmTPC5_QM_PQ_PI_2 0xF480A8 + +#define mmTPC5_QM_PQ_PI_3 0xF480AC + +#define mmTPC5_QM_PQ_CI_0 0xF480B0 + +#define mmTPC5_QM_PQ_CI_1 0xF480B4 + +#define mmTPC5_QM_PQ_CI_2 0xF480B8 + +#define mmTPC5_QM_PQ_CI_3 0xF480BC + +#define mmTPC5_QM_PQ_CFG0_0 0xF480C0 + +#define mmTPC5_QM_PQ_CFG0_1 0xF480C4 + +#define mmTPC5_QM_PQ_CFG0_2 0xF480C8 + +#define mmTPC5_QM_PQ_CFG0_3 0xF480CC + +#define mmTPC5_QM_PQ_CFG1_0 0xF480D0 + +#define mmTPC5_QM_PQ_CFG1_1 0xF480D4 + +#define mmTPC5_QM_PQ_CFG1_2 0xF480D8 + +#define mmTPC5_QM_PQ_CFG1_3 0xF480DC + +#define mmTPC5_QM_PQ_ARUSER_31_11_0 0xF480E0 + +#define mmTPC5_QM_PQ_ARUSER_31_11_1 0xF480E4 + +#define mmTPC5_QM_PQ_ARUSER_31_11_2 0xF480E8 + +#define mmTPC5_QM_PQ_ARUSER_31_11_3 0xF480EC + +#define mmTPC5_QM_PQ_STS0_0 0xF480F0 + +#define mmTPC5_QM_PQ_STS0_1 0xF480F4 + +#define mmTPC5_QM_PQ_STS0_2 0xF480F8 + +#define mmTPC5_QM_PQ_STS0_3 0xF480FC + +#define mmTPC5_QM_PQ_STS1_0 0xF48100 + +#define mmTPC5_QM_PQ_STS1_1 0xF48104 + +#define mmTPC5_QM_PQ_STS1_2 0xF48108 + +#define mmTPC5_QM_PQ_STS1_3 0xF4810C + +#define mmTPC5_QM_CQ_CFG0_0 0xF48110 + +#define mmTPC5_QM_CQ_CFG0_1 0xF48114 + +#define mmTPC5_QM_CQ_CFG0_2 0xF48118 + +#define mmTPC5_QM_CQ_CFG0_3 0xF4811C + +#define mmTPC5_QM_CQ_CFG0_4 0xF48120 + +#define mmTPC5_QM_CQ_CFG1_0 0xF48124 + +#define mmTPC5_QM_CQ_CFG1_1 0xF48128 + +#define mmTPC5_QM_CQ_CFG1_2 0xF4812C + +#define mmTPC5_QM_CQ_CFG1_3 0xF48130 + +#define mmTPC5_QM_CQ_CFG1_4 0xF48134 + +#define mmTPC5_QM_CQ_ARUSER_31_11_0 0xF48138 + +#define mmTPC5_QM_CQ_ARUSER_31_11_1 0xF4813C + +#define mmTPC5_QM_CQ_ARUSER_31_11_2 0xF48140 + +#define mmTPC5_QM_CQ_ARUSER_31_11_3 0xF48144 + +#define mmTPC5_QM_CQ_ARUSER_31_11_4 0xF48148 + +#define mmTPC5_QM_CQ_STS0_0 0xF4814C + +#define mmTPC5_QM_CQ_STS0_1 0xF48150 + +#define mmTPC5_QM_CQ_STS0_2 0xF48154 + +#define mmTPC5_QM_CQ_STS0_3 0xF48158 + +#define mmTPC5_QM_CQ_STS0_4 0xF4815C + +#define mmTPC5_QM_CQ_STS1_0 0xF48160 + +#define mmTPC5_QM_CQ_STS1_1 0xF48164 + +#define mmTPC5_QM_CQ_STS1_2 0xF48168 + +#define mmTPC5_QM_CQ_STS1_3 0xF4816C + +#define mmTPC5_QM_CQ_STS1_4 0xF48170 + +#define mmTPC5_QM_CQ_PTR_LO_0 0xF48174 + +#define mmTPC5_QM_CQ_PTR_HI_0 0xF48178 + +#define mmTPC5_QM_CQ_TSIZE_0 0xF4817C + +#define mmTPC5_QM_CQ_CTL_0 0xF48180 + +#define mmTPC5_QM_CQ_PTR_LO_1 0xF48184 + +#define mmTPC5_QM_CQ_PTR_HI_1 0xF48188 + +#define mmTPC5_QM_CQ_TSIZE_1 0xF4818C + +#define mmTPC5_QM_CQ_CTL_1 0xF48190 + +#define mmTPC5_QM_CQ_PTR_LO_2 0xF48194 + +#define mmTPC5_QM_CQ_PTR_HI_2 0xF48198 + +#define mmTPC5_QM_CQ_TSIZE_2 0xF4819C + +#define mmTPC5_QM_CQ_CTL_2 0xF481A0 + +#define mmTPC5_QM_CQ_PTR_LO_3 0xF481A4 + +#define mmTPC5_QM_CQ_PTR_HI_3 0xF481A8 + +#define mmTPC5_QM_CQ_TSIZE_3 0xF481AC + +#define mmTPC5_QM_CQ_CTL_3 0xF481B0 + +#define mmTPC5_QM_CQ_PTR_LO_4 0xF481B4 + +#define mmTPC5_QM_CQ_PTR_HI_4 0xF481B8 + +#define mmTPC5_QM_CQ_TSIZE_4 0xF481BC + +#define mmTPC5_QM_CQ_CTL_4 0xF481C0 + +#define mmTPC5_QM_CQ_PTR_LO_STS_0 0xF481C4 + +#define mmTPC5_QM_CQ_PTR_LO_STS_1 0xF481C8 + +#define mmTPC5_QM_CQ_PTR_LO_STS_2 0xF481CC + +#define mmTPC5_QM_CQ_PTR_LO_STS_3 0xF481D0 + +#define mmTPC5_QM_CQ_PTR_LO_STS_4 0xF481D4 + +#define mmTPC5_QM_CQ_PTR_HI_STS_0 0xF481D8 + +#define mmTPC5_QM_CQ_PTR_HI_STS_1 0xF481DC + +#define mmTPC5_QM_CQ_PTR_HI_STS_2 0xF481E0 + +#define mmTPC5_QM_CQ_PTR_HI_STS_3 0xF481E4 + +#define mmTPC5_QM_CQ_PTR_HI_STS_4 0xF481E8 + +#define mmTPC5_QM_CQ_TSIZE_STS_0 0xF481EC + +#define mmTPC5_QM_CQ_TSIZE_STS_1 0xF481F0 + +#define mmTPC5_QM_CQ_TSIZE_STS_2 0xF481F4 + +#define mmTPC5_QM_CQ_TSIZE_STS_3 0xF481F8 + +#define mmTPC5_QM_CQ_TSIZE_STS_4 0xF481FC + +#define mmTPC5_QM_CQ_CTL_STS_0 0xF48200 + +#define mmTPC5_QM_CQ_CTL_STS_1 0xF48204 + +#define mmTPC5_QM_CQ_CTL_STS_2 0xF48208 + +#define mmTPC5_QM_CQ_CTL_STS_3 0xF4820C + +#define mmTPC5_QM_CQ_CTL_STS_4 0xF48210 + +#define mmTPC5_QM_CQ_IFIFO_CNT_0 0xF48214 + +#define mmTPC5_QM_CQ_IFIFO_CNT_1 0xF48218 + +#define mmTPC5_QM_CQ_IFIFO_CNT_2 0xF4821C + +#define mmTPC5_QM_CQ_IFIFO_CNT_3 0xF48220 + +#define mmTPC5_QM_CQ_IFIFO_CNT_4 0xF48224 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_0 0xF48228 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_1 0xF4822C + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_2 0xF48230 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_3 0xF48234 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_LO_4 0xF48238 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_0 0xF4823C + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_1 0xF48240 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_2 0xF48244 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_3 0xF48248 + +#define mmTPC5_QM_CP_MSG_BASE0_ADDR_HI_4 0xF4824C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_0 0xF48250 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_1 0xF48254 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_2 0xF48258 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_3 0xF4825C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_LO_4 0xF48260 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_0 0xF48264 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_1 0xF48268 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_2 0xF4826C + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_3 0xF48270 + +#define mmTPC5_QM_CP_MSG_BASE1_ADDR_HI_4 0xF48274 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_0 0xF48278 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_1 0xF4827C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_2 0xF48280 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_3 0xF48284 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_LO_4 0xF48288 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_0 0xF4828C + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_1 0xF48290 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_2 0xF48294 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_3 0xF48298 + +#define mmTPC5_QM_CP_MSG_BASE2_ADDR_HI_4 0xF4829C + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_0 0xF482A0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_1 0xF482A4 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_2 0xF482A8 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_3 0xF482AC + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_LO_4 0xF482B0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_0 0xF482B4 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_1 0xF482B8 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_2 0xF482BC + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_3 0xF482C0 + +#define mmTPC5_QM_CP_MSG_BASE3_ADDR_HI_4 0xF482C4 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_0 0xF482C8 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_1 0xF482CC + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_2 0xF482D0 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_3 0xF482D4 + +#define mmTPC5_QM_CP_LDMA_TSIZE_OFFSET_4 0xF482D8 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF482E0 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF482E4 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF482E8 + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF482EC + +#define mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF482F0 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF482F4 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF482F8 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF482FC + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF48300 + +#define mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF48304 + +#define mmTPC5_QM_CP_FENCE0_RDATA_0 0xF48308 + +#define mmTPC5_QM_CP_FENCE0_RDATA_1 0xF4830C + +#define mmTPC5_QM_CP_FENCE0_RDATA_2 0xF48310 + +#define mmTPC5_QM_CP_FENCE0_RDATA_3 0xF48314 + +#define mmTPC5_QM_CP_FENCE0_RDATA_4 0xF48318 + +#define mmTPC5_QM_CP_FENCE1_RDATA_0 0xF4831C + +#define mmTPC5_QM_CP_FENCE1_RDATA_1 0xF48320 + +#define mmTPC5_QM_CP_FENCE1_RDATA_2 0xF48324 + +#define mmTPC5_QM_CP_FENCE1_RDATA_3 0xF48328 + +#define mmTPC5_QM_CP_FENCE1_RDATA_4 0xF4832C + +#define mmTPC5_QM_CP_FENCE2_RDATA_0 0xF48330 + +#define mmTPC5_QM_CP_FENCE2_RDATA_1 0xF48334 + +#define mmTPC5_QM_CP_FENCE2_RDATA_2 0xF48338 + +#define mmTPC5_QM_CP_FENCE2_RDATA_3 0xF4833C + +#define mmTPC5_QM_CP_FENCE2_RDATA_4 0xF48340 + +#define mmTPC5_QM_CP_FENCE3_RDATA_0 0xF48344 + +#define mmTPC5_QM_CP_FENCE3_RDATA_1 0xF48348 + +#define mmTPC5_QM_CP_FENCE3_RDATA_2 0xF4834C + +#define mmTPC5_QM_CP_FENCE3_RDATA_3 0xF48350 + +#define mmTPC5_QM_CP_FENCE3_RDATA_4 0xF48354 + +#define mmTPC5_QM_CP_FENCE0_CNT_0 0xF48358 + +#define mmTPC5_QM_CP_FENCE0_CNT_1 0xF4835C + +#define mmTPC5_QM_CP_FENCE0_CNT_2 0xF48360 + +#define mmTPC5_QM_CP_FENCE0_CNT_3 0xF48364 + +#define mmTPC5_QM_CP_FENCE0_CNT_4 0xF48368 + +#define mmTPC5_QM_CP_FENCE1_CNT_0 0xF4836C + +#define mmTPC5_QM_CP_FENCE1_CNT_1 0xF48370 + +#define mmTPC5_QM_CP_FENCE1_CNT_2 0xF48374 + +#define mmTPC5_QM_CP_FENCE1_CNT_3 0xF48378 + +#define mmTPC5_QM_CP_FENCE1_CNT_4 0xF4837C + +#define mmTPC5_QM_CP_FENCE2_CNT_0 0xF48380 + +#define mmTPC5_QM_CP_FENCE2_CNT_1 0xF48384 + +#define mmTPC5_QM_CP_FENCE2_CNT_2 0xF48388 + +#define mmTPC5_QM_CP_FENCE2_CNT_3 0xF4838C + +#define mmTPC5_QM_CP_FENCE2_CNT_4 0xF48390 + +#define mmTPC5_QM_CP_FENCE3_CNT_0 0xF48394 + +#define mmTPC5_QM_CP_FENCE3_CNT_1 0xF48398 + +#define mmTPC5_QM_CP_FENCE3_CNT_2 0xF4839C + +#define mmTPC5_QM_CP_FENCE3_CNT_3 0xF483A0 + +#define mmTPC5_QM_CP_FENCE3_CNT_4 0xF483A4 + +#define mmTPC5_QM_CP_STS_0 0xF483A8 + +#define mmTPC5_QM_CP_STS_1 0xF483AC + +#define mmTPC5_QM_CP_STS_2 0xF483B0 + +#define mmTPC5_QM_CP_STS_3 0xF483B4 + +#define mmTPC5_QM_CP_STS_4 0xF483B8 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_0 0xF483BC + +#define mmTPC5_QM_CP_CURRENT_INST_LO_1 0xF483C0 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_2 0xF483C4 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_3 0xF483C8 + +#define mmTPC5_QM_CP_CURRENT_INST_LO_4 0xF483CC + +#define mmTPC5_QM_CP_CURRENT_INST_HI_0 0xF483D0 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_1 0xF483D4 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_2 0xF483D8 + +#define mmTPC5_QM_CP_CURRENT_INST_HI_3 0xF483DC + +#define mmTPC5_QM_CP_CURRENT_INST_HI_4 0xF483E0 + +#define mmTPC5_QM_CP_BARRIER_CFG_0 0xF483F4 + +#define mmTPC5_QM_CP_BARRIER_CFG_1 0xF483F8 + +#define mmTPC5_QM_CP_BARRIER_CFG_2 0xF483FC + +#define mmTPC5_QM_CP_BARRIER_CFG_3 0xF48400 + +#define mmTPC5_QM_CP_BARRIER_CFG_4 0xF48404 + +#define mmTPC5_QM_CP_DBG_0_0 0xF48408 + +#define mmTPC5_QM_CP_DBG_0_1 0xF4840C + +#define mmTPC5_QM_CP_DBG_0_2 0xF48410 + +#define mmTPC5_QM_CP_DBG_0_3 0xF48414 + +#define mmTPC5_QM_CP_DBG_0_4 0xF48418 + +#define mmTPC5_QM_CP_ARUSER_31_11_0 0xF4841C + +#define mmTPC5_QM_CP_ARUSER_31_11_1 0xF48420 + +#define mmTPC5_QM_CP_ARUSER_31_11_2 0xF48424 + +#define mmTPC5_QM_CP_ARUSER_31_11_3 0xF48428 + +#define mmTPC5_QM_CP_ARUSER_31_11_4 0xF4842C + +#define mmTPC5_QM_CP_AWUSER_31_11_0 0xF48430 + +#define mmTPC5_QM_CP_AWUSER_31_11_1 0xF48434 + +#define mmTPC5_QM_CP_AWUSER_31_11_2 0xF48438 + +#define mmTPC5_QM_CP_AWUSER_31_11_3 0xF4843C + +#define mmTPC5_QM_CP_AWUSER_31_11_4 0xF48440 + +#define mmTPC5_QM_ARB_CFG_0 0xF48A00 + +#define mmTPC5_QM_ARB_CHOISE_Q_PUSH 0xF48A04 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_0 0xF48A08 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_1 0xF48A0C + +#define mmTPC5_QM_ARB_WRR_WEIGHT_2 0xF48A10 + +#define mmTPC5_QM_ARB_WRR_WEIGHT_3 0xF48A14 + +#define mmTPC5_QM_ARB_CFG_1 0xF48A18 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_0 0xF48A20 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_1 0xF48A24 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_2 0xF48A28 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_3 0xF48A2C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_4 0xF48A30 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_5 0xF48A34 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_6 0xF48A38 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_7 0xF48A3C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_8 0xF48A40 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_9 0xF48A44 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_10 0xF48A48 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_11 0xF48A4C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_12 0xF48A50 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_13 0xF48A54 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_14 0xF48A58 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_15 0xF48A5C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_16 0xF48A60 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_17 0xF48A64 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_18 0xF48A68 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_19 0xF48A6C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_20 0xF48A70 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_21 0xF48A74 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_22 0xF48A78 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_23 0xF48A7C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_24 0xF48A80 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_25 0xF48A84 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_26 0xF48A88 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_27 0xF48A8C + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_28 0xF48A90 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_29 0xF48A94 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_30 0xF48A98 + +#define mmTPC5_QM_ARB_MST_AVAIL_CRED_31 0xF48A9C + +#define mmTPC5_QM_ARB_MST_CRED_INC 0xF48AA0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF48AA4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF48AA8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF48AAC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF48AB0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF48AB4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF48AB8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF48ABC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF48AC0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF48AC4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF48AC8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF48ACC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF48AD0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF48AD4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF48AD8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF48ADC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF48AE0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF48AE4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF48AE8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF48AEC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF48AF0 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF48AF4 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF48AF8 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF48AFC + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF48B00 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF48B04 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF48B08 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF48B0C + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF48B10 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF48B14 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF48B18 + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF48B1C + +#define mmTPC5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF48B20 + +#define mmTPC5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF48B28 + +#define mmTPC5_QM_ARB_MST_SLAVE_EN 0xF48B2C + +#define mmTPC5_QM_ARB_MST_QUIET_PER 0xF48B34 + +#define mmTPC5_QM_ARB_SLV_CHOISE_WDT 0xF48B38 + +#define mmTPC5_QM_ARB_SLV_ID 0xF48B3C + +#define mmTPC5_QM_ARB_MSG_MAX_INFLIGHT 0xF48B44 + +#define mmTPC5_QM_ARB_MSG_AWUSER_31_11 0xF48B48 + +#define mmTPC5_QM_ARB_MSG_AWUSER_SEC_PROP 0xF48B4C + +#define mmTPC5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF48B50 + +#define mmTPC5_QM_ARB_BASE_LO 0xF48B54 + +#define mmTPC5_QM_ARB_BASE_HI 0xF48B58 + +#define mmTPC5_QM_ARB_STATE_STS 0xF48B80 + +#define mmTPC5_QM_ARB_CHOISE_FULLNESS_STS 0xF48B84 + +#define mmTPC5_QM_ARB_MSG_STS 0xF48B88 + +#define mmTPC5_QM_ARB_SLV_CHOISE_Q_HEAD 0xF48B8C + +#define mmTPC5_QM_ARB_ERR_CAUSE 0xF48B9C + +#define mmTPC5_QM_ARB_ERR_MSG_EN 0xF48BA0 + +#define mmTPC5_QM_ARB_ERR_STS_DRP 0xF48BA8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_0 0xF48BB0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_1 0xF48BB4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_2 0xF48BB8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_3 0xF48BBC + +#define mmTPC5_QM_ARB_MST_CRED_STS_4 0xF48BC0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_5 0xF48BC4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_6 0xF48BC8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_7 0xF48BCC + +#define mmTPC5_QM_ARB_MST_CRED_STS_8 0xF48BD0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_9 0xF48BD4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_10 0xF48BD8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_11 0xF48BDC + +#define mmTPC5_QM_ARB_MST_CRED_STS_12 0xF48BE0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_13 0xF48BE4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_14 0xF48BE8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_15 0xF48BEC + +#define mmTPC5_QM_ARB_MST_CRED_STS_16 0xF48BF0 + +#define mmTPC5_QM_ARB_MST_CRED_STS_17 0xF48BF4 + +#define mmTPC5_QM_ARB_MST_CRED_STS_18 0xF48BF8 + +#define mmTPC5_QM_ARB_MST_CRED_STS_19 0xF48BFC + +#define mmTPC5_QM_ARB_MST_CRED_STS_20 0xF48C00 + +#define mmTPC5_QM_ARB_MST_CRED_STS_21 0xF48C04 + +#define mmTPC5_QM_ARB_MST_CRED_STS_22 0xF48C08 + +#define mmTPC5_QM_ARB_MST_CRED_STS_23 0xF48C0C + +#define mmTPC5_QM_ARB_MST_CRED_STS_24 0xF48C10 + +#define mmTPC5_QM_ARB_MST_CRED_STS_25 0xF48C14 + +#define mmTPC5_QM_ARB_MST_CRED_STS_26 0xF48C18 + +#define mmTPC5_QM_ARB_MST_CRED_STS_27 0xF48C1C + +#define mmTPC5_QM_ARB_MST_CRED_STS_28 0xF48C20 + +#define mmTPC5_QM_ARB_MST_CRED_STS_29 0xF48C24 + +#define mmTPC5_QM_ARB_MST_CRED_STS_30 0xF48C28 + +#define mmTPC5_QM_ARB_MST_CRED_STS_31 0xF48C2C + +#define mmTPC5_QM_CGM_CFG 0xF48C70 + +#define mmTPC5_QM_CGM_STS 0xF48C74 + +#define mmTPC5_QM_CGM_CFG1 0xF48C78 + +#define mmTPC5_QM_LOCAL_RANGE_BASE 0xF48C80 + +#define mmTPC5_QM_LOCAL_RANGE_SIZE 0xF48C84 + +#define mmTPC5_QM_CSMR_STRICT_PRIO_CFG 0xF48C90 + +#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_1 0xF48C94 + +#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_0 0xF48C98 + +#define mmTPC5_QM_LBW_WR_RATE_LIM_CFG_1 0xF48C9C + +#define mmTPC5_QM_HBW_RD_RATE_LIM_CFG_0 0xF48CA0 + +#define mmTPC5_QM_GLBL_AXCACHE 0xF48CA4 + +#define mmTPC5_QM_IND_GW_APB_CFG 0xF48CB0 + +#define mmTPC5_QM_IND_GW_APB_WDATA 0xF48CB4 + +#define mmTPC5_QM_IND_GW_APB_RDATA 0xF48CB8 + +#define mmTPC5_QM_IND_GW_APB_STATUS 0xF48CBC + +#define mmTPC5_QM_GLBL_ERR_ADDR_LO 0xF48CD0 + +#define mmTPC5_QM_GLBL_ERR_ADDR_HI 0xF48CD4 + +#define mmTPC5_QM_GLBL_ERR_WDATA 0xF48CD8 + +#define mmTPC5_QM_GLBL_MEM_INIT_BUSY 0xF48D00 + +#endif /* ASIC_REG_TPC5_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h new file mode 100644 index 000000000000..eb251e72813f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_CFG_REGS_H_ +#define ASIC_REG_TPC6_CFG_REGS_H_ + +/* + ***************************************** + * TPC6_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF86400 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF86404 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF86408 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF8640C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF86410 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF86414 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF86418 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF8641C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF86420 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF86424 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF86428 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF8642C + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF86430 + +#define mmTPC6_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF86434 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF86438 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF8643C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF86440 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF86444 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF86448 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF8644C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF86450 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF86454 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF86458 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF8645C + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF86460 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF86464 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF86468 + +#define mmTPC6_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF8646C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF86470 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF86474 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF86478 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF8647C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF86480 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF86484 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF86488 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF8648C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF86490 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF86494 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF86498 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF8649C + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF864A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF864A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF864A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF864AC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF864B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF864B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF864B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF864BC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF864C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF864C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF864C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF864CC + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF864D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF864D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF864D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF864DC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF864E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF864E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF864E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF864EC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF864F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF864F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF864F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF864FC + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF86500 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF86504 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF86508 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF8650C + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF86510 + +#define mmTPC6_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF86514 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF86518 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF8651C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF86520 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF86524 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF86528 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF8652C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF86530 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF86534 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF86538 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF8653C + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF86540 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF86544 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF86548 + +#define mmTPC6_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF8654C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF86550 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF86554 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF86558 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF8655C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF86560 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF86564 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF86568 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF8656C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF86570 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF86574 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF86578 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF8657C + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF86580 + +#define mmTPC6_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF86584 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF86588 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF8658C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF86590 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF86594 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF86598 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF8659C + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF865A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF865A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF865A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF865AC + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF865B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF865B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF865B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF865BC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xF865C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xF865C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xF865C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xF865CC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xF865D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xF865D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xF865D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xF865DC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xF865E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xF865E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xF865E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xF865EC + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xF865F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xF865F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xF865F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xF865FC + +#define mmTPC6_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xF86600 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xF86604 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xF86608 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xF8660C + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xF86610 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xF86614 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xF86618 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xF8661C + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xF86620 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xF86624 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xF86628 + +#define mmTPC6_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xF8662C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xF86630 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xF86634 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xF86638 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xF8663C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xF86640 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xF86644 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xF86648 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xF8664C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xF86650 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xF86654 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xF86658 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xF8665C + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xF86660 + +#define mmTPC6_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xF86664 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xF86668 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xF8666C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xF86670 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xF86674 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xF86678 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xF8667C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xF86680 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xF86684 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xF86688 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xF8668C + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xF86690 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xF86694 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xF86698 + +#define mmTPC6_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xF8669C + +#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xF866A0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xF866A4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xF866A8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xF866AC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xF866B0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xF866B4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xF866B8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xF866BC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xF866C0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xF866C4 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xF866C8 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xF866CC + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xF866D0 + +#define mmTPC6_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xF866D4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xF866D8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xF866DC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xF866E0 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xF866E4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xF866E8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xF866EC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xF866F0 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xF866F4 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xF866F8 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xF866FC + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xF86700 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xF86704 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xF86708 + +#define mmTPC6_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xF8670C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xF86710 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xF86714 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xF86718 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xF8671C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xF86720 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xF86724 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xF86728 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xF8672C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xF86730 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xF86734 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xF86738 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xF8673C + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xF86740 + +#define mmTPC6_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xF86744 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xF86748 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xF8674C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xF86750 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xF86754 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xF86758 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xF8675C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xF86760 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xF86764 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xF86768 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xF8676C + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xF86770 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xF86774 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xF86778 + +#define mmTPC6_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xF8677C + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF86780 + +#define mmTPC6_CFG_KERNEL_SYNC_OBJECT_ADDR 0xF86784 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF86788 + +#define mmTPC6_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF8678C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_0 0xF86790 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_0 0xF86794 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_1 0xF86798 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_1 0xF8679C + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_2 0xF867A0 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_2 0xF867A4 + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_3 0xF867A8 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_3 0xF867AC + +#define mmTPC6_CFG_KERNEL_TID_BASE_DIM_4 0xF867B0 + +#define mmTPC6_CFG_KERNEL_TID_SIZE_DIM_4 0xF867B4 + +#define mmTPC6_CFG_KERNEL_KERNEL_CONFIG 0xF867B8 + +#define mmTPC6_CFG_KERNEL_KERNEL_ID 0xF867BC + +#define mmTPC6_CFG_KERNEL_SRF_0 0xF867C0 + +#define mmTPC6_CFG_KERNEL_SRF_1 0xF867C4 + +#define mmTPC6_CFG_KERNEL_SRF_2 0xF867C8 + +#define mmTPC6_CFG_KERNEL_SRF_3 0xF867CC + +#define mmTPC6_CFG_KERNEL_SRF_4 0xF867D0 + +#define mmTPC6_CFG_KERNEL_SRF_5 0xF867D4 + +#define mmTPC6_CFG_KERNEL_SRF_6 0xF867D8 + +#define mmTPC6_CFG_KERNEL_SRF_7 0xF867DC + +#define mmTPC6_CFG_KERNEL_SRF_8 0xF867E0 + +#define mmTPC6_CFG_KERNEL_SRF_9 0xF867E4 + +#define mmTPC6_CFG_KERNEL_SRF_10 0xF867E8 + +#define mmTPC6_CFG_KERNEL_SRF_11 0xF867EC + +#define mmTPC6_CFG_KERNEL_SRF_12 0xF867F0 + +#define mmTPC6_CFG_KERNEL_SRF_13 0xF867F4 + +#define mmTPC6_CFG_KERNEL_SRF_14 0xF867F8 + +#define mmTPC6_CFG_KERNEL_SRF_15 0xF867FC + +#define mmTPC6_CFG_KERNEL_SRF_16 0xF86800 + +#define mmTPC6_CFG_KERNEL_SRF_17 0xF86804 + +#define mmTPC6_CFG_KERNEL_SRF_18 0xF86808 + +#define mmTPC6_CFG_KERNEL_SRF_19 0xF8680C + +#define mmTPC6_CFG_KERNEL_SRF_20 0xF86810 + +#define mmTPC6_CFG_KERNEL_SRF_21 0xF86814 + +#define mmTPC6_CFG_KERNEL_SRF_22 0xF86818 + +#define mmTPC6_CFG_KERNEL_SRF_23 0xF8681C + +#define mmTPC6_CFG_KERNEL_SRF_24 0xF86820 + +#define mmTPC6_CFG_KERNEL_SRF_25 0xF86824 + +#define mmTPC6_CFG_KERNEL_SRF_26 0xF86828 + +#define mmTPC6_CFG_KERNEL_SRF_27 0xF8682C + +#define mmTPC6_CFG_KERNEL_SRF_28 0xF86830 + +#define mmTPC6_CFG_KERNEL_SRF_29 0xF86834 + +#define mmTPC6_CFG_KERNEL_SRF_30 0xF86838 + +#define mmTPC6_CFG_KERNEL_SRF_31 0xF8683C + +#define mmTPC6_CFG_ROUND_CSR 0xF868FC + +#define mmTPC6_CFG_PROT 0xF86900 + +#define mmTPC6_CFG_SEMAPHORE 0xF86908 + +#define mmTPC6_CFG_VFLAGS 0xF8690C + +#define mmTPC6_CFG_SFLAGS 0xF86910 + +#define mmTPC6_CFG_LFSR_POLYNOM 0xF86918 + +#define mmTPC6_CFG_STATUS 0xF8691C + +#define mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH 0xF86920 + +#define mmTPC6_CFG_CFG_SUBTRACT_VALUE 0xF86924 + +#define mmTPC6_CFG_SM_BASE_ADDRESS_HIGH 0xF8692C + +#define mmTPC6_CFG_TPC_CMD 0xF86930 + +#define mmTPC6_CFG_TPC_EXECUTE 0xF86938 + +#define mmTPC6_CFG_TPC_STALL 0xF8693C + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_LOW 0xF86940 + +#define mmTPC6_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF86944 + +#define mmTPC6_CFG_RD_RATE_LIMIT 0xF86948 + +#define mmTPC6_CFG_WR_RATE_LIMIT 0xF86950 + +#define mmTPC6_CFG_MSS_CONFIG 0xF86954 + +#define mmTPC6_CFG_TPC_INTR_CAUSE 0xF86958 + +#define mmTPC6_CFG_TPC_INTR_MASK 0xF8695C + +#define mmTPC6_CFG_WQ_CREDITS 0xF86960 + +#define mmTPC6_CFG_ARUSER_LO 0xF86964 + +#define mmTPC6_CFG_ARUSER_HI 0xF86968 + +#define mmTPC6_CFG_AWUSER_LO 0xF8696C + +#define mmTPC6_CFG_AWUSER_HI 0xF86970 + +#define mmTPC6_CFG_OPCODE_EXEC 0xF86974 + +#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_LO 0xF86978 + +#define mmTPC6_CFG_LUT_FUNC32_BASE_ADDR_HI 0xF8697C + +#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_LO 0xF86980 + +#define mmTPC6_CFG_LUT_FUNC64_BASE_ADDR_HI 0xF86984 + +#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_LO 0xF86988 + +#define mmTPC6_CFG_LUT_FUNC128_BASE_ADDR_HI 0xF8698C + +#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_LO 0xF86990 + +#define mmTPC6_CFG_LUT_FUNC256_BASE_ADDR_HI 0xF86994 + +#define mmTPC6_CFG_TSB_CFG_MAX_SIZE 0xF86998 + +#define mmTPC6_CFG_TSB_CFG 0xF8699C + +#define mmTPC6_CFG_DBGMEM_ADD 0xF869A0 + +#define mmTPC6_CFG_DBGMEM_DATA_WR 0xF869A4 + +#define mmTPC6_CFG_DBGMEM_DATA_RD 0xF869A8 + +#define mmTPC6_CFG_DBGMEM_CTRL 0xF869AC + +#define mmTPC6_CFG_DBGMEM_RC 0xF869B0 + +#define mmTPC6_CFG_TSB_INFLIGHT_CNTR 0xF869B4 + +#define mmTPC6_CFG_WQ_INFLIGHT_CNTR 0xF869B8 + +#define mmTPC6_CFG_WQ_LBW_TOTAL_CNTR 0xF869BC + +#define mmTPC6_CFG_WQ_HBW_TOTAL_CNTR 0xF869C0 + +#define mmTPC6_CFG_IRQ_OCCOUPY_CNTR 0xF869C4 + +#define mmTPC6_CFG_FUNC_MBIST_CNTRL 0xF869D0 + +#define mmTPC6_CFG_FUNC_MBIST_PAT 0xF869D4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_0 0xF869D8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_1 0xF869DC + +#define mmTPC6_CFG_FUNC_MBIST_MEM_2 0xF869E0 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_3 0xF869E4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_4 0xF869E8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_5 0xF869EC + +#define mmTPC6_CFG_FUNC_MBIST_MEM_6 0xF869F0 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_7 0xF869F4 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_8 0xF869F8 + +#define mmTPC6_CFG_FUNC_MBIST_MEM_9 0xF869FC + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF86A00 + +#define mmTPC6_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF86A04 + +#define mmTPC6_CFG_QM_TENSOR_0_PADDING_VALUE 0xF86A08 + +#define mmTPC6_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF86A0C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF86A10 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF86A14 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF86A18 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF86A1C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF86A20 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF86A24 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF86A28 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF86A2C + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF86A30 + +#define mmTPC6_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF86A34 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF86A38 + +#define mmTPC6_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF86A3C + +#define mmTPC6_CFG_QM_TENSOR_1_PADDING_VALUE 0xF86A40 + +#define mmTPC6_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF86A44 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF86A48 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF86A4C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF86A50 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF86A54 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF86A58 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF86A5C + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF86A60 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF86A64 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF86A68 + +#define mmTPC6_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF86A6C + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF86A70 + +#define mmTPC6_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF86A74 + +#define mmTPC6_CFG_QM_TENSOR_2_PADDING_VALUE 0xF86A78 + +#define mmTPC6_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF86A7C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF86A80 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF86A84 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF86A88 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF86A8C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF86A90 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF86A94 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF86A98 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF86A9C + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF86AA0 + +#define mmTPC6_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF86AA4 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF86AA8 + +#define mmTPC6_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF86AAC + +#define mmTPC6_CFG_QM_TENSOR_3_PADDING_VALUE 0xF86AB0 + +#define mmTPC6_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF86AB4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF86AB8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF86ABC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF86AC0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF86AC4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF86AC8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF86ACC + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF86AD0 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF86AD4 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF86AD8 + +#define mmTPC6_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF86ADC + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF86AE0 + +#define mmTPC6_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF86AE4 + +#define mmTPC6_CFG_QM_TENSOR_4_PADDING_VALUE 0xF86AE8 + +#define mmTPC6_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF86AEC + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF86AF0 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF86AF4 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF86AF8 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF86AFC + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF86B00 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF86B04 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF86B08 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF86B0C + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF86B10 + +#define mmTPC6_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF86B14 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF86B18 + +#define mmTPC6_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF86B1C + +#define mmTPC6_CFG_QM_TENSOR_5_PADDING_VALUE 0xF86B20 + +#define mmTPC6_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF86B24 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF86B28 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF86B2C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF86B30 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF86B34 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF86B38 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF86B3C + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF86B40 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF86B44 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF86B48 + +#define mmTPC6_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF86B4C + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF86B50 + +#define mmTPC6_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF86B54 + +#define mmTPC6_CFG_QM_TENSOR_6_PADDING_VALUE 0xF86B58 + +#define mmTPC6_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF86B5C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF86B60 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF86B64 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF86B68 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF86B6C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF86B70 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF86B74 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF86B78 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF86B7C + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF86B80 + +#define mmTPC6_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF86B84 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF86B88 + +#define mmTPC6_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF86B8C + +#define mmTPC6_CFG_QM_TENSOR_7_PADDING_VALUE 0xF86B90 + +#define mmTPC6_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF86B94 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF86B98 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF86B9C + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF86BA0 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF86BA4 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF86BA8 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF86BAC + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF86BB0 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF86BB4 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF86BB8 + +#define mmTPC6_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF86BBC + +#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xF86BC0 + +#define mmTPC6_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xF86BC4 + +#define mmTPC6_CFG_QM_TENSOR_8_PADDING_VALUE 0xF86BC8 + +#define mmTPC6_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xF86BCC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_SIZE 0xF86BD0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xF86BD4 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_SIZE 0xF86BD8 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xF86BDC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_SIZE 0xF86BE0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xF86BE4 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_SIZE 0xF86BE8 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xF86BEC + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_SIZE 0xF86BF0 + +#define mmTPC6_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xF86BF4 + +#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xF86BF8 + +#define mmTPC6_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xF86BFC + +#define mmTPC6_CFG_QM_TENSOR_9_PADDING_VALUE 0xF86C00 + +#define mmTPC6_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xF86C04 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_SIZE 0xF86C08 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xF86C0C + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_SIZE 0xF86C10 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xF86C14 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_SIZE 0xF86C18 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xF86C1C + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_SIZE 0xF86C20 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xF86C24 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_SIZE 0xF86C28 + +#define mmTPC6_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xF86C2C + +#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xF86C30 + +#define mmTPC6_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xF86C34 + +#define mmTPC6_CFG_QM_TENSOR_10_PADDING_VALUE 0xF86C38 + +#define mmTPC6_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xF86C3C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_SIZE 0xF86C40 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xF86C44 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_SIZE 0xF86C48 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xF86C4C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_SIZE 0xF86C50 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xF86C54 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_SIZE 0xF86C58 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xF86C5C + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_SIZE 0xF86C60 + +#define mmTPC6_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xF86C64 + +#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xF86C68 + +#define mmTPC6_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xF86C6C + +#define mmTPC6_CFG_QM_TENSOR_11_PADDING_VALUE 0xF86C70 + +#define mmTPC6_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xF86C74 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_SIZE 0xF86C78 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xF86C7C + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_SIZE 0xF86C80 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xF86C84 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_SIZE 0xF86C88 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xF86C8C + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_SIZE 0xF86C90 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xF86C94 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_SIZE 0xF86C98 + +#define mmTPC6_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xF86C9C + +#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xF86CA0 + +#define mmTPC6_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xF86CA4 + +#define mmTPC6_CFG_QM_TENSOR_12_PADDING_VALUE 0xF86CA8 + +#define mmTPC6_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xF86CAC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_SIZE 0xF86CB0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xF86CB4 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_SIZE 0xF86CB8 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xF86CBC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_SIZE 0xF86CC0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xF86CC4 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_SIZE 0xF86CC8 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xF86CCC + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_SIZE 0xF86CD0 + +#define mmTPC6_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xF86CD4 + +#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xF86CD8 + +#define mmTPC6_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xF86CDC + +#define mmTPC6_CFG_QM_TENSOR_13_PADDING_VALUE 0xF86CE0 + +#define mmTPC6_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xF86CE4 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_SIZE 0xF86CE8 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xF86CEC + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_SIZE 0xF86CF0 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xF86CF4 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_SIZE 0xF86CF8 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xF86CFC + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_SIZE 0xF86D00 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xF86D04 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_SIZE 0xF86D08 + +#define mmTPC6_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xF86D0C + +#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xF86D10 + +#define mmTPC6_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xF86D14 + +#define mmTPC6_CFG_QM_TENSOR_14_PADDING_VALUE 0xF86D18 + +#define mmTPC6_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xF86D1C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_SIZE 0xF86D20 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xF86D24 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_SIZE 0xF86D28 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xF86D2C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_SIZE 0xF86D30 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xF86D34 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_SIZE 0xF86D38 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xF86D3C + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_SIZE 0xF86D40 + +#define mmTPC6_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xF86D44 + +#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xF86D48 + +#define mmTPC6_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xF86D4C + +#define mmTPC6_CFG_QM_TENSOR_15_PADDING_VALUE 0xF86D50 + +#define mmTPC6_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xF86D54 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_SIZE 0xF86D58 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xF86D5C + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_SIZE 0xF86D60 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xF86D64 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_SIZE 0xF86D68 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xF86D6C + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_SIZE 0xF86D70 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xF86D74 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_SIZE 0xF86D78 + +#define mmTPC6_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xF86D7C + +#define mmTPC6_CFG_QM_SYNC_OBJECT_MESSAGE 0xF86D80 + +#define mmTPC6_CFG_QM_SYNC_OBJECT_ADDR 0xF86D84 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF86D88 + +#define mmTPC6_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF86D8C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_0 0xF86D90 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_0 0xF86D94 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_1 0xF86D98 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_1 0xF86D9C + +#define mmTPC6_CFG_QM_TID_BASE_DIM_2 0xF86DA0 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_2 0xF86DA4 + +#define mmTPC6_CFG_QM_TID_BASE_DIM_3 0xF86DA8 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_3 0xF86DAC + +#define mmTPC6_CFG_QM_TID_BASE_DIM_4 0xF86DB0 + +#define mmTPC6_CFG_QM_TID_SIZE_DIM_4 0xF86DB4 + +#define mmTPC6_CFG_QM_KERNEL_CONFIG 0xF86DB8 + +#define mmTPC6_CFG_QM_KERNEL_ID 0xF86DBC + +#define mmTPC6_CFG_QM_SRF_0 0xF86DC0 + +#define mmTPC6_CFG_QM_SRF_1 0xF86DC4 + +#define mmTPC6_CFG_QM_SRF_2 0xF86DC8 + +#define mmTPC6_CFG_QM_SRF_3 0xF86DCC + +#define mmTPC6_CFG_QM_SRF_4 0xF86DD0 + +#define mmTPC6_CFG_QM_SRF_5 0xF86DD4 + +#define mmTPC6_CFG_QM_SRF_6 0xF86DD8 + +#define mmTPC6_CFG_QM_SRF_7 0xF86DDC + +#define mmTPC6_CFG_QM_SRF_8 0xF86DE0 + +#define mmTPC6_CFG_QM_SRF_9 0xF86DE4 + +#define mmTPC6_CFG_QM_SRF_10 0xF86DE8 + +#define mmTPC6_CFG_QM_SRF_11 0xF86DEC + +#define mmTPC6_CFG_QM_SRF_12 0xF86DF0 + +#define mmTPC6_CFG_QM_SRF_13 0xF86DF4 + +#define mmTPC6_CFG_QM_SRF_14 0xF86DF8 + +#define mmTPC6_CFG_QM_SRF_15 0xF86DFC + +#define mmTPC6_CFG_QM_SRF_16 0xF86E00 + +#define mmTPC6_CFG_QM_SRF_17 0xF86E04 + +#define mmTPC6_CFG_QM_SRF_18 0xF86E08 + +#define mmTPC6_CFG_QM_SRF_19 0xF86E0C + +#define mmTPC6_CFG_QM_SRF_20 0xF86E10 + +#define mmTPC6_CFG_QM_SRF_21 0xF86E14 + +#define mmTPC6_CFG_QM_SRF_22 0xF86E18 + +#define mmTPC6_CFG_QM_SRF_23 0xF86E1C + +#define mmTPC6_CFG_QM_SRF_24 0xF86E20 + +#define mmTPC6_CFG_QM_SRF_25 0xF86E24 + +#define mmTPC6_CFG_QM_SRF_26 0xF86E28 + +#define mmTPC6_CFG_QM_SRF_27 0xF86E2C + +#define mmTPC6_CFG_QM_SRF_28 0xF86E30 + +#define mmTPC6_CFG_QM_SRF_29 0xF86E34 + +#define mmTPC6_CFG_QM_SRF_30 0xF86E38 + +#define mmTPC6_CFG_QM_SRF_31 0xF86E3C + +#endif /* ASIC_REG_TPC6_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h new file mode 100644 index 000000000000..e35ef7fd8b1c --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc6_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC6_QM_REGS_H_ +#define ASIC_REG_TPC6_QM_REGS_H_ + +/* + ***************************************** + * TPC6_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC6_QM_GLBL_CFG0 0xF88000 + +#define mmTPC6_QM_GLBL_CFG1 0xF88004 + +#define mmTPC6_QM_GLBL_PROT 0xF88008 + +#define mmTPC6_QM_GLBL_ERR_CFG 0xF8800C + +#define mmTPC6_QM_GLBL_SECURE_PROPS_0 0xF88010 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_1 0xF88014 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_2 0xF88018 + +#define mmTPC6_QM_GLBL_SECURE_PROPS_3 0xF8801C + +#define mmTPC6_QM_GLBL_SECURE_PROPS_4 0xF88020 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_0 0xF88024 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_1 0xF88028 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_2 0xF8802C + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_3 0xF88030 + +#define mmTPC6_QM_GLBL_NON_SECURE_PROPS_4 0xF88034 + +#define mmTPC6_QM_GLBL_STS0 0xF88038 + +#define mmTPC6_QM_GLBL_STS1_0 0xF88040 + +#define mmTPC6_QM_GLBL_STS1_1 0xF88044 + +#define mmTPC6_QM_GLBL_STS1_2 0xF88048 + +#define mmTPC6_QM_GLBL_STS1_3 0xF8804C + +#define mmTPC6_QM_GLBL_STS1_4 0xF88050 + +#define mmTPC6_QM_GLBL_MSG_EN_0 0xF88054 + +#define mmTPC6_QM_GLBL_MSG_EN_1 0xF88058 + +#define mmTPC6_QM_GLBL_MSG_EN_2 0xF8805C + +#define mmTPC6_QM_GLBL_MSG_EN_3 0xF88060 + +#define mmTPC6_QM_GLBL_MSG_EN_4 0xF88068 + +#define mmTPC6_QM_PQ_BASE_LO_0 0xF88070 + +#define mmTPC6_QM_PQ_BASE_LO_1 0xF88074 + +#define mmTPC6_QM_PQ_BASE_LO_2 0xF88078 + +#define mmTPC6_QM_PQ_BASE_LO_3 0xF8807C + +#define mmTPC6_QM_PQ_BASE_HI_0 0xF88080 + +#define mmTPC6_QM_PQ_BASE_HI_1 0xF88084 + +#define mmTPC6_QM_PQ_BASE_HI_2 0xF88088 + +#define mmTPC6_QM_PQ_BASE_HI_3 0xF8808C + +#define mmTPC6_QM_PQ_SIZE_0 0xF88090 + +#define mmTPC6_QM_PQ_SIZE_1 0xF88094 + +#define mmTPC6_QM_PQ_SIZE_2 0xF88098 + +#define mmTPC6_QM_PQ_SIZE_3 0xF8809C + +#define mmTPC6_QM_PQ_PI_0 0xF880A0 + +#define mmTPC6_QM_PQ_PI_1 0xF880A4 + +#define mmTPC6_QM_PQ_PI_2 0xF880A8 + +#define mmTPC6_QM_PQ_PI_3 0xF880AC + +#define mmTPC6_QM_PQ_CI_0 0xF880B0 + +#define mmTPC6_QM_PQ_CI_1 0xF880B4 + +#define mmTPC6_QM_PQ_CI_2 0xF880B8 + +#define mmTPC6_QM_PQ_CI_3 0xF880BC + +#define mmTPC6_QM_PQ_CFG0_0 0xF880C0 + +#define mmTPC6_QM_PQ_CFG0_1 0xF880C4 + +#define mmTPC6_QM_PQ_CFG0_2 0xF880C8 + +#define mmTPC6_QM_PQ_CFG0_3 0xF880CC + +#define mmTPC6_QM_PQ_CFG1_0 0xF880D0 + +#define mmTPC6_QM_PQ_CFG1_1 0xF880D4 + +#define mmTPC6_QM_PQ_CFG1_2 0xF880D8 + +#define mmTPC6_QM_PQ_CFG1_3 0xF880DC + +#define mmTPC6_QM_PQ_ARUSER_31_11_0 0xF880E0 + +#define mmTPC6_QM_PQ_ARUSER_31_11_1 0xF880E4 + +#define mmTPC6_QM_PQ_ARUSER_31_11_2 0xF880E8 + +#define mmTPC6_QM_PQ_ARUSER_31_11_3 0xF880EC + +#define mmTPC6_QM_PQ_STS0_0 0xF880F0 + +#define mmTPC6_QM_PQ_STS0_1 0xF880F4 + +#define mmTPC6_QM_PQ_STS0_2 0xF880F8 + +#define mmTPC6_QM_PQ_STS0_3 0xF880FC + +#define mmTPC6_QM_PQ_STS1_0 0xF88100 + +#define mmTPC6_QM_PQ_STS1_1 0xF88104 + +#define mmTPC6_QM_PQ_STS1_2 0xF88108 + +#define mmTPC6_QM_PQ_STS1_3 0xF8810C + +#define mmTPC6_QM_CQ_CFG0_0 0xF88110 + +#define mmTPC6_QM_CQ_CFG0_1 0xF88114 + +#define mmTPC6_QM_CQ_CFG0_2 0xF88118 + +#define mmTPC6_QM_CQ_CFG0_3 0xF8811C + +#define mmTPC6_QM_CQ_CFG0_4 0xF88120 + +#define mmTPC6_QM_CQ_CFG1_0 0xF88124 + +#define mmTPC6_QM_CQ_CFG1_1 0xF88128 + +#define mmTPC6_QM_CQ_CFG1_2 0xF8812C + +#define mmTPC6_QM_CQ_CFG1_3 0xF88130 + +#define mmTPC6_QM_CQ_CFG1_4 0xF88134 + +#define mmTPC6_QM_CQ_ARUSER_31_11_0 0xF88138 + +#define mmTPC6_QM_CQ_ARUSER_31_11_1 0xF8813C + +#define mmTPC6_QM_CQ_ARUSER_31_11_2 0xF88140 + +#define mmTPC6_QM_CQ_ARUSER_31_11_3 0xF88144 + +#define mmTPC6_QM_CQ_ARUSER_31_11_4 0xF88148 + +#define mmTPC6_QM_CQ_STS0_0 0xF8814C + +#define mmTPC6_QM_CQ_STS0_1 0xF88150 + +#define mmTPC6_QM_CQ_STS0_2 0xF88154 + +#define mmTPC6_QM_CQ_STS0_3 0xF88158 + +#define mmTPC6_QM_CQ_STS0_4 0xF8815C + +#define mmTPC6_QM_CQ_STS1_0 0xF88160 + +#define mmTPC6_QM_CQ_STS1_1 0xF88164 + +#define mmTPC6_QM_CQ_STS1_2 0xF88168 + +#define mmTPC6_QM_CQ_STS1_3 0xF8816C + +#define mmTPC6_QM_CQ_STS1_4 0xF88170 + +#define mmTPC6_QM_CQ_PTR_LO_0 0xF88174 + +#define mmTPC6_QM_CQ_PTR_HI_0 0xF88178 + +#define mmTPC6_QM_CQ_TSIZE_0 0xF8817C + +#define mmTPC6_QM_CQ_CTL_0 0xF88180 + +#define mmTPC6_QM_CQ_PTR_LO_1 0xF88184 + +#define mmTPC6_QM_CQ_PTR_HI_1 0xF88188 + +#define mmTPC6_QM_CQ_TSIZE_1 0xF8818C + +#define mmTPC6_QM_CQ_CTL_1 0xF88190 + +#define mmTPC6_QM_CQ_PTR_LO_2 0xF88194 + +#define mmTPC6_QM_CQ_PTR_HI_2 0xF88198 + +#define mmTPC6_QM_CQ_TSIZE_2 0xF8819C + +#define mmTPC6_QM_CQ_CTL_2 0xF881A0 + +#define mmTPC6_QM_CQ_PTR_LO_3 0xF881A4 + +#define mmTPC6_QM_CQ_PTR_HI_3 0xF881A8 + +#define mmTPC6_QM_CQ_TSIZE_3 0xF881AC + +#define mmTPC6_QM_CQ_CTL_3 0xF881B0 + +#define mmTPC6_QM_CQ_PTR_LO_4 0xF881B4 + +#define mmTPC6_QM_CQ_PTR_HI_4 0xF881B8 + +#define mmTPC6_QM_CQ_TSIZE_4 0xF881BC + +#define mmTPC6_QM_CQ_CTL_4 0xF881C0 + +#define mmTPC6_QM_CQ_PTR_LO_STS_0 0xF881C4 + +#define mmTPC6_QM_CQ_PTR_LO_STS_1 0xF881C8 + +#define mmTPC6_QM_CQ_PTR_LO_STS_2 0xF881CC + +#define mmTPC6_QM_CQ_PTR_LO_STS_3 0xF881D0 + +#define mmTPC6_QM_CQ_PTR_LO_STS_4 0xF881D4 + +#define mmTPC6_QM_CQ_PTR_HI_STS_0 0xF881D8 + +#define mmTPC6_QM_CQ_PTR_HI_STS_1 0xF881DC + +#define mmTPC6_QM_CQ_PTR_HI_STS_2 0xF881E0 + +#define mmTPC6_QM_CQ_PTR_HI_STS_3 0xF881E4 + +#define mmTPC6_QM_CQ_PTR_HI_STS_4 0xF881E8 + +#define mmTPC6_QM_CQ_TSIZE_STS_0 0xF881EC + +#define mmTPC6_QM_CQ_TSIZE_STS_1 0xF881F0 + +#define mmTPC6_QM_CQ_TSIZE_STS_2 0xF881F4 + +#define mmTPC6_QM_CQ_TSIZE_STS_3 0xF881F8 + +#define mmTPC6_QM_CQ_TSIZE_STS_4 0xF881FC + +#define mmTPC6_QM_CQ_CTL_STS_0 0xF88200 + +#define mmTPC6_QM_CQ_CTL_STS_1 0xF88204 + +#define mmTPC6_QM_CQ_CTL_STS_2 0xF88208 + +#define mmTPC6_QM_CQ_CTL_STS_3 0xF8820C + +#define mmTPC6_QM_CQ_CTL_STS_4 0xF88210 + +#define mmTPC6_QM_CQ_IFIFO_CNT_0 0xF88214 + +#define mmTPC6_QM_CQ_IFIFO_CNT_1 0xF88218 + +#define mmTPC6_QM_CQ_IFIFO_CNT_2 0xF8821C + +#define mmTPC6_QM_CQ_IFIFO_CNT_3 0xF88220 + +#define mmTPC6_QM_CQ_IFIFO_CNT_4 0xF88224 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_0 0xF88228 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_1 0xF8822C + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_2 0xF88230 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_3 0xF88234 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_LO_4 0xF88238 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_0 0xF8823C + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_1 0xF88240 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_2 0xF88244 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_3 0xF88248 + +#define mmTPC6_QM_CP_MSG_BASE0_ADDR_HI_4 0xF8824C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_0 0xF88250 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_1 0xF88254 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_2 0xF88258 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_3 0xF8825C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_LO_4 0xF88260 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_0 0xF88264 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_1 0xF88268 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_2 0xF8826C + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_3 0xF88270 + +#define mmTPC6_QM_CP_MSG_BASE1_ADDR_HI_4 0xF88274 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_0 0xF88278 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_1 0xF8827C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_2 0xF88280 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_3 0xF88284 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_LO_4 0xF88288 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_0 0xF8828C + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_1 0xF88290 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_2 0xF88294 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_3 0xF88298 + +#define mmTPC6_QM_CP_MSG_BASE2_ADDR_HI_4 0xF8829C + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_0 0xF882A0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_1 0xF882A4 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_2 0xF882A8 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_3 0xF882AC + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_LO_4 0xF882B0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_0 0xF882B4 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_1 0xF882B8 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_2 0xF882BC + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_3 0xF882C0 + +#define mmTPC6_QM_CP_MSG_BASE3_ADDR_HI_4 0xF882C4 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_0 0xF882C8 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_1 0xF882CC + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_2 0xF882D0 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_3 0xF882D4 + +#define mmTPC6_QM_CP_LDMA_TSIZE_OFFSET_4 0xF882D8 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF882E0 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF882E4 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF882E8 + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF882EC + +#define mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF882F0 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF882F4 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF882F8 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF882FC + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF88300 + +#define mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF88304 + +#define mmTPC6_QM_CP_FENCE0_RDATA_0 0xF88308 + +#define mmTPC6_QM_CP_FENCE0_RDATA_1 0xF8830C + +#define mmTPC6_QM_CP_FENCE0_RDATA_2 0xF88310 + +#define mmTPC6_QM_CP_FENCE0_RDATA_3 0xF88314 + +#define mmTPC6_QM_CP_FENCE0_RDATA_4 0xF88318 + +#define mmTPC6_QM_CP_FENCE1_RDATA_0 0xF8831C + +#define mmTPC6_QM_CP_FENCE1_RDATA_1 0xF88320 + +#define mmTPC6_QM_CP_FENCE1_RDATA_2 0xF88324 + +#define mmTPC6_QM_CP_FENCE1_RDATA_3 0xF88328 + +#define mmTPC6_QM_CP_FENCE1_RDATA_4 0xF8832C + +#define mmTPC6_QM_CP_FENCE2_RDATA_0 0xF88330 + +#define mmTPC6_QM_CP_FENCE2_RDATA_1 0xF88334 + +#define mmTPC6_QM_CP_FENCE2_RDATA_2 0xF88338 + +#define mmTPC6_QM_CP_FENCE2_RDATA_3 0xF8833C + +#define mmTPC6_QM_CP_FENCE2_RDATA_4 0xF88340 + +#define mmTPC6_QM_CP_FENCE3_RDATA_0 0xF88344 + +#define mmTPC6_QM_CP_FENCE3_RDATA_1 0xF88348 + +#define mmTPC6_QM_CP_FENCE3_RDATA_2 0xF8834C + +#define mmTPC6_QM_CP_FENCE3_RDATA_3 0xF88350 + +#define mmTPC6_QM_CP_FENCE3_RDATA_4 0xF88354 + +#define mmTPC6_QM_CP_FENCE0_CNT_0 0xF88358 + +#define mmTPC6_QM_CP_FENCE0_CNT_1 0xF8835C + +#define mmTPC6_QM_CP_FENCE0_CNT_2 0xF88360 + +#define mmTPC6_QM_CP_FENCE0_CNT_3 0xF88364 + +#define mmTPC6_QM_CP_FENCE0_CNT_4 0xF88368 + +#define mmTPC6_QM_CP_FENCE1_CNT_0 0xF8836C + +#define mmTPC6_QM_CP_FENCE1_CNT_1 0xF88370 + +#define mmTPC6_QM_CP_FENCE1_CNT_2 0xF88374 + +#define mmTPC6_QM_CP_FENCE1_CNT_3 0xF88378 + +#define mmTPC6_QM_CP_FENCE1_CNT_4 0xF8837C + +#define mmTPC6_QM_CP_FENCE2_CNT_0 0xF88380 + +#define mmTPC6_QM_CP_FENCE2_CNT_1 0xF88384 + +#define mmTPC6_QM_CP_FENCE2_CNT_2 0xF88388 + +#define mmTPC6_QM_CP_FENCE2_CNT_3 0xF8838C + +#define mmTPC6_QM_CP_FENCE2_CNT_4 0xF88390 + +#define mmTPC6_QM_CP_FENCE3_CNT_0 0xF88394 + +#define mmTPC6_QM_CP_FENCE3_CNT_1 0xF88398 + +#define mmTPC6_QM_CP_FENCE3_CNT_2 0xF8839C + +#define mmTPC6_QM_CP_FENCE3_CNT_3 0xF883A0 + +#define mmTPC6_QM_CP_FENCE3_CNT_4 0xF883A4 + +#define mmTPC6_QM_CP_STS_0 0xF883A8 + +#define mmTPC6_QM_CP_STS_1 0xF883AC + +#define mmTPC6_QM_CP_STS_2 0xF883B0 + +#define mmTPC6_QM_CP_STS_3 0xF883B4 + +#define mmTPC6_QM_CP_STS_4 0xF883B8 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_0 0xF883BC + +#define mmTPC6_QM_CP_CURRENT_INST_LO_1 0xF883C0 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_2 0xF883C4 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_3 0xF883C8 + +#define mmTPC6_QM_CP_CURRENT_INST_LO_4 0xF883CC + +#define mmTPC6_QM_CP_CURRENT_INST_HI_0 0xF883D0 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_1 0xF883D4 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_2 0xF883D8 + +#define mmTPC6_QM_CP_CURRENT_INST_HI_3 0xF883DC + +#define mmTPC6_QM_CP_CURRENT_INST_HI_4 0xF883E0 + +#define mmTPC6_QM_CP_BARRIER_CFG_0 0xF883F4 + +#define mmTPC6_QM_CP_BARRIER_CFG_1 0xF883F8 + +#define mmTPC6_QM_CP_BARRIER_CFG_2 0xF883FC + +#define mmTPC6_QM_CP_BARRIER_CFG_3 0xF88400 + +#define mmTPC6_QM_CP_BARRIER_CFG_4 0xF88404 + +#define mmTPC6_QM_CP_DBG_0_0 0xF88408 + +#define mmTPC6_QM_CP_DBG_0_1 0xF8840C + +#define mmTPC6_QM_CP_DBG_0_2 0xF88410 + +#define mmTPC6_QM_CP_DBG_0_3 0xF88414 + +#define mmTPC6_QM_CP_DBG_0_4 0xF88418 + +#define mmTPC6_QM_CP_ARUSER_31_11_0 0xF8841C + +#define mmTPC6_QM_CP_ARUSER_31_11_1 0xF88420 + +#define mmTPC6_QM_CP_ARUSER_31_11_2 0xF88424 + +#define mmTPC6_QM_CP_ARUSER_31_11_3 0xF88428 + +#define mmTPC6_QM_CP_ARUSER_31_11_4 0xF8842C + +#define mmTPC6_QM_CP_AWUSER_31_11_0 0xF88430 + +#define mmTPC6_QM_CP_AWUSER_31_11_1 0xF88434 + +#define mmTPC6_QM_CP_AWUSER_31_11_2 0xF88438 + +#define mmTPC6_QM_CP_AWUSER_31_11_3 0xF8843C + +#define mmTPC6_QM_CP_AWUSER_31_11_4 0xF88440 + +#define mmTPC6_QM_ARB_CFG_0 0xF88A00 + +#define mmTPC6_QM_ARB_CHOISE_Q_PUSH 0xF88A04 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_0 0xF88A08 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_1 0xF88A0C + +#define mmTPC6_QM_ARB_WRR_WEIGHT_2 0xF88A10 + +#define mmTPC6_QM_ARB_WRR_WEIGHT_3 0xF88A14 + +#define mmTPC6_QM_ARB_CFG_1 0xF88A18 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_0 0xF88A20 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_1 0xF88A24 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_2 0xF88A28 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_3 0xF88A2C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_4 0xF88A30 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_5 0xF88A34 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_6 0xF88A38 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_7 0xF88A3C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_8 0xF88A40 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_9 0xF88A44 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_10 0xF88A48 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_11 0xF88A4C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_12 0xF88A50 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_13 0xF88A54 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_14 0xF88A58 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_15 0xF88A5C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_16 0xF88A60 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_17 0xF88A64 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_18 0xF88A68 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_19 0xF88A6C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_20 0xF88A70 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_21 0xF88A74 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_22 0xF88A78 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_23 0xF88A7C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_24 0xF88A80 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_25 0xF88A84 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_26 0xF88A88 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_27 0xF88A8C + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_28 0xF88A90 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_29 0xF88A94 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_30 0xF88A98 + +#define mmTPC6_QM_ARB_MST_AVAIL_CRED_31 0xF88A9C + +#define mmTPC6_QM_ARB_MST_CRED_INC 0xF88AA0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF88AA4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF88AA8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF88AAC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF88AB0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF88AB4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF88AB8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF88ABC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF88AC0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF88AC4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF88AC8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF88ACC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF88AD0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF88AD4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF88AD8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF88ADC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF88AE0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF88AE4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF88AE8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF88AEC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF88AF0 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF88AF4 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF88AF8 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF88AFC + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF88B00 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF88B04 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF88B08 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF88B0C + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF88B10 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF88B14 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF88B18 + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF88B1C + +#define mmTPC6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF88B20 + +#define mmTPC6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF88B28 + +#define mmTPC6_QM_ARB_MST_SLAVE_EN 0xF88B2C + +#define mmTPC6_QM_ARB_MST_QUIET_PER 0xF88B34 + +#define mmTPC6_QM_ARB_SLV_CHOISE_WDT 0xF88B38 + +#define mmTPC6_QM_ARB_SLV_ID 0xF88B3C + +#define mmTPC6_QM_ARB_MSG_MAX_INFLIGHT 0xF88B44 + +#define mmTPC6_QM_ARB_MSG_AWUSER_31_11 0xF88B48 + +#define mmTPC6_QM_ARB_MSG_AWUSER_SEC_PROP 0xF88B4C + +#define mmTPC6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF88B50 + +#define mmTPC6_QM_ARB_BASE_LO 0xF88B54 + +#define mmTPC6_QM_ARB_BASE_HI 0xF88B58 + +#define mmTPC6_QM_ARB_STATE_STS 0xF88B80 + +#define mmTPC6_QM_ARB_CHOISE_FULLNESS_STS 0xF88B84 + +#define mmTPC6_QM_ARB_MSG_STS 0xF88B88 + +#define mmTPC6_QM_ARB_SLV_CHOISE_Q_HEAD 0xF88B8C + +#define mmTPC6_QM_ARB_ERR_CAUSE 0xF88B9C + +#define mmTPC6_QM_ARB_ERR_MSG_EN 0xF88BA0 + +#define mmTPC6_QM_ARB_ERR_STS_DRP 0xF88BA8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_0 0xF88BB0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_1 0xF88BB4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_2 0xF88BB8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_3 0xF88BBC + +#define mmTPC6_QM_ARB_MST_CRED_STS_4 0xF88BC0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_5 0xF88BC4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_6 0xF88BC8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_7 0xF88BCC + +#define mmTPC6_QM_ARB_MST_CRED_STS_8 0xF88BD0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_9 0xF88BD4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_10 0xF88BD8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_11 0xF88BDC + +#define mmTPC6_QM_ARB_MST_CRED_STS_12 0xF88BE0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_13 0xF88BE4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_14 0xF88BE8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_15 0xF88BEC + +#define mmTPC6_QM_ARB_MST_CRED_STS_16 0xF88BF0 + +#define mmTPC6_QM_ARB_MST_CRED_STS_17 0xF88BF4 + +#define mmTPC6_QM_ARB_MST_CRED_STS_18 0xF88BF8 + +#define mmTPC6_QM_ARB_MST_CRED_STS_19 0xF88BFC + +#define mmTPC6_QM_ARB_MST_CRED_STS_20 0xF88C00 + +#define mmTPC6_QM_ARB_MST_CRED_STS_21 0xF88C04 + +#define mmTPC6_QM_ARB_MST_CRED_STS_22 0xF88C08 + +#define mmTPC6_QM_ARB_MST_CRED_STS_23 0xF88C0C + +#define mmTPC6_QM_ARB_MST_CRED_STS_24 0xF88C10 + +#define mmTPC6_QM_ARB_MST_CRED_STS_25 0xF88C14 + +#define mmTPC6_QM_ARB_MST_CRED_STS_26 0xF88C18 + +#define mmTPC6_QM_ARB_MST_CRED_STS_27 0xF88C1C + +#define mmTPC6_QM_ARB_MST_CRED_STS_28 0xF88C20 + +#define mmTPC6_QM_ARB_MST_CRED_STS_29 0xF88C24 + +#define mmTPC6_QM_ARB_MST_CRED_STS_30 0xF88C28 + +#define mmTPC6_QM_ARB_MST_CRED_STS_31 0xF88C2C + +#define mmTPC6_QM_CGM_CFG 0xF88C70 + +#define mmTPC6_QM_CGM_STS 0xF88C74 + +#define mmTPC6_QM_CGM_CFG1 0xF88C78 + +#define mmTPC6_QM_LOCAL_RANGE_BASE 0xF88C80 + +#define mmTPC6_QM_LOCAL_RANGE_SIZE 0xF88C84 + +#define mmTPC6_QM_CSMR_STRICT_PRIO_CFG 0xF88C90 + +#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_1 0xF88C94 + +#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_0 0xF88C98 + +#define mmTPC6_QM_LBW_WR_RATE_LIM_CFG_1 0xF88C9C + +#define mmTPC6_QM_HBW_RD_RATE_LIM_CFG_0 0xF88CA0 + +#define mmTPC6_QM_GLBL_AXCACHE 0xF88CA4 + +#define mmTPC6_QM_IND_GW_APB_CFG 0xF88CB0 + +#define mmTPC6_QM_IND_GW_APB_WDATA 0xF88CB4 + +#define mmTPC6_QM_IND_GW_APB_RDATA 0xF88CB8 + +#define mmTPC6_QM_IND_GW_APB_STATUS 0xF88CBC + +#define mmTPC6_QM_GLBL_ERR_ADDR_LO 0xF88CD0 + +#define mmTPC6_QM_GLBL_ERR_ADDR_HI 0xF88CD4 + +#define mmTPC6_QM_GLBL_ERR_WDATA 0xF88CD8 + +#define mmTPC6_QM_GLBL_MEM_INIT_BUSY 0xF88D00 + +#endif /* ASIC_REG_TPC6_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h new file mode 100644 index 000000000000..1887b10e58e2 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_cfg_regs.h @@ -0,0 +1,1226 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_CFG_REGS_H_ +#define ASIC_REG_TPC7_CFG_REGS_H_ + +/* + ***************************************** + * TPC7_CFG (Prototype: TPC) + ***************************************** + */ + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xFC6400 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xFC6404 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xFC6408 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xFC640C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xFC6410 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xFC6414 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xFC6418 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xFC641C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xFC6420 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xFC6424 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xFC6428 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xFC642C + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xFC6430 + +#define mmTPC7_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xFC6434 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xFC6438 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xFC643C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xFC6440 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xFC6444 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xFC6448 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xFC644C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xFC6450 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xFC6454 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xFC6458 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xFC645C + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xFC6460 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xFC6464 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xFC6468 + +#define mmTPC7_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xFC646C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xFC6470 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xFC6474 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xFC6478 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xFC647C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xFC6480 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xFC6484 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xFC6488 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xFC648C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xFC6490 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xFC6494 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xFC6498 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xFC649C + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xFC64A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xFC64A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xFC64A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xFC64AC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xFC64B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xFC64B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xFC64B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xFC64BC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xFC64C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xFC64C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xFC64C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xFC64CC + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xFC64D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xFC64D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xFC64D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xFC64DC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xFC64E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xFC64E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xFC64E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xFC64EC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xFC64F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xFC64F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xFC64F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xFC64FC + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xFC6500 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xFC6504 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xFC6508 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xFC650C + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xFC6510 + +#define mmTPC7_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xFC6514 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xFC6518 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xFC651C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xFC6520 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xFC6524 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xFC6528 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xFC652C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xFC6530 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xFC6534 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xFC6538 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xFC653C + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xFC6540 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xFC6544 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xFC6548 + +#define mmTPC7_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xFC654C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xFC6550 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xFC6554 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xFC6558 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xFC655C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xFC6560 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xFC6564 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xFC6568 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xFC656C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xFC6570 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xFC6574 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xFC6578 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xFC657C + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xFC6580 + +#define mmTPC7_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xFC6584 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xFC6588 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xFC658C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xFC6590 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xFC6594 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xFC6598 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xFC659C + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xFC65A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xFC65A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xFC65A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xFC65AC + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xFC65B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xFC65B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xFC65B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xFC65BC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xFC65C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xFC65C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xFC65C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xFC65CC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xFC65D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xFC65D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xFC65D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xFC65DC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xFC65E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xFC65E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xFC65E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xFC65EC + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xFC65F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xFC65F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xFC65F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xFC65FC + +#define mmTPC7_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xFC6600 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xFC6604 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xFC6608 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xFC660C + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xFC6610 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xFC6614 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xFC6618 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xFC661C + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xFC6620 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xFC6624 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xFC6628 + +#define mmTPC7_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xFC662C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xFC6630 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xFC6634 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xFC6638 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xFC663C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xFC6640 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xFC6644 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xFC6648 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xFC664C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xFC6650 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xFC6654 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xFC6658 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xFC665C + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xFC6660 + +#define mmTPC7_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xFC6664 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xFC6668 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xFC666C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xFC6670 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xFC6674 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xFC6678 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xFC667C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xFC6680 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xFC6684 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xFC6688 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xFC668C + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xFC6690 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xFC6694 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xFC6698 + +#define mmTPC7_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xFC669C + +#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xFC66A0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xFC66A4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xFC66A8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xFC66AC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xFC66B0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xFC66B4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xFC66B8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xFC66BC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xFC66C0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xFC66C4 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xFC66C8 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xFC66CC + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xFC66D0 + +#define mmTPC7_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xFC66D4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xFC66D8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xFC66DC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xFC66E0 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xFC66E4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xFC66E8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xFC66EC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xFC66F0 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xFC66F4 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xFC66F8 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xFC66FC + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xFC6700 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xFC6704 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xFC6708 + +#define mmTPC7_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xFC670C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xFC6710 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xFC6714 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xFC6718 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xFC671C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xFC6720 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xFC6724 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xFC6728 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xFC672C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xFC6730 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xFC6734 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xFC6738 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xFC673C + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xFC6740 + +#define mmTPC7_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xFC6744 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xFC6748 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xFC674C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xFC6750 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xFC6754 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xFC6758 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xFC675C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xFC6760 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xFC6764 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xFC6768 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xFC676C + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xFC6770 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xFC6774 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xFC6778 + +#define mmTPC7_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xFC677C + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xFC6780 + +#define mmTPC7_CFG_KERNEL_SYNC_OBJECT_ADDR 0xFC6784 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xFC6788 + +#define mmTPC7_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xFC678C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_0 0xFC6790 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_0 0xFC6794 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_1 0xFC6798 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_1 0xFC679C + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_2 0xFC67A0 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_2 0xFC67A4 + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_3 0xFC67A8 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_3 0xFC67AC + +#define mmTPC7_CFG_KERNEL_TID_BASE_DIM_4 0xFC67B0 + +#define mmTPC7_CFG_KERNEL_TID_SIZE_DIM_4 0xFC67B4 + +#define mmTPC7_CFG_KERNEL_KERNEL_CONFIG 0xFC67B8 + +#define mmTPC7_CFG_KERNEL_KERNEL_ID 0xFC67BC + +#define mmTPC7_CFG_KERNEL_SRF_0 0xFC67C0 + +#define mmTPC7_CFG_KERNEL_SRF_1 0xFC67C4 + +#define mmTPC7_CFG_KERNEL_SRF_2 0xFC67C8 + +#define mmTPC7_CFG_KERNEL_SRF_3 0xFC67CC + +#define mmTPC7_CFG_KERNEL_SRF_4 0xFC67D0 + +#define mmTPC7_CFG_KERNEL_SRF_5 0xFC67D4 + +#define mmTPC7_CFG_KERNEL_SRF_6 0xFC67D8 + +#define mmTPC7_CFG_KERNEL_SRF_7 0xFC67DC + +#define mmTPC7_CFG_KERNEL_SRF_8 0xFC67E0 + +#define mmTPC7_CFG_KERNEL_SRF_9 0xFC67E4 + +#define mmTPC7_CFG_KERNEL_SRF_10 0xFC67E8 + +#define mmTPC7_CFG_KERNEL_SRF_11 0xFC67EC + +#define mmTPC7_CFG_KERNEL_SRF_12 0xFC67F0 + +#define mmTPC7_CFG_KERNEL_SRF_13 0xFC67F4 + +#define mmTPC7_CFG_KERNEL_SRF_14 0xFC67F8 + +#define mmTPC7_CFG_KERNEL_SRF_15 0xFC67FC + +#define mmTPC7_CFG_KERNEL_SRF_16 0xFC6800 + +#define mmTPC7_CFG_KERNEL_SRF_17 0xFC6804 + +#define mmTPC7_CFG_KERNEL_SRF_18 0xFC6808 + +#define mmTPC7_CFG_KERNEL_SRF_19 0xFC680C + +#define mmTPC7_CFG_KERNEL_SRF_20 0xFC6810 + +#define mmTPC7_CFG_KERNEL_SRF_21 0xFC6814 + +#define mmTPC7_CFG_KERNEL_SRF_22 0xFC6818 + +#define mmTPC7_CFG_KERNEL_SRF_23 0xFC681C + +#define mmTPC7_CFG_KERNEL_SRF_24 0xFC6820 + +#define mmTPC7_CFG_KERNEL_SRF_25 0xFC6824 + +#define mmTPC7_CFG_KERNEL_SRF_26 0xFC6828 + +#define mmTPC7_CFG_KERNEL_SRF_27 0xFC682C + +#define mmTPC7_CFG_KERNEL_SRF_28 0xFC6830 + +#define mmTPC7_CFG_KERNEL_SRF_29 0xFC6834 + +#define mmTPC7_CFG_KERNEL_SRF_30 0xFC6838 + +#define mmTPC7_CFG_KERNEL_SRF_31 0xFC683C + +#define mmTPC7_CFG_ROUND_CSR 0xFC68FC + +#define mmTPC7_CFG_PROT 0xFC6900 + +#define mmTPC7_CFG_SEMAPHORE 0xFC6908 + +#define mmTPC7_CFG_VFLAGS 0xFC690C + +#define mmTPC7_CFG_SFLAGS 0xFC6910 + +#define mmTPC7_CFG_LFSR_POLYNOM 0xFC6918 + +#define mmTPC7_CFG_STATUS 0xFC691C + +#define mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH 0xFC6920 + +#define mmTPC7_CFG_CFG_SUBTRACT_VALUE 0xFC6924 + +#define mmTPC7_CFG_SM_BASE_ADDRESS_HIGH 0xFC692C + +#define mmTPC7_CFG_TPC_CMD 0xFC6930 + +#define mmTPC7_CFG_TPC_EXECUTE 0xFC6938 + +#define mmTPC7_CFG_TPC_STALL 0xFC693C + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_LOW 0xFC6940 + +#define mmTPC7_CFG_ICACHE_BASE_ADDERESS_HIGH 0xFC6944 + +#define mmTPC7_CFG_RD_RATE_LIMIT 0xFC6948 + +#define mmTPC7_CFG_WR_RATE_LIMIT 0xFC6950 + +#define mmTPC7_CFG_MSS_CONFIG 0xFC6954 + +#define mmTPC7_CFG_TPC_INTR_CAUSE 0xFC6958 + +#define mmTPC7_CFG_TPC_INTR_MASK 0xFC695C + +#define mmTPC7_CFG_WQ_CREDITS 0xFC6960 + +#define mmTPC7_CFG_ARUSER_LO 0xFC6964 + +#define mmTPC7_CFG_ARUSER_HI 0xFC6968 + +#define mmTPC7_CFG_AWUSER_LO 0xFC696C + +#define mmTPC7_CFG_AWUSER_HI 0xFC6970 + +#define mmTPC7_CFG_OPCODE_EXEC 0xFC6974 + +#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_LO 0xFC6978 + +#define mmTPC7_CFG_LUT_FUNC32_BASE_ADDR_HI 0xFC697C + +#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_LO 0xFC6980 + +#define mmTPC7_CFG_LUT_FUNC64_BASE_ADDR_HI 0xFC6984 + +#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_LO 0xFC6988 + +#define mmTPC7_CFG_LUT_FUNC128_BASE_ADDR_HI 0xFC698C + +#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_LO 0xFC6990 + +#define mmTPC7_CFG_LUT_FUNC256_BASE_ADDR_HI 0xFC6994 + +#define mmTPC7_CFG_TSB_CFG_MAX_SIZE 0xFC6998 + +#define mmTPC7_CFG_TSB_CFG 0xFC699C + +#define mmTPC7_CFG_DBGMEM_ADD 0xFC69A0 + +#define mmTPC7_CFG_DBGMEM_DATA_WR 0xFC69A4 + +#define mmTPC7_CFG_DBGMEM_DATA_RD 0xFC69A8 + +#define mmTPC7_CFG_DBGMEM_CTRL 0xFC69AC + +#define mmTPC7_CFG_DBGMEM_RC 0xFC69B0 + +#define mmTPC7_CFG_TSB_INFLIGHT_CNTR 0xFC69B4 + +#define mmTPC7_CFG_WQ_INFLIGHT_CNTR 0xFC69B8 + +#define mmTPC7_CFG_WQ_LBW_TOTAL_CNTR 0xFC69BC + +#define mmTPC7_CFG_WQ_HBW_TOTAL_CNTR 0xFC69C0 + +#define mmTPC7_CFG_IRQ_OCCOUPY_CNTR 0xFC69C4 + +#define mmTPC7_CFG_FUNC_MBIST_CNTRL 0xFC69D0 + +#define mmTPC7_CFG_FUNC_MBIST_PAT 0xFC69D4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_0 0xFC69D8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_1 0xFC69DC + +#define mmTPC7_CFG_FUNC_MBIST_MEM_2 0xFC69E0 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_3 0xFC69E4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_4 0xFC69E8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_5 0xFC69EC + +#define mmTPC7_CFG_FUNC_MBIST_MEM_6 0xFC69F0 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_7 0xFC69F4 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_8 0xFC69F8 + +#define mmTPC7_CFG_FUNC_MBIST_MEM_9 0xFC69FC + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xFC6A00 + +#define mmTPC7_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xFC6A04 + +#define mmTPC7_CFG_QM_TENSOR_0_PADDING_VALUE 0xFC6A08 + +#define mmTPC7_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xFC6A0C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_SIZE 0xFC6A10 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xFC6A14 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_SIZE 0xFC6A18 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xFC6A1C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_SIZE 0xFC6A20 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xFC6A24 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_SIZE 0xFC6A28 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xFC6A2C + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_SIZE 0xFC6A30 + +#define mmTPC7_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xFC6A34 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xFC6A38 + +#define mmTPC7_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xFC6A3C + +#define mmTPC7_CFG_QM_TENSOR_1_PADDING_VALUE 0xFC6A40 + +#define mmTPC7_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xFC6A44 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_SIZE 0xFC6A48 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xFC6A4C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_SIZE 0xFC6A50 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xFC6A54 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_SIZE 0xFC6A58 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xFC6A5C + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_SIZE 0xFC6A60 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xFC6A64 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_SIZE 0xFC6A68 + +#define mmTPC7_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xFC6A6C + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xFC6A70 + +#define mmTPC7_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xFC6A74 + +#define mmTPC7_CFG_QM_TENSOR_2_PADDING_VALUE 0xFC6A78 + +#define mmTPC7_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xFC6A7C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_SIZE 0xFC6A80 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xFC6A84 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_SIZE 0xFC6A88 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xFC6A8C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_SIZE 0xFC6A90 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xFC6A94 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_SIZE 0xFC6A98 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xFC6A9C + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_SIZE 0xFC6AA0 + +#define mmTPC7_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xFC6AA4 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xFC6AA8 + +#define mmTPC7_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xFC6AAC + +#define mmTPC7_CFG_QM_TENSOR_3_PADDING_VALUE 0xFC6AB0 + +#define mmTPC7_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xFC6AB4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_SIZE 0xFC6AB8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xFC6ABC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_SIZE 0xFC6AC0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xFC6AC4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_SIZE 0xFC6AC8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xFC6ACC + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_SIZE 0xFC6AD0 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xFC6AD4 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_SIZE 0xFC6AD8 + +#define mmTPC7_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xFC6ADC + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xFC6AE0 + +#define mmTPC7_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xFC6AE4 + +#define mmTPC7_CFG_QM_TENSOR_4_PADDING_VALUE 0xFC6AE8 + +#define mmTPC7_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xFC6AEC + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_SIZE 0xFC6AF0 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xFC6AF4 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_SIZE 0xFC6AF8 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xFC6AFC + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_SIZE 0xFC6B00 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xFC6B04 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_SIZE 0xFC6B08 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xFC6B0C + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_SIZE 0xFC6B10 + +#define mmTPC7_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xFC6B14 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xFC6B18 + +#define mmTPC7_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xFC6B1C + +#define mmTPC7_CFG_QM_TENSOR_5_PADDING_VALUE 0xFC6B20 + +#define mmTPC7_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xFC6B24 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_SIZE 0xFC6B28 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xFC6B2C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_SIZE 0xFC6B30 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xFC6B34 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_SIZE 0xFC6B38 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xFC6B3C + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_SIZE 0xFC6B40 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xFC6B44 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_SIZE 0xFC6B48 + +#define mmTPC7_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xFC6B4C + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xFC6B50 + +#define mmTPC7_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xFC6B54 + +#define mmTPC7_CFG_QM_TENSOR_6_PADDING_VALUE 0xFC6B58 + +#define mmTPC7_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xFC6B5C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_SIZE 0xFC6B60 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xFC6B64 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_SIZE 0xFC6B68 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xFC6B6C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_SIZE 0xFC6B70 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xFC6B74 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_SIZE 0xFC6B78 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xFC6B7C + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_SIZE 0xFC6B80 + +#define mmTPC7_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xFC6B84 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xFC6B88 + +#define mmTPC7_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xFC6B8C + +#define mmTPC7_CFG_QM_TENSOR_7_PADDING_VALUE 0xFC6B90 + +#define mmTPC7_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xFC6B94 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_SIZE 0xFC6B98 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xFC6B9C + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_SIZE 0xFC6BA0 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xFC6BA4 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_SIZE 0xFC6BA8 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xFC6BAC + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_SIZE 0xFC6BB0 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xFC6BB4 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_SIZE 0xFC6BB8 + +#define mmTPC7_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xFC6BBC + +#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xFC6BC0 + +#define mmTPC7_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xFC6BC4 + +#define mmTPC7_CFG_QM_TENSOR_8_PADDING_VALUE 0xFC6BC8 + +#define mmTPC7_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xFC6BCC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_SIZE 0xFC6BD0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xFC6BD4 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_SIZE 0xFC6BD8 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xFC6BDC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_SIZE 0xFC6BE0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xFC6BE4 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_SIZE 0xFC6BE8 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xFC6BEC + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_SIZE 0xFC6BF0 + +#define mmTPC7_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xFC6BF4 + +#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xFC6BF8 + +#define mmTPC7_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xFC6BFC + +#define mmTPC7_CFG_QM_TENSOR_9_PADDING_VALUE 0xFC6C00 + +#define mmTPC7_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xFC6C04 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_SIZE 0xFC6C08 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xFC6C0C + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_SIZE 0xFC6C10 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xFC6C14 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_SIZE 0xFC6C18 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xFC6C1C + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_SIZE 0xFC6C20 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xFC6C24 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_SIZE 0xFC6C28 + +#define mmTPC7_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xFC6C2C + +#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xFC6C30 + +#define mmTPC7_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xFC6C34 + +#define mmTPC7_CFG_QM_TENSOR_10_PADDING_VALUE 0xFC6C38 + +#define mmTPC7_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xFC6C3C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_SIZE 0xFC6C40 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xFC6C44 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_SIZE 0xFC6C48 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xFC6C4C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_SIZE 0xFC6C50 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xFC6C54 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_SIZE 0xFC6C58 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xFC6C5C + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_SIZE 0xFC6C60 + +#define mmTPC7_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xFC6C64 + +#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xFC6C68 + +#define mmTPC7_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xFC6C6C + +#define mmTPC7_CFG_QM_TENSOR_11_PADDING_VALUE 0xFC6C70 + +#define mmTPC7_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xFC6C74 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_SIZE 0xFC6C78 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xFC6C7C + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_SIZE 0xFC6C80 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xFC6C84 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_SIZE 0xFC6C88 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xFC6C8C + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_SIZE 0xFC6C90 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xFC6C94 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_SIZE 0xFC6C98 + +#define mmTPC7_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xFC6C9C + +#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xFC6CA0 + +#define mmTPC7_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xFC6CA4 + +#define mmTPC7_CFG_QM_TENSOR_12_PADDING_VALUE 0xFC6CA8 + +#define mmTPC7_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xFC6CAC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_SIZE 0xFC6CB0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xFC6CB4 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_SIZE 0xFC6CB8 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xFC6CBC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_SIZE 0xFC6CC0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xFC6CC4 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_SIZE 0xFC6CC8 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xFC6CCC + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_SIZE 0xFC6CD0 + +#define mmTPC7_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xFC6CD4 + +#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xFC6CD8 + +#define mmTPC7_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xFC6CDC + +#define mmTPC7_CFG_QM_TENSOR_13_PADDING_VALUE 0xFC6CE0 + +#define mmTPC7_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xFC6CE4 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_SIZE 0xFC6CE8 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xFC6CEC + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_SIZE 0xFC6CF0 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xFC6CF4 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_SIZE 0xFC6CF8 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xFC6CFC + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_SIZE 0xFC6D00 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xFC6D04 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_SIZE 0xFC6D08 + +#define mmTPC7_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xFC6D0C + +#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xFC6D10 + +#define mmTPC7_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xFC6D14 + +#define mmTPC7_CFG_QM_TENSOR_14_PADDING_VALUE 0xFC6D18 + +#define mmTPC7_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xFC6D1C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_SIZE 0xFC6D20 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xFC6D24 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_SIZE 0xFC6D28 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xFC6D2C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_SIZE 0xFC6D30 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xFC6D34 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_SIZE 0xFC6D38 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xFC6D3C + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_SIZE 0xFC6D40 + +#define mmTPC7_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xFC6D44 + +#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xFC6D48 + +#define mmTPC7_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xFC6D4C + +#define mmTPC7_CFG_QM_TENSOR_15_PADDING_VALUE 0xFC6D50 + +#define mmTPC7_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xFC6D54 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_SIZE 0xFC6D58 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xFC6D5C + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_SIZE 0xFC6D60 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xFC6D64 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_SIZE 0xFC6D68 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xFC6D6C + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_SIZE 0xFC6D70 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xFC6D74 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_SIZE 0xFC6D78 + +#define mmTPC7_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xFC6D7C + +#define mmTPC7_CFG_QM_SYNC_OBJECT_MESSAGE 0xFC6D80 + +#define mmTPC7_CFG_QM_SYNC_OBJECT_ADDR 0xFC6D84 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xFC6D88 + +#define mmTPC7_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xFC6D8C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_0 0xFC6D90 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_0 0xFC6D94 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_1 0xFC6D98 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_1 0xFC6D9C + +#define mmTPC7_CFG_QM_TID_BASE_DIM_2 0xFC6DA0 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_2 0xFC6DA4 + +#define mmTPC7_CFG_QM_TID_BASE_DIM_3 0xFC6DA8 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_3 0xFC6DAC + +#define mmTPC7_CFG_QM_TID_BASE_DIM_4 0xFC6DB0 + +#define mmTPC7_CFG_QM_TID_SIZE_DIM_4 0xFC6DB4 + +#define mmTPC7_CFG_QM_KERNEL_CONFIG 0xFC6DB8 + +#define mmTPC7_CFG_QM_KERNEL_ID 0xFC6DBC + +#define mmTPC7_CFG_QM_SRF_0 0xFC6DC0 + +#define mmTPC7_CFG_QM_SRF_1 0xFC6DC4 + +#define mmTPC7_CFG_QM_SRF_2 0xFC6DC8 + +#define mmTPC7_CFG_QM_SRF_3 0xFC6DCC + +#define mmTPC7_CFG_QM_SRF_4 0xFC6DD0 + +#define mmTPC7_CFG_QM_SRF_5 0xFC6DD4 + +#define mmTPC7_CFG_QM_SRF_6 0xFC6DD8 + +#define mmTPC7_CFG_QM_SRF_7 0xFC6DDC + +#define mmTPC7_CFG_QM_SRF_8 0xFC6DE0 + +#define mmTPC7_CFG_QM_SRF_9 0xFC6DE4 + +#define mmTPC7_CFG_QM_SRF_10 0xFC6DE8 + +#define mmTPC7_CFG_QM_SRF_11 0xFC6DEC + +#define mmTPC7_CFG_QM_SRF_12 0xFC6DF0 + +#define mmTPC7_CFG_QM_SRF_13 0xFC6DF4 + +#define mmTPC7_CFG_QM_SRF_14 0xFC6DF8 + +#define mmTPC7_CFG_QM_SRF_15 0xFC6DFC + +#define mmTPC7_CFG_QM_SRF_16 0xFC6E00 + +#define mmTPC7_CFG_QM_SRF_17 0xFC6E04 + +#define mmTPC7_CFG_QM_SRF_18 0xFC6E08 + +#define mmTPC7_CFG_QM_SRF_19 0xFC6E0C + +#define mmTPC7_CFG_QM_SRF_20 0xFC6E10 + +#define mmTPC7_CFG_QM_SRF_21 0xFC6E14 + +#define mmTPC7_CFG_QM_SRF_22 0xFC6E18 + +#define mmTPC7_CFG_QM_SRF_23 0xFC6E1C + +#define mmTPC7_CFG_QM_SRF_24 0xFC6E20 + +#define mmTPC7_CFG_QM_SRF_25 0xFC6E24 + +#define mmTPC7_CFG_QM_SRF_26 0xFC6E28 + +#define mmTPC7_CFG_QM_SRF_27 0xFC6E2C + +#define mmTPC7_CFG_QM_SRF_28 0xFC6E30 + +#define mmTPC7_CFG_QM_SRF_29 0xFC6E34 + +#define mmTPC7_CFG_QM_SRF_30 0xFC6E38 + +#define mmTPC7_CFG_QM_SRF_31 0xFC6E3C + +#endif /* ASIC_REG_TPC7_CFG_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h new file mode 100644 index 000000000000..5c36c972c027 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/asic_reg/tpc7_qm_regs.h @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_TPC7_QM_REGS_H_ +#define ASIC_REG_TPC7_QM_REGS_H_ + +/* + ***************************************** + * TPC7_QM (Prototype: QMAN) + ***************************************** + */ + +#define mmTPC7_QM_GLBL_CFG0 0xFC8000 + +#define mmTPC7_QM_GLBL_CFG1 0xFC8004 + +#define mmTPC7_QM_GLBL_PROT 0xFC8008 + +#define mmTPC7_QM_GLBL_ERR_CFG 0xFC800C + +#define mmTPC7_QM_GLBL_SECURE_PROPS_0 0xFC8010 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_1 0xFC8014 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_2 0xFC8018 + +#define mmTPC7_QM_GLBL_SECURE_PROPS_3 0xFC801C + +#define mmTPC7_QM_GLBL_SECURE_PROPS_4 0xFC8020 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_0 0xFC8024 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_1 0xFC8028 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_2 0xFC802C + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_3 0xFC8030 + +#define mmTPC7_QM_GLBL_NON_SECURE_PROPS_4 0xFC8034 + +#define mmTPC7_QM_GLBL_STS0 0xFC8038 + +#define mmTPC7_QM_GLBL_STS1_0 0xFC8040 + +#define mmTPC7_QM_GLBL_STS1_1 0xFC8044 + +#define mmTPC7_QM_GLBL_STS1_2 0xFC8048 + +#define mmTPC7_QM_GLBL_STS1_3 0xFC804C + +#define mmTPC7_QM_GLBL_STS1_4 0xFC8050 + +#define mmTPC7_QM_GLBL_MSG_EN_0 0xFC8054 + +#define mmTPC7_QM_GLBL_MSG_EN_1 0xFC8058 + +#define mmTPC7_QM_GLBL_MSG_EN_2 0xFC805C + +#define mmTPC7_QM_GLBL_MSG_EN_3 0xFC8060 + +#define mmTPC7_QM_GLBL_MSG_EN_4 0xFC8068 + +#define mmTPC7_QM_PQ_BASE_LO_0 0xFC8070 + +#define mmTPC7_QM_PQ_BASE_LO_1 0xFC8074 + +#define mmTPC7_QM_PQ_BASE_LO_2 0xFC8078 + +#define mmTPC7_QM_PQ_BASE_LO_3 0xFC807C + +#define mmTPC7_QM_PQ_BASE_HI_0 0xFC8080 + +#define mmTPC7_QM_PQ_BASE_HI_1 0xFC8084 + +#define mmTPC7_QM_PQ_BASE_HI_2 0xFC8088 + +#define mmTPC7_QM_PQ_BASE_HI_3 0xFC808C + +#define mmTPC7_QM_PQ_SIZE_0 0xFC8090 + +#define mmTPC7_QM_PQ_SIZE_1 0xFC8094 + +#define mmTPC7_QM_PQ_SIZE_2 0xFC8098 + +#define mmTPC7_QM_PQ_SIZE_3 0xFC809C + +#define mmTPC7_QM_PQ_PI_0 0xFC80A0 + +#define mmTPC7_QM_PQ_PI_1 0xFC80A4 + +#define mmTPC7_QM_PQ_PI_2 0xFC80A8 + +#define mmTPC7_QM_PQ_PI_3 0xFC80AC + +#define mmTPC7_QM_PQ_CI_0 0xFC80B0 + +#define mmTPC7_QM_PQ_CI_1 0xFC80B4 + +#define mmTPC7_QM_PQ_CI_2 0xFC80B8 + +#define mmTPC7_QM_PQ_CI_3 0xFC80BC + +#define mmTPC7_QM_PQ_CFG0_0 0xFC80C0 + +#define mmTPC7_QM_PQ_CFG0_1 0xFC80C4 + +#define mmTPC7_QM_PQ_CFG0_2 0xFC80C8 + +#define mmTPC7_QM_PQ_CFG0_3 0xFC80CC + +#define mmTPC7_QM_PQ_CFG1_0 0xFC80D0 + +#define mmTPC7_QM_PQ_CFG1_1 0xFC80D4 + +#define mmTPC7_QM_PQ_CFG1_2 0xFC80D8 + +#define mmTPC7_QM_PQ_CFG1_3 0xFC80DC + +#define mmTPC7_QM_PQ_ARUSER_31_11_0 0xFC80E0 + +#define mmTPC7_QM_PQ_ARUSER_31_11_1 0xFC80E4 + +#define mmTPC7_QM_PQ_ARUSER_31_11_2 0xFC80E8 + +#define mmTPC7_QM_PQ_ARUSER_31_11_3 0xFC80EC + +#define mmTPC7_QM_PQ_STS0_0 0xFC80F0 + +#define mmTPC7_QM_PQ_STS0_1 0xFC80F4 + +#define mmTPC7_QM_PQ_STS0_2 0xFC80F8 + +#define mmTPC7_QM_PQ_STS0_3 0xFC80FC + +#define mmTPC7_QM_PQ_STS1_0 0xFC8100 + +#define mmTPC7_QM_PQ_STS1_1 0xFC8104 + +#define mmTPC7_QM_PQ_STS1_2 0xFC8108 + +#define mmTPC7_QM_PQ_STS1_3 0xFC810C + +#define mmTPC7_QM_CQ_CFG0_0 0xFC8110 + +#define mmTPC7_QM_CQ_CFG0_1 0xFC8114 + +#define mmTPC7_QM_CQ_CFG0_2 0xFC8118 + +#define mmTPC7_QM_CQ_CFG0_3 0xFC811C + +#define mmTPC7_QM_CQ_CFG0_4 0xFC8120 + +#define mmTPC7_QM_CQ_CFG1_0 0xFC8124 + +#define mmTPC7_QM_CQ_CFG1_1 0xFC8128 + +#define mmTPC7_QM_CQ_CFG1_2 0xFC812C + +#define mmTPC7_QM_CQ_CFG1_3 0xFC8130 + +#define mmTPC7_QM_CQ_CFG1_4 0xFC8134 + +#define mmTPC7_QM_CQ_ARUSER_31_11_0 0xFC8138 + +#define mmTPC7_QM_CQ_ARUSER_31_11_1 0xFC813C + +#define mmTPC7_QM_CQ_ARUSER_31_11_2 0xFC8140 + +#define mmTPC7_QM_CQ_ARUSER_31_11_3 0xFC8144 + +#define mmTPC7_QM_CQ_ARUSER_31_11_4 0xFC8148 + +#define mmTPC7_QM_CQ_STS0_0 0xFC814C + +#define mmTPC7_QM_CQ_STS0_1 0xFC8150 + +#define mmTPC7_QM_CQ_STS0_2 0xFC8154 + +#define mmTPC7_QM_CQ_STS0_3 0xFC8158 + +#define mmTPC7_QM_CQ_STS0_4 0xFC815C + +#define mmTPC7_QM_CQ_STS1_0 0xFC8160 + +#define mmTPC7_QM_CQ_STS1_1 0xFC8164 + +#define mmTPC7_QM_CQ_STS1_2 0xFC8168 + +#define mmTPC7_QM_CQ_STS1_3 0xFC816C + +#define mmTPC7_QM_CQ_STS1_4 0xFC8170 + +#define mmTPC7_QM_CQ_PTR_LO_0 0xFC8174 + +#define mmTPC7_QM_CQ_PTR_HI_0 0xFC8178 + +#define mmTPC7_QM_CQ_TSIZE_0 0xFC817C + +#define mmTPC7_QM_CQ_CTL_0 0xFC8180 + +#define mmTPC7_QM_CQ_PTR_LO_1 0xFC8184 + +#define mmTPC7_QM_CQ_PTR_HI_1 0xFC8188 + +#define mmTPC7_QM_CQ_TSIZE_1 0xFC818C + +#define mmTPC7_QM_CQ_CTL_1 0xFC8190 + +#define mmTPC7_QM_CQ_PTR_LO_2 0xFC8194 + +#define mmTPC7_QM_CQ_PTR_HI_2 0xFC8198 + +#define mmTPC7_QM_CQ_TSIZE_2 0xFC819C + +#define mmTPC7_QM_CQ_CTL_2 0xFC81A0 + +#define mmTPC7_QM_CQ_PTR_LO_3 0xFC81A4 + +#define mmTPC7_QM_CQ_PTR_HI_3 0xFC81A8 + +#define mmTPC7_QM_CQ_TSIZE_3 0xFC81AC + +#define mmTPC7_QM_CQ_CTL_3 0xFC81B0 + +#define mmTPC7_QM_CQ_PTR_LO_4 0xFC81B4 + +#define mmTPC7_QM_CQ_PTR_HI_4 0xFC81B8 + +#define mmTPC7_QM_CQ_TSIZE_4 0xFC81BC + +#define mmTPC7_QM_CQ_CTL_4 0xFC81C0 + +#define mmTPC7_QM_CQ_PTR_LO_STS_0 0xFC81C4 + +#define mmTPC7_QM_CQ_PTR_LO_STS_1 0xFC81C8 + +#define mmTPC7_QM_CQ_PTR_LO_STS_2 0xFC81CC + +#define mmTPC7_QM_CQ_PTR_LO_STS_3 0xFC81D0 + +#define mmTPC7_QM_CQ_PTR_LO_STS_4 0xFC81D4 + +#define mmTPC7_QM_CQ_PTR_HI_STS_0 0xFC81D8 + +#define mmTPC7_QM_CQ_PTR_HI_STS_1 0xFC81DC + +#define mmTPC7_QM_CQ_PTR_HI_STS_2 0xFC81E0 + +#define mmTPC7_QM_CQ_PTR_HI_STS_3 0xFC81E4 + +#define mmTPC7_QM_CQ_PTR_HI_STS_4 0xFC81E8 + +#define mmTPC7_QM_CQ_TSIZE_STS_0 0xFC81EC + +#define mmTPC7_QM_CQ_TSIZE_STS_1 0xFC81F0 + +#define mmTPC7_QM_CQ_TSIZE_STS_2 0xFC81F4 + +#define mmTPC7_QM_CQ_TSIZE_STS_3 0xFC81F8 + +#define mmTPC7_QM_CQ_TSIZE_STS_4 0xFC81FC + +#define mmTPC7_QM_CQ_CTL_STS_0 0xFC8200 + +#define mmTPC7_QM_CQ_CTL_STS_1 0xFC8204 + +#define mmTPC7_QM_CQ_CTL_STS_2 0xFC8208 + +#define mmTPC7_QM_CQ_CTL_STS_3 0xFC820C + +#define mmTPC7_QM_CQ_CTL_STS_4 0xFC8210 + +#define mmTPC7_QM_CQ_IFIFO_CNT_0 0xFC8214 + +#define mmTPC7_QM_CQ_IFIFO_CNT_1 0xFC8218 + +#define mmTPC7_QM_CQ_IFIFO_CNT_2 0xFC821C + +#define mmTPC7_QM_CQ_IFIFO_CNT_3 0xFC8220 + +#define mmTPC7_QM_CQ_IFIFO_CNT_4 0xFC8224 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_0 0xFC8228 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_1 0xFC822C + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_2 0xFC8230 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_3 0xFC8234 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_LO_4 0xFC8238 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_0 0xFC823C + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_1 0xFC8240 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_2 0xFC8244 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_3 0xFC8248 + +#define mmTPC7_QM_CP_MSG_BASE0_ADDR_HI_4 0xFC824C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_0 0xFC8250 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_1 0xFC8254 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_2 0xFC8258 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_3 0xFC825C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_LO_4 0xFC8260 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_0 0xFC8264 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_1 0xFC8268 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_2 0xFC826C + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_3 0xFC8270 + +#define mmTPC7_QM_CP_MSG_BASE1_ADDR_HI_4 0xFC8274 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_0 0xFC8278 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_1 0xFC827C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_2 0xFC8280 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_3 0xFC8284 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_LO_4 0xFC8288 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_0 0xFC828C + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_1 0xFC8290 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_2 0xFC8294 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_3 0xFC8298 + +#define mmTPC7_QM_CP_MSG_BASE2_ADDR_HI_4 0xFC829C + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_0 0xFC82A0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_1 0xFC82A4 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_2 0xFC82A8 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_3 0xFC82AC + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_LO_4 0xFC82B0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_0 0xFC82B4 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_1 0xFC82B8 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_2 0xFC82BC + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_3 0xFC82C0 + +#define mmTPC7_QM_CP_MSG_BASE3_ADDR_HI_4 0xFC82C4 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_0 0xFC82C8 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_1 0xFC82CC + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_2 0xFC82D0 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_3 0xFC82D4 + +#define mmTPC7_QM_CP_LDMA_TSIZE_OFFSET_4 0xFC82D8 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xFC82E0 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xFC82E4 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xFC82E8 + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xFC82EC + +#define mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xFC82F0 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xFC82F4 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xFC82F8 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xFC82FC + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xFC8300 + +#define mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xFC8304 + +#define mmTPC7_QM_CP_FENCE0_RDATA_0 0xFC8308 + +#define mmTPC7_QM_CP_FENCE0_RDATA_1 0xFC830C + +#define mmTPC7_QM_CP_FENCE0_RDATA_2 0xFC8310 + +#define mmTPC7_QM_CP_FENCE0_RDATA_3 0xFC8314 + +#define mmTPC7_QM_CP_FENCE0_RDATA_4 0xFC8318 + +#define mmTPC7_QM_CP_FENCE1_RDATA_0 0xFC831C + +#define mmTPC7_QM_CP_FENCE1_RDATA_1 0xFC8320 + +#define mmTPC7_QM_CP_FENCE1_RDATA_2 0xFC8324 + +#define mmTPC7_QM_CP_FENCE1_RDATA_3 0xFC8328 + +#define mmTPC7_QM_CP_FENCE1_RDATA_4 0xFC832C + +#define mmTPC7_QM_CP_FENCE2_RDATA_0 0xFC8330 + +#define mmTPC7_QM_CP_FENCE2_RDATA_1 0xFC8334 + +#define mmTPC7_QM_CP_FENCE2_RDATA_2 0xFC8338 + +#define mmTPC7_QM_CP_FENCE2_RDATA_3 0xFC833C + +#define mmTPC7_QM_CP_FENCE2_RDATA_4 0xFC8340 + +#define mmTPC7_QM_CP_FENCE3_RDATA_0 0xFC8344 + +#define mmTPC7_QM_CP_FENCE3_RDATA_1 0xFC8348 + +#define mmTPC7_QM_CP_FENCE3_RDATA_2 0xFC834C + +#define mmTPC7_QM_CP_FENCE3_RDATA_3 0xFC8350 + +#define mmTPC7_QM_CP_FENCE3_RDATA_4 0xFC8354 + +#define mmTPC7_QM_CP_FENCE0_CNT_0 0xFC8358 + +#define mmTPC7_QM_CP_FENCE0_CNT_1 0xFC835C + +#define mmTPC7_QM_CP_FENCE0_CNT_2 0xFC8360 + +#define mmTPC7_QM_CP_FENCE0_CNT_3 0xFC8364 + +#define mmTPC7_QM_CP_FENCE0_CNT_4 0xFC8368 + +#define mmTPC7_QM_CP_FENCE1_CNT_0 0xFC836C + +#define mmTPC7_QM_CP_FENCE1_CNT_1 0xFC8370 + +#define mmTPC7_QM_CP_FENCE1_CNT_2 0xFC8374 + +#define mmTPC7_QM_CP_FENCE1_CNT_3 0xFC8378 + +#define mmTPC7_QM_CP_FENCE1_CNT_4 0xFC837C + +#define mmTPC7_QM_CP_FENCE2_CNT_0 0xFC8380 + +#define mmTPC7_QM_CP_FENCE2_CNT_1 0xFC8384 + +#define mmTPC7_QM_CP_FENCE2_CNT_2 0xFC8388 + +#define mmTPC7_QM_CP_FENCE2_CNT_3 0xFC838C + +#define mmTPC7_QM_CP_FENCE2_CNT_4 0xFC8390 + +#define mmTPC7_QM_CP_FENCE3_CNT_0 0xFC8394 + +#define mmTPC7_QM_CP_FENCE3_CNT_1 0xFC8398 + +#define mmTPC7_QM_CP_FENCE3_CNT_2 0xFC839C + +#define mmTPC7_QM_CP_FENCE3_CNT_3 0xFC83A0 + +#define mmTPC7_QM_CP_FENCE3_CNT_4 0xFC83A4 + +#define mmTPC7_QM_CP_STS_0 0xFC83A8 + +#define mmTPC7_QM_CP_STS_1 0xFC83AC + +#define mmTPC7_QM_CP_STS_2 0xFC83B0 + +#define mmTPC7_QM_CP_STS_3 0xFC83B4 + +#define mmTPC7_QM_CP_STS_4 0xFC83B8 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_0 0xFC83BC + +#define mmTPC7_QM_CP_CURRENT_INST_LO_1 0xFC83C0 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_2 0xFC83C4 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_3 0xFC83C8 + +#define mmTPC7_QM_CP_CURRENT_INST_LO_4 0xFC83CC + +#define mmTPC7_QM_CP_CURRENT_INST_HI_0 0xFC83D0 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_1 0xFC83D4 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_2 0xFC83D8 + +#define mmTPC7_QM_CP_CURRENT_INST_HI_3 0xFC83DC + +#define mmTPC7_QM_CP_CURRENT_INST_HI_4 0xFC83E0 + +#define mmTPC7_QM_CP_BARRIER_CFG_0 0xFC83F4 + +#define mmTPC7_QM_CP_BARRIER_CFG_1 0xFC83F8 + +#define mmTPC7_QM_CP_BARRIER_CFG_2 0xFC83FC + +#define mmTPC7_QM_CP_BARRIER_CFG_3 0xFC8400 + +#define mmTPC7_QM_CP_BARRIER_CFG_4 0xFC8404 + +#define mmTPC7_QM_CP_DBG_0_0 0xFC8408 + +#define mmTPC7_QM_CP_DBG_0_1 0xFC840C + +#define mmTPC7_QM_CP_DBG_0_2 0xFC8410 + +#define mmTPC7_QM_CP_DBG_0_3 0xFC8414 + +#define mmTPC7_QM_CP_DBG_0_4 0xFC8418 + +#define mmTPC7_QM_CP_ARUSER_31_11_0 0xFC841C + +#define mmTPC7_QM_CP_ARUSER_31_11_1 0xFC8420 + +#define mmTPC7_QM_CP_ARUSER_31_11_2 0xFC8424 + +#define mmTPC7_QM_CP_ARUSER_31_11_3 0xFC8428 + +#define mmTPC7_QM_CP_ARUSER_31_11_4 0xFC842C + +#define mmTPC7_QM_CP_AWUSER_31_11_0 0xFC8430 + +#define mmTPC7_QM_CP_AWUSER_31_11_1 0xFC8434 + +#define mmTPC7_QM_CP_AWUSER_31_11_2 0xFC8438 + +#define mmTPC7_QM_CP_AWUSER_31_11_3 0xFC843C + +#define mmTPC7_QM_CP_AWUSER_31_11_4 0xFC8440 + +#define mmTPC7_QM_ARB_CFG_0 0xFC8A00 + +#define mmTPC7_QM_ARB_CHOISE_Q_PUSH 0xFC8A04 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_0 0xFC8A08 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_1 0xFC8A0C + +#define mmTPC7_QM_ARB_WRR_WEIGHT_2 0xFC8A10 + +#define mmTPC7_QM_ARB_WRR_WEIGHT_3 0xFC8A14 + +#define mmTPC7_QM_ARB_CFG_1 0xFC8A18 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_0 0xFC8A20 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_1 0xFC8A24 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_2 0xFC8A28 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_3 0xFC8A2C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_4 0xFC8A30 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_5 0xFC8A34 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_6 0xFC8A38 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_7 0xFC8A3C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_8 0xFC8A40 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_9 0xFC8A44 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_10 0xFC8A48 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_11 0xFC8A4C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_12 0xFC8A50 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_13 0xFC8A54 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_14 0xFC8A58 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_15 0xFC8A5C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_16 0xFC8A60 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_17 0xFC8A64 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_18 0xFC8A68 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_19 0xFC8A6C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_20 0xFC8A70 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_21 0xFC8A74 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_22 0xFC8A78 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_23 0xFC8A7C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_24 0xFC8A80 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_25 0xFC8A84 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_26 0xFC8A88 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_27 0xFC8A8C + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_28 0xFC8A90 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_29 0xFC8A94 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_30 0xFC8A98 + +#define mmTPC7_QM_ARB_MST_AVAIL_CRED_31 0xFC8A9C + +#define mmTPC7_QM_ARB_MST_CRED_INC 0xFC8AA0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xFC8AA4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xFC8AA8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xFC8AAC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xFC8AB0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xFC8AB4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xFC8AB8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xFC8ABC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xFC8AC0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xFC8AC4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xFC8AC8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xFC8ACC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xFC8AD0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xFC8AD4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xFC8AD8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xFC8ADC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xFC8AE0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xFC8AE4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xFC8AE8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xFC8AEC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xFC8AF0 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xFC8AF4 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xFC8AF8 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xFC8AFC + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xFC8B00 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xFC8B04 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xFC8B08 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xFC8B0C + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xFC8B10 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xFC8B14 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xFC8B18 + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xFC8B1C + +#define mmTPC7_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xFC8B20 + +#define mmTPC7_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xFC8B28 + +#define mmTPC7_QM_ARB_MST_SLAVE_EN 0xFC8B2C + +#define mmTPC7_QM_ARB_MST_QUIET_PER 0xFC8B34 + +#define mmTPC7_QM_ARB_SLV_CHOISE_WDT 0xFC8B38 + +#define mmTPC7_QM_ARB_SLV_ID 0xFC8B3C + +#define mmTPC7_QM_ARB_MSG_MAX_INFLIGHT 0xFC8B44 + +#define mmTPC7_QM_ARB_MSG_AWUSER_31_11 0xFC8B48 + +#define mmTPC7_QM_ARB_MSG_AWUSER_SEC_PROP 0xFC8B4C + +#define mmTPC7_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xFC8B50 + +#define mmTPC7_QM_ARB_BASE_LO 0xFC8B54 + +#define mmTPC7_QM_ARB_BASE_HI 0xFC8B58 + +#define mmTPC7_QM_ARB_STATE_STS 0xFC8B80 + +#define mmTPC7_QM_ARB_CHOISE_FULLNESS_STS 0xFC8B84 + +#define mmTPC7_QM_ARB_MSG_STS 0xFC8B88 + +#define mmTPC7_QM_ARB_SLV_CHOISE_Q_HEAD 0xFC8B8C + +#define mmTPC7_QM_ARB_ERR_CAUSE 0xFC8B9C + +#define mmTPC7_QM_ARB_ERR_MSG_EN 0xFC8BA0 + +#define mmTPC7_QM_ARB_ERR_STS_DRP 0xFC8BA8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_0 0xFC8BB0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_1 0xFC8BB4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_2 0xFC8BB8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_3 0xFC8BBC + +#define mmTPC7_QM_ARB_MST_CRED_STS_4 0xFC8BC0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_5 0xFC8BC4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_6 0xFC8BC8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_7 0xFC8BCC + +#define mmTPC7_QM_ARB_MST_CRED_STS_8 0xFC8BD0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_9 0xFC8BD4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_10 0xFC8BD8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_11 0xFC8BDC + +#define mmTPC7_QM_ARB_MST_CRED_STS_12 0xFC8BE0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_13 0xFC8BE4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_14 0xFC8BE8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_15 0xFC8BEC + +#define mmTPC7_QM_ARB_MST_CRED_STS_16 0xFC8BF0 + +#define mmTPC7_QM_ARB_MST_CRED_STS_17 0xFC8BF4 + +#define mmTPC7_QM_ARB_MST_CRED_STS_18 0xFC8BF8 + +#define mmTPC7_QM_ARB_MST_CRED_STS_19 0xFC8BFC + +#define mmTPC7_QM_ARB_MST_CRED_STS_20 0xFC8C00 + +#define mmTPC7_QM_ARB_MST_CRED_STS_21 0xFC8C04 + +#define mmTPC7_QM_ARB_MST_CRED_STS_22 0xFC8C08 + +#define mmTPC7_QM_ARB_MST_CRED_STS_23 0xFC8C0C + +#define mmTPC7_QM_ARB_MST_CRED_STS_24 0xFC8C10 + +#define mmTPC7_QM_ARB_MST_CRED_STS_25 0xFC8C14 + +#define mmTPC7_QM_ARB_MST_CRED_STS_26 0xFC8C18 + +#define mmTPC7_QM_ARB_MST_CRED_STS_27 0xFC8C1C + +#define mmTPC7_QM_ARB_MST_CRED_STS_28 0xFC8C20 + +#define mmTPC7_QM_ARB_MST_CRED_STS_29 0xFC8C24 + +#define mmTPC7_QM_ARB_MST_CRED_STS_30 0xFC8C28 + +#define mmTPC7_QM_ARB_MST_CRED_STS_31 0xFC8C2C + +#define mmTPC7_QM_CGM_CFG 0xFC8C70 + +#define mmTPC7_QM_CGM_STS 0xFC8C74 + +#define mmTPC7_QM_CGM_CFG1 0xFC8C78 + +#define mmTPC7_QM_LOCAL_RANGE_BASE 0xFC8C80 + +#define mmTPC7_QM_LOCAL_RANGE_SIZE 0xFC8C84 + +#define mmTPC7_QM_CSMR_STRICT_PRIO_CFG 0xFC8C90 + +#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_1 0xFC8C94 + +#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_0 0xFC8C98 + +#define mmTPC7_QM_LBW_WR_RATE_LIM_CFG_1 0xFC8C9C + +#define mmTPC7_QM_HBW_RD_RATE_LIM_CFG_0 0xFC8CA0 + +#define mmTPC7_QM_GLBL_AXCACHE 0xFC8CA4 + +#define mmTPC7_QM_IND_GW_APB_CFG 0xFC8CB0 + +#define mmTPC7_QM_IND_GW_APB_WDATA 0xFC8CB4 + +#define mmTPC7_QM_IND_GW_APB_RDATA 0xFC8CB8 + +#define mmTPC7_QM_IND_GW_APB_STATUS 0xFC8CBC + +#define mmTPC7_QM_GLBL_ERR_ADDR_LO 0xFC8CD0 + +#define mmTPC7_QM_GLBL_ERR_ADDR_HI 0xFC8CD4 + +#define mmTPC7_QM_GLBL_ERR_WDATA 0xFC8CD8 + +#define mmTPC7_QM_GLBL_MEM_INIT_BUSY 0xFC8D00 + +#endif /* ASIC_REG_TPC7_QM_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi.h b/drivers/misc/habanalabs/include/gaudi/gaudi.h new file mode 100644 index 000000000000..8829891d3eef --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_H +#define GAUDI_H + +#define SRAM_BAR_ID 0 +#define CFG_BAR_ID 2 +#define HBM_BAR_ID 4 + +#define SRAM_BAR_SIZE 0x4000000ull /* 64MB */ +#define CFG_BAR_SIZE 0x8000000ull /* 128MB */ + +#define CFG_BASE 0x7FFC000000ull +#define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ + +#define SRAM_BASE_ADDR 0x7FF0000000ull +#define SRAM_SIZE 0x1400000 /* 20MB */ + +#define SPI_FLASH_BASE_ADDR 0x7FF8000000ull + +#define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull +#define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */ + +#define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull +#define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ + +#define DRAM_PHYS_BASE 0x0ull + +#define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ +#define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ + +#define GAUDI_MSI_ENTRIES 32 + +#define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ + +#define MAX_ASID 1024 + +#define PROT_BITS_OFFS 0xF80 + +#define MME_NUMBER_OF_MASTER_ENGINES 2 + +#define TPC_NUMBER_OF_ENGINES 8 + +#define DMA_NUMBER_OF_CHANNELS 8 + +#define NIC_NUMBER_OF_MACROS 5 + +#define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) + +#define NUMBER_OF_IF 8 + +#define DEVICE_CACHE_LINE_SIZE 128 + +#endif /* GAUDI_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h b/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h new file mode 100644 index 000000000000..9ccba8437ec9 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_async_events.h @@ -0,0 +1,310 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI_ASYNC_EVENTS_H_ +#define __GAUDI_ASYNC_EVENTS_H_ + +enum gaudi_async_event_id { + GAUDI_EVENT_PCIE_CORE_SERR = 32, + GAUDI_EVENT_PCIE_CORE_DERR = 33, + GAUDI_EVENT_PCIE_IF_SERR = 34, + GAUDI_EVENT_PCIE_IF_DERR = 35, + GAUDI_EVENT_PCIE_PHY_SERR = 36, + GAUDI_EVENT_PCIE_PHY_DERR = 37, + GAUDI_EVENT_TPC0_SERR = 38, + GAUDI_EVENT_TPC1_SERR = 39, + GAUDI_EVENT_TPC2_SERR = 40, + GAUDI_EVENT_TPC3_SERR = 41, + GAUDI_EVENT_TPC4_SERR = 42, + GAUDI_EVENT_TPC5_SERR = 43, + GAUDI_EVENT_TPC6_SERR = 44, + GAUDI_EVENT_TPC7_SERR = 45, + GAUDI_EVENT_TPC0_DERR = 46, + GAUDI_EVENT_TPC1_DERR = 47, + GAUDI_EVENT_TPC2_DERR = 48, + GAUDI_EVENT_TPC3_DERR = 49, + GAUDI_EVENT_TPC4_DERR = 50, + GAUDI_EVENT_TPC5_DERR = 51, + GAUDI_EVENT_TPC6_DERR = 52, + GAUDI_EVENT_TPC7_DERR = 53, + GAUDI_EVENT_MME0_ACC_SERR = 54, + GAUDI_EVENT_MME0_ACC_DERR = 55, + GAUDI_EVENT_MME0_SBAB_SERR = 56, + GAUDI_EVENT_MME0_SBAB_DERR = 57, + GAUDI_EVENT_MME1_ACC_SERR = 58, + GAUDI_EVENT_MME1_ACC_DERR = 59, + GAUDI_EVENT_MME1_SBAB_SERR = 60, + GAUDI_EVENT_MME1_SBAB_DERR = 61, + GAUDI_EVENT_MME2_ACC_SERR = 62, + GAUDI_EVENT_MME2_ACC_DERR = 63, + GAUDI_EVENT_MME2_SBAB_SERR = 64, + GAUDI_EVENT_MME2_SBAB_DERR = 65, + GAUDI_EVENT_MME3_ACC_SERR = 66, + GAUDI_EVENT_MME3_ACC_DERR = 67, + GAUDI_EVENT_MME3_SBAB_SERR = 68, + GAUDI_EVENT_MME3_SBAB_DERR = 69, + GAUDI_EVENT_DMA0_SERR_ECC = 70, + GAUDI_EVENT_DMA1_SERR_ECC = 71, + GAUDI_EVENT_DMA2_SERR_ECC = 72, + GAUDI_EVENT_DMA3_SERR_ECC = 73, + GAUDI_EVENT_DMA4_SERR_ECC = 74, + GAUDI_EVENT_DMA5_SERR_ECC = 75, + GAUDI_EVENT_DMA6_SERR_ECC = 76, + GAUDI_EVENT_DMA7_SERR_ECC = 77, + GAUDI_EVENT_DMA0_DERR_ECC = 78, + GAUDI_EVENT_DMA1_DERR_ECC = 79, + GAUDI_EVENT_DMA2_DERR_ECC = 80, + GAUDI_EVENT_DMA3_DERR_ECC = 81, + GAUDI_EVENT_DMA4_DERR_ECC = 82, + GAUDI_EVENT_DMA5_DERR_ECC = 83, + GAUDI_EVENT_DMA6_DERR_ECC = 84, + GAUDI_EVENT_DMA7_DERR_ECC = 85, + GAUDI_EVENT_CPU_IF_ECC_SERR = 86, + GAUDI_EVENT_CPU_IF_ECC_DERR = 87, + GAUDI_EVENT_PSOC_MEM_SERR = 88, + GAUDI_EVENT_PSOC_CORESIGHT_SERR = 89, + GAUDI_EVENT_PSOC_MEM_DERR = 90, + GAUDI_EVENT_PSOC_CORESIGHT_DERR = 91, + GAUDI_EVENT_SRAM0_SERR = 92, + GAUDI_EVENT_SRAM1_SERR = 93, + GAUDI_EVENT_SRAM2_SERR = 94, + GAUDI_EVENT_SRAM3_SERR = 95, + GAUDI_EVENT_SRAM7_SERR = 96, + GAUDI_EVENT_SRAM6_SERR = 97, + GAUDI_EVENT_SRAM5_SERR = 98, + GAUDI_EVENT_SRAM4_SERR = 99, + GAUDI_EVENT_SRAM8_SERR = 100, + GAUDI_EVENT_SRAM9_SERR = 101, + GAUDI_EVENT_SRAM10_SERR = 102, + GAUDI_EVENT_SRAM11_SERR = 103, + GAUDI_EVENT_SRAM15_SERR = 104, + GAUDI_EVENT_SRAM14_SERR = 105, + GAUDI_EVENT_SRAM13_SERR = 106, + GAUDI_EVENT_SRAM12_SERR = 107, + GAUDI_EVENT_SRAM16_SERR = 108, + GAUDI_EVENT_SRAM17_SERR = 109, + GAUDI_EVENT_SRAM18_SERR = 110, + GAUDI_EVENT_SRAM19_SERR = 111, + GAUDI_EVENT_SRAM23_SERR = 112, + GAUDI_EVENT_SRAM22_SERR = 113, + GAUDI_EVENT_SRAM21_SERR = 114, + GAUDI_EVENT_SRAM20_SERR = 115, + GAUDI_EVENT_SRAM24_SERR = 116, + GAUDI_EVENT_SRAM25_SERR = 117, + GAUDI_EVENT_SRAM26_SERR = 118, + GAUDI_EVENT_SRAM27_SERR = 119, + GAUDI_EVENT_SRAM31_SERR = 120, + GAUDI_EVENT_SRAM30_SERR = 121, + GAUDI_EVENT_SRAM29_SERR = 122, + GAUDI_EVENT_SRAM28_SERR = 123, + GAUDI_EVENT_SRAM0_DERR = 124, + GAUDI_EVENT_SRAM1_DERR = 125, + GAUDI_EVENT_SRAM2_DERR = 126, + GAUDI_EVENT_SRAM3_DERR = 127, + GAUDI_EVENT_SRAM7_DERR = 128, + GAUDI_EVENT_SRAM6_DERR = 129, + GAUDI_EVENT_SRAM5_DERR = 130, + GAUDI_EVENT_SRAM4_DERR = 131, + GAUDI_EVENT_SRAM8_DERR = 132, + GAUDI_EVENT_SRAM9_DERR = 133, + GAUDI_EVENT_SRAM10_DERR = 134, + GAUDI_EVENT_SRAM11_DERR = 135, + GAUDI_EVENT_SRAM15_DERR = 136, + GAUDI_EVENT_SRAM14_DERR = 137, + GAUDI_EVENT_SRAM13_DERR = 138, + GAUDI_EVENT_SRAM12_DERR = 139, + GAUDI_EVENT_SRAM16_DERR = 140, + GAUDI_EVENT_SRAM17_DERR = 141, + GAUDI_EVENT_SRAM18_DERR = 142, + GAUDI_EVENT_SRAM19_DERR = 143, + GAUDI_EVENT_SRAM23_DERR = 144, + GAUDI_EVENT_SRAM22_DERR = 145, + GAUDI_EVENT_SRAM21_DERR = 146, + GAUDI_EVENT_SRAM20_DERR = 147, + GAUDI_EVENT_SRAM24_DERR = 148, + GAUDI_EVENT_SRAM25_DERR = 149, + GAUDI_EVENT_SRAM26_DERR = 150, + GAUDI_EVENT_SRAM27_DERR = 151, + GAUDI_EVENT_SRAM31_DERR = 152, + GAUDI_EVENT_SRAM30_DERR = 153, + GAUDI_EVENT_SRAM29_DERR = 154, + GAUDI_EVENT_SRAM28_DERR = 155, + GAUDI_EVENT_NIC0_SERR = 156, + GAUDI_EVENT_NIC1_SERR = 157, + GAUDI_EVENT_NIC2_SERR = 158, + GAUDI_EVENT_NIC3_SERR = 159, + GAUDI_EVENT_NIC4_SERR = 160, + GAUDI_EVENT_NIC0_DERR = 166, + GAUDI_EVENT_NIC1_DERR = 167, + GAUDI_EVENT_NIC2_DERR = 168, + GAUDI_EVENT_NIC3_DERR = 169, + GAUDI_EVENT_NIC4_DERR = 170, + GAUDI_EVENT_DMA_IF0_SERR = 176, + GAUDI_EVENT_DMA_IF1_SERR = 177, + GAUDI_EVENT_DMA_IF2_SERR = 178, + GAUDI_EVENT_DMA_IF3_SERR = 179, + GAUDI_EVENT_DMA_IF0_DERR = 180, + GAUDI_EVENT_DMA_IF1_DERR = 181, + GAUDI_EVENT_DMA_IF2_DERR = 182, + GAUDI_EVENT_DMA_IF3_DERR = 183, + GAUDI_EVENT_GIC500 = 184, + GAUDI_EVENT_HBM_0_SERR = 185, + GAUDI_EVENT_HBM_1_SERR = 186, + GAUDI_EVENT_HBM_2_SERR = 187, + GAUDI_EVENT_HBM_3_SERR = 188, + GAUDI_EVENT_HBM_0_DERR = 189, + GAUDI_EVENT_HBM_1_DERR = 190, + GAUDI_EVENT_HBM_2_DERR = 191, + GAUDI_EVENT_HBM_3_DERR = 192, + GAUDI_EVENT_MMU_SERR = 193, + GAUDI_EVENT_MMU_DERR = 194, + GAUDI_EVENT_PCIE_DEC = 200, + GAUDI_EVENT_TPC0_DEC = 201, + GAUDI_EVENT_TPC1_DEC = 203, + GAUDI_EVENT_TPC2_DEC = 205, + GAUDI_EVENT_TPC3_DEC = 207, + GAUDI_EVENT_TPC4_DEC = 209, + GAUDI_EVENT_TPC5_DEC = 211, + GAUDI_EVENT_TPC6_DEC = 213, + GAUDI_EVENT_TPC7_DEC = 215, + GAUDI_EVENT_AXI_ECC = 217, + GAUDI_EVENT_L2_RAM_ECC = 218, + GAUDI_EVENT_MME0_WBC_RSP = 219, + GAUDI_EVENT_MME0_SBAB0_RSP = 220, + GAUDI_EVENT_MME1_WBC_RSP = 224, + GAUDI_EVENT_MME1_SBAB0_RSP = 225, + GAUDI_EVENT_MME2_WBC_RSP = 229, + GAUDI_EVENT_MME2_SBAB0_RSP = 230, + GAUDI_EVENT_MME3_WBC_RSP = 234, + GAUDI_EVENT_MME3_SBAB0_RSP = 235, + GAUDI_EVENT_PLL0 = 239, + GAUDI_EVENT_PLL1 = 240, + GAUDI_EVENT_PLL2 = 241, + GAUDI_EVENT_PLL3 = 242, + GAUDI_EVENT_PLL4 = 243, + GAUDI_EVENT_PLL5 = 244, + GAUDI_EVENT_PLL6 = 245, + GAUDI_EVENT_PLL7 = 246, + GAUDI_EVENT_PLL8 = 247, + GAUDI_EVENT_PLL9 = 248, + GAUDI_EVENT_PLL10 = 249, + GAUDI_EVENT_PLL11 = 250, + GAUDI_EVENT_PLL12 = 251, + GAUDI_EVENT_PLL13 = 252, + GAUDI_EVENT_PLL14 = 253, + GAUDI_EVENT_PLL15 = 254, + GAUDI_EVENT_PLL16 = 255, + GAUDI_EVENT_PLL17 = 256, + GAUDI_EVENT_CPU_AXI_SPLITTER = 257, + GAUDI_EVENT_PSOC_AXI_DEC = 262, + GAUDI_EVENT_PSOC_PRSTN_FALL = 263, + GAUDI_EVENT_NIC_SEI_0 = 264, + GAUDI_EVENT_NIC_SEI_1 = 265, + GAUDI_EVENT_NIC_SEI_2 = 266, + GAUDI_EVENT_NIC_SEI_3 = 267, + GAUDI_EVENT_NIC_SEI_4 = 268, + GAUDI_EVENT_PCIE_FLR = 290, + GAUDI_EVENT_TPC0_BMON_SPMU = 300, + GAUDI_EVENT_TPC0_KRN_ERR = 301, + GAUDI_EVENT_TPC1_BMON_SPMU = 306, + GAUDI_EVENT_TPC1_KRN_ERR = 307, + GAUDI_EVENT_TPC2_BMON_SPMU = 312, + GAUDI_EVENT_TPC2_KRN_ERR = 313, + GAUDI_EVENT_TPC3_BMON_SPMU = 318, + GAUDI_EVENT_TPC3_KRN_ERR = 319, + GAUDI_EVENT_TPC4_BMON_SPMU = 324, + GAUDI_EVENT_TPC4_KRN_ERR = 325, + GAUDI_EVENT_TPC5_BMON_SPMU = 330, + GAUDI_EVENT_TPC5_KRN_ERR = 331, + GAUDI_EVENT_TPC6_BMON_SPMU = 336, + GAUDI_EVENT_TPC6_KRN_ERR = 337, + GAUDI_EVENT_TPC7_BMON_SPMU = 342, + GAUDI_EVENT_TPC7_KRN_ERR = 343, + GAUDI_EVENT_MMU_PAGE_FAULT = 380, + GAUDI_EVENT_MMU_WR_PERM = 381, + GAUDI_EVENT_DMA_BM_CH0 = 383, + GAUDI_EVENT_DMA_BM_CH1 = 384, + GAUDI_EVENT_DMA_BM_CH2 = 385, + GAUDI_EVENT_DMA_BM_CH3 = 386, + GAUDI_EVENT_DMA_BM_CH4 = 387, + GAUDI_EVENT_DMA_BM_CH5 = 388, + GAUDI_EVENT_DMA_BM_CH6 = 389, + GAUDI_EVENT_DMA_BM_CH7 = 390, + GAUDI_EVENT_HBM0_SPI_0 = 395, + GAUDI_EVENT_HBM0_SPI_1 = 396, + GAUDI_EVENT_HBM1_SPI_0 = 399, + GAUDI_EVENT_HBM1_SPI_1 = 400, + GAUDI_EVENT_HBM2_SPI_0 = 403, + GAUDI_EVENT_HBM2_SPI_1 = 404, + GAUDI_EVENT_HBM3_SPI_0 = 407, + GAUDI_EVENT_HBM3_SPI_1 = 408, + GAUDI_EVENT_PSOC_GPIO_U16_0 = 421, + GAUDI_EVENT_PI_UPDATE = 484, + GAUDI_EVENT_HALT_MACHINE = 485, + GAUDI_EVENT_INTS_REGISTER = 486, + GAUDI_EVENT_SOFT_RESET = 487, + GAUDI_EVENT_RAZWI_OR_ADC = 548, + GAUDI_EVENT_TPC0_QM = 572, + GAUDI_EVENT_TPC1_QM = 573, + GAUDI_EVENT_TPC2_QM = 574, + GAUDI_EVENT_TPC3_QM = 575, + GAUDI_EVENT_TPC4_QM = 576, + GAUDI_EVENT_TPC5_QM = 577, + GAUDI_EVENT_TPC6_QM = 578, + GAUDI_EVENT_TPC7_QM = 579, + GAUDI_EVENT_MME0_QM = 581, + GAUDI_EVENT_MME2_QM = 582, + GAUDI_EVENT_DMA0_QM = 583, + GAUDI_EVENT_DMA1_QM = 584, + GAUDI_EVENT_DMA2_QM = 585, + GAUDI_EVENT_DMA3_QM = 586, + GAUDI_EVENT_DMA4_QM = 587, + GAUDI_EVENT_DMA5_QM = 588, + GAUDI_EVENT_DMA6_QM = 589, + GAUDI_EVENT_DMA7_QM = 590, + GAUDI_EVENT_NIC0_QM0 = 594, + GAUDI_EVENT_NIC0_QM1 = 595, + GAUDI_EVENT_NIC1_QM0 = 596, + GAUDI_EVENT_NIC1_QM1 = 597, + GAUDI_EVENT_NIC2_QM0 = 598, + GAUDI_EVENT_NIC2_QM1 = 599, + GAUDI_EVENT_NIC3_QM0 = 600, + GAUDI_EVENT_NIC3_QM1 = 601, + GAUDI_EVENT_NIC4_QM0 = 602, + GAUDI_EVENT_NIC4_QM1 = 603, + GAUDI_EVENT_DMA0_CORE = 604, + GAUDI_EVENT_DMA1_CORE = 605, + GAUDI_EVENT_DMA2_CORE = 606, + GAUDI_EVENT_DMA3_CORE = 607, + GAUDI_EVENT_DMA4_CORE = 608, + GAUDI_EVENT_DMA5_CORE = 609, + GAUDI_EVENT_DMA6_CORE = 610, + GAUDI_EVENT_DMA7_CORE = 611, + GAUDI_EVENT_NIC0_QP0 = 612, + GAUDI_EVENT_NIC0_QP1 = 613, + GAUDI_EVENT_NIC1_QP0 = 614, + GAUDI_EVENT_NIC1_QP1 = 615, + GAUDI_EVENT_NIC2_QP0 = 616, + GAUDI_EVENT_NIC2_QP1 = 617, + GAUDI_EVENT_NIC3_QP0 = 618, + GAUDI_EVENT_NIC3_QP1 = 619, + GAUDI_EVENT_NIC4_QP0 = 620, + GAUDI_EVENT_NIC4_QP1 = 621, + GAUDI_EVENT_FIX_POWER_ENV_S = 658, + GAUDI_EVENT_FIX_POWER_ENV_E = 659, + GAUDI_EVENT_FIX_THERMAL_ENV_S = 660, + GAUDI_EVENT_FIX_THERMAL_ENV_E = 661, + GAUDI_EVENT_RAZWI_OR_ADC_SW = 662, + GAUDI_EVENT_SIZE, +}; + +#endif /* __GAUDI_ASYNC_EVENTS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h b/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h new file mode 100644 index 000000000000..737176ba06fb --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_async_ids_map_extended.h @@ -0,0 +1,694 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ +#define __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ + +struct gaudi_async_events_ids_map { + int fc_id; + int cpu_id; + int valid; + char name[64]; +}; + +static struct gaudi_async_events_ids_map gaudi_irq_map_table[] = { + { .fc_id = 0, .cpu_id = 0, .valid = 0, .name = "" }, + { .fc_id = 1, .cpu_id = 1, .valid = 0, .name = "" }, + { .fc_id = 2, .cpu_id = 2, .valid = 0, .name = "" }, + { .fc_id = 3, .cpu_id = 3, .valid = 0, .name = "" }, + { .fc_id = 4, .cpu_id = 4, .valid = 0, .name = "" }, + { .fc_id = 5, .cpu_id = 5, .valid = 0, .name = "" }, + { .fc_id = 6, .cpu_id = 6, .valid = 0, .name = "" }, + { .fc_id = 7, .cpu_id = 7, .valid = 0, .name = "" }, + { .fc_id = 8, .cpu_id = 8, .valid = 0, .name = "" }, + { .fc_id = 9, .cpu_id = 9, .valid = 0, .name = "" }, + { .fc_id = 10, .cpu_id = 10, .valid = 0, .name = "" }, + { .fc_id = 11, .cpu_id = 11, .valid = 0, .name = "" }, + { .fc_id = 12, .cpu_id = 12, .valid = 0, .name = "" }, + { .fc_id = 13, .cpu_id = 13, .valid = 0, .name = "" }, + { .fc_id = 14, .cpu_id = 14, .valid = 0, .name = "" }, + { .fc_id = 15, .cpu_id = 15, .valid = 0, .name = "" }, + { .fc_id = 16, .cpu_id = 16, .valid = 0, .name = "" }, + { .fc_id = 17, .cpu_id = 17, .valid = 0, .name = "" }, + { .fc_id = 18, .cpu_id = 18, .valid = 0, .name = "" }, + { .fc_id = 19, .cpu_id = 19, .valid = 0, .name = "" }, + { .fc_id = 20, .cpu_id = 20, .valid = 0, .name = "" }, + { .fc_id = 21, .cpu_id = 21, .valid = 0, .name = "" }, + { .fc_id = 22, .cpu_id = 22, .valid = 0, .name = "" }, + { .fc_id = 23, .cpu_id = 23, .valid = 0, .name = "" }, + { .fc_id = 24, .cpu_id = 24, .valid = 0, .name = "" }, + { .fc_id = 25, .cpu_id = 25, .valid = 0, .name = "" }, + { .fc_id = 26, .cpu_id = 26, .valid = 0, .name = "" }, + { .fc_id = 27, .cpu_id = 27, .valid = 0, .name = "" }, + { .fc_id = 28, .cpu_id = 28, .valid = 0, .name = "" }, + { .fc_id = 29, .cpu_id = 29, .valid = 0, .name = "" }, + { .fc_id = 30, .cpu_id = 30, .valid = 0, .name = "" }, + { .fc_id = 31, .cpu_id = 31, .valid = 0, .name = "" }, + { .fc_id = 32, .cpu_id = 32, .valid = 1, .name = "PCIE_CORE_SERR" }, + { .fc_id = 33, .cpu_id = 33, .valid = 1, .name = "PCIE_CORE_DERR" }, + { .fc_id = 34, .cpu_id = 34, .valid = 1, .name = "PCIE_IF_SERR" }, + { .fc_id = 35, .cpu_id = 35, .valid = 1, .name = "PCIE_IF_DERR" }, + { .fc_id = 36, .cpu_id = 36, .valid = 1, .name = "PCIE_PHY_SERR" }, + { .fc_id = 37, .cpu_id = 37, .valid = 1, .name = "PCIE_PHY_DERR" }, + { .fc_id = 38, .cpu_id = 38, .valid = 1, .name = "TPC0_SERR" }, + { .fc_id = 39, .cpu_id = 38, .valid = 1, .name = "TPC1_SERR" }, + { .fc_id = 40, .cpu_id = 38, .valid = 1, .name = "TPC2_SERR" }, + { .fc_id = 41, .cpu_id = 38, .valid = 1, .name = "TPC3_SERR" }, + { .fc_id = 42, .cpu_id = 38, .valid = 1, .name = "TPC4_SERR" }, + { .fc_id = 43, .cpu_id = 38, .valid = 1, .name = "TPC5_SERR" }, + { .fc_id = 44, .cpu_id = 38, .valid = 1, .name = "TPC6_SERR" }, + { .fc_id = 45, .cpu_id = 38, .valid = 1, .name = "TPC7_SERR" }, + { .fc_id = 46, .cpu_id = 39, .valid = 1, .name = "TPC0_DERR" }, + { .fc_id = 47, .cpu_id = 39, .valid = 1, .name = "TPC1_DERR" }, + { .fc_id = 48, .cpu_id = 39, .valid = 1, .name = "TPC2_DERR" }, + { .fc_id = 49, .cpu_id = 39, .valid = 1, .name = "TPC3_DERR" }, + { .fc_id = 50, .cpu_id = 39, .valid = 1, .name = "TPC4_DERR" }, + { .fc_id = 51, .cpu_id = 39, .valid = 1, .name = "TPC5_DERR" }, + { .fc_id = 52, .cpu_id = 39, .valid = 1, .name = "TPC6_DERR" }, + { .fc_id = 53, .cpu_id = 39, .valid = 1, .name = "TPC7_DERR" }, + { .fc_id = 54, .cpu_id = 40, .valid = 1, .name = "MME0_ACC_SERR" }, + { .fc_id = 55, .cpu_id = 41, .valid = 1, .name = "MME0_ACC_DERR" }, + { .fc_id = 56, .cpu_id = 42, .valid = 1, .name = "MME0_SBAB_SERR" }, + { .fc_id = 57, .cpu_id = 43, .valid = 1, .name = "MME0_SBAB_DERR" }, + { .fc_id = 58, .cpu_id = 44, .valid = 1, .name = "MME1_ACC_SERR" }, + { .fc_id = 59, .cpu_id = 45, .valid = 1, .name = "MME1_ACC_DERR" }, + { .fc_id = 60, .cpu_id = 46, .valid = 1, .name = "MME1_SBAB_SERR" }, + { .fc_id = 61, .cpu_id = 47, .valid = 1, .name = "MME1_SBAB_DERR" }, + { .fc_id = 62, .cpu_id = 48, .valid = 1, .name = "MME2_ACC_SERR" }, + { .fc_id = 63, .cpu_id = 49, .valid = 1, .name = "MME2_ACC_DERR" }, + { .fc_id = 64, .cpu_id = 50, .valid = 1, .name = "MME2_SBAB_SERR" }, + { .fc_id = 65, .cpu_id = 51, .valid = 1, .name = "MME2_SBAB_DERR" }, + { .fc_id = 66, .cpu_id = 52, .valid = 1, .name = "MME3_ACC_SERR" }, + { .fc_id = 67, .cpu_id = 53, .valid = 1, .name = "MME3_ACC_DERR" }, + { .fc_id = 68, .cpu_id = 54, .valid = 1, .name = "MME3_SBAB_SERR" }, + { .fc_id = 69, .cpu_id = 55, .valid = 1, .name = "MME3_SBAB_DERR" }, + { .fc_id = 70, .cpu_id = 56, .valid = 1, .name = "DMA0_SERR_ECC" }, + { .fc_id = 71, .cpu_id = 56, .valid = 1, .name = "DMA1_SERR_ECC" }, + { .fc_id = 72, .cpu_id = 56, .valid = 1, .name = "DMA2_SERR_ECC" }, + { .fc_id = 73, .cpu_id = 56, .valid = 1, .name = "DMA3_SERR_ECC" }, + { .fc_id = 74, .cpu_id = 56, .valid = 1, .name = "DMA4_SERR_ECC" }, + { .fc_id = 75, .cpu_id = 56, .valid = 1, .name = "DMA5_SERR_ECC" }, + { .fc_id = 76, .cpu_id = 56, .valid = 1, .name = "DMA6_SERR_ECC" }, + { .fc_id = 77, .cpu_id = 56, .valid = 1, .name = "DMA7_SERR_ECC" }, + { .fc_id = 78, .cpu_id = 57, .valid = 1, .name = "DMA0_DERR_ECC" }, + { .fc_id = 79, .cpu_id = 57, .valid = 1, .name = "DMA1_DERR_ECC" }, + { .fc_id = 80, .cpu_id = 57, .valid = 1, .name = "DMA2_DERR_ECC" }, + { .fc_id = 81, .cpu_id = 57, .valid = 1, .name = "DMA3_DERR_ECC" }, + { .fc_id = 82, .cpu_id = 57, .valid = 1, .name = "DMA4_DERR_ECC" }, + { .fc_id = 83, .cpu_id = 57, .valid = 1, .name = "DMA5_DERR_ECC" }, + { .fc_id = 84, .cpu_id = 57, .valid = 1, .name = "DMA6_DERR_ECC" }, + { .fc_id = 85, .cpu_id = 57, .valid = 1, .name = "DMA7_DERR_ECC" }, + { .fc_id = 86, .cpu_id = 58, .valid = 1, .name = "CPU_IF_ECC_SERR" }, + { .fc_id = 87, .cpu_id = 59, .valid = 1, .name = "CPU_IF_ECC_DERR" }, + { .fc_id = 88, .cpu_id = 60, .valid = 1, .name = "PSOC_MEM_SERR" }, + { .fc_id = 89, .cpu_id = 61, .valid = 1, + .name = "PSOC_CORESIGHT_SERR" }, + { .fc_id = 90, .cpu_id = 62, .valid = 1, .name = "PSOC_MEM_DERR" }, + { .fc_id = 91, .cpu_id = 63, .valid = 1, + .name = "PSOC_CORESIGHT_DERR" }, + { .fc_id = 92, .cpu_id = 64, .valid = 1, .name = "SRAM0_SERR" }, + { .fc_id = 93, .cpu_id = 64, .valid = 1, .name = "SRAM1_SERR" }, + { .fc_id = 94, .cpu_id = 64, .valid = 1, .name = "SRAM2_SERR" }, + { .fc_id = 95, .cpu_id = 64, .valid = 1, .name = "SRAM3_SERR" }, + { .fc_id = 96, .cpu_id = 64, .valid = 1, .name = "SRAM7_SERR" }, + { .fc_id = 97, .cpu_id = 64, .valid = 1, .name = "SRAM6_SERR" }, + { .fc_id = 98, .cpu_id = 64, .valid = 1, .name = "SRAM5_SERR" }, + { .fc_id = 99, .cpu_id = 64, .valid = 1, .name = "SRAM4_SERR" }, + { .fc_id = 100, .cpu_id = 64, .valid = 1, .name = "SRAM8_SERR" }, + { .fc_id = 101, .cpu_id = 64, .valid = 1, .name = "SRAM9_SERR" }, + { .fc_id = 102, .cpu_id = 64, .valid = 1, .name = "SRAM10_SERR" }, + { .fc_id = 103, .cpu_id = 64, .valid = 1, .name = "SRAM11_SERR" }, + { .fc_id = 104, .cpu_id = 64, .valid = 1, .name = "SRAM15_SERR" }, + { .fc_id = 105, .cpu_id = 64, .valid = 1, .name = "SRAM14_SERR" }, + { .fc_id = 106, .cpu_id = 64, .valid = 1, .name = "SRAM13_SERR" }, + { .fc_id = 107, .cpu_id = 64, .valid = 1, .name = "SRAM12_SERR" }, + { .fc_id = 108, .cpu_id = 64, .valid = 1, .name = "SRAM16_SERR" }, + { .fc_id = 109, .cpu_id = 64, .valid = 1, .name = "SRAM17_SERR" }, + { .fc_id = 110, .cpu_id = 64, .valid = 1, .name = "SRAM18_SERR" }, + { .fc_id = 111, .cpu_id = 64, .valid = 1, .name = "SRAM19_SERR" }, + { .fc_id = 112, .cpu_id = 64, .valid = 1, .name = "SRAM23_SERR" }, + { .fc_id = 113, .cpu_id = 64, .valid = 1, .name = "SRAM22_SERR" }, + { .fc_id = 114, .cpu_id = 64, .valid = 1, .name = "SRAM21_SERR" }, + { .fc_id = 115, .cpu_id = 64, .valid = 1, .name = "SRAM20_SERR" }, + { .fc_id = 116, .cpu_id = 64, .valid = 1, .name = "SRAM24_SERR" }, + { .fc_id = 117, .cpu_id = 64, .valid = 1, .name = "SRAM25_SERR" }, + { .fc_id = 118, .cpu_id = 64, .valid = 1, .name = "SRAM26_SERR" }, + { .fc_id = 119, .cpu_id = 64, .valid = 1, .name = "SRAM27_SERR" }, + { .fc_id = 120, .cpu_id = 64, .valid = 1, .name = "SRAM31_SERR" }, + { .fc_id = 121, .cpu_id = 64, .valid = 1, .name = "SRAM30_SERR" }, + { .fc_id = 122, .cpu_id = 64, .valid = 1, .name = "SRAM29_SERR" }, + { .fc_id = 123, .cpu_id = 64, .valid = 1, .name = "SRAM28_SERR" }, + { .fc_id = 124, .cpu_id = 65, .valid = 1, .name = "SRAM0_DERR" }, + { .fc_id = 125, .cpu_id = 65, .valid = 1, .name = "SRAM1_DERR" }, + { .fc_id = 126, .cpu_id = 65, .valid = 1, .name = "SRAM2_DERR" }, + { .fc_id = 127, .cpu_id = 65, .valid = 1, .name = "SRAM3_DERR" }, + { .fc_id = 128, .cpu_id = 65, .valid = 1, .name = "SRAM7_DERR" }, + { .fc_id = 129, .cpu_id = 65, .valid = 1, .name = "SRAM6_DERR" }, + { .fc_id = 130, .cpu_id = 65, .valid = 1, .name = "SRAM5_DERR" }, + { .fc_id = 131, .cpu_id = 65, .valid = 1, .name = "SRAM4_DERR" }, + { .fc_id = 132, .cpu_id = 65, .valid = 1, .name = "SRAM8_DERR" }, + { .fc_id = 133, .cpu_id = 65, .valid = 1, .name = "SRAM9_DERR" }, + { .fc_id = 134, .cpu_id = 65, .valid = 1, .name = "SRAM10_DERR" }, + { .fc_id = 135, .cpu_id = 65, .valid = 1, .name = "SRAM11_DERR" }, + { .fc_id = 136, .cpu_id = 65, .valid = 1, .name = "SRAM15_DERR" }, + { .fc_id = 137, .cpu_id = 65, .valid = 1, .name = "SRAM14_DERR" }, + { .fc_id = 138, .cpu_id = 65, .valid = 1, .name = "SRAM13_DERR" }, + { .fc_id = 139, .cpu_id = 65, .valid = 1, .name = "SRAM12_DERR" }, + { .fc_id = 140, .cpu_id = 65, .valid = 1, .name = "SRAM16_DERR" }, + { .fc_id = 141, .cpu_id = 65, .valid = 1, .name = "SRAM17_DERR" }, + { .fc_id = 142, .cpu_id = 65, .valid = 1, .name = "SRAM18_DERR" }, + { .fc_id = 143, .cpu_id = 65, .valid = 1, .name = "SRAM19_DERR" }, + { .fc_id = 144, .cpu_id = 65, .valid = 1, .name = "SRAM23_DERR" }, + { .fc_id = 145, .cpu_id = 65, .valid = 1, .name = "SRAM22_DERR" }, + { .fc_id = 146, .cpu_id = 65, .valid = 1, .name = "SRAM21_DERR" }, + { .fc_id = 147, .cpu_id = 65, .valid = 1, .name = "SRAM20_DERR" }, + { .fc_id = 148, .cpu_id = 65, .valid = 1, .name = "SRAM24_DERR" }, + { .fc_id = 149, .cpu_id = 65, .valid = 1, .name = "SRAM25_DERR" }, + { .fc_id = 150, .cpu_id = 65, .valid = 1, .name = "SRAM26_DERR" }, + { .fc_id = 151, .cpu_id = 65, .valid = 1, .name = "SRAM27_DERR" }, + { .fc_id = 152, .cpu_id = 65, .valid = 1, .name = "SRAM31_DERR" }, + { .fc_id = 153, .cpu_id = 65, .valid = 1, .name = "SRAM30_DERR" }, + { .fc_id = 154, .cpu_id = 65, .valid = 1, .name = "SRAM29_DERR" }, + { .fc_id = 155, .cpu_id = 65, .valid = 1, .name = "SRAM28_DERR" }, + { .fc_id = 156, .cpu_id = 66, .valid = 1, .name = "NIC0_SERR" }, + { .fc_id = 157, .cpu_id = 66, .valid = 1, .name = "NIC1_SERR" }, + { .fc_id = 158, .cpu_id = 66, .valid = 1, .name = "NIC2_SERR" }, + { .fc_id = 159, .cpu_id = 66, .valid = 1, .name = "NIC3_SERR" }, + { .fc_id = 160, .cpu_id = 66, .valid = 1, .name = "NIC4_SERR" }, + { .fc_id = 161, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 162, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 163, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 164, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 165, .cpu_id = 66, .valid = 0, .name = "" }, + { .fc_id = 166, .cpu_id = 67, .valid = 1, .name = "NIC0_DERR" }, + { .fc_id = 167, .cpu_id = 67, .valid = 1, .name = "NIC1_DERR" }, + { .fc_id = 168, .cpu_id = 67, .valid = 1, .name = "NIC2_DERR" }, + { .fc_id = 169, .cpu_id = 67, .valid = 1, .name = "NIC3_DERR" }, + { .fc_id = 170, .cpu_id = 67, .valid = 1, .name = "NIC4_DERR" }, + { .fc_id = 171, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 172, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 173, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 174, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 175, .cpu_id = 67, .valid = 0, .name = "" }, + { .fc_id = 176, .cpu_id = 68, .valid = 1, .name = "DMA_IF0_SERR" }, + { .fc_id = 177, .cpu_id = 68, .valid = 1, .name = "DMA_IF1_SERR" }, + { .fc_id = 178, .cpu_id = 68, .valid = 1, .name = "DMA_IF2_SERR" }, + { .fc_id = 179, .cpu_id = 68, .valid = 1, .name = "DMA_IF3_SERR" }, + { .fc_id = 180, .cpu_id = 69, .valid = 1, .name = "DMA_IF0_DERR" }, + { .fc_id = 181, .cpu_id = 69, .valid = 1, .name = "DMA_IF1_DERR" }, + { .fc_id = 182, .cpu_id = 69, .valid = 1, .name = "DMA_IF2_DERR" }, + { .fc_id = 183, .cpu_id = 69, .valid = 1, .name = "DMA_IF3_DERR" }, + { .fc_id = 184, .cpu_id = 70, .valid = 1, .name = "GIC500" }, + { .fc_id = 185, .cpu_id = 71, .valid = 1, .name = "HBM_0_SERR" }, + { .fc_id = 186, .cpu_id = 71, .valid = 1, .name = "HBM_1_SERR" }, + { .fc_id = 187, .cpu_id = 71, .valid = 1, .name = "HBM_2_SERR" }, + { .fc_id = 188, .cpu_id = 71, .valid = 1, .name = "HBM_3_SERR" }, + { .fc_id = 189, .cpu_id = 72, .valid = 1, .name = "HBM_0_DERR" }, + { .fc_id = 190, .cpu_id = 72, .valid = 1, .name = "HBM_1_DERR" }, + { .fc_id = 191, .cpu_id = 72, .valid = 1, .name = "HBM_2_DERR" }, + { .fc_id = 192, .cpu_id = 72, .valid = 1, .name = "HBM_3_DERR" }, + { .fc_id = 193, .cpu_id = 73, .valid = 1, .name = "MMU_SERR" }, + { .fc_id = 194, .cpu_id = 74, .valid = 1, .name = "MMU_DERR" }, + { .fc_id = 195, .cpu_id = 75, .valid = 0, .name = "" }, + { .fc_id = 196, .cpu_id = 76, .valid = 0, .name = "" }, + { .fc_id = 197, .cpu_id = 77, .valid = 0, .name = "" }, + { .fc_id = 198, .cpu_id = 78, .valid = 0, .name = "" }, + { .fc_id = 199, .cpu_id = 79, .valid = 0, .name = "" }, + { .fc_id = 200, .cpu_id = 80, .valid = 1, .name = "PCIE_DEC" }, + { .fc_id = 201, .cpu_id = 81, .valid = 1, .name = "TPC0_DEC" }, + { .fc_id = 202, .cpu_id = 82, .valid = 0, .name = "" }, + { .fc_id = 203, .cpu_id = 83, .valid = 1, .name = "TPC1_DEC" }, + { .fc_id = 204, .cpu_id = 84, .valid = 0, .name = "" }, + { .fc_id = 205, .cpu_id = 85, .valid = 1, .name = "TPC2_DEC" }, + { .fc_id = 206, .cpu_id = 86, .valid = 0, .name = "" }, + { .fc_id = 207, .cpu_id = 87, .valid = 1, .name = "TPC3_DEC" }, + { .fc_id = 208, .cpu_id = 88, .valid = 0, .name = "" }, + { .fc_id = 209, .cpu_id = 89, .valid = 1, .name = "TPC4_DEC" }, + { .fc_id = 210, .cpu_id = 90, .valid = 0, .name = "" }, + { .fc_id = 211, .cpu_id = 91, .valid = 1, .name = "TPC5_DEC" }, + { .fc_id = 212, .cpu_id = 92, .valid = 0, .name = "" }, + { .fc_id = 213, .cpu_id = 93, .valid = 1, .name = "TPC6_DEC" }, + { .fc_id = 214, .cpu_id = 94, .valid = 0, .name = "" }, + { .fc_id = 215, .cpu_id = 95, .valid = 1, .name = "TPC7_DEC" }, + { .fc_id = 216, .cpu_id = 96, .valid = 0, .name = "" }, + { .fc_id = 217, .cpu_id = 97, .valid = 1, .name = "AXI_ECC" }, + { .fc_id = 218, .cpu_id = 98, .valid = 1, .name = "L2_RAM_ECC" }, + { .fc_id = 219, .cpu_id = 99, .valid = 1, .name = "MME0_WBC_RSP" }, + { .fc_id = 220, .cpu_id = 100, .valid = 1, .name = "MME0_SBAB0_RSP" }, + { .fc_id = 221, .cpu_id = 101, .valid = 0, .name = "" }, + { .fc_id = 222, .cpu_id = 102, .valid = 0, .name = "" }, + { .fc_id = 223, .cpu_id = 103, .valid = 0, .name = "" }, + { .fc_id = 224, .cpu_id = 104, .valid = 1, .name = "MME1_WBC_RSP" }, + { .fc_id = 225, .cpu_id = 105, .valid = 1, .name = "MME1_SBAB0_RSP" }, + { .fc_id = 226, .cpu_id = 106, .valid = 0, .name = "" }, + { .fc_id = 227, .cpu_id = 107, .valid = 0, .name = "" }, + { .fc_id = 228, .cpu_id = 108, .valid = 0, .name = "" }, + { .fc_id = 229, .cpu_id = 109, .valid = 1, .name = "MME2_WBC_RSP" }, + { .fc_id = 230, .cpu_id = 110, .valid = 1, .name = "MME2_SBAB0_RSP" }, + { .fc_id = 231, .cpu_id = 111, .valid = 0, .name = "" }, + { .fc_id = 232, .cpu_id = 112, .valid = 0, .name = "" }, + { .fc_id = 233, .cpu_id = 113, .valid = 0, .name = "" }, + { .fc_id = 234, .cpu_id = 114, .valid = 1, .name = "MME3_WBC_RSP" }, + { .fc_id = 235, .cpu_id = 115, .valid = 1, .name = "MME3_SBAB0_RSP" }, + { .fc_id = 236, .cpu_id = 116, .valid = 0, .name = "" }, + { .fc_id = 237, .cpu_id = 117, .valid = 0, .name = "" }, + { .fc_id = 238, .cpu_id = 118, .valid = 0, .name = "" }, + { .fc_id = 239, .cpu_id = 119, .valid = 1, .name = "PLL0" }, + { .fc_id = 240, .cpu_id = 119, .valid = 1, .name = "PLL1" }, + { .fc_id = 241, .cpu_id = 119, .valid = 1, .name = "PLL2" }, + { .fc_id = 242, .cpu_id = 119, .valid = 1, .name = "PLL3" }, + { .fc_id = 243, .cpu_id = 119, .valid = 1, .name = "PLL4" }, + { .fc_id = 244, .cpu_id = 119, .valid = 1, .name = "PLL5" }, + { .fc_id = 245, .cpu_id = 119, .valid = 1, .name = "PLL6" }, + { .fc_id = 246, .cpu_id = 119, .valid = 1, .name = "PLL7" }, + { .fc_id = 247, .cpu_id = 119, .valid = 1, .name = "PLL8" }, + { .fc_id = 248, .cpu_id = 119, .valid = 1, .name = "PLL9" }, + { .fc_id = 249, .cpu_id = 119, .valid = 1, .name = "PLL10" }, + { .fc_id = 250, .cpu_id = 119, .valid = 1, .name = "PLL11" }, + { .fc_id = 251, .cpu_id = 119, .valid = 1, .name = "PLL12" }, + { .fc_id = 252, .cpu_id = 119, .valid = 1, .name = "PLL13" }, + { .fc_id = 253, .cpu_id = 119, .valid = 1, .name = "PLL14" }, + { .fc_id = 254, .cpu_id = 119, .valid = 1, .name = "PLL15" }, + { .fc_id = 255, .cpu_id = 119, .valid = 1, .name = "PLL16" }, + { .fc_id = 256, .cpu_id = 119, .valid = 1, .name = "PLL17" }, + { .fc_id = 257, .cpu_id = 120, .valid = 1, + .name = "CPU_AXI_SPLITTER" }, + { .fc_id = 258, .cpu_id = 121, .valid = 0, .name = "" }, + { .fc_id = 259, .cpu_id = 122, .valid = 0, .name = "" }, + { .fc_id = 260, .cpu_id = 123, .valid = 0, .name = "" }, + { .fc_id = 261, .cpu_id = 124, .valid = 0, .name = "" }, + { .fc_id = 262, .cpu_id = 125, .valid = 1, .name = "PSOC_AXI_DEC" }, + { .fc_id = 263, .cpu_id = 126, .valid = 1, .name = "PSOC_PRSTN_FALL" }, + { .fc_id = 264, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_0" }, + { .fc_id = 265, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_1" }, + { .fc_id = 266, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_2" }, + { .fc_id = 267, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_3" }, + { .fc_id = 268, .cpu_id = 127, .valid = 1, .name = "NIC_SEI_4" }, + { .fc_id = 269, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 270, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 271, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 272, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 273, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 274, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 275, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 276, .cpu_id = 128, .valid = 0, .name = "" }, + { .fc_id = 277, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 278, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 279, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 280, .cpu_id = 129, .valid = 0, .name = "" }, + { .fc_id = 281, .cpu_id = 130, .valid = 0, .name = "" }, + { .fc_id = 282, .cpu_id = 131, .valid = 0, .name = "" }, + { .fc_id = 283, .cpu_id = 132, .valid = 0, .name = "" }, + { .fc_id = 284, .cpu_id = 133, .valid = 0, .name = "" }, + { .fc_id = 285, .cpu_id = 134, .valid = 0, .name = "" }, + { .fc_id = 286, .cpu_id = 135, .valid = 0, .name = "" }, + { .fc_id = 287, .cpu_id = 136, .valid = 0, .name = "" }, + { .fc_id = 288, .cpu_id = 137, .valid = 0, .name = "" }, + { .fc_id = 289, .cpu_id = 138, .valid = 0, .name = "" }, + { .fc_id = 290, .cpu_id = 139, .valid = 1, .name = "PCIE_FLR" }, + { .fc_id = 291, .cpu_id = 140, .valid = 0, .name = "" }, + { .fc_id = 292, .cpu_id = 141, .valid = 0, .name = "" }, + { .fc_id = 293, .cpu_id = 142, .valid = 0, .name = "" }, + { .fc_id = 294, .cpu_id = 143, .valid = 0, .name = "" }, + { .fc_id = 295, .cpu_id = 144, .valid = 0, .name = "" }, + { .fc_id = 296, .cpu_id = 145, .valid = 0, .name = "" }, + { .fc_id = 297, .cpu_id = 146, .valid = 0, .name = "" }, + { .fc_id = 298, .cpu_id = 147, .valid = 0, .name = "" }, + { .fc_id = 299, .cpu_id = 148, .valid = 0, .name = "" }, + { .fc_id = 300, .cpu_id = 149, .valid = 1, .name = "TPC0_BMON_SPMU" }, + { .fc_id = 301, .cpu_id = 150, .valid = 1, .name = "TPC0_KRN_ERR" }, + { .fc_id = 302, .cpu_id = 151, .valid = 0, .name = "" }, + { .fc_id = 303, .cpu_id = 152, .valid = 0, .name = "" }, + { .fc_id = 304, .cpu_id = 153, .valid = 0, .name = "" }, + { .fc_id = 305, .cpu_id = 154, .valid = 0, .name = "" }, + { .fc_id = 306, .cpu_id = 155, .valid = 1, .name = "TPC1_BMON_SPMU" }, + { .fc_id = 307, .cpu_id = 156, .valid = 1, .name = "TPC1_KRN_ERR" }, + { .fc_id = 308, .cpu_id = 157, .valid = 0, .name = "" }, + { .fc_id = 309, .cpu_id = 158, .valid = 0, .name = "" }, + { .fc_id = 310, .cpu_id = 159, .valid = 0, .name = "" }, + { .fc_id = 311, .cpu_id = 160, .valid = 0, .name = "" }, + { .fc_id = 312, .cpu_id = 161, .valid = 1, .name = "TPC2_BMON_SPMU" }, + { .fc_id = 313, .cpu_id = 162, .valid = 1, .name = "TPC2_KRN_ERR" }, + { .fc_id = 314, .cpu_id = 163, .valid = 0, .name = "" }, + { .fc_id = 315, .cpu_id = 164, .valid = 0, .name = "" }, + { .fc_id = 316, .cpu_id = 165, .valid = 0, .name = "" }, + { .fc_id = 317, .cpu_id = 166, .valid = 0, .name = "" }, + { .fc_id = 318, .cpu_id = 167, .valid = 1, .name = "TPC3_BMON_SPMU" }, + { .fc_id = 319, .cpu_id = 168, .valid = 1, .name = "TPC3_KRN_ERR" }, + { .fc_id = 320, .cpu_id = 169, .valid = 0, .name = "" }, + { .fc_id = 321, .cpu_id = 170, .valid = 0, .name = "" }, + { .fc_id = 322, .cpu_id = 171, .valid = 0, .name = "" }, + { .fc_id = 323, .cpu_id = 172, .valid = 0, .name = "" }, + { .fc_id = 324, .cpu_id = 173, .valid = 1, .name = "TPC4_BMON_SPMU" }, + { .fc_id = 325, .cpu_id = 174, .valid = 1, .name = "TPC4_KRN_ERR" }, + { .fc_id = 326, .cpu_id = 175, .valid = 0, .name = "" }, + { .fc_id = 327, .cpu_id = 176, .valid = 0, .name = "" }, + { .fc_id = 328, .cpu_id = 177, .valid = 0, .name = "" }, + { .fc_id = 329, .cpu_id = 178, .valid = 0, .name = "" }, + { .fc_id = 330, .cpu_id = 179, .valid = 1, .name = "TPC5_BMON_SPMU" }, + { .fc_id = 331, .cpu_id = 180, .valid = 1, .name = "TPC5_KRN_ERR" }, + { .fc_id = 332, .cpu_id = 181, .valid = 0, .name = "" }, + { .fc_id = 333, .cpu_id = 182, .valid = 0, .name = "" }, + { .fc_id = 334, .cpu_id = 183, .valid = 0, .name = "" }, + { .fc_id = 335, .cpu_id = 184, .valid = 0, .name = "" }, + { .fc_id = 336, .cpu_id = 185, .valid = 1, .name = "TPC6_BMON_SPMU" }, + { .fc_id = 337, .cpu_id = 186, .valid = 1, .name = "TPC6_KRN_ERR" }, + { .fc_id = 338, .cpu_id = 187, .valid = 0, .name = "" }, + { .fc_id = 339, .cpu_id = 188, .valid = 0, .name = "" }, + { .fc_id = 340, .cpu_id = 189, .valid = 0, .name = "" }, + { .fc_id = 341, .cpu_id = 190, .valid = 0, .name = "" }, + { .fc_id = 342, .cpu_id = 191, .valid = 1, .name = "TPC7_BMON_SPMU" }, + { .fc_id = 343, .cpu_id = 192, .valid = 1, .name = "TPC7_KRN_ERR" }, + { .fc_id = 344, .cpu_id = 193, .valid = 0, .name = "" }, + { .fc_id = 345, .cpu_id = 194, .valid = 0, .name = "" }, + { .fc_id = 346, .cpu_id = 195, .valid = 0, .name = "" }, + { .fc_id = 347, .cpu_id = 196, .valid = 0, .name = "" }, + { .fc_id = 348, .cpu_id = 197, .valid = 0, .name = "" }, + { .fc_id = 349, .cpu_id = 198, .valid = 0, .name = "" }, + { .fc_id = 350, .cpu_id = 199, .valid = 0, .name = "" }, + { .fc_id = 351, .cpu_id = 200, .valid = 0, .name = "" }, + { .fc_id = 352, .cpu_id = 201, .valid = 0, .name = "" }, + { .fc_id = 353, .cpu_id = 202, .valid = 0, .name = "" }, + { .fc_id = 354, .cpu_id = 203, .valid = 0, .name = "" }, + { .fc_id = 355, .cpu_id = 204, .valid = 0, .name = "" }, + { .fc_id = 356, .cpu_id = 205, .valid = 0, .name = "" }, + { .fc_id = 357, .cpu_id = 206, .valid = 0, .name = "" }, + { .fc_id = 358, .cpu_id = 207, .valid = 0, .name = "" }, + { .fc_id = 359, .cpu_id = 208, .valid = 0, .name = "" }, + { .fc_id = 360, .cpu_id = 209, .valid = 0, .name = "" }, + { .fc_id = 361, .cpu_id = 210, .valid = 0, .name = "" }, + { .fc_id = 362, .cpu_id = 211, .valid = 0, .name = "" }, + { .fc_id = 363, .cpu_id = 212, .valid = 0, .name = "" }, + { .fc_id = 364, .cpu_id = 213, .valid = 0, .name = "" }, + { .fc_id = 365, .cpu_id = 214, .valid = 0, .name = "" }, + { .fc_id = 366, .cpu_id = 215, .valid = 0, .name = "" }, + { .fc_id = 367, .cpu_id = 216, .valid = 0, .name = "" }, + { .fc_id = 368, .cpu_id = 217, .valid = 0, .name = "" }, + { .fc_id = 369, .cpu_id = 218, .valid = 0, .name = "" }, + { .fc_id = 370, .cpu_id = 219, .valid = 0, .name = "" }, + { .fc_id = 371, .cpu_id = 220, .valid = 0, .name = "" }, + { .fc_id = 372, .cpu_id = 221, .valid = 0, .name = "" }, + { .fc_id = 373, .cpu_id = 222, .valid = 0, .name = "" }, + { .fc_id = 374, .cpu_id = 223, .valid = 0, .name = "" }, + { .fc_id = 375, .cpu_id = 224, .valid = 0, .name = "" }, + { .fc_id = 376, .cpu_id = 225, .valid = 0, .name = "" }, + { .fc_id = 377, .cpu_id = 226, .valid = 0, .name = "" }, + { .fc_id = 378, .cpu_id = 227, .valid = 0, .name = "" }, + { .fc_id = 379, .cpu_id = 228, .valid = 0, .name = "" }, + { .fc_id = 380, .cpu_id = 229, .valid = 1, .name = "MMU_PAGE_FAULT" }, + { .fc_id = 381, .cpu_id = 230, .valid = 1, .name = "MMU_WR_PERM" }, + { .fc_id = 382, .cpu_id = 231, .valid = 0, .name = "" }, + { .fc_id = 383, .cpu_id = 232, .valid = 1, .name = "DMA_BM_CH0" }, + { .fc_id = 384, .cpu_id = 233, .valid = 1, .name = "DMA_BM_CH1" }, + { .fc_id = 385, .cpu_id = 234, .valid = 1, .name = "DMA_BM_CH2" }, + { .fc_id = 386, .cpu_id = 235, .valid = 1, .name = "DMA_BM_CH3" }, + { .fc_id = 387, .cpu_id = 236, .valid = 1, .name = "DMA_BM_CH4" }, + { .fc_id = 388, .cpu_id = 237, .valid = 1, .name = "DMA_BM_CH5" }, + { .fc_id = 389, .cpu_id = 238, .valid = 1, .name = "DMA_BM_CH6" }, + { .fc_id = 390, .cpu_id = 239, .valid = 1, .name = "DMA_BM_CH7" }, + { .fc_id = 391, .cpu_id = 240, .valid = 0, .name = "" }, + { .fc_id = 392, .cpu_id = 241, .valid = 0, .name = "" }, + { .fc_id = 393, .cpu_id = 242, .valid = 0, .name = "" }, + { .fc_id = 394, .cpu_id = 243, .valid = 0, .name = "" }, + { .fc_id = 395, .cpu_id = 244, .valid = 1, .name = "HBM0_SPI_0" }, + { .fc_id = 396, .cpu_id = 245, .valid = 1, .name = "HBM0_SPI_1" }, + { .fc_id = 397, .cpu_id = 246, .valid = 0, .name = "" }, + { .fc_id = 398, .cpu_id = 247, .valid = 0, .name = "" }, + { .fc_id = 399, .cpu_id = 248, .valid = 1, .name = "HBM1_SPI_0" }, + { .fc_id = 400, .cpu_id = 249, .valid = 1, .name = "HBM1_SPI_1" }, + { .fc_id = 401, .cpu_id = 250, .valid = 0, .name = "" }, + { .fc_id = 402, .cpu_id = 251, .valid = 0, .name = "" }, + { .fc_id = 403, .cpu_id = 252, .valid = 1, .name = "HBM2_SPI_0" }, + { .fc_id = 404, .cpu_id = 253, .valid = 1, .name = "HBM2_SPI_1" }, + { .fc_id = 405, .cpu_id = 254, .valid = 0, .name = "" }, + { .fc_id = 406, .cpu_id = 255, .valid = 0, .name = "" }, + { .fc_id = 407, .cpu_id = 256, .valid = 1, .name = "HBM3_SPI_0" }, + { .fc_id = 408, .cpu_id = 257, .valid = 1, .name = "HBM3_SPI_1" }, + { .fc_id = 409, .cpu_id = 258, .valid = 0, .name = "" }, + { .fc_id = 410, .cpu_id = 259, .valid = 0, .name = "" }, + { .fc_id = 411, .cpu_id = 260, .valid = 0, .name = "" }, + { .fc_id = 412, .cpu_id = 261, .valid = 0, .name = "" }, + { .fc_id = 413, .cpu_id = 262, .valid = 0, .name = "" }, + { .fc_id = 414, .cpu_id = 263, .valid = 0, .name = "" }, + { .fc_id = 415, .cpu_id = 264, .valid = 0, .name = "" }, + { .fc_id = 416, .cpu_id = 265, .valid = 0, .name = "" }, + { .fc_id = 417, .cpu_id = 266, .valid = 0, .name = "" }, + { .fc_id = 418, .cpu_id = 267, .valid = 0, .name = "" }, + { .fc_id = 419, .cpu_id = 268, .valid = 0, .name = "" }, + { .fc_id = 420, .cpu_id = 269, .valid = 0, .name = "" }, + { .fc_id = 421, .cpu_id = 270, .valid = 1, .name = "PSOC_GPIO_U16_0" }, + { .fc_id = 422, .cpu_id = 271, .valid = 0, .name = "" }, + { .fc_id = 423, .cpu_id = 272, .valid = 0, .name = "" }, + { .fc_id = 424, .cpu_id = 273, .valid = 0, .name = "" }, + { .fc_id = 425, .cpu_id = 274, .valid = 0, .name = "" }, + { .fc_id = 426, .cpu_id = 275, .valid = 0, .name = "" }, + { .fc_id = 427, .cpu_id = 276, .valid = 0, .name = "" }, + { .fc_id = 428, .cpu_id = 277, .valid = 0, .name = "" }, + { .fc_id = 429, .cpu_id = 278, .valid = 0, .name = "" }, + { .fc_id = 430, .cpu_id = 279, .valid = 0, .name = "" }, + { .fc_id = 431, .cpu_id = 280, .valid = 0, .name = "" }, + { .fc_id = 432, .cpu_id = 281, .valid = 0, .name = "" }, + { .fc_id = 433, .cpu_id = 282, .valid = 0, .name = "" }, + { .fc_id = 434, .cpu_id = 283, .valid = 0, .name = "" }, + { .fc_id = 435, .cpu_id = 284, .valid = 0, .name = "" }, + { .fc_id = 436, .cpu_id = 285, .valid = 0, .name = "" }, + { .fc_id = 437, .cpu_id = 286, .valid = 0, .name = "" }, + { .fc_id = 438, .cpu_id = 287, .valid = 0, .name = "" }, + { .fc_id = 439, .cpu_id = 288, .valid = 0, .name = "" }, + { .fc_id = 440, .cpu_id = 289, .valid = 0, .name = "" }, + { .fc_id = 441, .cpu_id = 290, .valid = 0, .name = "" }, + { .fc_id = 442, .cpu_id = 291, .valid = 0, .name = "" }, + { .fc_id = 443, .cpu_id = 292, .valid = 0, .name = "" }, + { .fc_id = 444, .cpu_id = 293, .valid = 0, .name = "" }, + { .fc_id = 445, .cpu_id = 294, .valid = 0, .name = "" }, + { .fc_id = 446, .cpu_id = 295, .valid = 0, .name = "" }, + { .fc_id = 447, .cpu_id = 296, .valid = 0, .name = "" }, + { .fc_id = 448, .cpu_id = 297, .valid = 0, .name = "" }, + { .fc_id = 449, .cpu_id = 298, .valid = 0, .name = "" }, + { .fc_id = 450, .cpu_id = 299, .valid = 0, .name = "" }, + { .fc_id = 451, .cpu_id = 300, .valid = 0, .name = "" }, + { .fc_id = 452, .cpu_id = 301, .valid = 0, .name = "" }, + { .fc_id = 453, .cpu_id = 302, .valid = 0, .name = "" }, + { .fc_id = 454, .cpu_id = 303, .valid = 0, .name = "" }, + { .fc_id = 455, .cpu_id = 304, .valid = 0, .name = "" }, + { .fc_id = 456, .cpu_id = 305, .valid = 0, .name = "" }, + { .fc_id = 457, .cpu_id = 306, .valid = 0, .name = "" }, + { .fc_id = 458, .cpu_id = 307, .valid = 0, .name = "" }, + { .fc_id = 459, .cpu_id = 308, .valid = 0, .name = "" }, + { .fc_id = 460, .cpu_id = 309, .valid = 0, .name = "" }, + { .fc_id = 461, .cpu_id = 310, .valid = 0, .name = "" }, + { .fc_id = 462, .cpu_id = 311, .valid = 0, .name = "" }, + { .fc_id = 463, .cpu_id = 312, .valid = 0, .name = "" }, + { .fc_id = 464, .cpu_id = 313, .valid = 0, .name = "" }, + { .fc_id = 465, .cpu_id = 314, .valid = 0, .name = "" }, + { .fc_id = 466, .cpu_id = 315, .valid = 0, .name = "" }, + { .fc_id = 467, .cpu_id = 316, .valid = 0, .name = "" }, + { .fc_id = 468, .cpu_id = 317, .valid = 0, .name = "" }, + { .fc_id = 469, .cpu_id = 318, .valid = 0, .name = "" }, + { .fc_id = 470, .cpu_id = 319, .valid = 0, .name = "" }, + { .fc_id = 471, .cpu_id = 320, .valid = 0, .name = "" }, + { .fc_id = 472, .cpu_id = 321, .valid = 0, .name = "" }, + { .fc_id = 473, .cpu_id = 322, .valid = 0, .name = "" }, + { .fc_id = 474, .cpu_id = 323, .valid = 0, .name = "" }, + { .fc_id = 475, .cpu_id = 324, .valid = 0, .name = "" }, + { .fc_id = 476, .cpu_id = 325, .valid = 0, .name = "" }, + { .fc_id = 477, .cpu_id = 326, .valid = 0, .name = "" }, + { .fc_id = 478, .cpu_id = 327, .valid = 0, .name = "" }, + { .fc_id = 479, .cpu_id = 328, .valid = 0, .name = "" }, + { .fc_id = 480, .cpu_id = 329, .valid = 0, .name = "" }, + { .fc_id = 481, .cpu_id = 330, .valid = 0, .name = "" }, + { .fc_id = 482, .cpu_id = 331, .valid = 0, .name = "" }, + { .fc_id = 483, .cpu_id = 332, .valid = 0, .name = "" }, + { .fc_id = 484, .cpu_id = 333, .valid = 1, .name = "PI_UPDATE" }, + { .fc_id = 485, .cpu_id = 334, .valid = 1, .name = "HALT_MACHINE" }, + { .fc_id = 486, .cpu_id = 335, .valid = 1, .name = "INTS_REGISTER" }, + { .fc_id = 487, .cpu_id = 336, .valid = 1, .name = "SOFT_RESET" }, + { .fc_id = 488, .cpu_id = 337, .valid = 0, .name = "" }, + { .fc_id = 489, .cpu_id = 338, .valid = 0, .name = "" }, + { .fc_id = 490, .cpu_id = 339, .valid = 0, .name = "" }, + { .fc_id = 491, .cpu_id = 340, .valid = 0, .name = "" }, + { .fc_id = 492, .cpu_id = 341, .valid = 0, .name = "" }, + { .fc_id = 493, .cpu_id = 342, .valid = 0, .name = "" }, + { .fc_id = 494, .cpu_id = 343, .valid = 0, .name = "" }, + { .fc_id = 495, .cpu_id = 344, .valid = 0, .name = "" }, + { .fc_id = 496, .cpu_id = 345, .valid = 0, .name = "" }, + { .fc_id = 497, .cpu_id = 346, .valid = 0, .name = "" }, + { .fc_id = 498, .cpu_id = 347, .valid = 0, .name = "" }, + { .fc_id = 499, .cpu_id = 348, .valid = 0, .name = "" }, + { .fc_id = 500, .cpu_id = 349, .valid = 0, .name = "" }, + { .fc_id = 501, .cpu_id = 350, .valid = 0, .name = "" }, + { .fc_id = 502, .cpu_id = 351, .valid = 0, .name = "" }, + { .fc_id = 503, .cpu_id = 352, .valid = 0, .name = "" }, + { .fc_id = 504, .cpu_id = 353, .valid = 0, .name = "" }, + { .fc_id = 505, .cpu_id = 354, .valid = 0, .name = "" }, + { .fc_id = 506, .cpu_id = 355, .valid = 0, .name = "" }, + { .fc_id = 507, .cpu_id = 356, .valid = 0, .name = "" }, + { .fc_id = 508, .cpu_id = 357, .valid = 0, .name = "" }, + { .fc_id = 509, .cpu_id = 358, .valid = 0, .name = "" }, + { .fc_id = 510, .cpu_id = 359, .valid = 0, .name = "" }, + { .fc_id = 511, .cpu_id = 360, .valid = 0, .name = "" }, + { .fc_id = 512, .cpu_id = 361, .valid = 0, .name = "" }, + { .fc_id = 513, .cpu_id = 362, .valid = 0, .name = "" }, + { .fc_id = 514, .cpu_id = 363, .valid = 0, .name = "" }, + { .fc_id = 515, .cpu_id = 364, .valid = 0, .name = "" }, + { .fc_id = 516, .cpu_id = 365, .valid = 0, .name = "" }, + { .fc_id = 517, .cpu_id = 366, .valid = 0, .name = "" }, + { .fc_id = 518, .cpu_id = 367, .valid = 0, .name = "" }, + { .fc_id = 519, .cpu_id = 368, .valid = 0, .name = "" }, + { .fc_id = 520, .cpu_id = 369, .valid = 0, .name = "" }, + { .fc_id = 521, .cpu_id = 370, .valid = 0, .name = "" }, + { .fc_id = 522, .cpu_id = 371, .valid = 0, .name = "" }, + { .fc_id = 523, .cpu_id = 372, .valid = 0, .name = "" }, + { .fc_id = 524, .cpu_id = 373, .valid = 0, .name = "" }, + { .fc_id = 525, .cpu_id = 374, .valid = 0, .name = "" }, + { .fc_id = 526, .cpu_id = 375, .valid = 0, .name = "" }, + { .fc_id = 527, .cpu_id = 376, .valid = 0, .name = "" }, + { .fc_id = 528, .cpu_id = 377, .valid = 0, .name = "" }, + { .fc_id = 529, .cpu_id = 378, .valid = 0, .name = "" }, + { .fc_id = 530, .cpu_id = 379, .valid = 0, .name = "" }, + { .fc_id = 531, .cpu_id = 380, .valid = 0, .name = "" }, + { .fc_id = 532, .cpu_id = 381, .valid = 0, .name = "" }, + { .fc_id = 533, .cpu_id = 382, .valid = 0, .name = "" }, + { .fc_id = 534, .cpu_id = 383, .valid = 0, .name = "" }, + { .fc_id = 535, .cpu_id = 384, .valid = 0, .name = "" }, + { .fc_id = 536, .cpu_id = 385, .valid = 0, .name = "" }, + { .fc_id = 537, .cpu_id = 386, .valid = 0, .name = "" }, + { .fc_id = 538, .cpu_id = 387, .valid = 0, .name = "" }, + { .fc_id = 539, .cpu_id = 388, .valid = 0, .name = "" }, + { .fc_id = 540, .cpu_id = 389, .valid = 0, .name = "" }, + { .fc_id = 541, .cpu_id = 390, .valid = 0, .name = "" }, + { .fc_id = 542, .cpu_id = 391, .valid = 0, .name = "" }, + { .fc_id = 543, .cpu_id = 392, .valid = 0, .name = "" }, + { .fc_id = 544, .cpu_id = 393, .valid = 0, .name = "" }, + { .fc_id = 545, .cpu_id = 394, .valid = 0, .name = "" }, + { .fc_id = 546, .cpu_id = 395, .valid = 0, .name = "" }, + { .fc_id = 547, .cpu_id = 396, .valid = 0, .name = "" }, + { .fc_id = 548, .cpu_id = 397, .valid = 1, .name = "RAZWI_OR_ADC" }, + { .fc_id = 549, .cpu_id = 398, .valid = 0, .name = "" }, + { .fc_id = 550, .cpu_id = 399, .valid = 0, .name = "" }, + { .fc_id = 551, .cpu_id = 400, .valid = 0, .name = "" }, + { .fc_id = 552, .cpu_id = 401, .valid = 0, .name = "" }, + { .fc_id = 553, .cpu_id = 402, .valid = 0, .name = "" }, + { .fc_id = 554, .cpu_id = 403, .valid = 0, .name = "" }, + { .fc_id = 555, .cpu_id = 404, .valid = 0, .name = "" }, + { .fc_id = 556, .cpu_id = 405, .valid = 0, .name = "" }, + { .fc_id = 557, .cpu_id = 406, .valid = 0, .name = "" }, + { .fc_id = 558, .cpu_id = 407, .valid = 0, .name = "" }, + { .fc_id = 559, .cpu_id = 408, .valid = 0, .name = "" }, + { .fc_id = 560, .cpu_id = 409, .valid = 0, .name = "" }, + { .fc_id = 561, .cpu_id = 410, .valid = 0, .name = "" }, + { .fc_id = 562, .cpu_id = 411, .valid = 0, .name = "" }, + { .fc_id = 563, .cpu_id = 412, .valid = 0, .name = "" }, + { .fc_id = 564, .cpu_id = 413, .valid = 0, .name = "" }, + { .fc_id = 565, .cpu_id = 414, .valid = 0, .name = "" }, + { .fc_id = 566, .cpu_id = 415, .valid = 0, .name = "" }, + { .fc_id = 567, .cpu_id = 416, .valid = 0, .name = "" }, + { .fc_id = 568, .cpu_id = 417, .valid = 0, .name = "" }, + { .fc_id = 569, .cpu_id = 418, .valid = 0, .name = "" }, + { .fc_id = 570, .cpu_id = 419, .valid = 0, .name = "" }, + { .fc_id = 571, .cpu_id = 420, .valid = 0, .name = "" }, + { .fc_id = 572, .cpu_id = 421, .valid = 1, .name = "TPC0_QM" }, + { .fc_id = 573, .cpu_id = 422, .valid = 1, .name = "TPC1_QM" }, + { .fc_id = 574, .cpu_id = 423, .valid = 1, .name = "TPC2_QM" }, + { .fc_id = 575, .cpu_id = 424, .valid = 1, .name = "TPC3_QM" }, + { .fc_id = 576, .cpu_id = 425, .valid = 1, .name = "TPC4_QM" }, + { .fc_id = 577, .cpu_id = 426, .valid = 1, .name = "TPC5_QM" }, + { .fc_id = 578, .cpu_id = 427, .valid = 1, .name = "TPC6_QM" }, + { .fc_id = 579, .cpu_id = 428, .valid = 1, .name = "TPC7_QM" }, + { .fc_id = 580, .cpu_id = 429, .valid = 0, .name = "" }, + { .fc_id = 581, .cpu_id = 430, .valid = 1, .name = "MME0_QM" }, + { .fc_id = 582, .cpu_id = 431, .valid = 1, .name = "MME2_QM" }, + { .fc_id = 583, .cpu_id = 432, .valid = 1, .name = "DMA0_QM" }, + { .fc_id = 584, .cpu_id = 433, .valid = 1, .name = "DMA1_QM" }, + { .fc_id = 585, .cpu_id = 434, .valid = 1, .name = "DMA2_QM" }, + { .fc_id = 586, .cpu_id = 435, .valid = 1, .name = "DMA3_QM" }, + { .fc_id = 587, .cpu_id = 436, .valid = 1, .name = "DMA4_QM" }, + { .fc_id = 588, .cpu_id = 437, .valid = 1, .name = "DMA5_QM" }, + { .fc_id = 589, .cpu_id = 438, .valid = 1, .name = "DMA6_QM" }, + { .fc_id = 590, .cpu_id = 439, .valid = 1, .name = "DMA7_QM" }, + { .fc_id = 591, .cpu_id = 440, .valid = 0, .name = "" }, + { .fc_id = 592, .cpu_id = 441, .valid = 0, .name = "" }, + { .fc_id = 593, .cpu_id = 442, .valid = 0, .name = "" }, + { .fc_id = 594, .cpu_id = 443, .valid = 1, .name = "NIC0_QM0" }, + { .fc_id = 595, .cpu_id = 444, .valid = 1, .name = "NIC0_QM1" }, + { .fc_id = 596, .cpu_id = 445, .valid = 1, .name = "NIC1_QM0" }, + { .fc_id = 597, .cpu_id = 446, .valid = 1, .name = "NIC1_QM1" }, + { .fc_id = 598, .cpu_id = 447, .valid = 1, .name = "NIC2_QM0" }, + { .fc_id = 599, .cpu_id = 448, .valid = 1, .name = "NIC2_QM1" }, + { .fc_id = 600, .cpu_id = 449, .valid = 1, .name = "NIC3_QM0" }, + { .fc_id = 601, .cpu_id = 450, .valid = 1, .name = "NIC3_QM1" }, + { .fc_id = 602, .cpu_id = 451, .valid = 1, .name = "NIC4_QM0" }, + { .fc_id = 603, .cpu_id = 452, .valid = 1, .name = "NIC4_QM1" }, + { .fc_id = 604, .cpu_id = 453, .valid = 1, .name = "DMA0_CORE" }, + { .fc_id = 605, .cpu_id = 454, .valid = 1, .name = "DMA1_CORE" }, + { .fc_id = 606, .cpu_id = 455, .valid = 1, .name = "DMA2_CORE" }, + { .fc_id = 607, .cpu_id = 456, .valid = 1, .name = "DMA3_CORE" }, + { .fc_id = 608, .cpu_id = 457, .valid = 1, .name = "DMA4_CORE" }, + { .fc_id = 609, .cpu_id = 458, .valid = 1, .name = "DMA5_CORE" }, + { .fc_id = 610, .cpu_id = 459, .valid = 1, .name = "DMA6_CORE" }, + { .fc_id = 611, .cpu_id = 460, .valid = 1, .name = "DMA7_CORE" }, + { .fc_id = 612, .cpu_id = 461, .valid = 1, .name = "NIC0_QP0" }, + { .fc_id = 613, .cpu_id = 462, .valid = 1, .name = "NIC0_QP1" }, + { .fc_id = 614, .cpu_id = 463, .valid = 1, .name = "NIC1_QP0" }, + { .fc_id = 615, .cpu_id = 464, .valid = 1, .name = "NIC1_QP1" }, + { .fc_id = 616, .cpu_id = 465, .valid = 1, .name = "NIC2_QP0" }, + { .fc_id = 617, .cpu_id = 466, .valid = 1, .name = "NIC2_QP1" }, + { .fc_id = 618, .cpu_id = 467, .valid = 1, .name = "NIC3_QP0" }, + { .fc_id = 619, .cpu_id = 468, .valid = 1, .name = "NIC3_QP1" }, + { .fc_id = 620, .cpu_id = 469, .valid = 1, .name = "NIC4_QP0" }, + { .fc_id = 621, .cpu_id = 470, .valid = 1, .name = "NIC4_QP1" }, + { .fc_id = 622, .cpu_id = 471, .valid = 0, .name = "" }, + { .fc_id = 623, .cpu_id = 472, .valid = 0, .name = "" }, + { .fc_id = 624, .cpu_id = 473, .valid = 0, .name = "" }, + { .fc_id = 625, .cpu_id = 474, .valid = 0, .name = "" }, + { .fc_id = 626, .cpu_id = 475, .valid = 0, .name = "" }, + { .fc_id = 627, .cpu_id = 476, .valid = 0, .name = "" }, + { .fc_id = 628, .cpu_id = 477, .valid = 0, .name = "" }, + { .fc_id = 629, .cpu_id = 478, .valid = 0, .name = "" }, + { .fc_id = 630, .cpu_id = 479, .valid = 0, .name = "" }, + { .fc_id = 631, .cpu_id = 480, .valid = 0, .name = "" }, + { .fc_id = 632, .cpu_id = 481, .valid = 0, .name = "" }, + { .fc_id = 633, .cpu_id = 482, .valid = 0, .name = "" }, + { .fc_id = 634, .cpu_id = 483, .valid = 0, .name = "" }, + { .fc_id = 635, .cpu_id = 484, .valid = 0, .name = "" }, + { .fc_id = 636, .cpu_id = 485, .valid = 0, .name = "" }, + { .fc_id = 637, .cpu_id = 486, .valid = 0, .name = "" }, + { .fc_id = 638, .cpu_id = 487, .valid = 0, .name = "" }, + { .fc_id = 639, .cpu_id = 488, .valid = 0, .name = "" }, + { .fc_id = 640, .cpu_id = 489, .valid = 0, .name = "" }, + { .fc_id = 641, .cpu_id = 490, .valid = 0, .name = "" }, + { .fc_id = 642, .cpu_id = 491, .valid = 0, .name = "" }, + { .fc_id = 643, .cpu_id = 492, .valid = 0, .name = "" }, + { .fc_id = 644, .cpu_id = 493, .valid = 0, .name = "" }, + { .fc_id = 645, .cpu_id = 494, .valid = 0, .name = "" }, + { .fc_id = 646, .cpu_id = 495, .valid = 0, .name = "" }, + { .fc_id = 647, .cpu_id = 496, .valid = 0, .name = "" }, + { .fc_id = 648, .cpu_id = 497, .valid = 0, .name = "" }, + { .fc_id = 649, .cpu_id = 498, .valid = 0, .name = "" }, + { .fc_id = 650, .cpu_id = 499, .valid = 0, .name = "" }, + { .fc_id = 651, .cpu_id = 500, .valid = 0, .name = "" }, + { .fc_id = 652, .cpu_id = 501, .valid = 0, .name = "" }, + { .fc_id = 653, .cpu_id = 502, .valid = 0, .name = "" }, + { .fc_id = 654, .cpu_id = 503, .valid = 0, .name = "" }, + { .fc_id = 655, .cpu_id = 504, .valid = 0, .name = "" }, + { .fc_id = 656, .cpu_id = 505, .valid = 0, .name = "" }, + { .fc_id = 657, .cpu_id = 506, .valid = 0, .name = "" }, + { .fc_id = 658, .cpu_id = 507, .valid = 1, .name = "FIX_POWER_ENV_S" }, + { .fc_id = 659, .cpu_id = 508, .valid = 1, .name = "FIX_POWER_ENV_E" }, + { .fc_id = 660, .cpu_id = 509, .valid = 1, + .name = "FIX_THERMAL_ENV_S" }, + { .fc_id = 661, .cpu_id = 510, .valid = 1, + .name = "FIX_THERMAL_ENV_E" }, + { .fc_id = 662, .cpu_id = 511, .valid = 1, .name = "RAZWI_OR_ADC_SW" }, +}; + +#endif /* __GAUDI_ASYNC_IDS_MAP_EVENTS_EXT_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h b/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h new file mode 100644 index 000000000000..c45cc7f4d4d7 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_coresight.h @@ -0,0 +1,367 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_CORESIGHT_H +#define GAUDI_CORESIGHT_H + +enum gaudi_debug_stm_regs_index { + GAUDI_STM_FIRST = 0, + GAUDI_STM_MME0_ACC = GAUDI_STM_FIRST, + GAUDI_STM_MME0_SBAB, + GAUDI_STM_MME0_CTRL, + GAUDI_STM_MME1_ACC, + GAUDI_STM_MME1_SBAB, + GAUDI_STM_MME1_CTRL, + GAUDI_STM_MME2_ACC, + GAUDI_STM_MME2_SBAB, + GAUDI_STM_MME2_CTRL, + GAUDI_STM_MME3_ACC, + GAUDI_STM_MME3_SBAB, + GAUDI_STM_MME3_CTRL, + GAUDI_STM_DMA_IF_W_S, + GAUDI_STM_DMA_IF_E_S, + GAUDI_STM_DMA_IF_W_N, + GAUDI_STM_DMA_IF_E_N, + GAUDI_STM_CPU, + GAUDI_STM_DMA_CH_0_CS, + GAUDI_STM_DMA_CH_1_CS, + GAUDI_STM_DMA_CH_2_CS, + GAUDI_STM_DMA_CH_3_CS, + GAUDI_STM_DMA_CH_4_CS, + GAUDI_STM_DMA_CH_5_CS, + GAUDI_STM_DMA_CH_6_CS, + GAUDI_STM_DMA_CH_7_CS, + GAUDI_STM_PCIE, + GAUDI_STM_MMU_CS, + GAUDI_STM_PSOC, + GAUDI_STM_NIC0_0, + GAUDI_STM_NIC0_1, + GAUDI_STM_NIC1_0, + GAUDI_STM_NIC1_1, + GAUDI_STM_NIC2_0, + GAUDI_STM_NIC2_1, + GAUDI_STM_NIC3_0, + GAUDI_STM_NIC3_1, + GAUDI_STM_NIC4_0, + GAUDI_STM_NIC4_1, + GAUDI_STM_TPC0_EML, + GAUDI_STM_TPC1_EML, + GAUDI_STM_TPC2_EML, + GAUDI_STM_TPC3_EML, + GAUDI_STM_TPC4_EML, + GAUDI_STM_TPC5_EML, + GAUDI_STM_TPC6_EML, + GAUDI_STM_TPC7_EML, + GAUDI_STM_LAST = GAUDI_STM_TPC7_EML +}; + +enum gaudi_debug_etf_regs_index { + GAUDI_ETF_FIRST = 0, + GAUDI_ETF_MME0_ACC = GAUDI_ETF_FIRST, + GAUDI_ETF_MME0_SBAB, + GAUDI_ETF_MME0_CTRL, + GAUDI_ETF_MME1_ACC, + GAUDI_ETF_MME1_SBAB, + GAUDI_ETF_MME1_CTRL, + GAUDI_ETF_MME2_ACC, + GAUDI_ETF_MME2_SBAB, + GAUDI_ETF_MME2_CTRL, + GAUDI_ETF_MME3_ACC, + GAUDI_ETF_MME3_SBAB, + GAUDI_ETF_MME3_CTRL, + GAUDI_ETF_DMA_IF_W_S, + GAUDI_ETF_DMA_IF_E_S, + GAUDI_ETF_DMA_IF_W_N, + GAUDI_ETF_DMA_IF_E_N, + GAUDI_ETF_CPU_0, + GAUDI_ETF_CPU_1, + GAUDI_ETF_CPU_TRACE, + GAUDI_ETF_DMA_CH_0_CS, + GAUDI_ETF_DMA_CH_1_CS, + GAUDI_ETF_DMA_CH_2_CS, + GAUDI_ETF_DMA_CH_3_CS, + GAUDI_ETF_DMA_CH_4_CS, + GAUDI_ETF_DMA_CH_5_CS, + GAUDI_ETF_DMA_CH_6_CS, + GAUDI_ETF_DMA_CH_7_CS, + GAUDI_ETF_PCIE, + GAUDI_ETF_MMU_CS, + GAUDI_ETF_PSOC, + GAUDI_ETF_NIC0_0, + GAUDI_ETF_NIC0_1, + GAUDI_ETF_NIC1_0, + GAUDI_ETF_NIC1_1, + GAUDI_ETF_NIC2_0, + GAUDI_ETF_NIC2_1, + GAUDI_ETF_NIC3_0, + GAUDI_ETF_NIC3_1, + GAUDI_ETF_NIC4_0, + GAUDI_ETF_NIC4_1, + GAUDI_ETF_TPC0_EML, + GAUDI_ETF_TPC1_EML, + GAUDI_ETF_TPC2_EML, + GAUDI_ETF_TPC3_EML, + GAUDI_ETF_TPC4_EML, + GAUDI_ETF_TPC5_EML, + GAUDI_ETF_TPC6_EML, + GAUDI_ETF_TPC7_EML, + GAUDI_ETF_LAST = GAUDI_ETF_TPC7_EML +}; + +enum gaudi_debug_funnel_regs_index { + GAUDI_FUNNEL_FIRST = 0, + GAUDI_FUNNEL_MME0_ACC = GAUDI_FUNNEL_FIRST, + GAUDI_FUNNEL_MME1_ACC, + GAUDI_FUNNEL_MME2_ACC, + GAUDI_FUNNEL_MME3_ACC, + GAUDI_FUNNEL_SRAM_Y0_X0, + GAUDI_FUNNEL_SRAM_Y0_X1, + GAUDI_FUNNEL_SRAM_Y0_X2, + GAUDI_FUNNEL_SRAM_Y0_X3, + GAUDI_FUNNEL_SRAM_Y0_X4, + GAUDI_FUNNEL_SRAM_Y0_X5, + GAUDI_FUNNEL_SRAM_Y0_X6, + GAUDI_FUNNEL_SRAM_Y0_X7, + GAUDI_FUNNEL_SRAM_Y1_X0, + GAUDI_FUNNEL_SRAM_Y1_X1, + GAUDI_FUNNEL_SRAM_Y1_X2, + GAUDI_FUNNEL_SRAM_Y1_X3, + GAUDI_FUNNEL_SRAM_Y1_X4, + GAUDI_FUNNEL_SRAM_Y1_X5, + GAUDI_FUNNEL_SRAM_Y1_X6, + GAUDI_FUNNEL_SRAM_Y1_X7, + GAUDI_FUNNEL_SRAM_Y2_X0, + GAUDI_FUNNEL_SRAM_Y2_X1, + GAUDI_FUNNEL_SRAM_Y2_X2, + GAUDI_FUNNEL_SRAM_Y2_X3, + GAUDI_FUNNEL_SRAM_Y2_X4, + GAUDI_FUNNEL_SRAM_Y2_X5, + GAUDI_FUNNEL_SRAM_Y2_X6, + GAUDI_FUNNEL_SRAM_Y2_X7, + GAUDI_FUNNEL_SRAM_Y3_X0, + GAUDI_FUNNEL_SRAM_Y3_X1, + GAUDI_FUNNEL_SRAM_Y3_X2, + GAUDI_FUNNEL_SRAM_Y3_X4, + GAUDI_FUNNEL_SRAM_Y3_X3, + GAUDI_FUNNEL_SRAM_Y3_X5, + GAUDI_FUNNEL_SRAM_Y3_X6, + GAUDI_FUNNEL_SRAM_Y3_X7, + GAUDI_FUNNEL_SIF_0, + GAUDI_FUNNEL_SIF_1, + GAUDI_FUNNEL_SIF_2, + GAUDI_FUNNEL_SIF_3, + GAUDI_FUNNEL_SIF_4, + GAUDI_FUNNEL_SIF_5, + GAUDI_FUNNEL_SIF_6, + GAUDI_FUNNEL_SIF_7, + GAUDI_FUNNEL_NIF_0, + GAUDI_FUNNEL_NIF_1, + GAUDI_FUNNEL_NIF_2, + GAUDI_FUNNEL_NIF_3, + GAUDI_FUNNEL_NIF_4, + GAUDI_FUNNEL_NIF_5, + GAUDI_FUNNEL_NIF_6, + GAUDI_FUNNEL_NIF_7, + GAUDI_FUNNEL_DMA_IF_W_S, + GAUDI_FUNNEL_DMA_IF_E_S, + GAUDI_FUNNEL_DMA_IF_W_N, + GAUDI_FUNNEL_DMA_IF_E_N, + GAUDI_FUNNEL_CPU, + GAUDI_FUNNEL_NIC_TPC_W_S, + GAUDI_FUNNEL_NIC_TPC_E_S, + GAUDI_FUNNEL_NIC_TPC_W_N, + GAUDI_FUNNEL_NIC_TPC_E_N, + GAUDI_FUNNEL_PCIE, + GAUDI_FUNNEL_PSOC, + GAUDI_FUNNEL_NIC0, + GAUDI_FUNNEL_NIC1, + GAUDI_FUNNEL_NIC2, + GAUDI_FUNNEL_NIC3, + GAUDI_FUNNEL_NIC4, + GAUDI_FUNNEL_TPC0_EML, + GAUDI_FUNNEL_TPC1_EML, + GAUDI_FUNNEL_TPC2_EML, + GAUDI_FUNNEL_TPC3_EML, + GAUDI_FUNNEL_TPC4_EML, + GAUDI_FUNNEL_TPC5_EML, + GAUDI_FUNNEL_TPC6_EML, + GAUDI_FUNNEL_TPC7_EML, + GAUDI_FUNNEL_LAST = GAUDI_FUNNEL_TPC7_EML +}; + +enum gaudi_debug_bmon_regs_index { + GAUDI_BMON_FIRST = 0, + GAUDI_BMON_MME0_ACC_0 = GAUDI_BMON_FIRST, + GAUDI_BMON_MME0_SBAB_0, + GAUDI_BMON_MME0_SBAB_1, + GAUDI_BMON_MME0_CTRL_0, + GAUDI_BMON_MME0_CTRL_1, + GAUDI_BMON_MME1_ACC_0, + GAUDI_BMON_MME1_SBAB_0, + GAUDI_BMON_MME1_SBAB_1, + GAUDI_BMON_MME1_CTRL_0, + GAUDI_BMON_MME1_CTRL_1, + GAUDI_BMON_MME2_ACC_0, + GAUDI_BMON_MME2_SBAB_0, + GAUDI_BMON_MME2_SBAB_1, + GAUDI_BMON_MME2_CTRL_0, + GAUDI_BMON_MME2_CTRL_1, + GAUDI_BMON_MME3_ACC_0, + GAUDI_BMON_MME3_SBAB_0, + GAUDI_BMON_MME3_SBAB_1, + GAUDI_BMON_MME3_CTRL_0, + GAUDI_BMON_MME3_CTRL_1, + GAUDI_BMON_DMA_IF_W_S_SOB_WR, + GAUDI_BMON_DMA_IF_W_S_0_WR, + GAUDI_BMON_DMA_IF_W_S_0_RD, + GAUDI_BMON_DMA_IF_W_S_1_WR, + GAUDI_BMON_DMA_IF_W_S_1_RD, + GAUDI_BMON_DMA_IF_E_S_SOB_WR, + GAUDI_BMON_DMA_IF_E_S_0_WR, + GAUDI_BMON_DMA_IF_E_S_0_RD, + GAUDI_BMON_DMA_IF_E_S_1_WR, + GAUDI_BMON_DMA_IF_E_S_1_RD, + GAUDI_BMON_DMA_IF_W_N_SOB_WR, + GAUDI_BMON_DMA_IF_W_N_HBM0_WR, + GAUDI_BMON_DMA_IF_W_N_HBM0_RD, + GAUDI_BMON_DMA_IF_W_N_HBM1_WR, + GAUDI_BMON_DMA_IF_W_N_HBM1_RD, + GAUDI_BMON_DMA_IF_E_N_SOB_WR, + GAUDI_BMON_DMA_IF_E_N_HBM0_WR, + GAUDI_BMON_DMA_IF_E_N_HBM0_RD, + GAUDI_BMON_DMA_IF_E_N_HBM1_WR, + GAUDI_BMON_DMA_IF_E_N_HBM1_RD, + GAUDI_BMON_CPU_WR, + GAUDI_BMON_CPU_RD, + GAUDI_BMON_DMA_CH_0_0, + GAUDI_BMON_DMA_CH_0_1, + GAUDI_BMON_DMA_CH_1_0, + GAUDI_BMON_DMA_CH_1_1, + GAUDI_BMON_DMA_CH_2_0, + GAUDI_BMON_DMA_CH_2_1, + GAUDI_BMON_DMA_CH_3_0, + GAUDI_BMON_DMA_CH_3_1, + GAUDI_BMON_DMA_CH_4_0, + GAUDI_BMON_DMA_CH_4_1, + GAUDI_BMON_DMA_CH_5_0, + GAUDI_BMON_DMA_CH_5_1, + GAUDI_BMON_DMA_CH_6_0, + GAUDI_BMON_DMA_CH_6_1, + GAUDI_BMON_DMA_CH_7_0, + GAUDI_BMON_DMA_CH_7_1, + GAUDI_BMON_PCIE_MSTR_WR, + GAUDI_BMON_PCIE_MSTR_RD, + GAUDI_BMON_PCIE_SLV_WR, + GAUDI_BMON_PCIE_SLV_RD, + GAUDI_BMON_MMU_0, + GAUDI_BMON_MMU_1, + GAUDI_BMON_NIC0_0, + GAUDI_BMON_NIC0_1, + GAUDI_BMON_NIC0_2, + GAUDI_BMON_NIC0_3, + GAUDI_BMON_NIC0_4, + GAUDI_BMON_NIC1_0, + GAUDI_BMON_NIC1_1, + GAUDI_BMON_NIC1_2, + GAUDI_BMON_NIC1_3, + GAUDI_BMON_NIC1_4, + GAUDI_BMON_NIC2_0, + GAUDI_BMON_NIC2_1, + GAUDI_BMON_NIC2_2, + GAUDI_BMON_NIC2_3, + GAUDI_BMON_NIC2_4, + GAUDI_BMON_NIC3_0, + GAUDI_BMON_NIC3_1, + GAUDI_BMON_NIC3_2, + GAUDI_BMON_NIC3_3, + GAUDI_BMON_NIC3_4, + GAUDI_BMON_NIC4_0, + GAUDI_BMON_NIC4_1, + GAUDI_BMON_NIC4_2, + GAUDI_BMON_NIC4_3, + GAUDI_BMON_NIC4_4, + GAUDI_BMON_TPC0_EML_0, + GAUDI_BMON_TPC0_EML_1, + GAUDI_BMON_TPC0_EML_2, + GAUDI_BMON_TPC0_EML_3, + GAUDI_BMON_TPC1_EML_0, + GAUDI_BMON_TPC1_EML_1, + GAUDI_BMON_TPC1_EML_2, + GAUDI_BMON_TPC1_EML_3, + GAUDI_BMON_TPC2_EML_0, + GAUDI_BMON_TPC2_EML_1, + GAUDI_BMON_TPC2_EML_2, + GAUDI_BMON_TPC2_EML_3, + GAUDI_BMON_TPC3_EML_0, + GAUDI_BMON_TPC3_EML_1, + GAUDI_BMON_TPC3_EML_2, + GAUDI_BMON_TPC3_EML_3, + GAUDI_BMON_TPC4_EML_0, + GAUDI_BMON_TPC4_EML_1, + GAUDI_BMON_TPC4_EML_2, + GAUDI_BMON_TPC4_EML_3, + GAUDI_BMON_TPC5_EML_0, + GAUDI_BMON_TPC5_EML_1, + GAUDI_BMON_TPC5_EML_2, + GAUDI_BMON_TPC5_EML_3, + GAUDI_BMON_TPC6_EML_0, + GAUDI_BMON_TPC6_EML_1, + GAUDI_BMON_TPC6_EML_2, + GAUDI_BMON_TPC6_EML_3, + GAUDI_BMON_TPC7_EML_0, + GAUDI_BMON_TPC7_EML_1, + GAUDI_BMON_TPC7_EML_2, + GAUDI_BMON_TPC7_EML_3, + GAUDI_BMON_LAST = GAUDI_BMON_TPC7_EML_3 +}; + +enum gaudi_debug_spmu_regs_index { + GAUDI_SPMU_FIRST = 0, + GAUDI_SPMU_MME0_ACC = GAUDI_SPMU_FIRST, + GAUDI_SPMU_MME0_SBAB, + GAUDI_SPMU_MME0_CTRL, + GAUDI_SPMU_MME1_ACC, + GAUDI_SPMU_MME1_SBAB, + GAUDI_SPMU_MME1_CTRL, + GAUDI_SPMU_MME2_MME2_ACC, + GAUDI_SPMU_MME2_SBAB, + GAUDI_SPMU_MME2_CTRL, + GAUDI_SPMU_MME3_ACC, + GAUDI_SPMU_MME3_SBAB, + GAUDI_SPMU_MME3_CTRL, + GAUDI_SPMU_DMA_CH_0_CS, + GAUDI_SPMU_DMA_CH_1_CS, + GAUDI_SPMU_DMA_CH_2_CS, + GAUDI_SPMU_DMA_CH_3_CS, + GAUDI_SPMU_DMA_CH_4_CS, + GAUDI_SPMU_DMA_CH_5_CS, + GAUDI_SPMU_DMA_CH_6_CS, + GAUDI_SPMU_DMA_CH_7_CS, + GAUDI_SPMU_PCIE, + GAUDI_SPMU_MMU_CS, + GAUDI_SPMU_NIC0_0, + GAUDI_SPMU_NIC0_1, + GAUDI_SPMU_NIC1_0, + GAUDI_SPMU_NIC1_1, + GAUDI_SPMU_NIC2_0, + GAUDI_SPMU_NIC2_1, + GAUDI_SPMU_NIC3_0, + GAUDI_SPMU_NIC3_1, + GAUDI_SPMU_NIC4_0, + GAUDI_SPMU_NIC4_1, + GAUDI_SPMU_TPC0_EML, + GAUDI_SPMU_TPC1_EML, + GAUDI_SPMU_TPC2_EML, + GAUDI_SPMU_TPC3_EML, + GAUDI_SPMU_TPC4_EML, + GAUDI_SPMU_TPC5_EML, + GAUDI_SPMU_TPC6_EML, + GAUDI_SPMU_TPC7_EML, + GAUDI_SPMU_LAST = GAUDI_SPMU_TPC7_EML +}; + +#endif /* GAUDI_CORESIGHT_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h new file mode 100644 index 000000000000..8aadc6357da1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_fw_if.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_FW_IF_H +#define GAUDI_FW_IF_H + +#define GAUDI_EVENT_QUEUE_MSI_IDX 8 +#define GAUDI_NIC_PORT1_MSI_IDX 10 +#define GAUDI_NIC_PORT3_MSI_IDX 12 +#define GAUDI_NIC_PORT5_MSI_IDX 14 +#define GAUDI_NIC_PORT7_MSI_IDX 16 +#define GAUDI_NIC_PORT9_MSI_IDX 18 + +#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ +#define LINUX_FW_OFFSET 0x800000 /* 8MB in HBM */ + +enum gaudi_pll_index { + CPU_PLL = 0, + PCI_PLL, + SRAM_PLL, + HBM_PLL, + NIC_PLL, + DMA_PLL, + MESH_PLL, + MME_PLL, + TPC_PLL, + IF_PLL +}; + +#define GAUDI_PLL_FREQ_LOW 200000000 /* 200 MHz */ + +#endif /* GAUDI_FW_IF_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h new file mode 100644 index 000000000000..96f08050ef0f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_masks.h @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_MASKS_H_ +#define GAUDI_MASKS_H_ + +#include "asic_reg/gaudi_regs.h" + +/* Useful masks for bits in various registers */ +#define PCI_DMA_QMAN_ENABLE (\ + (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_EXTERNAL_MAKE_TRUSTED (\ + (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \ + (0xF << DMA0_QM_GLBL_PROT_CQF_SHIFT) | \ + (0xF << DMA0_QM_GLBL_PROT_CP_SHIFT) | \ + (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT)) + +#define QMAN_INTERNAL_MAKE_TRUSTED (\ + (0xF << DMA0_QM_GLBL_PROT_PQF_SHIFT) | \ + (0x1 << DMA0_QM_GLBL_PROT_ERR_SHIFT)) + +#define HBM_DMA_QMAN_ENABLE (\ + (0xF << DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_MME_ENABLE (\ + (0xF << MME0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_TPC_ENABLE (\ + (0xF << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT)) + +#define QMAN_UPPER_CP_CGM_PWR_GATE_EN (\ + (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \ + (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \ + (0x10 << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \ + (1 << DMA0_QM_CGM_CFG_EN_SHIFT)) + +#define QMAN_COMMON_CP_CGM_PWR_GATE_EN (\ + (0x20 << DMA0_QM_CGM_CFG_IDLE_TH_SHIFT) | \ + (0xA << DMA0_QM_CGM_CFG_G2F_TH_SHIFT) | \ + (0xF << DMA0_QM_CGM_CFG_CP_IDLE_MASK_SHIFT) | \ + (1 << DMA0_QM_CGM_CFG_EN_SHIFT)) + +#define PCI_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define PCI_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0xF << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define HBM_DMA_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define HBM_DMA_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << DMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << DMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define TPC_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define TPC_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define MME_QMAN_GLBL_ERR_CFG_MSG_EN_MASK (\ + (0xF << MME0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) + +#define MME_QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK (\ + (0xF << MME0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ + (0x1F << MME0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) + +#define QMAN_CGM1_PWR_GATE_EN (0xA << DMA0_QM_CGM_CFG1_MASK_TH_SHIFT) + +/* RESET registers configuration */ +#define CFG_RST_L_PSOC_SHIFT 0 +#define CFG_RST_L_PCIE_SHIFT 1 +#define CFG_RST_L_PCIE_IF_SHIFT 2 +#define CFG_RST_L_HBM_S_PLL_SHIFT 3 +#define CFG_RST_L_TPC_S_PLL_SHIFT 4 +#define CFG_RST_L_MME_S_PLL_SHIFT 5 +#define CFG_RST_L_CPU_PLL_SHIFT 6 +#define CFG_RST_L_PCIE_PLL_SHIFT 7 +#define CFG_RST_L_NIC_S_PLL_SHIFT 8 +#define CFG_RST_L_HBM_N_PLL_SHIFT 9 +#define CFG_RST_L_TPC_N_PLL_SHIFT 10 +#define CFG_RST_L_MME_N_PLL_SHIFT 11 +#define CFG_RST_L_NIC_N_PLL_SHIFT 12 +#define CFG_RST_L_DMA_W_PLL_SHIFT 13 +#define CFG_RST_L_SIF_W_PLL_SHIFT 14 +#define CFG_RST_L_MESH_W_PLL_SHIFT 15 +#define CFG_RST_L_SRAM_W_PLL_SHIFT 16 +#define CFG_RST_L_DMA_E_PLL_SHIFT 17 +#define CFG_RST_L_SIF_E_PLL_SHIFT 18 +#define CFG_RST_L_MESH_E_PLL_SHIFT 19 +#define CFG_RST_L_SRAM_E_PLL_SHIFT 20 +#define CFG_RST_L_IF_1_SHIFT 21 +#define CFG_RST_L_IF_0_SHIFT 22 +#define CFG_RST_L_IF_2_SHIFT 23 +#define CFG_RST_L_IF_3_SHIFT 24 +#define CFG_RST_L_TPC_0_SHIFT 25 +#define CFG_RST_L_TPC_1_SHIFT 26 +#define CFG_RST_L_TPC_2_SHIFT 27 +#define CFG_RST_L_TPC_3_SHIFT 28 +#define CFG_RST_L_TPC_4_SHIFT 29 +#define CFG_RST_L_TPC_5_SHIFT 30 +#define CFG_RST_L_TPC_6_SHIFT 31 +#define CFG_RST_H_TPC_7_SHIFT 0 +#define CFG_RST_H_MME_0_SHIFT 1 +#define CFG_RST_H_MME_1_SHIFT 2 +#define CFG_RST_H_MME_2_SHIFT 3 +#define CFG_RST_H_MME_3_SHIFT 4 +#define CFG_RST_H_HBM_0_SHIFT 5 +#define CFG_RST_H_HBM_1_SHIFT 6 +#define CFG_RST_H_HBM_2_SHIFT 7 +#define CFG_RST_H_HBM_3_SHIFT 8 +#define CFG_RST_H_NIC_0_SHIFT 9 +#define CFG_RST_H_NIC_1_SHIFT 10 +#define CFG_RST_H_NIC_2_SHIFT 11 +#define CFG_RST_H_NIC_3_SHIFT 12 +#define CFG_RST_H_NIC_4_SHIFT 13 +#define CFG_RST_H_SM_0_SHIFT 14 +#define CFG_RST_H_SM_1_SHIFT 15 +#define CFG_RST_H_SM_2_SHIFT 16 +#define CFG_RST_H_SM_3_SHIFT 17 +#define CFG_RST_H_DMA_0_SHIFT 18 +#define CFG_RST_H_DMA_1_SHIFT 19 +#define CFG_RST_H_CPU_SHIFT 20 +#define CFG_RST_H_MMU_SHIFT 21 + + +#define CFG_RST_H_DMA_MASK ((1 << CFG_RST_H_DMA_0_SHIFT) | \ + (1 << CFG_RST_H_DMA_1_SHIFT)) + +#define CFG_RST_H_CPU_MASK (1 << CFG_RST_H_CPU_SHIFT) +#define CFG_RST_H_MMU_MASK (1 << CFG_RST_H_MMU_SHIFT) + +#define CFG_RST_H_HBM_MASK ((1 << CFG_RST_H_HBM_0_SHIFT) | \ + (1 << CFG_RST_H_HBM_1_SHIFT) | \ + (1 << CFG_RST_H_HBM_2_SHIFT) | \ + (1 << CFG_RST_H_HBM_3_SHIFT)) + +#define CFG_RST_H_NIC_MASK ((1 << CFG_RST_H_NIC_0_SHIFT) | \ + (1 << CFG_RST_H_NIC_1_SHIFT) | \ + (1 << CFG_RST_H_NIC_2_SHIFT) | \ + (1 << CFG_RST_H_NIC_3_SHIFT) | \ + (1 << CFG_RST_H_NIC_4_SHIFT)) + +#define CFG_RST_H_SM_MASK ((1 << CFG_RST_H_SM_0_SHIFT) | \ + (1 << CFG_RST_H_SM_1_SHIFT) | \ + (1 << CFG_RST_H_SM_2_SHIFT) | \ + (1 << CFG_RST_H_SM_3_SHIFT)) + +#define CFG_RST_H_MME_MASK ((1 << CFG_RST_H_MME_0_SHIFT) | \ + (1 << CFG_RST_H_MME_1_SHIFT) | \ + (1 << CFG_RST_H_MME_2_SHIFT) | \ + (1 << CFG_RST_H_MME_3_SHIFT)) + +#define CFG_RST_L_PSOC_MASK (1 << CFG_RST_L_PSOC_SHIFT) + +#define CFG_RST_L_IF_MASK ((1 << CFG_RST_L_IF_0_SHIFT) | \ + (1 << CFG_RST_L_IF_1_SHIFT) | \ + (1 << CFG_RST_L_IF_2_SHIFT) | \ + (1 << CFG_RST_L_IF_3_SHIFT)) + +#define CFG_RST_L_TPC_MASK ((1 << CFG_RST_L_TPC_0_SHIFT) | \ + (1 << CFG_RST_L_TPC_1_SHIFT) | \ + (1 << CFG_RST_L_TPC_2_SHIFT) | \ + (1 << CFG_RST_L_TPC_3_SHIFT) | \ + (1 << CFG_RST_L_TPC_4_SHIFT) | \ + (1 << CFG_RST_L_TPC_5_SHIFT) | \ + (1 << CFG_RST_L_TPC_6_SHIFT)) + +#define CFG_RST_H_TPC_MASK (1 << CFG_RST_H_TPC_7_SHIFT) + +#define CA53_RESET (1 << CFG_RST_H_CPU_SHIFT) + +#define UNIT_RST_L_PSOC_SHIFT 0 +#define UNIT_RST_L_PCIE_SHIFT 1 +#define UNIT_RST_L_PCIE_IF_SHIFT 2 +#define UNIT_RST_L_HBM_S_PLL_SHIFT 3 +#define UNIT_RST_L_TPC_S_PLL_SHIFT 4 +#define UNIT_RST_L_MME_S_PLL_SHIFT 5 +#define UNIT_RST_L_CPU_PLL_SHIFT 6 +#define UNIT_RST_L_PCIE_PLL_SHIFT 7 +#define UNIT_RST_L_NIC_S_PLL_SHIFT 8 +#define UNIT_RST_L_HBM_N_PLL_SHIFT 9 +#define UNIT_RST_L_TPC_N_PLL_SHIFT 10 +#define UNIT_RST_L_MME_N_PLL_SHIFT 11 +#define UNIT_RST_L_NIC_N_PLL_SHIFT 12 +#define UNIT_RST_L_DMA_W_PLL_SHIFT 13 +#define UNIT_RST_L_SIF_W_PLL_SHIFT 14 +#define UNIT_RST_L_MESH_W_PLL_SHIFT 15 +#define UNIT_RST_L_SRAM_W_PLL_SHIFT 16 +#define UNIT_RST_L_DMA_E_PLL_SHIFT 17 +#define UNIT_RST_L_SIF_E_PLL_SHIFT 18 +#define UNIT_RST_L_MESH_E_PLL_SHIFT 19 +#define UNIT_RST_L_SRAM_E_PLL_SHIFT 20 +#define UNIT_RST_L_TPC_0_SHIFT 21 +#define UNIT_RST_L_TPC_1_SHIFT 22 +#define UNIT_RST_L_TPC_2_SHIFT 23 +#define UNIT_RST_L_TPC_3_SHIFT 24 +#define UNIT_RST_L_TPC_4_SHIFT 25 +#define UNIT_RST_L_TPC_5_SHIFT 26 +#define UNIT_RST_L_TPC_6_SHIFT 27 +#define UNIT_RST_L_TPC_7_SHIFT 28 +#define UNIT_RST_L_MME_0_SHIFT 29 +#define UNIT_RST_L_MME_1_SHIFT 30 +#define UNIT_RST_L_MME_2_SHIFT 31 + +#define UNIT_RST_H_MME_3_SHIFT 0 +#define UNIT_RST_H_HBM_0_SHIFT 1 +#define UNIT_RST_H_HBM_1_SHIFT 2 +#define UNIT_RST_H_HBM_2_SHIFT 3 +#define UNIT_RST_H_HBM_3_SHIFT 4 +#define UNIT_RST_H_NIC_0_SHIFT 5 +#define UNIT_RST_H_NIC_1_SHIFT 6 +#define UNIT_RST_H_NIC_2_SHIFT 7 +#define UNIT_RST_H_NIC_3_SHIFT 8 +#define UNIT_RST_H_NIC_4_SHIFT 9 +#define UNIT_RST_H_SM_0_SHIFT 10 +#define UNIT_RST_H_SM_1_SHIFT 11 +#define UNIT_RST_H_SM_2_SHIFT 12 +#define UNIT_RST_H_SM_3_SHIFT 13 +#define UNIT_RST_H_IF_0_SHIFT 14 +#define UNIT_RST_H_IF_1_SHIFT 15 +#define UNIT_RST_H_IF_2_SHIFT 16 +#define UNIT_RST_H_IF_3_SHIFT 17 +#define UNIT_RST_H_DMA_0_SHIFT 18 +#define UNIT_RST_H_DMA_1_SHIFT 19 +#define UNIT_RST_H_CPU_SHIFT 20 +#define UNIT_RST_H_MMU_SHIFT 21 + +#define UNIT_RST_H_HBM_MASK ((1 << UNIT_RST_H_HBM_0_SHIFT) | \ + (1 << UNIT_RST_H_HBM_1_SHIFT) | \ + (1 << UNIT_RST_H_HBM_2_SHIFT) | \ + (1 << UNIT_RST_H_HBM_3_SHIFT)) + +#define UNIT_RST_H_NIC_MASK ((1 << UNIT_RST_H_NIC_0_SHIFT) | \ + (1 << UNIT_RST_H_NIC_1_SHIFT) | \ + (1 << UNIT_RST_H_NIC_2_SHIFT) | \ + (1 << UNIT_RST_H_NIC_3_SHIFT) | \ + (1 << UNIT_RST_H_NIC_4_SHIFT)) + +#define UNIT_RST_H_SM_MASK ((1 << UNIT_RST_H_SM_0_SHIFT) | \ + (1 << UNIT_RST_H_SM_1_SHIFT) | \ + (1 << UNIT_RST_H_SM_2_SHIFT) | \ + (1 << UNIT_RST_H_SM_3_SHIFT)) + +#define UNIT_RST_H_MME_MASK ((1 << UNIT_RST_H_MME_0_SHIFT) | \ + (1 << UNIT_RST_H_MME_1_SHIFT) | \ + (1 << UNIT_RST_H_MME_2_SHIFT)) + +#define UNIT_RST_L_MME_MASK (1 << UNIT_RST_L_MME_3_SHIFT) + +#define UNIT_RST_L_IF_MASK ((1 << UNIT_RST_L_IF_0_SHIFT) | \ + (1 << UNIT_RST_L_IF_1_SHIFT) | \ + (1 << UNIT_RST_L_IF_2_SHIFT) | \ + (1 << UNIT_RST_L_IF_3_SHIFT)) + +#define UNIT_RST_L_TPC_MASK ((1 << UNIT_RST_L_TPC_0_SHIFT) | \ + (1 << UNIT_RST_L_TPC_1_SHIFT) | \ + (1 << UNIT_RST_L_TPC_2_SHIFT) | \ + (1 << UNIT_RST_L_TPC_3_SHIFT) | \ + (1 << UNIT_RST_L_TPC_4_SHIFT) | \ + (1 << UNIT_RST_L_TPC_5_SHIFT) | \ + (1 << UNIT_RST_L_TPC_6_SHIFT) | \ + (1 << UNIT_RST_L_TPC_7_SHIFT)) + +/* CPU_CA53_CFG_ARM_RST_CONTROL */ +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 +#define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 +#define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 + +#define CPU_RESET_ASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +#define CPU_RESET_CORE0_DEASSERT (\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ + 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) + +/* QM_IDLE_MASK is valid for all engines QM idle check */ +#define QM_IDLE_MASK (DMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ + DMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ + DMA0_QM_GLBL_STS0_CP_IDLE_MASK) + +/* CGM_IDLE_MASK is valid for all engines CGM idle check */ +#define CGM_IDLE_MASK DMA0_QM_CGM_STS_AGENT_IDLE_MASK + +#define TPC_IDLE_MASK ((1 << TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_IQ_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_SB_EMPTY_SHIFT) | \ + (1 << TPC0_CFG_STATUS_QM_IDLE_SHIFT) | \ + (1 << TPC0_CFG_STATUS_QM_RDY_SHIFT)) + +#define MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 +#define MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 +#define MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x1000 + +#define MME_ARCH_IDLE_MASK (MME0_CTRL_ARCH_STATUS_SB_A_EMPTY_MASK | \ + MME0_CTRL_ARCH_STATUS_SB_B_EMPTY_MASK | \ + MME0_CTRL_ARCH_STATUS_WBC_AXI_IDLE_MASK) + +#define IS_QM_IDLE(qm_glbl_sts0, qm_cgm_sts) \ + ((((qm_glbl_sts0) & QM_IDLE_MASK) == QM_IDLE_MASK) && \ + (((qm_cgm_sts) & CGM_IDLE_MASK) == CGM_IDLE_MASK)) + +#define IS_DMA_IDLE(dma_core_sts0) \ + !(dma_core_sts0 & DMA0_CORE_STS0_BUSY_MASK) + +#define IS_TPC_IDLE(tpc_cfg_sts) \ + (((tpc_cfg_sts) & TPC_IDLE_MASK) == TPC_IDLE_MASK) + +#define IS_MME_IDLE(mme_arch_sts) \ + (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) + +enum axi_id { + AXI_ID_MME, + AXI_ID_TPC, + AXI_ID_DMA, + AXI_ID_NIC, /* Local NIC */ + AXI_ID_PCI, + AXI_ID_CPU, + AXI_ID_PSOC, + AXI_ID_MMU, + AXI_ID_NIC_FT /* Feed-Through NIC */ +}; + +/* RAZWI initiator ID is built from the location in the chip and the AXI ID */ + +#define RAZWI_INITIATOR_AXI_ID_SHIFT 20 +#define RAZWI_INITIATOR_AXI_ID_MASK 0xF +#define RAZWI_INITIATOR_X_SHIFT 24 +#define RAZWI_INITIATOR_X_MASK 0xF +#define RAZWI_INITIATOR_Y_SHIFT 28 +#define RAZWI_INITIATOR_Y_MASK 0x7 + +#define RAZWI_INITIATOR_ID_AXI_ID(axi_id) \ + (((axi_id) & RAZWI_INITIATOR_AXI_ID_MASK) << \ + RAZWI_INITIATOR_AXI_ID_SHIFT) + +#define RAZWI_INITIATOR_ID_X_Y(x, y) \ + ((((y) & RAZWI_INITIATOR_Y_MASK) << RAZWI_INITIATOR_Y_SHIFT) | \ + (((x) & RAZWI_INITIATOR_X_MASK) << RAZWI_INITIATOR_X_SHIFT)) + +#define RAZWI_INITIATOR_ID_X_Y_TPC0_NIC0 RAZWI_INITIATOR_ID_X_Y(1, 0) +#define RAZWI_INITIATOR_ID_X_Y_TPC1 RAZWI_INITIATOR_ID_X_Y(2, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME0_0 RAZWI_INITIATOR_ID_X_Y(3, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME0_1 RAZWI_INITIATOR_ID_X_Y(4, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME1_0 RAZWI_INITIATOR_ID_X_Y(5, 0) +#define RAZWI_INITIATOR_ID_X_Y_MME1_1 RAZWI_INITIATOR_ID_X_Y(6, 0) +#define RAZWI_INITIATOR_ID_X_Y_TPC2 RAZWI_INITIATOR_ID_X_Y(7, 0) +#define RAZWI_INITIATOR_ID_X_Y_TPC3_PCI_CPU_PSOC \ + RAZWI_INITIATOR_ID_X_Y(8, 0) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_0 RAZWI_INITIATOR_ID_X_Y(0, 1) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_0 RAZWI_INITIATOR_ID_X_Y(9, 1) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_S_1 RAZWI_INITIATOR_ID_X_Y(0, 2) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_S_1 RAZWI_INITIATOR_ID_X_Y(9, 2) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_0 RAZWI_INITIATOR_ID_X_Y(0, 3) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_0 RAZWI_INITIATOR_ID_X_Y(9, 3) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_W_N_1 RAZWI_INITIATOR_ID_X_Y(0, 4) +#define RAZWI_INITIATOR_ID_X_Y_DMA_IF_E_N_1 RAZWI_INITIATOR_ID_X_Y(9, 4) +#define RAZWI_INITIATOR_ID_X_Y_TPC4_NIC1_NIC2 RAZWI_INITIATOR_ID_X_Y(1, 5) +#define RAZWI_INITIATOR_ID_X_Y_TPC5 RAZWI_INITIATOR_ID_X_Y(2, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME2_0 RAZWI_INITIATOR_ID_X_Y(3, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME2_1 RAZWI_INITIATOR_ID_X_Y(4, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME3_0 RAZWI_INITIATOR_ID_X_Y(5, 5) +#define RAZWI_INITIATOR_ID_X_Y_MME3_1 RAZWI_INITIATOR_ID_X_Y(6, 5) +#define RAZWI_INITIATOR_ID_X_Y_TPC6 RAZWI_INITIATOR_ID_X_Y(7, 5) +#define RAZWI_INITIATOR_ID_X_Y_TPC7_NIC4_NIC5 RAZWI_INITIATOR_ID_X_Y(8, 5) + +#define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 + +/* STLB_CACHE_INV */ +#define STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 +#define STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF +#define STLB_CACHE_INV_INDEX_MASK_SHIFT 8 +#define STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 + +#define MME_ACC_ACC_STALL_R_SHIFT 0 +#define MME_SBAB_SB_STALL_R_SHIFT 0 + +#define PCIE_WRAP_LBW_PROT_OVR_RD_EN_MASK 0x700 +#define PCIE_WRAP_LBW_PROT_OVR_WR_EN_MASK 0x7000 + +#define PCIE_WRAP_LBW_DRAIN_CFG_EN_SHIFT 0 +#define PCIE_WRAP_HBW_DRAIN_CFG_EN_SHIFT 0 + +/* DMA_IF_HBM_CRED_EN */ +#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_SHIFT 0 +#define DMA_IF_HBM_CRED_EN_READ_CREDIT_EN_MASK 0x1 +#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_SHIFT 1 +#define DMA_IF_HBM_CRED_EN_WRITE_CREDIT_EN_MASK 0x2 + +#define DMA_IF_DOWN_CHX_SCRAM_SRAM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_SCRAM_HBM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_E2E_HBM_EN_VAL_SHIFT 0 +#define DMA_IF_DOWN_CHX_E2E_PCI_EN_VAL_SHIFT 0 + +#define IF_RTR_CTRL_SCRAM_SRAM_EN_VAL_SHIFT 0 +#define IF_RTR_CTRL_SCRAM_HBM_EN_VAL_SHIFT 0 + +#define IF_RTR_CTRL_E2E_HBM_EN_VAL_SHIFT 0 +#define IF_RTR_CTRL_E2E_PCI_EN_VAL_SHIFT 0 + +/* MMU_UP_PAGE_ERROR_CAPTURE */ +#define MMU_UP_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_UP_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +/* MMU_UP_ACCESS_ERROR_CAPTURE */ +#define MMU_UP_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF +#define MMU_UP_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 + +#define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 +#define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 +#define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 + +#define QM_ARB_ERR_MSG_EN_MASK (\ + QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ + QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ + QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) + +#endif /* GAUDI_MASKS_H_ */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h b/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h new file mode 100644 index 000000000000..9a5800b0086b --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_packets.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2017-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_PACKETS_H +#define GAUDI_PACKETS_H + +#include <linux/types.h> + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull + +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_REPEAT = 0x6, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + PACKET_ARB_POINT = 0xC, + PACKET_WAIT = 0xD, + PACKET_LOAD_AND_EXE = 0xF, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +#define GAUDI_PKT_CTL_OPCODE_SHIFT 24 +#define GAUDI_PKT_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI_PKT_CTL_EB_SHIFT 29 +#define GAUDI_PKT_CTL_EB_MASK 0x20000000 + +#define GAUDI_PKT_CTL_RB_SHIFT 30 +#define GAUDI_PKT_CTL_RB_MASK 0x40000000 + +#define GAUDI_PKT_CTL_MB_SHIFT 31 +#define GAUDI_PKT_CTL_MB_MASK 0x80000000 + +/* All packets have, at least, an 8-byte header, which contains + * the packet type. The kernel driver uses the packet header for packet + * validation and to perform any necessary required preparation before + * sending them off to the hardware. + */ +struct gaudi_packet { + __le64 header; + /* The rest of the packet data follows. Use the corresponding + * packet_XXX struct to deference the data, based on packet type + */ + u8 contents[0]; +}; + +struct packet_nop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_stop { + __le32 reserved; + __le32 ctl; +}; + +struct packet_wreg32 { + __le32 value; + __le32 ctl; +}; + +struct packet_wreg_bulk { + __le32 size64; + __le32 ctl; + __le64 values[0]; /* data starts here */ +}; + +struct packet_msg_long { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_SHIFT 0 +#define GAUDI_PKT_SHORT_VAL_SOB_SYNC_VAL_MASK 0x0000EFFF + +#define GAUDI_PKT_SHORT_VAL_SOB_MOD_SHIFT 31 +#define GAUDI_PKT_SHORT_VAL_SOB_MOD_MASK 0x80000000 + +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_SHIFT 0 +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_GID_MASK 0x000000FF + +#define GAUDI_PKT_SHORT_VAL_MON_MASK_SHIFT 8 +#define GAUDI_PKT_SHORT_VAL_MON_MASK_MASK 0x0000FF00 + +#define GAUDI_PKT_SHORT_VAL_MON_MODE_SHIFT 16 +#define GAUDI_PKT_SHORT_VAL_MON_MODE_MASK 0x00010000 + +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_SHIFT 17 +#define GAUDI_PKT_SHORT_VAL_MON_SYNC_VAL_MASK 0xFFFE0000 + +#define GAUDI_PKT_SHORT_CTL_ADDR_SHIFT 0 +#define GAUDI_PKT_SHORT_CTL_ADDR_MASK 0x0000FFFF + +#define GAUDI_PKT_SHORT_CTL_OP_SHIFT 20 +#define GAUDI_PKT_SHORT_CTL_OP_MASK 0x00300000 + +#define GAUDI_PKT_SHORT_CTL_BASE_SHIFT 22 +#define GAUDI_PKT_SHORT_CTL_BASE_MASK 0x00C00000 + +#define GAUDI_PKT_SHORT_CTL_OPCODE_SHIFT 24 +#define GAUDI_PKT_SHORT_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI_PKT_SHORT_CTL_EB_SHIFT 29 +#define GAUDI_PKT_SHORT_CTL_EB_MASK 0x20000000 + +#define GAUDI_PKT_SHORT_CTL_RB_SHIFT 30 +#define GAUDI_PKT_SHORT_CTL_RB_MASK 0x40000000 + +#define GAUDI_PKT_SHORT_CTL_MB_SHIFT 31 +#define GAUDI_PKT_SHORT_CTL_MB_MASK 0x80000000 + +struct packet_msg_short { + __le32 value; + __le32 ctl; +}; + +struct packet_msg_prot { + __le32 value; + __le32 ctl; + __le64 addr; +}; + +#define GAUDI_PKT_FENCE_CFG_DEC_VAL_SHIFT 0 +#define GAUDI_PKT_FENCE_CFG_DEC_VAL_MASK 0x0000000F + +#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_SHIFT 16 +#define GAUDI_PKT_FENCE_CFG_TARGET_VAL_MASK 0x00FF0000 + +#define GAUDI_PKT_FENCE_CFG_ID_SHIFT 30 +#define GAUDI_PKT_FENCE_CFG_ID_MASK 0xC000000 + +#define GAUDI_PKT_FENCE_CTL_PRED_SHIFT 0 +#define GAUDI_PKT_FENCE_CTL_PRED_MASK 0x0000001F + +#define GAUDI_PKT_FENCE_CTL_OPCODE_SHIFT 24 +#define GAUDI_PKT_FENCE_CTL_OPCODE_MASK 0x1F000000 + +#define GAUDI_PKT_FENCE_CTL_EB_SHIFT 29 +#define GAUDI_PKT_FENCE_CTL_EB_MASK 0x20000000 + +#define GAUDI_PKT_FENCE_CTL_RB_SHIFT 30 +#define GAUDI_PKT_FENCE_CTL_RB_MASK 0x40000000 + +#define GAUDI_PKT_FENCE_CTL_MB_SHIFT 31 +#define GAUDI_PKT_FENCE_CTL_MB_MASK 0x80000000 + +struct packet_fence { + __le32 cfg; + __le32 ctl; +}; + +#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_SHIFT 0 +#define GAUDI_PKT_LIN_DMA_CTL_WRCOMP_EN_MASK 0x00000001 + +#define GAUDI_PKT_LIN_DMA_CTL_LIN_SHIFT 3 +#define GAUDI_PKT_LIN_DMA_CTL_LIN_MASK 0x00000008 + +#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_SHIFT 4 +#define GAUDI_PKT_LIN_DMA_CTL_MEMSET_MASK 0x00000010 + +#define GAUDI_PKT_LIN_DMA_DST_ADDR_SHIFT 0 +#define GAUDI_PKT_LIN_DMA_DST_ADDR_MASK 0x00FFFFFFFFFFFFFFull + +struct packet_lin_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; + __le64 dst_addr; +}; + +struct packet_arb_point { + __le32 cfg; + __le32 ctl; +}; + +struct packet_repeat { + __le32 cfg; + __le32 ctl; +}; + +struct packet_wait { + __le32 cfg; + __le32 ctl; +}; + +struct packet_load_and_exe { + __le32 cfg; + __le32 ctl; + __le64 src_addr; +}; + +struct packet_cp_dma { + __le32 tsize; + __le32 ctl; + __le64 src_addr; +}; + +#endif /* GAUDI_PACKETS_H */ diff --git a/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h new file mode 100644 index 000000000000..f25c60a2c243 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi/gaudi_reg_map.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2019-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI_REG_MAP_H_ +#define GAUDI_REG_MAP_H_ + +/* + * PSOC scratch-pad registers + */ +#define mmHW_STATE mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 +#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1 +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3 + +#endif /* GAUDI_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h index 3c44ef3a23ed..067489bd048e 100644 --- a/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h @@ -55,8 +55,7 @@ (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ - (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ - (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) + (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) #define QMAN_MME_ENABLE (\ (1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h index fce490e6a231..ce65c9da5c60 100644 --- a/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h +++ b/drivers/misc/habanalabs/include/goya/asic_reg/goya_regs.h @@ -18,6 +18,7 @@ #include "psoc_mme_pll_regs.h" #include "psoc_pci_pll_regs.h" #include "psoc_emmc_pll_regs.h" +#include "psoc_timestamp_regs.h" #include "cpu_if_regs.h" #include "cpu_ca53_cfg_regs.h" #include "cpu_pll_regs.h" diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h new file mode 100644 index 000000000000..9ce24597d4b0 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/psoc_timestamp_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_PSOC_TIMESTAMP_REGS_H_ +#define ASIC_REG_PSOC_TIMESTAMP_REGS_H_ + +/* + ***************************************** + * PSOC_TIMESTAMP (Prototype: TIMESTAMP) + ***************************************** + */ + +#define mmPSOC_TIMESTAMP_CNTCR 0xC49000 + +#define mmPSOC_TIMESTAMP_CNTSR 0xC49004 + +#define mmPSOC_TIMESTAMP_CNTCVL 0xC49008 + +#define mmPSOC_TIMESTAMP_CNTCVU 0xC4900C + +#define mmPSOC_TIMESTAMP_CNTFID0 0xC49020 + +#define mmPSOC_TIMESTAMP_PIDR4 0xC49FD0 + +#define mmPSOC_TIMESTAMP_PIDR5 0xC49FD4 + +#define mmPSOC_TIMESTAMP_PIDR6 0xC49FD8 + +#define mmPSOC_TIMESTAMP_PIDR7 0xC49FDC + +#define mmPSOC_TIMESTAMP_PIDR0 0xC49FE0 + +#define mmPSOC_TIMESTAMP_PIDR1 0xC49FE4 + +#define mmPSOC_TIMESTAMP_PIDR2 0xC49FE8 + +#define mmPSOC_TIMESTAMP_PIDR3 0xC49FEC + +#define mmPSOC_TIMESTAMP_CIDR0 0xC49FF0 + +#define mmPSOC_TIMESTAMP_CIDR1 0xC49FF4 + +#define mmPSOC_TIMESTAMP_CIDR2 0xC49FF8 + +#define mmPSOC_TIMESTAMP_CIDR3 0xC49FFC + +#endif /* ASIC_REG_PSOC_TIMESTAMP_REGS_H_ */ diff --git a/drivers/misc/habanalabs/include/goya/goya_reg_map.h b/drivers/misc/habanalabs/include/goya/goya_reg_map.h index 08061282cd9c..0195f62d7254 100644 --- a/drivers/misc/habanalabs/include/goya/goya_reg_map.h +++ b/drivers/misc/habanalabs/include/goya/goya_reg_map.h @@ -11,27 +11,30 @@ /* * PSOC scratch-pad registers */ -#define mmCPU_PQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 -#define mmCPU_PQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 -#define mmCPU_EQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 -#define mmCPU_EQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 -#define mmCPU_EQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 -#define mmCPU_PQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 -#define mmCPU_EQ_CI mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 -#define mmCPU_PQ_INIT_STATUS mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 -#define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 -#define mmCPU_CQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 -#define mmCPU_CQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 -#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 -#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 -#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 -#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 -#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 -#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 -#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 -#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 +#define mmCPU_PQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 +#define mmCPU_PQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 +#define mmCPU_EQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 +#define mmCPU_EQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 +#define mmCPU_EQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 +#define mmCPU_PQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 +#define mmCPU_EQ_CI mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 +#define mmCPU_PQ_INIT_STATUS mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 +#define mmCPU_CQ_BASE_ADDR_LOW mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 +#define mmCPU_CQ_BASE_ADDR_HIGH mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 +#define mmCPU_CQ_LENGTH mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 +#define mmCPU_CMD_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 +#define mmCPU_BOOT_ERR0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 +#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 +#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 +#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 +#define mmPREBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 +#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 +#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 +#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 -#define mmHW_STATE mmPSOC_GLOBAL_CONF_APP_STATUS +#define mmHW_STATE mmPSOC_GLOBAL_CONF_APP_STATUS #define mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS mmPSOC_GLOBAL_CONF_WARM_REBOOT +#define mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU mmPSOC_GLOBAL_CONF_UBOOT_MAGIC +#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 #endif /* GOYA_REG_MAP_H_ */ diff --git a/drivers/misc/habanalabs/include/hl_boot_if.h b/drivers/misc/habanalabs/include/hl_boot_if.h index f7992a69fd3a..c22d134e73af 100644 --- a/drivers/misc/habanalabs/include/hl_boot_if.h +++ b/drivers/misc/habanalabs/include/hl_boot_if.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2018 HabanaLabs, Ltd. + * Copyright 2018-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -9,8 +9,47 @@ #define HL_BOOT_IF_H #define LKD_HARD_RESET_MAGIC 0xED7BD694 +#define HL_POWER9_HOST_MAGIC 0x1DA30009 -/* CPU error bits in BOOT_ERROR registers */ +#define BOOT_FIT_SRAM_OFFSET 0x200000 + +/* + * CPU error bits in BOOT_ERROR registers + * + * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. + * DRAM is not reliable to use. + * + * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the + * image provided by the host has failed. + * + * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. + * Boot continues as usual, but keep in + * mind this is a warning. + * + * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. + * Skipping DRAM initialization has been + * requested (e.g. strap, command, etc.) + * and FW skipped the DRAM initialization. + * Host can initialize the DRAM. + * + * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. + * Meaning the BMC data might not be + * available until reset. + * + * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. + * BMC has not provided the NIC data yet. + * Once provided this bit will be cleared. + * + * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. + * The NIC FW loading and initialization + * failed. This means NICs are not usable. + * + * CPU_BOOT_ERR0_ENABLED Error registers enabled. + * This is a main indication that the + * running FW populates the error + * registers. Meaning the error bits are + * not garbage, but actual error statuses. + */ #define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << 0) #define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << 1) #define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << 2) @@ -27,22 +66,33 @@ enum cpu_boot_status { CPU_BOOT_STATUS_SRAM_AVAIL = 3, CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */ CPU_BOOT_STATUS_IN_PREBOOT = 5, - CPU_BOOT_STATUS_IN_SPL = 6, + CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */ CPU_BOOT_STATUS_IN_UBOOT = 7, CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */ CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */ + /* U-Boot console prompt activated, commands are not processed */ CPU_BOOT_STATUS_UBOOT_NOT_READY = 10, + /* Finished NICs init, reported after DRAM and NICs */ CPU_BOOT_STATUS_NIC_FW_RDY = 11, CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */ CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */ CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */ + /* Last boot loader progress status, ready to receive commands */ CPU_BOOT_STATUS_READY_TO_BOOT = 15, + CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16, }; enum kmd_msg { KMD_MSG_NA = 0, KMD_MSG_GOTO_WFE, - KMD_MSG_FIT_RDY + KMD_MSG_FIT_RDY, + KMD_MSG_SKIP_BMC, +}; + +enum cpu_msg_status { + CPU_MSG_CLR = 0, + CPU_MSG_OK, + CPU_MSG_ERR, }; #endif /* HL_BOOT_IF_H */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h index a6851a9d3f03..468bb045fbd1 100644 --- a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_general.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright 2016-2018 HabanaLabs, Ltd. + * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ diff --git a/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h new file mode 100644 index 000000000000..b2a9570583ac --- /dev/null +++ b/drivers/misc/habanalabs/include/hw_ip/mmu/mmu_v1_1.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef INCLUDE_MMU_V1_1_H_ +#define INCLUDE_MMU_V1_1_H_ + +#define MMU_ASID 0xC12004 +#define MMU_HOP0_PA43_12 0xC12008 +#define MMU_HOP0_PA49_44 0xC1200C +#define MMU_BUSY 0xC12000 + +#endif /* INCLUDE_MMU_V1_1_H_ */ diff --git a/drivers/misc/habanalabs/memory.c b/drivers/misc/habanalabs/memory.c index a72f766ca470..47da84a17719 100644 --- a/drivers/misc/habanalabs/memory.c +++ b/drivers/misc/habanalabs/memory.c @@ -886,6 +886,7 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, vm_type = (enum vm_type_t *) userptr; hint_addr = args->map_host.hint_addr; + handle = phys_pg_pack->handle; } else { handle = lower_32_bits(args->map_device.handle); @@ -954,10 +955,17 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_mem_in *args, goto map_err; } - hdev->asic_funcs->mmu_invalidate_cache(hdev, false, *vm_type); + rc = hdev->asic_funcs->mmu_invalidate_cache(hdev, false, *vm_type); mutex_unlock(&ctx->mmu_lock); + if (rc) { + dev_err(hdev->dev, + "mapping handle %u failed due to MMU cache invalidation\n", + handle); + goto map_err; + } + ret_vaddr += phys_pg_pack->offset; hnode->ptr = vm_type; @@ -1015,7 +1023,7 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr, bool ctx_free) struct hl_va_range *va_range; enum vm_type_t *vm_type; bool is_userptr; - int rc; + int rc = 0; /* protect from double entrance */ mutex_lock(&ctx->mem_hash_lock); @@ -1083,21 +1091,34 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr, bool ctx_free) * at the loop end rather than for each iteration */ if (!ctx_free) - hdev->asic_funcs->mmu_invalidate_cache(hdev, true, *vm_type); + rc = hdev->asic_funcs->mmu_invalidate_cache(hdev, true, + *vm_type); mutex_unlock(&ctx->mmu_lock); /* - * No point in maintaining the free VA block list if the context is - * closing as the list will be freed anyway + * If the context is closing we don't need to check for the MMU cache + * invalidation return code and update the VA free list as in this flow + * we invalidate the MMU cache outside of this unmap function and the VA + * free list will be freed anyway. */ if (!ctx_free) { - rc = add_va_block(hdev, va_range, vaddr, - vaddr + phys_pg_pack->total_size - 1); + int tmp_rc; + if (rc) + dev_err(hdev->dev, + "unmapping vaddr 0x%llx failed due to MMU cache invalidation\n", + vaddr); + + tmp_rc = add_va_block(hdev, va_range, vaddr, + vaddr + phys_pg_pack->total_size - 1); + if (tmp_rc) { dev_warn(hdev->dev, "add va block failed for vaddr: 0x%llx\n", vaddr); + if (!rc) + rc = tmp_rc; + } } atomic_dec(&phys_pg_pack->mapping_cnt); @@ -1108,7 +1129,7 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 vaddr, bool ctx_free) dma_unmap_host_va(hdev, userptr); } - return 0; + return rc; mapping_cnt_err: if (is_userptr) diff --git a/drivers/misc/habanalabs/pci.c b/drivers/misc/habanalabs/pci.c index c98d88c7a5c6..9f634ef6f5b3 100644 --- a/drivers/misc/habanalabs/pci.c +++ b/drivers/misc/habanalabs/pci.c @@ -267,6 +267,12 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, /* Enable + Bar match + match enable */ rc |= hl_pci_iatu_write(hdev, 0x104, 0xC0080000); + /* Return the DBI window to the default location */ + rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0); + rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0); + + hdev->asic_funcs->set_dma_mask_from_fw(hdev); + /* Point to DRAM */ if (!hdev->asic_funcs->set_dram_bar_base) return -EINVAL; @@ -274,7 +280,6 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, U64_MAX) return -EIO; - /* Outbound Region 0 - Point to Host */ host_phys_end_addr = host_phys_base_address + host_phys_size - 1; rc |= hl_pci_iatu_write(hdev, 0x008, @@ -283,7 +288,12 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, upper_32_bits(host_phys_base_address)); rc |= hl_pci_iatu_write(hdev, 0x010, lower_32_bits(host_phys_end_addr)); rc |= hl_pci_iatu_write(hdev, 0x014, 0); - rc |= hl_pci_iatu_write(hdev, 0x018, 0); + + if ((hdev->power9_64bit_dma_enable) && (hdev->dma_mask == 64)) + rc |= hl_pci_iatu_write(hdev, 0x018, 0x08000000); + else + rc |= hl_pci_iatu_write(hdev, 0x018, 0); + rc |= hl_pci_iatu_write(hdev, 0x020, upper_32_bits(host_phys_end_addr)); /* Increase region size */ rc |= hl_pci_iatu_write(hdev, 0x000, 0x00002000); @@ -310,41 +320,25 @@ int hl_pci_init_iatu(struct hl_device *hdev, u64 sram_base_address, * * Return: 0 on success, non-zero for failure. */ -int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask) +static int hl_pci_set_dma_mask(struct hl_device *hdev) { struct pci_dev *pdev = hdev->pdev; int rc; /* set DMA mask */ - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)); + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask)); if (rc) { - dev_warn(hdev->dev, + dev_err(hdev->dev, "Failed to set pci dma mask to %d bits, error %d\n", - dma_mask, rc); - - dma_mask = hdev->dma_mask; - - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)); - if (rc) { - dev_err(hdev->dev, - "Failed to set pci dma mask to %d bits, error %d\n", - dma_mask, rc); - return rc; - } + hdev->dma_mask, rc); + return rc; } - /* - * We managed to set the dma mask, so update the dma mask field. If - * the set to the coherent mask will fail with that mask, we will - * fail the entire function - */ - hdev->dma_mask = dma_mask; - - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_mask)); + rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(hdev->dma_mask)); if (rc) { dev_err(hdev->dev, "Failed to set pci consistent dma mask to %d bits, error %d\n", - dma_mask, rc); + hdev->dma_mask, rc); return rc; } @@ -354,21 +348,16 @@ int hl_pci_set_dma_mask(struct hl_device *hdev, u8 dma_mask) /** * hl_pci_init() - PCI initialization code. * @hdev: Pointer to hl_device structure. - * @dma_mask: number of bits for the requested dma mask. * * Set DMA masks, initialize the PCI controller and map the PCI BARs. * * Return: 0 on success, non-zero for failure. */ -int hl_pci_init(struct hl_device *hdev, u8 dma_mask) +int hl_pci_init(struct hl_device *hdev) { struct pci_dev *pdev = hdev->pdev; int rc; - rc = hl_pci_set_dma_mask(hdev, dma_mask); - if (rc) - return rc; - if (hdev->reset_pcilink) hl_pci_reset_link_through_bridge(hdev); @@ -380,18 +369,22 @@ int hl_pci_init(struct hl_device *hdev, u8 dma_mask) pci_set_master(pdev); - rc = hdev->asic_funcs->init_iatu(hdev); + rc = hdev->asic_funcs->pci_bars_map(hdev); if (rc) { - dev_err(hdev->dev, "Failed to initialize iATU\n"); + dev_err(hdev->dev, "Failed to initialize PCI BARs\n"); goto disable_device; } - rc = hdev->asic_funcs->pci_bars_map(hdev); + rc = hdev->asic_funcs->init_iatu(hdev); if (rc) { - dev_err(hdev->dev, "Failed to initialize PCI BARs\n"); + dev_err(hdev->dev, "Failed to initialize iATU\n"); goto disable_device; } + rc = hl_pci_set_dma_mask(hdev); + if (rc) + goto disable_device; + return 0; disable_device: diff --git a/drivers/misc/habanalabs/sysfs.c b/drivers/misc/habanalabs/sysfs.c index 4cd622b017b9..5d78d5e1c782 100644 --- a/drivers/misc/habanalabs/sysfs.c +++ b/drivers/misc/habanalabs/sysfs.c @@ -183,6 +183,13 @@ static ssize_t soft_reset_store(struct device *dev, goto out; } + if (!hdev->supports_soft_reset) { + dev_err(hdev->dev, "Device does not support soft-reset\n"); + goto out; + } + + dev_warn(hdev->dev, "Soft-Reset requested through sysfs\n"); + hl_device_reset(hdev, false, false); out: @@ -204,6 +211,8 @@ static ssize_t hard_reset_store(struct device *dev, goto out; } + dev_warn(hdev->dev, "Hard-Reset requested through sysfs\n"); + hl_device_reset(hdev, true, false); out: @@ -220,6 +229,9 @@ static ssize_t device_type_show(struct device *dev, case ASIC_GOYA: str = "GOYA"; break; + case ASIC_GAUDI: + str = "GAUDI"; + break; default: dev_err(hdev->dev, "Unrecognized ASIC type %d\n", hdev->asic_type); @@ -406,7 +418,10 @@ int hl_sysfs_init(struct hl_device *hdev) { int rc; - hdev->pm_mng_profile = PM_AUTO; + if (hdev->asic_type == ASIC_GOYA) + hdev->pm_mng_profile = PM_AUTO; + else + hdev->pm_mng_profile = PM_MANUAL; hdev->max_power = hdev->asic_prop.max_power_default; hdev->asic_funcs->add_device_attr(hdev, &hl_dev_clks_attr_group); diff --git a/drivers/misc/lkdtm/bugs.c b/drivers/misc/lkdtm/bugs.c index 886459e0ddd9..736675f0a246 100644 --- a/drivers/misc/lkdtm/bugs.c +++ b/drivers/misc/lkdtm/bugs.c @@ -208,7 +208,7 @@ void lkdtm_OVERFLOW_UNSIGNED(void) ignored = value; } -/* Intentially using old-style flex array definition of 1 byte. */ +/* Intentionally using old-style flex array definition of 1 byte. */ struct array_bounds_flex_array { int one; int two; diff --git a/drivers/misc/mic/scif/scif_nodeqp.c b/drivers/misc/mic/scif/scif_nodeqp.c index fcd999f50d14..ea084626fe11 100644 --- a/drivers/misc/mic/scif/scif_nodeqp.c +++ b/drivers/misc/mic/scif/scif_nodeqp.c @@ -660,7 +660,7 @@ int scif_nodeqp_send(struct scif_dev *scifdev, struct scifmsg *msg) struct device *spdev = NULL; if (msg->uop > SCIF_EXIT_ACK) { - /* Dont send messages once the exit flow has begun */ + /* Don't send messages once the exit flow has begun */ if (OP_IDLE != scifdev->exit) return -ENODEV; spdev = scif_get_peer_dev(scifdev); diff --git a/drivers/misc/mic/scif/scif_rma.c b/drivers/misc/mic/scif/scif_rma.c index 01e27682ea30..406cd5abfa72 100644 --- a/drivers/misc/mic/scif/scif_rma.c +++ b/drivers/misc/mic/scif/scif_rma.c @@ -113,14 +113,17 @@ static int scif_destroy_pinned_pages(struct scif_pinned_pages *pin) int writeable = pin->prot & SCIF_PROT_WRITE; int kernel = SCIF_MAP_KERNEL & pin->map_flags; - for (j = 0; j < pin->nr_pages; j++) { - if (pin->pages[j] && !kernel) { - if (writeable) - SetPageDirty(pin->pages[j]); - put_page(pin->pages[j]); + if (kernel) { + for (j = 0; j < pin->nr_pages; j++) { + if (pin->pages[j] && !kernel) { + if (writeable) + set_page_dirty_lock(pin->pages[j]); + put_page(pin->pages[j]); + } } - } - + } else + unpin_user_pages_dirty_lock(pin->pages, pin->nr_pages, + writeable); scif_free(pin->pages, pin->nr_pages * sizeof(*pin->pages)); scif_free(pin, sizeof(*pin)); @@ -1375,7 +1378,7 @@ retry: } } - pinned_pages->nr_pages = get_user_pages_fast( + pinned_pages->nr_pages = pin_user_pages_fast( (u64)addr, nr_pages, (prot & SCIF_PROT_WRITE) ? FOLL_WRITE : 0, @@ -1385,11 +1388,8 @@ retry: if (ulimit) __scif_dec_pinned_vm_lock(mm, nr_pages); /* Roll back any pinned pages */ - for (i = 0; i < pinned_pages->nr_pages; i++) { - if (pinned_pages->pages[i]) - put_page( - pinned_pages->pages[i]); - } + unpin_user_pages(pinned_pages->pages, + pinned_pages->nr_pages); prot &= ~SCIF_PROT_WRITE; try_upgrade = false; goto retry; diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index ef5a1af6bab7..41c40971979e 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -73,6 +73,8 @@ #define is_am654_pci_dev(pdev) \ ((pdev)->device == PCI_DEVICE_ID_TI_AM654) +#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -942,6 +944,8 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), .driver_data = (kernel_ulong_t)&am654_data }, + { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0), + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); diff --git a/drivers/misc/sgi-xp/xpc_main.c b/drivers/misc/sgi-xp/xpc_main.c index 79a963105983..d5e097cd556d 100644 --- a/drivers/misc/sgi-xp/xpc_main.c +++ b/drivers/misc/sgi-xp/xpc_main.c @@ -59,16 +59,16 @@ /* define two XPC debug device structures to be used with dev_dbg() et al */ -struct device_driver xpc_dbg_name = { +static struct device_driver xpc_dbg_name = { .name = "xpc" }; -struct device xpc_part_dbg_subname = { +static struct device xpc_part_dbg_subname = { .init_name = "", /* set to "part" at xpc_init() time */ .driver = &xpc_dbg_name }; -struct device xpc_chan_dbg_subname = { +static struct device xpc_chan_dbg_subname = { .init_name = "", /* set to "chan" at xpc_init() time */ .driver = &xpc_dbg_name }; @@ -1217,7 +1217,7 @@ xpc_system_die(struct notifier_block *nb, unsigned long event, void *_die_args) return NOTIFY_DONE; } -int __init +static int __init xpc_init(void) { int ret; @@ -1319,7 +1319,7 @@ out_1: module_init(xpc_init); -void __exit +static void __exit xpc_exit(void) { xpc_do_exit(xpUnloading); diff --git a/drivers/misc/sgi-xp/xpnet.c b/drivers/misc/sgi-xp/xpnet.c index ada94e6a3c91..837d6c3fe69c 100644 --- a/drivers/misc/sgi-xp/xpnet.c +++ b/drivers/misc/sgi-xp/xpnet.c @@ -96,7 +96,7 @@ struct xpnet_pending_msg { atomic_t use_count; }; -struct net_device *xpnet_device; +static struct net_device *xpnet_device; /* * When we are notified of other partitions activating, we add them to @@ -131,16 +131,16 @@ static DEFINE_SPINLOCK(xpnet_broadcast_lock); /* Define the XPNET debug device structures to be used with dev_dbg() et al */ -struct device_driver xpnet_dbg_name = { +static struct device_driver xpnet_dbg_name = { .name = "xpnet" }; -struct device xpnet_dbg_subname = { +static struct device xpnet_dbg_subname = { .init_name = "", /* set to "" */ .driver = &xpnet_dbg_name }; -struct device *xpnet = &xpnet_dbg_subname; +static struct device *xpnet = &xpnet_dbg_subname; /* * Packet was recevied by XPC and forwarded to us. diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c index 71bbaa56bdb5..92291292756a 100644 --- a/drivers/misc/xilinx_sdfec.c +++ b/drivers/misc/xilinx_sdfec.c @@ -602,10 +602,10 @@ static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, const u32 depth) { u32 reg = 0; - u32 res; - u32 n, i; + int res, i, nr_pages; + u32 n; u32 *addr = NULL; - struct page *page[MAX_NUM_PAGES]; + struct page *pages[MAX_NUM_PAGES]; /* * Writes that go beyond the length of @@ -622,15 +622,21 @@ static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, if ((len * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE) n += 1; - res = get_user_pages_fast((unsigned long)src_ptr, n, 0, page); - if (res < n) { - for (i = 0; i < res; i++) - put_page(page[i]); + if (WARN_ON_ONCE(n > INT_MAX)) + return -EINVAL; + + nr_pages = n; + + res = pin_user_pages_fast((unsigned long)src_ptr, nr_pages, 0, pages); + if (res < nr_pages) { + if (res > 0) + unpin_user_pages(pages, res); + return -EINVAL; } - for (i = 0; i < n; i++) { - addr = kmap(page[i]); + for (i = 0; i < nr_pages; i++) { + addr = kmap(pages[i]); do { xsdfec_regwrite(xsdfec, base_addr + ((offset + reg) * @@ -639,9 +645,9 @@ static int xsdfec_table_write(struct xsdfec_dev *xsdfec, u32 offset, reg++; } while ((reg < len) && ((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)); - put_page(page[i]); + unpin_user_page(pages[i]); } - return reg; + return 0; } static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) @@ -649,14 +655,9 @@ static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) struct xsdfec_ldpc_params *ldpc; int ret, n; - ldpc = kzalloc(sizeof(*ldpc), GFP_KERNEL); - if (!ldpc) - return -ENOMEM; - - if (copy_from_user(ldpc, arg, sizeof(*ldpc))) { - ret = -EFAULT; - goto err_out; - } + ldpc = memdup_user(arg, sizeof(*ldpc)); + if (IS_ERR(ldpc)) + return PTR_ERR(ldpc); if (xsdfec->config.code == XSDFEC_TURBO_CODE) { ret = -EIO; @@ -720,8 +721,6 @@ static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg) ret = xsdfec_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table, ldpc->nqc, XSDFEC_LDPC_QC_TABLE_ADDR_BASE, XSDFEC_QC_TABLE_DEPTH); - if (ret > 0) - ret = 0; err_out: kfree(ldpc); return ret; @@ -1484,25 +1483,7 @@ static struct platform_driver xsdfec_driver = { .remove = xsdfec_remove, }; -static int __init xsdfec_init(void) -{ - int err; - - err = platform_driver_register(&xsdfec_driver); - if (err < 0) { - pr_err("%s Unabled to register SDFEC driver", __func__); - return err; - } - return 0; -} - -static void __exit xsdfec_exit(void) -{ - platform_driver_unregister(&xsdfec_driver); -} - -module_init(xsdfec_init); -module_exit(xsdfec_exit); +module_platform_driver(xsdfec_driver); MODULE_AUTHOR("Xilinx, Inc"); MODULE_DESCRIPTION("Xilinx SD-FEC16 Driver"); diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 2a4c8a2f3e64..db9b544465cd 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -123,10 +123,6 @@ struct sdhci_arasan_clk_data { void *clk_of_data; }; -struct sdhci_arasan_zynqmp_clk_data { - const struct zynqmp_eemi_ops *eemi_ops; -}; - /** * struct sdhci_arasan_data - Arasan Controller Data * @@ -599,9 +595,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) struct sdhci_arasan_data *sdhci_arasan = container_of(clk_data, struct sdhci_arasan_data, clk_data); struct sdhci_host *host = sdhci_arasan->host; - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = - clk_data->clk_of_data; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; const char *clk_name = clk_hw_get_name(hw); u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; u8 tap_delay, tap_max = 0; @@ -641,8 +634,7 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) tap_delay = (degrees * tap_max) / 360; /* Set the Clock Phase */ - ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, - PM_TAPDELAY_OUTPUT, tap_delay, NULL); + ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay); if (ret) pr_err("Error setting Output Tap Delay\n"); @@ -671,9 +663,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) struct sdhci_arasan_data *sdhci_arasan = container_of(clk_data, struct sdhci_arasan_data, clk_data); struct sdhci_host *host = sdhci_arasan->host; - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = - clk_data->clk_of_data; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; const char *clk_name = clk_hw_get_name(hw); u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1; u8 tap_delay, tap_max = 0; @@ -713,8 +702,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) tap_delay = (degrees * tap_max) / 360; /* Set the Clock Phase */ - ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY, - PM_TAPDELAY_INPUT, tap_delay, NULL); + ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay); if (ret) pr_err("Error setting Input Tap Delay\n"); @@ -874,11 +862,6 @@ static const struct clk_ops versal_sampleclk_ops = { static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) { - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data = - sdhci_arasan->clk_data.clk_of_data; - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops; u16 clk; clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); @@ -886,8 +869,7 @@ static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); /* Issue DLL Reset */ - eemi_ops->ioctl(deviceid, IOCTL_SD_DLL_RESET, - PM_DLL_RESET_PULSE, 0, NULL); + zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE); clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); @@ -1617,20 +1599,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev) goto clk_disable_all; if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { - struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data; - const struct zynqmp_eemi_ops *eemi_ops; - - zynqmp_clk_data = devm_kzalloc(&pdev->dev, - sizeof(*zynqmp_clk_data), - GFP_KERNEL); - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) { - ret = PTR_ERR(eemi_ops); - goto unreg_clk; - } - - zynqmp_clk_data->eemi_ops = eemi_ops; - sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data; host->mmc_host_ops.execute_tuning = arasan_zynqmp_execute_tuning; } diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 05c6ae4b0b97..927eb5f6003f 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -66,6 +66,30 @@ static LIST_HEAD(nvmem_lookup_list); static BLOCKING_NOTIFIER_HEAD(nvmem_notifier); +static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, + void *val, size_t bytes) +{ + if (nvmem->reg_read) + return nvmem->reg_read(nvmem->priv, offset, val, bytes); + + return -EINVAL; +} + +static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset, + void *val, size_t bytes) +{ + int ret; + + if (nvmem->reg_write) { + gpiod_set_value_cansleep(nvmem->wp_gpio, 0); + ret = nvmem->reg_write(nvmem->priv, offset, val, bytes); + gpiod_set_value_cansleep(nvmem->wp_gpio, 1); + return ret; + } + + return -EINVAL; +} + #ifdef CONFIG_NVMEM_SYSFS static const char * const nvmem_type_str[] = { [NVMEM_TYPE_UNKNOWN] = "Unknown", @@ -122,7 +146,7 @@ static ssize_t bin_attr_nvmem_read(struct file *filp, struct kobject *kobj, if (!nvmem->reg_read) return -EPERM; - rc = nvmem->reg_read(nvmem->priv, pos, buf, count); + rc = nvmem_reg_read(nvmem, pos, buf, count); if (rc) return rc; @@ -159,7 +183,7 @@ static ssize_t bin_attr_nvmem_write(struct file *filp, struct kobject *kobj, if (!nvmem->reg_write) return -EPERM; - rc = nvmem->reg_write(nvmem->priv, pos, buf, count); + rc = nvmem_reg_write(nvmem, pos, buf, count); if (rc) return rc; @@ -167,11 +191,8 @@ static ssize_t bin_attr_nvmem_write(struct file *filp, struct kobject *kobj, return count; } -static umode_t nvmem_bin_attr_is_visible(struct kobject *kobj, - struct bin_attribute *attr, int i) +static umode_t nvmem_bin_attr_get_umode(struct nvmem_device *nvmem) { - struct device *dev = container_of(kobj, struct device, kobj); - struct nvmem_device *nvmem = to_nvmem_device(dev); umode_t mode = 0400; if (!nvmem->root_only) @@ -189,6 +210,15 @@ static umode_t nvmem_bin_attr_is_visible(struct kobject *kobj, return mode; } +static umode_t nvmem_bin_attr_is_visible(struct kobject *kobj, + struct bin_attribute *attr, int i) +{ + struct device *dev = container_of(kobj, struct device, kobj); + struct nvmem_device *nvmem = to_nvmem_device(dev); + + return nvmem_bin_attr_get_umode(nvmem); +} + /* default read/write permissions */ static struct bin_attribute bin_attr_rw_nvmem = { .attr = { @@ -215,34 +245,14 @@ static const struct attribute_group *nvmem_dev_groups[] = { NULL, }; -/* read only permission */ -static struct bin_attribute bin_attr_ro_nvmem = { +static struct bin_attribute bin_attr_nvmem_eeprom_compat = { .attr = { - .name = "nvmem", - .mode = 0444, - }, - .read = bin_attr_nvmem_read, -}; - -/* default read/write permissions, root only */ -static struct bin_attribute bin_attr_rw_root_nvmem = { - .attr = { - .name = "nvmem", - .mode = 0600, + .name = "eeprom", }, .read = bin_attr_nvmem_read, .write = bin_attr_nvmem_write, }; -/* read only permission, root only */ -static struct bin_attribute bin_attr_ro_root_nvmem = { - .attr = { - .name = "nvmem", - .mode = 0400, - }, - .read = bin_attr_nvmem_read, -}; - /* * nvmem_setup_compat() - Create an additional binary entry in * drivers sys directory, to be backwards compatible with the older @@ -259,18 +269,8 @@ static int nvmem_sysfs_setup_compat(struct nvmem_device *nvmem, if (!config->base_dev) return -EINVAL; - if (nvmem->read_only) { - if (config->root_only) - nvmem->eeprom = bin_attr_ro_root_nvmem; - else - nvmem->eeprom = bin_attr_ro_nvmem; - } else { - if (config->root_only) - nvmem->eeprom = bin_attr_rw_root_nvmem; - else - nvmem->eeprom = bin_attr_rw_nvmem; - } - nvmem->eeprom.attr.name = "eeprom"; + nvmem->eeprom = bin_attr_nvmem_eeprom_compat; + nvmem->eeprom.attr.mode = nvmem_bin_attr_get_umode(nvmem); nvmem->eeprom.size = nvmem->size; #ifdef CONFIG_DEBUG_LOCK_ALLOC nvmem->eeprom.attr.key = &eeprom_lock_key; @@ -311,30 +311,6 @@ static void nvmem_sysfs_remove_compat(struct nvmem_device *nvmem, #endif /* CONFIG_NVMEM_SYSFS */ -static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, - void *val, size_t bytes) -{ - if (nvmem->reg_read) - return nvmem->reg_read(nvmem->priv, offset, val, bytes); - - return -EINVAL; -} - -static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset, - void *val, size_t bytes) -{ - int ret; - - if (nvmem->reg_write) { - gpiod_set_value_cansleep(nvmem->wp_gpio, 0); - ret = nvmem->reg_write(nvmem->priv, offset, val, bytes); - gpiod_set_value_cansleep(nvmem->wp_gpio, 1); - return ret; - } - - return -EINVAL; -} - static void nvmem_release(struct device *dev) { struct nvmem_device *nvmem = to_nvmem_device(dev); diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 50bea2aadc1b..7a1ebd6fd08b 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -196,7 +196,6 @@ static int imx_ocotp_read(void *context, unsigned int offset, if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL) imx_ocotp_clr_err_if_set(priv); } - ret = 0; read_end: clk_disable_unprepare(priv->clk); @@ -435,17 +434,13 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, priv->base + IMX_OCOTP_ADDR_CTRL_SET); ret = imx_ocotp_wait_for_busy(priv, priv->params->ctrl.bm_rel_shadows); - if (ret < 0) { + if (ret < 0) dev_err(priv->dev, "timeout during shadow register reload\n"); - goto write_end; - } write_end: clk_disable_unprepare(priv->clk); mutex_unlock(&ocotp_mutex); - if (ret < 0) - return ret; - return bytes; + return ret < 0 ? ret : bytes; } static struct nvmem_config imx_ocotp_nvmem_config = { diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c index 512e1872ba36..0b01b840edd9 100644 --- a/drivers/nvmem/jz4780-efuse.c +++ b/drivers/nvmem/jz4780-efuse.c @@ -211,10 +211,8 @@ static int jz4780_efuse_probe(struct platform_device *pdev) cfg.priv = efuse; nvmem = devm_nvmem_register(dev, &cfg); - if (IS_ERR(nvmem)) - return PTR_ERR(nvmem); - return 0; + return PTR_ERR_OR_ZERO(nvmem); } static const struct of_device_id jz4780_efuse_match[] = { diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index d057f1bfb2e9..8a91717600be 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -27,25 +27,11 @@ static int qfprom_reg_read(void *context, return 0; } -static int qfprom_reg_write(void *context, - unsigned int reg, void *_val, size_t bytes) -{ - struct qfprom_priv *priv = context; - u8 *val = _val; - int i = 0, words = bytes; - - while (words--) - writeb(*val++, priv->base + reg + i++); - - return 0; -} - static struct nvmem_config econfig = { .name = "qfprom", .stride = 1, .word_size = 1, .reg_read = qfprom_reg_read, - .reg_write = qfprom_reg_write, }; static int qfprom_probe(struct platform_device *pdev) diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c index 5893543918c8..e28d7b133e11 100644 --- a/drivers/nvmem/zynqmp_nvmem.c +++ b/drivers/nvmem/zynqmp_nvmem.c @@ -16,8 +16,6 @@ struct zynqmp_nvmem_data { struct nvmem_device *nvmem; }; -static const struct zynqmp_eemi_ops *eemi_ops; - static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes) { @@ -25,10 +23,7 @@ static int zynqmp_nvmem_read(void *context, unsigned int offset, int idcode, version; struct zynqmp_nvmem_data *priv = context; - if (!eemi_ops->get_chipid) - return -ENXIO; - - ret = eemi_ops->get_chipid(&idcode, &version); + ret = zynqmp_pm_get_chipid(&idcode, &version); if (ret < 0) return ret; @@ -61,10 +56,6 @@ static int zynqmp_nvmem_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - priv->dev = dev; econfig.dev = dev; econfig.reg_read = zynqmp_nvmem_read; diff --git a/drivers/parport/daisy.c b/drivers/parport/daisy.c index 3b00e2c8e2e9..6d78ec3a762f 100644 --- a/drivers/parport/daisy.c +++ b/drivers/parport/daisy.c @@ -30,12 +30,6 @@ #undef DEBUG -#ifdef DEBUG -#define DPRINTK(stuff...) printk(stuff) -#else -#define DPRINTK(stuff...) -#endif - static struct daisydev { struct daisydev *next; struct parport *port; @@ -145,8 +139,7 @@ again: ((num_ports = num_mux_ports(port)) == 2 || num_ports == 4)) { /* Leave original as port zero. */ port->muxport = 0; - printk(KERN_INFO - "%s: 1st (default) port of %d-way multiplexor\n", + pr_info("%s: 1st (default) port of %d-way multiplexor\n", port->name, num_ports); for (i = 1; i < num_ports; i++) { /* Clone the port. */ @@ -159,8 +152,7 @@ again: continue; } - printk(KERN_INFO - "%s: %d%s port of %d-way multiplexor on %s\n", + pr_info("%s: %d%s port of %d-way multiplexor on %s\n", extra->name, i + 1, th[i + 1], num_ports, port->name); @@ -323,8 +315,7 @@ static int cpp_daisy(struct parport *port, int cmd) | PARPORT_STATUS_PAPEROUT | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: cpp_daisy: aa5500ff(%02x)\n", - port->name, s); + pr_debug("%s: cpp_daisy: aa5500ff(%02x)\n", port->name, s); return -ENXIO; } @@ -334,8 +325,7 @@ static int cpp_daisy(struct parport *port, int cmd) | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR); if (s != (PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: cpp_daisy: aa5500ff87(%02x)\n", - port->name, s); + pr_debug("%s: cpp_daisy: aa5500ff87(%02x)\n", port->name, s); return -ENXIO; } @@ -370,7 +360,7 @@ static int cpp_mux(struct parport *port, int cmd) s = parport_read_status(port); if (!(s & PARPORT_STATUS_ACK)) { - DPRINTK(KERN_DEBUG "%s: cpp_mux: aa55f00f52ad%02x(%02x)\n", + pr_debug("%s: cpp_mux: aa55f00f52ad%02x(%02x)\n", port->name, cmd, s); return -EIO; } @@ -456,8 +446,7 @@ static int assign_addrs(struct parport *port) | PARPORT_STATUS_PAPEROUT | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: assign_addrs: aa5500ff(%02x)\n", - port->name, s); + pr_debug("%s: assign_addrs: aa5500ff(%02x)\n", port->name, s); return 0; } @@ -467,8 +456,7 @@ static int assign_addrs(struct parport *port) | PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR); if (s != (PARPORT_STATUS_SELECT | PARPORT_STATUS_ERROR)) { - DPRINTK(KERN_DEBUG "%s: assign_addrs: aa5500ff87(%02x)\n", - port->name, s); + pr_debug("%s: assign_addrs: aa5500ff87(%02x)\n", port->name, s); return 0; } @@ -505,8 +493,7 @@ static int assign_addrs(struct parport *port) parport_write_data(port, 0xff); udelay(2); detected = numdevs - thisdev; - DPRINTK(KERN_DEBUG "%s: Found %d daisy-chained devices\n", port->name, - detected); + pr_debug("%s: Found %d daisy-chained devices\n", port->name, detected); /* Ask the new devices to introduce themselves. */ deviceid = kmalloc(1024, GFP_KERNEL); diff --git a/drivers/parport/ieee1284.c b/drivers/parport/ieee1284.c index 90fb73575495..f28d6a3c5a68 100644 --- a/drivers/parport/ieee1284.c +++ b/drivers/parport/ieee1284.c @@ -31,12 +31,6 @@ #undef DEBUG /* Don't want a garbled console */ #endif -#ifdef DEBUG -#define DPRINTK(stuff...) printk (stuff) -#else -#define DPRINTK(stuff...) -#endif - /* Make parport_wait_peripheral wake up. * It will be useful to call this from an interrupt handler. */ static void parport_ieee1284_wakeup (struct parport *port) @@ -258,12 +252,11 @@ static void parport_ieee1284_terminate (struct parport *port) PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) - DPRINTK (KERN_INFO "%s: Timeout at event 49\n", + pr_debug("%s: Timeout at event 49\n", port->name); parport_data_forward (port); - DPRINTK (KERN_DEBUG "%s: ECP direction: forward\n", - port->name); + pr_debug("%s: ECP direction: forward\n", port->name); port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; } @@ -281,8 +274,7 @@ static void parport_ieee1284_terminate (struct parport *port) /* Event 24: nAck goes low */ r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0); if (r) - DPRINTK (KERN_INFO "%s: Timeout at event 24\n", - port->name); + pr_debug("%s: Timeout at event 24\n", port->name); /* Event 25: Set nAutoFd low */ parport_frob_control (port, @@ -294,8 +286,7 @@ static void parport_ieee1284_terminate (struct parport *port) PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); if (r) - DPRINTK (KERN_INFO "%s: Timeout at event 27\n", - port->name); + pr_debug("%s: Timeout at event 27\n", port->name); /* Event 29: Set nAutoFd high */ parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0); @@ -304,8 +295,7 @@ static void parport_ieee1284_terminate (struct parport *port) port->ieee1284.mode = IEEE1284_MODE_COMPAT; port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; - DPRINTK (KERN_DEBUG "%s: In compatibility (forward idle) mode\n", - port->name); + pr_debug("%s: In compatibility (forward idle) mode\n", port->name); } #endif /* IEEE1284 support */ @@ -329,7 +319,7 @@ int parport_negotiate (struct parport *port, int mode) #ifndef CONFIG_PARPORT_1284 if (mode == IEEE1284_MODE_COMPAT) return 0; - printk (KERN_ERR "parport: IEEE1284 not supported in this kernel\n"); + pr_err("parport: IEEE1284 not supported in this kernel\n"); return -1; #else int m = mode & ~IEEE1284_ADDR; @@ -406,8 +396,7 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_CONTROL_SELECT | PARPORT_CONTROL_AUTOFD, PARPORT_CONTROL_SELECT); - DPRINTK (KERN_DEBUG - "%s: Peripheral not IEEE1284 compliant (0x%02X)\n", + pr_debug("%s: Peripheral not IEEE1284 compliant (0x%02X)\n", port->name, parport_read_status (port)); port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; return -1; /* Not IEEE1284 compliant */ @@ -430,8 +419,7 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_STATUS_ACK, PARPORT_STATUS_ACK)) { /* This shouldn't really happen with a compliant device. */ - DPRINTK (KERN_DEBUG - "%s: Mode 0x%02x not supported? (0x%02x)\n", + pr_debug("%s: Mode 0x%02x not supported? (0x%02x)\n", port->name, mode, port->ops->read_status (port)); parport_ieee1284_terminate (port); return 1; @@ -442,7 +430,7 @@ int parport_negotiate (struct parport *port, int mode) /* xflag should be high for all modes other than nibble (0). */ if (mode && !xflag) { /* Mode not supported. */ - DPRINTK (KERN_DEBUG "%s: Mode 0x%02x rejected by peripheral\n", + pr_debug("%s: Mode 0x%02x rejected by peripheral\n", port->name, mode); parport_ieee1284_terminate (port); return 1; @@ -463,9 +451,7 @@ int parport_negotiate (struct parport *port, int mode) /* Event 52: nAck goes low */ if (parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0)) { /* This peripheral is _very_ slow. */ - DPRINTK (KERN_DEBUG - "%s: Event 52 didn't happen\n", - port->name); + pr_debug("%s: Event 52 didn't happen\n", port->name); parport_ieee1284_terminate (port); return 1; } @@ -481,10 +467,9 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_STATUS_ACK)) { /* This shouldn't really happen with a compliant * device. */ - DPRINTK (KERN_DEBUG - "%s: Mode 0x%02x not supported? (0x%02x)\n", + pr_debug("%s: Mode 0x%02x not supported? (0x%02x)\n", port->name, mode, - port->ops->read_status (port)); + port->ops->read_status(port)); parport_ieee1284_terminate (port); return 1; } @@ -495,8 +480,8 @@ int parport_negotiate (struct parport *port, int mode) /* xflag should be high. */ if (!xflag) { /* Extended mode not supported. */ - DPRINTK (KERN_DEBUG "%s: Extended mode 0x%02x not " - "supported\n", port->name, mode); + pr_debug("%s: Extended mode 0x%02x not supported\n", + port->name, mode); parport_ieee1284_terminate (port); return 1; } @@ -505,7 +490,7 @@ int parport_negotiate (struct parport *port, int mode) } /* Mode is supported */ - DPRINTK (KERN_DEBUG "%s: In mode 0x%02x\n", port->name, mode); + pr_debug("%s: In mode 0x%02x\n", port->name, mode); port->ieee1284.mode = mode; /* But ECP is special */ @@ -522,13 +507,11 @@ int parport_negotiate (struct parport *port, int mode) PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) { - DPRINTK (KERN_INFO "%s: Timeout at event 31\n", - port->name); + pr_debug("%s: Timeout at event 31\n", port->name); } port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; - DPRINTK (KERN_DEBUG "%s: ECP direction: forward\n", - port->name); + pr_debug("%s: ECP direction: forward\n", port->name); } else switch (mode) { case IEEE1284_MODE_NIBBLE: case IEEE1284_MODE_BYTE: @@ -573,7 +556,7 @@ void parport_ieee1284_interrupt (void *handle) if (port->ieee1284.phase == IEEE1284_PH_REV_IDLE) { /* An interrupt in this phase means that data * is now available. */ - DPRINTK (KERN_DEBUG "%s: Data available\n", port->name); + pr_debug("%s: Data available\n", port->name); parport_ieee1284_ack_data_avail (port); } #endif /* IEEE1284 support */ @@ -617,13 +600,12 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) parport_negotiate (port, IEEE1284_MODE_COMPAT); /* fall through */ case IEEE1284_MODE_COMPAT: - DPRINTK (KERN_DEBUG "%s: Using compatibility mode\n", - port->name); + pr_debug("%s: Using compatibility mode\n", port->name); fn = port->ops->compat_write_data; break; case IEEE1284_MODE_EPP: - DPRINTK (KERN_DEBUG "%s: Using EPP mode\n", port->name); + pr_debug("%s: Using EPP mode\n", port->name); if (addr) { fn = port->ops->epp_write_addr; } else { @@ -631,8 +613,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) } break; case IEEE1284_MODE_EPPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated EPP mode\n", - port->name); + pr_debug("%s: Using software-emulated EPP mode\n", port->name); if (addr) { fn = parport_ieee1284_epp_write_addr; } else { @@ -641,7 +622,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) break; case IEEE1284_MODE_ECP: case IEEE1284_MODE_ECPRLE: - DPRINTK (KERN_DEBUG "%s: Using ECP mode\n", port->name); + pr_debug("%s: Using ECP mode\n", port->name); if (addr) { fn = port->ops->ecp_write_addr; } else { @@ -650,8 +631,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) break; case IEEE1284_MODE_ECPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated ECP mode\n", - port->name); + pr_debug("%s: Using software-emulated ECP mode\n", port->name); /* The caller has specified that it must be emulated, * even if we have ECP hardware! */ if (addr) { @@ -662,13 +642,13 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) break; default: - DPRINTK (KERN_DEBUG "%s: Unknown mode 0x%02x\n", port->name, - port->ieee1284.mode); + pr_debug("%s: Unknown mode 0x%02x\n", + port->name, port->ieee1284.mode); return -ENOSYS; } retval = (*fn) (port, buffer, len, 0); - DPRINTK (KERN_DEBUG "%s: wrote %d/%d bytes\n", port->name, retval, len); + pr_debug("%s: wrote %zd/%zu bytes\n", port->name, retval, len); return retval; #endif /* IEEE1284 support */ } @@ -694,7 +674,7 @@ ssize_t parport_write (struct parport *port, const void *buffer, size_t len) ssize_t parport_read (struct parport *port, void *buffer, size_t len) { #ifndef CONFIG_PARPORT_1284 - printk (KERN_ERR "parport: IEEE1284 not supported in this kernel\n"); + pr_err("parport: IEEE1284 not supported in this kernel\n"); return -ENODEV; #else int mode = port->physport->ieee1284.mode; @@ -715,7 +695,7 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) if ((port->physport->modes & PARPORT_MODE_TRISTATE) && !parport_negotiate (port, IEEE1284_MODE_BYTE)) { /* got into BYTE mode OK */ - DPRINTK (KERN_DEBUG "%s: Using byte mode\n", port->name); + pr_debug("%s: Using byte mode\n", port->name); fn = port->ops->byte_read_data; break; } @@ -724,17 +704,17 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) } /* fall through - to NIBBLE */ case IEEE1284_MODE_NIBBLE: - DPRINTK (KERN_DEBUG "%s: Using nibble mode\n", port->name); + pr_debug("%s: Using nibble mode\n", port->name); fn = port->ops->nibble_read_data; break; case IEEE1284_MODE_BYTE: - DPRINTK (KERN_DEBUG "%s: Using byte mode\n", port->name); + pr_debug("%s: Using byte mode\n", port->name); fn = port->ops->byte_read_data; break; case IEEE1284_MODE_EPP: - DPRINTK (KERN_DEBUG "%s: Using EPP mode\n", port->name); + pr_debug("%s: Using EPP mode\n", port->name); if (addr) { fn = port->ops->epp_read_addr; } else { @@ -742,8 +722,7 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) } break; case IEEE1284_MODE_EPPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated EPP mode\n", - port->name); + pr_debug("%s: Using software-emulated EPP mode\n", port->name); if (addr) { fn = parport_ieee1284_epp_read_addr; } else { @@ -752,19 +731,18 @@ ssize_t parport_read (struct parport *port, void *buffer, size_t len) break; case IEEE1284_MODE_ECP: case IEEE1284_MODE_ECPRLE: - DPRINTK (KERN_DEBUG "%s: Using ECP mode\n", port->name); + pr_debug("%s: Using ECP mode\n", port->name); fn = port->ops->ecp_read_data; break; case IEEE1284_MODE_ECPSWE: - DPRINTK (KERN_DEBUG "%s: Using software-emulated ECP mode\n", - port->name); + pr_debug("%s: Using software-emulated ECP mode\n", port->name); fn = parport_ieee1284_ecp_read_data; break; default: - DPRINTK (KERN_DEBUG "%s: Unknown mode 0x%02x\n", port->name, - port->physport->ieee1284.mode); + pr_debug("%s: Unknown mode 0x%02x\n", + port->name, port->physport->ieee1284.mode); return -ENOSYS; } diff --git a/drivers/parport/ieee1284_ops.c b/drivers/parport/ieee1284_ops.c index 5d41dda6da4e..2c11bd3fe1fd 100644 --- a/drivers/parport/ieee1284_ops.c +++ b/drivers/parport/ieee1284_ops.c @@ -27,12 +27,6 @@ #undef DEBUG /* Don't want a garbled console */ #endif -#ifdef DEBUG -#define DPRINTK(stuff...) printk (stuff) -#else -#define DPRINTK(stuff...) -#endif - /*** * * One-way data transfer functions. * * ***/ @@ -115,7 +109,7 @@ size_t parport_ieee1284_write_compat (struct parport *port, if (signal_pending (current)) break; - DPRINTK (KERN_DEBUG "%s: Timed out\n", port->name); + pr_debug("%s: Timed out\n", port->name); break; ready: @@ -178,9 +172,8 @@ size_t parport_ieee1284_read_nibble (struct parport *port, if (parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0)) { /* Timeout -- no more data? */ - DPRINTK (KERN_DEBUG - "%s: Nibble timeout at event 9 (%d bytes)\n", - port->name, i/2); + pr_debug("%s: Nibble timeout at event 9 (%d bytes)\n", + port->name, i / 2); parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0); break; } @@ -201,8 +194,7 @@ size_t parport_ieee1284_read_nibble (struct parport *port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK)) { /* Timeout -- no more data? */ - DPRINTK (KERN_DEBUG - "%s: Nibble timeout at event 11\n", + pr_debug("%s: Nibble timeout at event 11\n", port->name); break; } @@ -219,9 +211,8 @@ size_t parport_ieee1284_read_nibble (struct parport *port, /* Read the last nibble without checking data avail. */ if (parport_read_status (port) & PARPORT_STATUS_ERROR) { end_of_data: - DPRINTK (KERN_DEBUG - "%s: No more nibble data (%d bytes)\n", - port->name, i/2); + pr_debug("%s: No more nibble data (%d bytes)\n", + port->name, i / 2); /* Go to reverse idle phase. */ parport_frob_control (port, @@ -272,8 +263,7 @@ size_t parport_ieee1284_read_byte (struct parport *port, /* Timeout -- no more data? */ parport_frob_control (port, PARPORT_CONTROL_AUTOFD, 0); - DPRINTK (KERN_DEBUG "%s: Byte timeout at event 9\n", - port->name); + pr_debug("%s: Byte timeout at event 9\n", port->name); break; } @@ -288,8 +278,7 @@ size_t parport_ieee1284_read_byte (struct parport *port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK)) { /* Timeout -- no more data? */ - DPRINTK (KERN_DEBUG "%s: Byte timeout at event 11\n", - port->name); + pr_debug("%s: Byte timeout at event 11\n", port->name); break; } @@ -307,8 +296,7 @@ size_t parport_ieee1284_read_byte (struct parport *port, /* Read the last byte without checking data avail. */ if (parport_read_status (port) & PARPORT_STATUS_ERROR) { end_of_data: - DPRINTK (KERN_DEBUG - "%s: No more byte data (%zd bytes)\n", + pr_debug("%s: No more byte data (%zd bytes)\n", port->name, count); /* Go to reverse idle phase. */ @@ -353,12 +341,10 @@ int ecp_forward_to_reverse (struct parport *port) PARPORT_STATUS_PAPEROUT, 0); if (!retval) { - DPRINTK (KERN_DEBUG "%s: ECP direction: reverse\n", - port->name); + pr_debug("%s: ECP direction: reverse\n", port->name); port->ieee1284.phase = IEEE1284_PH_REV_IDLE; } else { - DPRINTK (KERN_DEBUG "%s: ECP direction: failed to reverse\n", - port->name); + pr_debug("%s: ECP direction: failed to reverse\n", port->name); port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; } @@ -384,12 +370,10 @@ int ecp_reverse_to_forward (struct parport *port) if (!retval) { parport_data_forward (port); - DPRINTK (KERN_DEBUG "%s: ECP direction: forward\n", - port->name); + pr_debug("%s: ECP direction: forward\n", port->name); port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; } else { - DPRINTK (KERN_DEBUG - "%s: ECP direction: failed to switch forward\n", + pr_debug("%s: ECP direction: failed to switch forward\n", port->name); port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; } @@ -450,7 +434,7 @@ size_t parport_ieee1284_ecp_write_data (struct parport *port, } /* Time for Host Transfer Recovery (page 41 of IEEE1284) */ - DPRINTK (KERN_DEBUG "%s: ECP transfer stalled!\n", port->name); + pr_debug("%s: ECP transfer stalled!\n", port->name); parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); @@ -466,8 +450,7 @@ size_t parport_ieee1284_ecp_write_data (struct parport *port, if (!(parport_read_status (port) & PARPORT_STATUS_PAPEROUT)) break; - DPRINTK (KERN_DEBUG "%s: Host transfer recovered\n", - port->name); + pr_debug("%s: Host transfer recovered\n", port->name); if (time_after_eq (jiffies, expire)) break; goto try_again; @@ -565,23 +548,20 @@ size_t parport_ieee1284_ecp_read_data (struct parport *port, command or a normal data byte, don't accept it. */ if (command) { if (byte & 0x80) { - DPRINTK (KERN_DEBUG "%s: stopping short at " - "channel command (%02x)\n", + pr_debug("%s: stopping short at channel command (%02x)\n", port->name, byte); goto out; } else if (port->ieee1284.mode != IEEE1284_MODE_ECPRLE) - DPRINTK (KERN_DEBUG "%s: device illegally " - "using RLE; accepting anyway\n", + pr_debug("%s: device illegally using RLE; accepting anyway\n", port->name); rle_count = byte + 1; /* Are we allowed to read that many bytes? */ if (rle_count > (len - count)) { - DPRINTK (KERN_DEBUG "%s: leaving %d RLE bytes " - "for next time\n", port->name, - rle_count); + pr_debug("%s: leaving %d RLE bytes for next time\n", + port->name, rle_count); break; } @@ -596,11 +576,10 @@ size_t parport_ieee1284_ecp_read_data (struct parport *port, PARPORT_STATUS_ACK)) { /* It's gone wrong. Return what data we have to the caller. */ - DPRINTK (KERN_DEBUG "ECP read timed out at 45\n"); + pr_debug("ECP read timed out at 45\n"); if (command) - printk (KERN_WARNING - "%s: command ignored (%02x)\n", + pr_warn("%s: command ignored (%02x)\n", port->name, byte); break; @@ -620,7 +599,7 @@ size_t parport_ieee1284_ecp_read_data (struct parport *port, memset (buf, byte, rle_count); buf += rle_count; count += rle_count; - DPRINTK (KERN_DEBUG "%s: decompressed to %d bytes\n", + pr_debug("%s: decompressed to %d bytes\n", port->name, rle_count); } else { /* Normal data byte. */ @@ -686,7 +665,7 @@ size_t parport_ieee1284_ecp_write_addr (struct parport *port, } /* Time for Host Transfer Recovery (page 41 of IEEE1284) */ - DPRINTK (KERN_DEBUG "%s: ECP transfer stalled!\n", port->name); + pr_debug("%s: ECP transfer stalled!\n", port->name); parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT); @@ -702,8 +681,7 @@ size_t parport_ieee1284_ecp_write_addr (struct parport *port, if (!(parport_read_status (port) & PARPORT_STATUS_PAPEROUT)) break; - DPRINTK (KERN_DEBUG "%s: Host transfer recovered\n", - port->name); + pr_debug("%s: Host transfer recovered\n", port->name); if (time_after_eq (jiffies, expire)) break; goto try_again; diff --git a/drivers/parport/parport_amiga.c b/drivers/parport/parport_amiga.c index 3301861f69fa..1e88bcfe0d7b 100644 --- a/drivers/parport/parport_amiga.c +++ b/drivers/parport/parport_amiga.c @@ -28,16 +28,10 @@ #include <asm/amigaints.h> #undef DEBUG -#ifdef DEBUG -#define DPRINTK printk -#else -#define DPRINTK(x...) do { } while (0) -#endif - static void amiga_write_data(struct parport *p, unsigned char data) { - DPRINTK(KERN_DEBUG "write_data %c\n",data); + pr_debug("write_data %c\n", data); /* Triggers also /STROBE. This behavior cannot be changed */ ciaa.prb = data; mb(); @@ -59,13 +53,13 @@ static unsigned char control_amiga_to_pc(unsigned char control) static void amiga_write_control(struct parport *p, unsigned char control) { - DPRINTK(KERN_DEBUG "write_control %02x\n",control); + pr_debug("write_control %02x\n", control); /* No implementation possible */ } static unsigned char amiga_read_control( struct parport *p) { - DPRINTK(KERN_DEBUG "read_control \n"); + pr_debug("read_control\n"); return control_amiga_to_pc(0); } @@ -73,7 +67,7 @@ static unsigned char amiga_frob_control( struct parport *p, unsigned char mask, { unsigned char old; - DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); + pr_debug("frob_control mask %02x, value %02x\n", mask, val); old = amiga_read_control(p); amiga_write_control(p, (old & ~mask) ^ val); return old; @@ -99,7 +93,7 @@ static unsigned char amiga_read_status(struct parport *p) unsigned char status; status = status_amiga_to_pc(ciab.pra & 7); - DPRINTK(KERN_DEBUG "read_status %02x\n", status); + pr_debug("read_status %02x\n", status); return status; } @@ -115,14 +109,14 @@ static void amiga_disable_irq(struct parport *p) static void amiga_data_forward(struct parport *p) { - DPRINTK(KERN_DEBUG "forward\n"); + pr_debug("forward\n"); ciaa.ddrb = 0xff; /* all pins output */ mb(); } static void amiga_data_reverse(struct parport *p) { - DPRINTK(KERN_DEBUG "reverse\n"); + pr_debug("reverse\n"); ciaa.ddrb = 0; /* all pins input */ mb(); } @@ -212,7 +206,7 @@ static int __init amiga_parallel_probe(struct platform_device *pdev) if (err) goto out_irq; - printk(KERN_INFO "%s: Amiga built-in port using irq\n", p->name); + pr_info("%s: Amiga built-in port using irq\n", p->name); /* XXX: set operating mode */ parport_announce_port(p); diff --git a/drivers/parport/parport_atari.c b/drivers/parport/parport_atari.c index f8dd368bfdbb..2ff0fe053e6e 100644 --- a/drivers/parport/parport_atari.c +++ b/drivers/parport/parport_atari.c @@ -200,7 +200,7 @@ static int __init parport_atari_init(void) } this_port = p; - printk(KERN_INFO "%s: Atari built-in port using irq\n", p->name); + pr_info("%s: Atari built-in port using irq\n", p->name); parport_announce_port (p); return 0; diff --git a/drivers/parport/parport_cs.c b/drivers/parport/parport_cs.c index e77044c2bf62..8e7e3ac4bb87 100644 --- a/drivers/parport/parport_cs.c +++ b/drivers/parport/parport_cs.c @@ -142,10 +142,8 @@ static int parport_config(struct pcmcia_device *link) link->irq, PARPORT_DMA_NONE, &link->dev, IRQF_SHARED); if (p == NULL) { - printk(KERN_NOTICE "parport_cs: parport_pc_probe_port() at " - "0x%3x, irq %u failed\n", - (unsigned int) link->resource[0]->start, - link->irq); + pr_notice("parport_cs: parport_pc_probe_port() at 0x%3x, irq %u failed\n", + (unsigned int)link->resource[0]->start, link->irq); goto failed; } diff --git a/drivers/parport/parport_gsc.c b/drivers/parport/parport_gsc.c index 922535a118ba..9228e8f90309 100644 --- a/drivers/parport/parport_gsc.c +++ b/drivers/parport/parport_gsc.c @@ -238,14 +238,14 @@ struct parport *parport_gsc_probe_port(unsigned long base, priv = kzalloc (sizeof (struct parport_gsc_private), GFP_KERNEL); if (!priv) { - printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base); + printk(KERN_DEBUG "parport (0x%lx): no memory!\n", base); return NULL; } ops = kmemdup(&parport_gsc_ops, sizeof(struct parport_operations), GFP_KERNEL); if (!ops) { - printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n", - base); + printk(KERN_DEBUG "parport (0x%lx): no memory for ops!\n", + base); kfree (priv); return NULL; } @@ -282,7 +282,7 @@ struct parport *parport_gsc_probe_port(unsigned long base, p->size = (p->modes & PARPORT_MODE_EPP)?8:3; p->private_data = priv; - printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); + pr_info("%s: PC-style at 0x%lx", p->name, p->base); p->irq = irq; if (p->irq == PARPORT_IRQ_AUTO) { p->irq = PARPORT_IRQ_NONE; @@ -299,12 +299,16 @@ struct parport *parport_gsc_probe_port(unsigned long base, p->dma = PARPORT_DMA_NONE; pr_cont(" ["); -#define printmode(x) {if(p->modes&PARPORT_MODE_##x){pr_cont("%s%s",f?",":"",#x);f++;}} +#define printmode(x) \ +do { \ + if (p->modes & PARPORT_MODE_##x) \ + pr_cont("%s%s", f++ ? "," : "", #x); \ +} while (0) { int f = 0; printmode(PCSPP); printmode(TRISTATE); - printmode(COMPAT) + printmode(COMPAT); printmode(EPP); // printmode(ECP); // printmode(DMA); @@ -315,8 +319,7 @@ struct parport *parport_gsc_probe_port(unsigned long base, if (p->irq != PARPORT_IRQ_NONE) { if (request_irq (p->irq, parport_irq_handler, 0, p->name, p)) { - printk (KERN_WARNING "%s: irq %d in use, " - "resorting to polled operation\n", + pr_warn("%s: irq %d in use, resorting to polled operation\n", p->name, p->irq); p->irq = PARPORT_IRQ_NONE; p->dma = PARPORT_DMA_NONE; @@ -347,7 +350,7 @@ static int __init parport_init_chip(struct parisc_device *dev) unsigned long port; if (!dev->irq) { - printk(KERN_WARNING "IRQ not found for parallel device at 0x%llx\n", + pr_warn("IRQ not found for parallel device at 0x%llx\n", (unsigned long long)dev->hpa.start); return -ENODEV; } @@ -360,11 +363,11 @@ static int __init parport_init_chip(struct parisc_device *dev) if (boot_cpu_data.cpu_type > pcxt && !pdc_add_valid(port+4)) { /* Initialize bidirectional-mode (0x10) & data-tranfer-mode #1 (0x20) */ - printk("%s: initialize bidirectional-mode.\n", __func__); + pr_info("%s: initialize bidirectional-mode\n", __func__); parport_writeb ( (0x10 + 0x20), port + 4); } else { - printk("%s: enhanced parport-modes not supported.\n", __func__); + pr_info("%s: enhanced parport-modes not supported\n", __func__); } p = parport_gsc_probe_port(port, 0, dev->irq, diff --git a/drivers/parport/parport_gsc.h b/drivers/parport/parport_gsc.h index 4c4d3c6cd77e..9301217edf12 100644 --- a/drivers/parport/parport_gsc.h +++ b/drivers/parport/parport_gsc.h @@ -71,7 +71,7 @@ struct parport_gsc_private { static inline void parport_gsc_write_data(struct parport *p, unsigned char d) { #ifdef DEBUG_PARPORT - printk (KERN_DEBUG "parport_gsc_write_data(%p,0x%02x)\n", p, d); + printk(KERN_DEBUG "%s(%p,0x%02x)\n", __func__, p, d); #endif parport_writeb(d, DATA(p)); } @@ -80,8 +80,7 @@ static inline unsigned char parport_gsc_read_data(struct parport *p) { unsigned char val = parport_readb (DATA (p)); #ifdef DEBUG_PARPORT - printk (KERN_DEBUG "parport_gsc_read_data(%p) = 0x%02x\n", - p, val); + printk(KERN_DEBUG "%s(%p) = 0x%02x\n", __func__, p, val); #endif return val; } @@ -95,9 +94,9 @@ static inline unsigned char __parport_gsc_frob_control(struct parport *p, struct parport_gsc_private *priv = p->physport->private_data; unsigned char ctr = priv->ctr; #ifdef DEBUG_PARPORT - printk (KERN_DEBUG - "__parport_gsc_frob_control(%02x,%02x): %02x -> %02x\n", - mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); + printk(KERN_DEBUG "%s(%02x,%02x): %02x -> %02x\n", + __func__, mask, val, + ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); #endif ctr = (ctr & ~mask) ^ val; ctr &= priv->ctr_writable; /* only write writable bits. */ @@ -126,8 +125,8 @@ static inline void parport_gsc_write_control(struct parport *p, /* Take this out when drivers have adapted to newer interface. */ if (d & 0x20) { - printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n", - p->name, p->cad->name); + printk(KERN_DEBUG "%s (%s): use data_reverse for this!\n", + p->name, p->cad->name); parport_gsc_data_reverse (p); } @@ -155,9 +154,9 @@ static inline unsigned char parport_gsc_frob_control(struct parport *p, /* Take this out when drivers have adapted to newer interface. */ if (mask & 0x20) { - printk (KERN_DEBUG "%s (%s): use data_%s for this!\n", - p->name, p->cad->name, - (val & 0x20) ? "reverse" : "forward"); + printk(KERN_DEBUG "%s (%s): use data_%s for this!\n", + p->name, p->cad->name, + (val & 0x20) ? "reverse" : "forward"); if (val & 0x20) parport_gsc_data_reverse (p); else diff --git a/drivers/parport/parport_ip32.c b/drivers/parport/parport_ip32.c index ab215b650f41..48b084e86dc6 100644 --- a/drivers/parport/parport_ip32.c +++ b/drivers/parport/parport_ip32.c @@ -328,19 +328,19 @@ static void parport_ip32_dump_state(struct parport *p, char *str, "TST", "CFG"}; unsigned int ecr = readb(priv->regs.ecr); printk(KERN_DEBUG PPIP32 " ecr=0x%02x", ecr); - printk(" %s", - ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]); + pr_cont(" %s", + ecr_modes[(ecr & ECR_MODE_MASK) >> ECR_MODE_SHIFT]); if (ecr & ECR_nERRINTR) - printk(",nErrIntrEn"); + pr_cont(",nErrIntrEn"); if (ecr & ECR_DMAEN) - printk(",dmaEn"); + pr_cont(",dmaEn"); if (ecr & ECR_SERVINTR) - printk(",serviceIntr"); + pr_cont(",serviceIntr"); if (ecr & ECR_F_FULL) - printk(",f_full"); + pr_cont(",f_full"); if (ecr & ECR_F_EMPTY) - printk(",f_empty"); - printk("\n"); + pr_cont(",f_empty"); + pr_cont("\n"); } if (show_ecp_config) { unsigned int oecr, cnfgA, cnfgB; @@ -352,52 +352,53 @@ static void parport_ip32_dump_state(struct parport *p, char *str, writeb(ECR_MODE_PS2, priv->regs.ecr); writeb(oecr, priv->regs.ecr); printk(KERN_DEBUG PPIP32 " cnfgA=0x%02x", cnfgA); - printk(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses"); + pr_cont(" ISA-%s", (cnfgA & CNFGA_IRQ) ? "Level" : "Pulses"); switch (cnfgA & CNFGA_ID_MASK) { case CNFGA_ID_8: - printk(",8 bits"); + pr_cont(",8 bits"); break; case CNFGA_ID_16: - printk(",16 bits"); + pr_cont(",16 bits"); break; case CNFGA_ID_32: - printk(",32 bits"); + pr_cont(",32 bits"); break; default: - printk(",unknown ID"); + pr_cont(",unknown ID"); break; } if (!(cnfgA & CNFGA_nBYTEINTRANS)) - printk(",ByteInTrans"); + pr_cont(",ByteInTrans"); if ((cnfgA & CNFGA_ID_MASK) != CNFGA_ID_8) - printk(",%d byte%s left", cnfgA & CNFGA_PWORDLEFT, - ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : ""); - printk("\n"); + pr_cont(",%d byte%s left", + cnfgA & CNFGA_PWORDLEFT, + ((cnfgA & CNFGA_PWORDLEFT) > 1) ? "s" : ""); + pr_cont("\n"); printk(KERN_DEBUG PPIP32 " cnfgB=0x%02x", cnfgB); - printk(" irq=%u,dma=%u", - (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT, - (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT); - printk(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL)); + pr_cont(" irq=%u,dma=%u", + (cnfgB & CNFGB_IRQ_MASK) >> CNFGB_IRQ_SHIFT, + (cnfgB & CNFGB_DMA_MASK) >> CNFGB_DMA_SHIFT); + pr_cont(",intrValue=%d", !!(cnfgB & CNFGB_INTRVAL)); if (cnfgB & CNFGB_COMPRESS) - printk(",compress"); - printk("\n"); + pr_cont(",compress"); + pr_cont("\n"); } for (i = 0; i < 2; i++) { unsigned int dcr = i ? priv->dcr_cache : readb(priv->regs.dcr); printk(KERN_DEBUG PPIP32 " dcr(%s)=0x%02x", i ? "soft" : "hard", dcr); - printk(" %s", (dcr & DCR_DIR) ? "rev" : "fwd"); + pr_cont(" %s", (dcr & DCR_DIR) ? "rev" : "fwd"); if (dcr & DCR_IRQ) - printk(",ackIntEn"); + pr_cont(",ackIntEn"); if (!(dcr & DCR_SELECT)) - printk(",nSelectIn"); + pr_cont(",nSelectIn"); if (dcr & DCR_nINIT) - printk(",nInit"); + pr_cont(",nInit"); if (!(dcr & DCR_AUTOFD)) - printk(",nAutoFD"); + pr_cont(",nAutoFD"); if (!(dcr & DCR_STROBE)) - printk(",nStrobe"); - printk("\n"); + pr_cont(",nStrobe"); + pr_cont("\n"); } #define sep (f++ ? ',' : ' ') { @@ -405,20 +406,20 @@ static void parport_ip32_dump_state(struct parport *p, char *str, unsigned int dsr = readb(priv->regs.dsr); printk(KERN_DEBUG PPIP32 " dsr=0x%02x", dsr); if (!(dsr & DSR_nBUSY)) - printk("%cBusy", sep); + pr_cont("%cBusy", sep); if (dsr & DSR_nACK) - printk("%cnAck", sep); + pr_cont("%cnAck", sep); if (dsr & DSR_PERROR) - printk("%cPError", sep); + pr_cont("%cPError", sep); if (dsr & DSR_SELECT) - printk("%cSelect", sep); + pr_cont("%cSelect", sep); if (dsr & DSR_nFAULT) - printk("%cnFault", sep); + pr_cont("%cnFault", sep); if (!(dsr & DSR_nPRINT)) - printk("%c(Print)", sep); + pr_cont("%c(Print)", sep); if (dsr & DSR_TIMEOUT) - printk("%cTimeout", sep); - printk("\n"); + pr_cont("%cTimeout", sep); + pr_cont("\n"); } #undef sep } @@ -1337,9 +1338,8 @@ static unsigned int parport_ip32_fwp_wait_interrupt(struct parport *p) ecr = parport_ip32_read_econtrol(p); if ((ecr & ECR_F_EMPTY) && !(ecr & ECR_SERVINTR) && !lost_interrupt) { - printk(KERN_WARNING PPIP32 - "%s: lost interrupt in %s\n", - p->name, __func__); + pr_warn(PPIP32 "%s: lost interrupt in %s\n", + p->name, __func__); lost_interrupt = 1; } } @@ -1643,8 +1643,8 @@ static size_t parport_ip32_compat_write_data(struct parport *p, DSR_nBUSY | DSR_nFAULT)) { /* Avoid to flood the logs */ if (ready_before) - printk(KERN_INFO PPIP32 "%s: not ready in %s\n", - p->name, __func__); + pr_info(PPIP32 "%s: not ready in %s\n", + p->name, __func__); ready_before = 0; goto stop; } @@ -1704,7 +1704,7 @@ static size_t parport_ip32_ecp_write_data(struct parport *p, /* Event 49: PError goes high. */ if (parport_wait_peripheral(p, DSR_PERROR, DSR_PERROR)) { - printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s", + printk(KERN_DEBUG PPIP32 "%s: PError timeout in %s\n", p->name, __func__); physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; return 0; @@ -1724,8 +1724,8 @@ static size_t parport_ip32_ecp_write_data(struct parport *p, DSR_nBUSY | DSR_nFAULT)) { /* Avoid to flood the logs */ if (ready_before) - printk(KERN_INFO PPIP32 "%s: not ready in %s\n", - p->name, __func__); + pr_info(PPIP32 "%s: not ready in %s\n", + p->name, __func__); ready_before = 0; goto stop; } @@ -2064,8 +2064,7 @@ static __init struct parport *parport_ip32_probe_port(void) p->modes |= PARPORT_MODE_TRISTATE; if (!parport_ip32_fifo_supported(p)) { - printk(KERN_WARNING PPIP32 - "%s: error: FIFO disabled\n", p->name); + pr_warn(PPIP32 "%s: error: FIFO disabled\n", p->name); /* Disable hardware modes depending on a working FIFO. */ features &= ~PARPORT_IP32_ENABLE_SPP; features &= ~PARPORT_IP32_ENABLE_ECP; @@ -2077,8 +2076,7 @@ static __init struct parport *parport_ip32_probe_port(void) if (features & PARPORT_IP32_ENABLE_IRQ) { int irq = MACEISA_PARALLEL_IRQ; if (request_irq(irq, parport_ip32_interrupt, 0, p->name, p)) { - printk(KERN_WARNING PPIP32 - "%s: error: IRQ disabled\n", p->name); + pr_warn(PPIP32 "%s: error: IRQ disabled\n", p->name); /* DMA cannot work without interrupts. */ features &= ~PARPORT_IP32_ENABLE_DMA; } else { @@ -2091,8 +2089,7 @@ static __init struct parport *parport_ip32_probe_port(void) /* Allocate DMA resources */ if (features & PARPORT_IP32_ENABLE_DMA) { if (parport_ip32_dma_register()) - printk(KERN_WARNING PPIP32 - "%s: error: DMA disabled\n", p->name); + pr_warn(PPIP32 "%s: error: DMA disabled\n", p->name); else { pr_probe(p, "DMA support enabled\n"); p->dma = 0; /* arbitrary value != PARPORT_DMA_NONE */ @@ -2134,13 +2131,15 @@ static __init struct parport *parport_ip32_probe_port(void) parport_ip32_dump_state(p, "end init", 0); /* Print out what we found */ - printk(KERN_INFO "%s: SGI IP32 at 0x%lx (0x%lx)", - p->name, p->base, p->base_hi); + pr_info("%s: SGI IP32 at 0x%lx (0x%lx)", p->name, p->base, p->base_hi); if (p->irq != PARPORT_IRQ_NONE) - printk(", irq %d", p->irq); - printk(" ["); -#define printmode(x) if (p->modes & PARPORT_MODE_##x) \ - printk("%s%s", f++ ? "," : "", #x) + pr_cont(", irq %d", p->irq); + pr_cont(" ["); +#define printmode(x) \ +do { \ + if (p->modes & PARPORT_MODE_##x) \ + pr_cont("%s%s", f++ ? "," : "", #x); \ +} while (0) { unsigned int f = 0; printmode(PCSPP); @@ -2151,7 +2150,7 @@ static __init struct parport *parport_ip32_probe_port(void) printmode(DMA); } #undef printmode - printk("]\n"); + pr_cont("]\n"); parport_announce_port(p); return p; diff --git a/drivers/parport/parport_mfc3.c b/drivers/parport/parport_mfc3.c index 9f87faf939e3..d6bbe8446301 100644 --- a/drivers/parport/parport_mfc3.c +++ b/drivers/parport/parport_mfc3.c @@ -70,11 +70,6 @@ #define MAX_MFC 5 #undef DEBUG -#ifdef DEBUG -#define DPRINTK printk -#else -static inline int DPRINTK(void *nothing, ...) {return 0;} -#endif static struct parport *this_port[MAX_MFC] = {NULL, }; static volatile int dummy; /* for trigger readds */ @@ -84,7 +79,7 @@ static struct parport_operations pp_mfc3_ops; static void mfc3_write_data(struct parport *p, unsigned char data) { -DPRINTK(KERN_DEBUG "write_data %c\n",data); + pr_debug("write_data %c\n", data); dummy = pia(p)->pprb; /* clears irq bit */ /* Triggers also /STROBE.*/ @@ -128,13 +123,13 @@ static unsigned char control_mfc3_to_pc(unsigned char control) static void mfc3_write_control(struct parport *p, unsigned char control) { -DPRINTK(KERN_DEBUG "write_control %02x\n",control); + pr_debug("write_control %02x\n", control); pia(p)->ppra = (pia(p)->ppra & 0x1f) | control_pc_to_mfc3(control); } static unsigned char mfc3_read_control( struct parport *p) { -DPRINTK(KERN_DEBUG "read_control \n"); + pr_debug("read_control\n"); return control_mfc3_to_pc(pia(p)->ppra & 0xe0); } @@ -142,7 +137,7 @@ static unsigned char mfc3_frob_control( struct parport *p, unsigned char mask, u { unsigned char old; -DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); + pr_debug("frob_control mask %02x, value %02x\n", mask, val); old = mfc3_read_control(p); mfc3_write_control(p, (old & ~mask) ^ val); return old; @@ -171,7 +166,7 @@ static unsigned char mfc3_read_status(struct parport *p) unsigned char status; status = status_mfc3_to_pc(pia(p)->ppra & 0x1f); -DPRINTK(KERN_DEBUG "read_status %02x\n", status); + pr_debug("read_status %02x\n", status); return status; } @@ -202,7 +197,7 @@ static void mfc3_disable_irq(struct parport *p) static void mfc3_data_forward(struct parport *p) { - DPRINTK(KERN_DEBUG "forward\n"); + pr_debug("forward\n"); pia(p)->crb &= ~PIA_DDR; /* make data direction register visible */ pia(p)->pddrb = 255; /* all pins output */ pia(p)->crb |= PIA_DDR; /* make data register visible - default */ @@ -210,7 +205,7 @@ static void mfc3_data_forward(struct parport *p) static void mfc3_data_reverse(struct parport *p) { - DPRINTK(KERN_DEBUG "reverse\n"); + pr_debug("reverse\n"); pia(p)->crb &= ~PIA_DDR; /* make data direction register visible */ pia(p)->pddrb = 0; /* all pins input */ pia(p)->crb |= PIA_DDR; /* make data register visible - default */ @@ -325,7 +320,7 @@ static int __init parport_mfc3_init(void) p->dev = &z->dev; this_port[pias++] = p; - printk(KERN_INFO "%s: Multiface III port using irq\n", p->name); + pr_info("%s: Multiface III port using irq\n", p->name); /* XXX: set operating mode */ p->private_data = (void *)piabase; diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c index 1f17a39eabe8..77e37e3cb3a0 100644 --- a/drivers/parport/parport_pc.c +++ b/drivers/parport/parport_pc.c @@ -87,13 +87,6 @@ #undef DEBUG -#ifdef DEBUG -#define DPRINTK printk -#else -#define DPRINTK(stuff...) -#endif - - #define NR_SUPERIOS 3 static struct superio_struct { /* For Super-IO chips autodetection */ int io; @@ -118,8 +111,8 @@ static void frob_econtrol(struct parport *pb, unsigned char m, if (m != 0xff) ectr = inb(ECONTROL(pb)); - DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n", - m, v, ectr, (ectr & ~m) ^ v); + pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", + m, v, ectr, (ectr & ~m) ^ v); outb((ectr & ~m) ^ v, ECONTROL(pb)); } @@ -142,7 +135,7 @@ static int change_mode(struct parport *p, int m) unsigned char oecr; int mode; - DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m); + pr_debug("parport change_mode ECP-ISA to mode 0x%02x\n", m); if (!priv->ecr) { printk(KERN_DEBUG "change_mode: but there's no ECR!\n"); @@ -298,8 +291,8 @@ static size_t parport_pc_epp_read_data(struct parport *port, void *buf, status = inb(STATUS(port)); if (status & 0x01) { /* EPP timeout should never occur... */ - printk(KERN_DEBUG -"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name); + printk(KERN_DEBUG "%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", + port->name); clear_epp_timeout(port); } } @@ -727,7 +720,7 @@ static size_t parport_pc_compat_write_block_pio(struct parport *port, r = change_mode(port, ECR_PPF); /* Parallel port FIFO */ if (r) printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", - port->name); + port->name); port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; @@ -770,9 +763,8 @@ static size_t parport_pc_compat_write_block_pio(struct parport *port, PARPORT_STATUS_BUSY, PARPORT_STATUS_BUSY); if (r) - printk(KERN_DEBUG - "%s: BUSY timeout (%d) in compat_write_block_pio\n", - port->name, r); + printk(KERN_DEBUG "%s: BUSY timeout (%d) in compat_write_block_pio\n", + port->name, r); port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; @@ -810,8 +802,8 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) { - printk(KERN_DEBUG "%s: PError timeout (%d) " - "in ecp_write_block_pio\n", port->name, r); + printk(KERN_DEBUG "%s: PError timeout (%d) in ecp_write_block_pio\n", + port->name, r); } } @@ -824,7 +816,7 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, r = change_mode(port, ECR_ECP); /* ECP FIFO */ if (r) printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", - port->name); + port->name); port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; /* Write the data to the FIFO. */ @@ -867,8 +859,8 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, parport_frob_control(port, PARPORT_CONTROL_INIT, 0); r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0); if (r) - printk(KERN_DEBUG "%s: PE,1 timeout (%d) " - "in ecp_write_block_pio\n", port->name, r); + printk(KERN_DEBUG "%s: PE,1 timeout (%d) in ecp_write_block_pio\n", + port->name, r); parport_frob_control(port, PARPORT_CONTROL_INIT, @@ -877,17 +869,16 @@ static size_t parport_pc_ecp_write_block_pio(struct parport *port, PARPORT_STATUS_PAPEROUT, PARPORT_STATUS_PAPEROUT); if (r) - printk(KERN_DEBUG "%s: PE,2 timeout (%d) " - "in ecp_write_block_pio\n", port->name, r); + printk(KERN_DEBUG "%s: PE,2 timeout (%d) in ecp_write_block_pio\n", + port->name, r); } r = parport_wait_peripheral(port, PARPORT_STATUS_BUSY, PARPORT_STATUS_BUSY); if (r) - printk(KERN_DEBUG - "%s: BUSY timeout (%d) in ecp_write_block_pio\n", - port->name, r); + printk(KERN_DEBUG "%s: BUSY timeout (%d) in ecp_write_block_pio\n", + port->name, r); port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; @@ -982,28 +973,24 @@ static void show_parconfig_smsc37c669(int io, int key) outb(0xaa, io); if (verbose_probing) { - printk(KERN_INFO - "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, " - "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", + pr_info("SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n", cr1, cr4, cra, cr23, cr26, cr27); /* The documentation calls DMA and IRQ-Lines by letters, so the board maker can/will wire them appropriately/randomly... G=reserved H=IDE-irq, */ - printk(KERN_INFO - "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", - cr23 * 4, - (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', - (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', - cra & 0x0f); - printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n", - (cr23 * 4 >= 0x100) ? "yes" : "no", - (cr1 & 4) ? "yes" : "no"); - printk(KERN_INFO - "SMSC LPT Config: Port mode=%s, EPP version =%s\n", - (cr1 & 0x08) ? "Standard mode only (SPP)" - : modes[cr4 & 0x03], - (cr4 & 0x40) ? "1.7" : "1.9"); + pr_info("SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n", + cr23 * 4, + (cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-', + (cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-', + cra & 0x0f); + pr_info("SMSC LPT Config: enabled=%s power=%s\n", + (cr23 * 4 >= 0x100) ? "yes" : "no", + (cr1 & 4) ? "yes" : "no"); + pr_info("SMSC LPT Config: Port mode=%s, EPP version =%s\n", + (cr1 & 0x08) ? "Standard mode only (SPP)" + : modes[cr4 & 0x03], + (cr4 & 0x40) ? "1.7" : "1.9"); } /* Heuristics ! BIOS setup for this mainboard device limits @@ -1013,7 +1000,7 @@ static void show_parconfig_smsc37c669(int io, int key) if (cr23 * 4 >= 0x100) { /* if active */ s = find_free_superio(); if (s == NULL) - printk(KERN_INFO "Super-IO: too many chips!\n"); + pr_info("Super-IO: too many chips!\n"); else { int d; switch (cr23 * 4) { @@ -1078,26 +1065,24 @@ static void show_parconfig_winbond(int io, int key) outb(0xaa, io); if (verbose_probing) { - printk(KERN_INFO - "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", - cr30, cr60, cr61, cr70, cr74, crf0); - printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", - (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); + pr_info("Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n", + cr30, cr60, cr61, cr70, cr74, crf0); + pr_info("Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ", + (cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f); if ((cr74 & 0x07) > 3) pr_cont("dma=none\n"); else pr_cont("dma=%d\n", cr74 & 0x07); - printk(KERN_INFO - "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", - irqtypes[crf0>>7], (crf0>>3)&0x0f); - printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", - modes[crf0 & 0x07]); + pr_info("Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n", + irqtypes[crf0 >> 7], (crf0 >> 3) & 0x0f); + pr_info("Winbond LPT Config: Port mode=%s\n", + modes[crf0 & 0x07]); } if (cr30 & 0x01) { /* the settings can be interrogated later ... */ s = find_free_superio(); if (s == NULL) - printk(KERN_INFO "Super-IO: too many chips!\n"); + pr_info("Super-IO: too many chips!\n"); else { s->io = (cr60 << 8) | cr61; s->irq = cr70 & 0x0f; @@ -1151,9 +1136,8 @@ static void decode_winbond(int efer, int key, int devid, int devrev, int oldid) progif = 0; if (verbose_probing) - printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x " - "devid=%02x devrev=%02x oldid=%02x type=%s\n", - efer, key, devid, devrev, oldid, type); + pr_info("Winbond chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x oldid=%02x type=%s\n", + efer, key, devid, devrev, oldid, type); if (progif == 2) show_parconfig_winbond(efer, key); @@ -1184,9 +1168,8 @@ static void decode_smsc(int efer, int key, int devid, int devrev) type = "37c666GT"; if (verbose_probing) - printk(KERN_INFO "SMSC chip at EFER=0x%x " - "key=0x%02x devid=%02x devrev=%02x type=%s\n", - efer, key, devid, devrev, type); + pr_info("SMSC chip at EFER=0x%x key=0x%02x devid=%02x devrev=%02x type=%s\n", + efer, key, devid, devrev, type); if (func) func(efer, key); @@ -1358,7 +1341,7 @@ static void detect_and_report_it87(void) dev |= inb(0x2f); if (dev == 0x8712 || dev == 0x8705 || dev == 0x8715 || dev == 0x8716 || dev == 0x8718 || dev == 0x8726) { - printk(KERN_INFO "IT%04X SuperIO detected.\n", dev); + pr_info("IT%04X SuperIO detected\n", dev); outb(0x07, 0x2E); /* Parallel Port */ outb(0x03, 0x2F); outb(0xF0, 0x2E); /* BOOT 0x80 off */ @@ -1445,8 +1428,8 @@ static int parport_SPP_supported(struct parport *pb) if (user_specified) /* That didn't work, but the user thinks there's a * port here. */ - printk(KERN_INFO "parport 0x%lx (WARNING): CTR: " - "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); + pr_info("parport 0x%lx (WARNING): CTR: wrote 0x%02x, read 0x%02x\n", + pb->base, w, r); /* Try the data register. The data lines aren't tri-stated at * this stage, so we expect back what we wrote. */ @@ -1464,10 +1447,9 @@ static int parport_SPP_supported(struct parport *pb) if (user_specified) { /* Didn't work, but the user is convinced this is the * place. */ - printk(KERN_INFO "parport 0x%lx (WARNING): DATA: " - "wrote 0x%02x, read 0x%02x\n", pb->base, w, r); - printk(KERN_INFO "parport 0x%lx: You gave this address, " - "but there is probably no parallel port there!\n", + pr_info("parport 0x%lx (WARNING): DATA: wrote 0x%02x, read 0x%02x\n", + pb->base, w, r); + pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n", pb->base); } @@ -1620,7 +1602,7 @@ static int parport_ECP_supported(struct parport *pb) if (i <= priv->fifo_depth) { if (verbose_probing) printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n", - pb->base, i); + pb->base, i); } else /* Number of bytes we know we can write if we get an interrupt. */ @@ -1642,7 +1624,7 @@ static int parport_ECP_supported(struct parport *pb) if (i <= priv->fifo_depth) { if (verbose_probing) - printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n", + pr_info("0x%lx: readIntrThreshold is %d\n", pb->base, i); } else /* Number of bytes we can read if we get an interrupt. */ @@ -1657,17 +1639,14 @@ static int parport_ECP_supported(struct parport *pb) switch (pword) { case 0: pword = 2; - printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", - pb->base); + pr_warn("0x%lx: Unsupported pword size!\n", pb->base); break; case 2: pword = 4; - printk(KERN_WARNING "0x%lx: Unsupported pword size!\n", - pb->base); + pr_warn("0x%lx: Unsupported pword size!\n", pb->base); break; default: - printk(KERN_WARNING "0x%lx: Unknown implementation ID\n", - pb->base); + pr_warn("0x%lx: Unknown implementation ID\n", pb->base); /* Fall through - Assume 1 */ case 1: pword = 1; @@ -1676,14 +1655,14 @@ static int parport_ECP_supported(struct parport *pb) if (verbose_probing) { printk(KERN_DEBUG "0x%lx: PWord is %d bits\n", - pb->base, 8 * pword); + pb->base, 8 * pword); - printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base, - config & 0x80 ? "Level" : "Pulses"); + printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", + pb->base, config & 0x80 ? "Level" : "Pulses"); configb = inb(CONFIGB(pb)); printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n", - pb->base, config, configb); + pb->base, config, configb); printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base); if ((configb >> 3) & 0x07) pr_cont("%d", intrline[(configb >> 3) & 0x07]); @@ -2107,9 +2086,9 @@ struct parport *parport_pc_probe_port(unsigned long int base, p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3; - printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base); + pr_info("%s: PC-style at 0x%lx", p->name, p->base); if (p->base_hi && priv->ecr) - printk(KERN_CONT " (0x%lx)", p->base_hi); + pr_cont(" (0x%lx)", p->base_hi); if (p->irq == PARPORT_IRQ_AUTO) { p->irq = PARPORT_IRQ_NONE; parport_irq_probe(p); @@ -2120,7 +2099,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, p->irq = PARPORT_IRQ_NONE; } if (p->irq != PARPORT_IRQ_NONE) { - printk(KERN_CONT ", irq %d", p->irq); + pr_cont(", irq %d", p->irq); priv->ctr_writable |= 0x10; if (p->dma == PARPORT_DMA_AUTO) { @@ -2144,41 +2123,39 @@ struct parport *parport_pc_probe_port(unsigned long int base, /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ #endif /* IEEE 1284 support */ if (p->dma != PARPORT_DMA_NONE) { - printk(KERN_CONT ", dma %d", p->dma); + pr_cont(", dma %d", p->dma); p->modes |= PARPORT_MODE_DMA; } else - printk(KERN_CONT ", using FIFO"); + pr_cont(", using FIFO"); } else /* We can't use the DMA channel after all. */ p->dma = PARPORT_DMA_NONE; #endif /* Allowed to use FIFO/DMA */ - printk(KERN_CONT " ["); + pr_cont(" ["); -#define printmode(x) \ - {\ - if (p->modes & PARPORT_MODE_##x) {\ - printk(KERN_CONT "%s%s", f ? "," : "", #x);\ - f++;\ - } \ - } +#define printmode(x) \ +do { \ + if (p->modes & PARPORT_MODE_##x) \ + pr_cont("%s%s", f++ ? "," : "", #x); \ +} while (0) { int f = 0; printmode(PCSPP); printmode(TRISTATE); - printmode(COMPAT) + printmode(COMPAT); printmode(EPP); printmode(ECP); printmode(DMA); } #undef printmode #ifndef CONFIG_PARPORT_1284 - printk(KERN_CONT "(,...)"); + pr_cont("(,...)"); #endif /* CONFIG_PARPORT_1284 */ - printk(KERN_CONT "]\n"); + pr_cont("]\n"); if (probedirq != PARPORT_IRQ_NONE) - printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq); + pr_info("%s: irq %d detected\n", p->name, probedirq); /* If No ECP release the ports grabbed above. */ if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) { @@ -2193,8 +2170,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, if (p->irq != PARPORT_IRQ_NONE) { if (request_irq(p->irq, parport_irq_handler, irqflags, p->name, p)) { - printk(KERN_WARNING "%s: irq %d in use, " - "resorting to polled operation\n", + pr_warn("%s: irq %d in use, resorting to polled operation\n", p->name, p->irq); p->irq = PARPORT_IRQ_NONE; p->dma = PARPORT_DMA_NONE; @@ -2204,8 +2180,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, #ifdef HAS_DMA if (p->dma != PARPORT_DMA_NONE) { if (request_dma(p->dma, p->name)) { - printk(KERN_WARNING "%s: dma %d in use, " - "resorting to PIO operation\n", + pr_warn("%s: dma %d in use, resorting to PIO operation\n", p->name, p->dma); p->dma = PARPORT_DMA_NONE; } else { @@ -2215,9 +2190,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, &priv->dma_handle, GFP_KERNEL); if (!priv->dma_buf) { - printk(KERN_WARNING "%s: " - "cannot get buffer for DMA, " - "resorting to PIO operation\n", + pr_warn("%s: cannot get buffer for DMA, resorting to PIO operation\n", p->name); free_dma(p->dma); p->dma = PARPORT_DMA_NONE; @@ -2313,7 +2286,7 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, int irq; int i; - DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n"); + pr_debug("sio_ite_8872_probe()\n"); /* make sure which one chip */ for (i = 0; i < 5; i++) { @@ -2330,7 +2303,7 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, } } if (i >= 5) { - printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n"); + pr_info("parport_pc: cannot find ITE8872 INTA\n"); return 0; } @@ -2339,29 +2312,28 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, switch (type) { case 0x2: - printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n"); + pr_info("parport_pc: ITE8871 found (1P)\n"); ite8872set = 0x64200000; break; case 0xa: - printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n"); + pr_info("parport_pc: ITE8875 found (1P)\n"); ite8872set = 0x64200000; break; case 0xe: - printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n"); + pr_info("parport_pc: ITE8872 found (2S1P)\n"); ite8872set = 0x64e00000; break; case 0x6: - printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n"); + pr_info("parport_pc: ITE8873 found (1S)\n"); release_region(inta_addr[i], 32); return 0; case 0x8: - printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n"); + pr_info("parport_pc: ITE8874 found (2S)\n"); release_region(inta_addr[i], 32); return 0; default: - printk(KERN_INFO "parport_pc: unknown ITE887x\n"); - printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' " - "output to Rich.Liu@ite.com.tw\n"); + pr_info("parport_pc: unknown ITE887x\n"); + pr_info("parport_pc: please mail 'lspci -nvv' output to Rich.Liu@ite.com.tw\n"); release_region(inta_addr[i], 32); return 0; } @@ -2379,11 +2351,9 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, pci_write_config_dword(pdev, 0x9c, ite8872set | (ite8872_irq * 0x11111)); - DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq); - DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n", - ite8872_lpt); - DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n", - ite8872_lpthi); + pr_debug("ITE887x: The IRQ is %d\n", ite8872_irq); + pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt); + pr_debug("ITE887x: The PARALLEL I/O porthi is 0x%x\n", ite8872_lpthi); /* Let the user (or defaults) steer us away from interrupts */ irq = ite8872_irq; @@ -2396,9 +2366,8 @@ static int sio_ite_8872_probe(struct pci_dev *pdev, int autoirq, int autodma, release_region(inta_addr[i], 32); if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi, irq, PARPORT_DMA_NONE, &pdev->dev, 0)) { - printk(KERN_INFO - "parport_pc: ITE 8872 parallel port: io=0x%X", - ite8872_lpt); + pr_info("parport_pc: ITE 8872 parallel port: io=0x%X", + ite8872_lpt); if (irq != PARPORT_IRQ_NONE) pr_cont(", irq=%d", irq); pr_cont("\n"); @@ -2471,8 +2440,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, have_epp = 1; break; default: - printk(KERN_DEBUG - "parport_pc: probing current configuration\n"); + printk(KERN_DEBUG "parport_pc: probing current configuration\n"); siofunc = VIA_FUNCTION_PROBE; break; } @@ -2508,12 +2476,11 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, port1 = inb(VIA_CONFIG_DATA) << 2; printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n", - port1); + port1); if (port1 == 0x3BC && have_epp) { outb(via->viacfg_parport_base, VIA_CONFIG_INDEX); outb((0x378 >> 2), VIA_CONFIG_DATA); - printk(KERN_DEBUG - "parport_pc: Parallel port base changed to 0x378\n"); + printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n"); port1 = 0x378; } @@ -2525,7 +2492,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp); if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) { - printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n"); + pr_info("parport_pc: VIA parallel port disabled in BIOS\n"); return 0; } @@ -2558,9 +2525,8 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, case 0x278: port2 = 0x678; break; default: - printk(KERN_INFO - "parport_pc: Weird VIA parport base 0x%X, ignoring\n", - port1); + pr_info("parport_pc: Weird VIA parport base 0x%X, ignoring\n", + port1); return 0; } @@ -2579,8 +2545,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, /* finally, do the probe with values obtained */ if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) { - printk(KERN_INFO - "parport_pc: VIA parallel port: io=0x%X", port1); + pr_info("parport_pc: VIA parallel port: io=0x%X", port1); if (irq != PARPORT_IRQ_NONE) pr_cont(", irq=%d", irq); if (dma != PARPORT_DMA_NONE) @@ -2589,7 +2554,7 @@ static int sio_via_probe(struct pci_dev *pdev, int autoirq, int autodma, return 1; } - printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", + pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n", port1, irq, dma); return 0; } @@ -2854,14 +2819,12 @@ static int parport_pc_pci_probe(struct pci_dev *dev, /* TODO: test if sharing interrupts works */ irq = dev->irq; if (irq == IRQ_NONE) { - printk(KERN_DEBUG - "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", - id->vendor, id->device, io_lo, io_hi); + printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n", + id->vendor, id->device, io_lo, io_hi); irq = PARPORT_IRQ_NONE; } else { - printk(KERN_DEBUG - "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", - id->vendor, id->device, io_lo, io_hi, irq); + printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n", + id->vendor, id->device, io_lo, io_hi, irq); } data->ports[count] = parport_pc_probe_port(io_lo, io_hi, irq, @@ -3111,7 +3074,7 @@ static int __init parport_parse_param(const char *s, int *val, if (ep != s) *val = r; else { - printk(KERN_ERR "parport: bad specifier `%s'\n", s); + pr_err("parport: bad specifier `%s'\n", s); return -1; } } @@ -3133,8 +3096,8 @@ static int __init parport_parse_dma(const char *dmastr, int *val) #ifdef CONFIG_PCI static int __init parport_init_mode_setup(char *str) { - printk(KERN_DEBUG - "parport_pc.c: Specified parameter parport_init_mode=%s\n", str); + printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", + str); if (!strcmp(str, "spp")) parport_init_mode = 1; @@ -3201,10 +3164,7 @@ static int __init parse_parport_params(void) irqval[0] = val; break; default: - printk(KERN_WARNING - "parport_pc: irq specified " - "without base address. Use 'io=' " - "to specify one\n"); + pr_warn("parport_pc: irq specified without base address. Use 'io=' to specify one\n"); } if (dma[0] && !parport_parse_dma(dma[0], &val)) @@ -3214,10 +3174,7 @@ static int __init parse_parport_params(void) dmaval[0] = val; break; default: - printk(KERN_WARNING - "parport_pc: dma specified " - "without base address. Use 'io=' " - "to specify one\n"); + pr_warn("parport_pc: dma specified without base address. Use 'io=' to specify one\n"); } } return 0; @@ -3256,12 +3213,12 @@ static int __init parport_setup(char *str) val = simple_strtoul(str, &endptr, 0); if (endptr == str) { - printk(KERN_WARNING "parport=%s not understood\n", str); + pr_warn("parport=%s not understood\n", str); return 1; } if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) { - printk(KERN_ERR "parport=%s ignored, too many ports\n", str); + pr_err("parport=%s ignored, too many ports\n", str); return 1; } diff --git a/drivers/parport/parport_sunbpp.c b/drivers/parport/parport_sunbpp.c index d5a669b60c27..e840c1b5ab90 100644 --- a/drivers/parport/parport_sunbpp.c +++ b/drivers/parport/parport_sunbpp.c @@ -314,7 +314,7 @@ static int bpp_probe(struct platform_device *op) value_tcr &= ~P_TCR_DIR; sbus_writeb(value_tcr, ®s->p_tcr); - printk(KERN_INFO "%s: sunbpp at 0x%lx\n", p->name, p->base); + pr_info("%s: sunbpp at 0x%lx\n", p->name, p->base); dev_set_drvdata(&op->dev, p); diff --git a/drivers/parport/probe.c b/drivers/parport/probe.c index e5e6a463a941..7e6d713fa5ac 100644 --- a/drivers/parport/probe.c +++ b/drivers/parport/probe.c @@ -38,16 +38,16 @@ static void pretty_print(struct parport *port, int device) { struct parport_device_info *info = &port->probe_info[device + 1]; - printk(KERN_INFO "%s", port->name); + pr_info("%s", port->name); if (device >= 0) - printk (" (addr %d)", device); + pr_cont(" (addr %d)", device); - printk (": %s", classes[info->class].descr); + pr_cont(": %s", classes[info->class].descr); if (info->class) - printk(", %s %s", info->mfr, info->model); + pr_cont(", %s %s", info->mfr, info->model); - printk("\n"); + pr_cont("\n"); } static void parse_data(struct parport *port, int device, char *str) @@ -58,7 +58,7 @@ static void parse_data(struct parport *port, int device, char *str) struct parport_device_info *info = &port->probe_info[device + 1]; if (!txt) { - printk(KERN_WARNING "%s probe: memory squeeze\n", port->name); + pr_warn("%s probe: memory squeeze\n", port->name); return; } strcpy(txt, str); @@ -98,7 +98,8 @@ static void parse_data(struct parport *port, int device, char *str) goto rock_on; } } - printk(KERN_WARNING "%s probe: warning, class '%s' not understood.\n", port->name, sep); + pr_warn("%s probe: warning, class '%s' not understood\n", + port->name, sep); info->class = PARPORT_CLASS_OTHER; } else if (!strcmp(p, "CMD") || !strcmp(p, "COMMAND SET")) { @@ -177,9 +178,8 @@ static ssize_t parport_read_device_id (struct parport *port, char *buffer, * just return constant nibble forever. This catches * also those cases. */ if (idlens[0] == 0 || idlens[0] > 0xFFF) { - printk (KERN_DEBUG "%s: reported broken Device ID" - " length of %#zX bytes\n", - port->name, idlens[0]); + printk(KERN_DEBUG "%s: reported broken Device ID length of %#zX bytes\n", + port->name, idlens[0]); return -EIO; } numidlens = 2; @@ -201,10 +201,8 @@ static ssize_t parport_read_device_id (struct parport *port, char *buffer, if (port->physport->ieee1284.phase != IEEE1284_PH_HBUSY_DAVAIL) { if (belen != len) { - printk (KERN_DEBUG "%s: Device ID was %zd bytes" - " while device told it would be %d" - " bytes\n", - port->name, len, belen); + printk(KERN_DEBUG "%s: Device ID was %zd bytes while device told it would be %d bytes\n", + port->name, len, belen); } goto done; } @@ -214,11 +212,9 @@ static ssize_t parport_read_device_id (struct parport *port, char *buffer, * the first 256 bytes or so that we must have read so * far. */ if (buffer[len-1] == ';') { - printk (KERN_DEBUG "%s: Device ID reading stopped" - " before device told data not available. " - "Current idlen %u of %u, len bytes %02X %02X\n", - port->name, current_idlen, numidlens, - length[0], length[1]); + printk(KERN_DEBUG "%s: Device ID reading stopped before device told data not available. Current idlen %u of %u, len bytes %02X %02X\n", + port->name, current_idlen, numidlens, + length[0], length[1]); goto done; } } diff --git a/drivers/parport/procfs.c b/drivers/parport/procfs.c index ee7b5daabfd4..d740eba3c099 100644 --- a/drivers/parport/procfs.c +++ b/drivers/parport/procfs.c @@ -210,7 +210,11 @@ static int do_hardware_modes(struct ctl_table *table, int write, return -EACCES; { -#define printmode(x) {if(port->modes&PARPORT_MODE_##x){len+=sprintf(buffer+len,"%s%s",f?",":"",#x);f++;}} +#define printmode(x) \ +do { \ + if (port->modes & PARPORT_MODE_##x) \ + len += sprintf(buffer + len, "%s%s", f++ ? "," : "", #x); \ +} while (0) int f = 0; printmode(PCSPP); printmode(TRISTATE); diff --git a/drivers/parport/share.c b/drivers/parport/share.c index d6920ebeabcd..7fec4fefe151 100644 --- a/drivers/parport/share.c +++ b/drivers/parport/share.c @@ -278,46 +278,32 @@ static int port_detect(struct device *dev, void *dev_drv) int __parport_register_driver(struct parport_driver *drv, struct module *owner, const char *mod_name) { - if (drv->devmodel) { - /* using device model */ - int ret; - - /* initialize common driver fields */ - drv->driver.name = drv->name; - drv->driver.bus = &parport_bus_type; - drv->driver.owner = owner; - drv->driver.mod_name = mod_name; - ret = driver_register(&drv->driver); - if (ret) - return ret; + /* using device model */ + int ret; - /* - * check if bus has any parallel port registered, if - * none is found then load the lowlevel driver. - */ - ret = bus_for_each_dev(&parport_bus_type, NULL, NULL, - port_detect); - if (!ret) - get_lowlevel_driver(); - - mutex_lock(®istration_lock); - if (drv->match_port) - bus_for_each_dev(&parport_bus_type, NULL, drv, - port_check); - mutex_unlock(®istration_lock); - } else { - struct parport *port; - - drv->devmodel = false; - - if (list_empty(&portlist)) - get_lowlevel_driver(); - mutex_lock(®istration_lock); - list_for_each_entry(port, &portlist, list) - drv->attach(port); - list_add(&drv->list, &drivers); - mutex_unlock(®istration_lock); - } + /* initialize common driver fields */ + drv->driver.name = drv->name; + drv->driver.bus = &parport_bus_type; + drv->driver.owner = owner; + drv->driver.mod_name = mod_name; + ret = driver_register(&drv->driver); + if (ret) + return ret; + + /* + * check if bus has any parallel port registered, if + * none is found then load the lowlevel driver. + */ + ret = bus_for_each_dev(&parport_bus_type, NULL, NULL, + port_detect); + if (!ret) + get_lowlevel_driver(); + + mutex_lock(®istration_lock); + if (drv->match_port) + bus_for_each_dev(&parport_bus_type, NULL, drv, + port_check); + mutex_unlock(®istration_lock); return 0; } @@ -352,17 +338,9 @@ static int port_detach(struct device *dev, void *_drv) void parport_unregister_driver(struct parport_driver *drv) { - struct parport *port; - mutex_lock(®istration_lock); - if (drv->devmodel) { - bus_for_each_dev(&parport_bus_type, NULL, drv, port_detach); - driver_unregister(&drv->driver); - } else { - list_del_init(&drv->list); - list_for_each_entry(port, &portlist, list) - drv->detach(port); - } + bus_for_each_dev(&parport_bus_type, NULL, drv, port_detach); + driver_unregister(&drv->driver); mutex_unlock(®istration_lock); } EXPORT_SYMBOL(parport_unregister_driver); @@ -554,8 +532,8 @@ void parport_announce_port(struct parport *port) #endif if (!port->dev) - printk(KERN_WARNING "%s: fix this legacy no-device port driver!\n", - port->name); + pr_warn("%s: fix this legacy no-device port driver!\n", + port->name); parport_proc_register(port); mutex_lock(®istration_lock); @@ -641,47 +619,48 @@ void parport_remove_port(struct parport *port) } EXPORT_SYMBOL(parport_remove_port); +static void free_pardevice(struct device *dev) +{ + struct pardevice *par_dev = to_pardevice(dev); + + kfree(par_dev->name); + kfree(par_dev); +} + /** - * parport_register_device - register a device on a parallel port + * parport_register_dev_model - register a device on a parallel port * @port: port to which the device is attached * @name: a name to refer to the device - * @pf: preemption callback - * @kf: kick callback (wake-up) - * @irq_func: interrupt handler - * @flags: registration flags - * @handle: data for callback functions + * @par_dev_cb: struct containing callbacks + * @id: device number to be given to the device * * This function, called by parallel port device drivers, * declares that a device is connected to a port, and tells the * system all it needs to know. * - * The @name is allocated by the caller and must not be - * deallocated until the caller calls @parport_unregister_device - * for that device. - * - * The preemption callback function, @pf, is called when this - * device driver has claimed access to the port but another - * device driver wants to use it. It is given @handle as its - * parameter, and should return zero if it is willing for the - * system to release the port to another driver on its behalf. - * If it wants to keep control of the port it should return - * non-zero, and no action will be taken. It is good manners for - * the driver to try to release the port at the earliest - * opportunity after its preemption callback rejects a preemption - * attempt. Note that if a preemption callback is happy for - * preemption to go ahead, there is no need to release the port; - * it is done automatically. This function may not block, as it - * may be called from interrupt context. If the device driver - * does not support preemption, @pf can be %NULL. + * The struct pardev_cb contains pointer to callbacks. preemption + * callback function, @preempt, is called when this device driver + * has claimed access to the port but another device driver wants + * to use it. It is given, @private, as its parameter, and should + * return zero if it is willing for the system to release the port + * to another driver on its behalf. If it wants to keep control of + * the port it should return non-zero, and no action will be taken. + * It is good manners for the driver to try to release the port at + * the earliest opportunity after its preemption callback rejects a + * preemption attempt. Note that if a preemption callback is happy + * for preemption to go ahead, there is no need to release the + * port; it is done automatically. This function may not block, as + * it may be called from interrupt context. If the device driver + * does not support preemption, @preempt can be %NULL. * - * The wake-up ("kick") callback function, @kf, is called when + * The wake-up ("kick") callback function, @wakeup, is called when * the port is available to be claimed for exclusive access; that * is, parport_claim() is guaranteed to succeed when called from * inside the wake-up callback function. If the driver wants to * claim the port it should do so; otherwise, it need not take * any action. This function may not block, as it may be called * from interrupt context. If the device driver does not want to - * be explicitly invited to claim the port in this way, @kf can + * be explicitly invited to claim the port in this way, @wakeup can * be %NULL. * * The interrupt handler, @irq_func, is called when an interrupt @@ -711,138 +690,6 @@ EXPORT_SYMBOL(parport_remove_port); **/ struct pardevice * -parport_register_device(struct parport *port, const char *name, - int (*pf)(void *), void (*kf)(void *), - void (*irq_func)(void *), - int flags, void *handle) -{ - struct pardevice *tmp; - - if (port->physport->flags & PARPORT_FLAG_EXCL) { - /* An exclusive device is registered. */ - printk(KERN_DEBUG "%s: no more devices allowed\n", - port->name); - return NULL; - } - - if (flags & PARPORT_DEV_LURK) { - if (!pf || !kf) { - printk(KERN_INFO "%s: refused to register lurking device (%s) without callbacks\n", port->name, name); - return NULL; - } - } - - if (flags & PARPORT_DEV_EXCL) { - if (port->physport->devices) { - /* - * If a device is already registered and this new - * device wants exclusive access, then no need to - * continue as we can not grant exclusive access to - * this device. - */ - pr_err("%s: cannot grant exclusive access for device %s\n", - port->name, name); - return NULL; - } - } - - /* - * We up our own module reference count, and that of the port - * on which a device is to be registered, to ensure that - * neither of us gets unloaded while we sleep in (e.g.) - * kmalloc. - */ - if (!try_module_get(port->ops->owner)) - return NULL; - - parport_get_port(port); - - tmp = kmalloc(sizeof(struct pardevice), GFP_KERNEL); - if (!tmp) - goto out; - - tmp->state = kmalloc(sizeof(struct parport_state), GFP_KERNEL); - if (!tmp->state) - goto out_free_pardevice; - - tmp->name = name; - tmp->port = port; - tmp->daisy = -1; - tmp->preempt = pf; - tmp->wakeup = kf; - tmp->private = handle; - tmp->flags = flags; - tmp->irq_func = irq_func; - tmp->waiting = 0; - tmp->timeout = 5 * HZ; - tmp->devmodel = false; - - /* Chain this onto the list */ - tmp->prev = NULL; - /* - * This function must not run from an irq handler so we don' t need - * to clear irq on the local CPU. -arca - */ - spin_lock(&port->physport->pardevice_lock); - - if (flags & PARPORT_DEV_EXCL) { - if (port->physport->devices) { - spin_unlock(&port->physport->pardevice_lock); - printk(KERN_DEBUG - "%s: cannot grant exclusive access for device %s\n", - port->name, name); - goto out_free_all; - } - port->flags |= PARPORT_FLAG_EXCL; - } - - tmp->next = port->physport->devices; - wmb(); /* - * Make sure that tmp->next is written before it's - * added to the list; see comments marked 'no locking - * required' - */ - if (port->physport->devices) - port->physport->devices->prev = tmp; - port->physport->devices = tmp; - spin_unlock(&port->physport->pardevice_lock); - - init_waitqueue_head(&tmp->wait_q); - tmp->timeslice = parport_default_timeslice; - tmp->waitnext = tmp->waitprev = NULL; - - /* - * This has to be run as last thing since init_state may need other - * pardevice fields. -arca - */ - port->ops->init_state(tmp, tmp->state); - if (!test_and_set_bit(PARPORT_DEVPROC_REGISTERED, &port->devflags)) { - port->proc_device = tmp; - parport_device_proc_register(tmp); - } - return tmp; - - out_free_all: - kfree(tmp->state); - out_free_pardevice: - kfree(tmp); - out: - parport_put_port(port); - module_put(port->ops->owner); - - return NULL; -} -EXPORT_SYMBOL(parport_register_device); - -static void free_pardevice(struct device *dev) -{ - struct pardevice *par_dev = to_pardevice(dev); - - kfree(par_dev->name); - kfree(par_dev); -} - -struct pardevice * parport_register_dev_model(struct parport *port, const char *name, const struct pardev_cb *par_dev_cb, int id) { @@ -996,7 +843,7 @@ void parport_unregister_device(struct pardevice *dev) #ifdef PARPORT_PARANOID if (!dev) { - printk(KERN_ERR "parport_unregister_device: passed NULL\n"); + pr_err("%s: passed NULL\n", __func__); return; } #endif @@ -1046,10 +893,7 @@ void parport_unregister_device(struct pardevice *dev) spin_unlock_irq(&port->waitlist_lock); kfree(dev->state); - if (dev->devmodel) - device_unregister(&dev->dev); - else - kfree(dev); + device_unregister(&dev->dev); module_put(port->ops->owner); parport_put_port(port); @@ -1137,8 +981,7 @@ int parport_claim(struct pardevice *dev) unsigned long flags; if (port->cad == dev) { - printk(KERN_INFO "%s: %s already owner\n", - dev->port->name,dev->name); + pr_info("%s: %s already owner\n", dev->port->name, dev->name); return 0; } @@ -1158,9 +1001,8 @@ int parport_claim(struct pardevice *dev) * I think we'll actually deadlock rather than * get here, but just in case.. */ - printk(KERN_WARNING - "%s: %s released port when preempted!\n", - port->name, oldcad->name); + pr_warn("%s: %s released port when preempted!\n", + port->name, oldcad->name); if (port->cad) goto blocked; } @@ -1260,7 +1102,8 @@ int parport_claim_or_block(struct pardevice *dev) r = parport_claim(dev); if (r == -EAGAIN) { #ifdef PARPORT_DEBUG_SHARING - printk(KERN_DEBUG "%s: parport_claim() returned -EAGAIN\n", dev->name); + printk(KERN_DEBUG "%s: parport_claim() returned -EAGAIN\n", + dev->name); #endif /* * FIXME!!! Use the proper locking for dev->waiting, @@ -1293,7 +1136,7 @@ int parport_claim_or_block(struct pardevice *dev) if (dev->port->physport->cad != dev) printk(KERN_DEBUG "%s: exiting parport_claim_or_block but %s owns port!\n", dev->name, dev->port->physport->cad ? - dev->port->physport->cad->name:"nobody"); + dev->port->physport->cad->name : "nobody"); #endif } dev->waiting = 0; @@ -1320,8 +1163,8 @@ void parport_release(struct pardevice *dev) write_lock_irqsave(&port->cad_lock, flags); if (port->cad != dev) { write_unlock_irqrestore(&port->cad_lock, flags); - printk(KERN_WARNING "%s: %s tried to release parport when not owner\n", - port->name, dev->name); + pr_warn("%s: %s tried to release parport when not owner\n", + port->name, dev->name); return; } @@ -1361,7 +1204,8 @@ void parport_release(struct pardevice *dev) if (dev->port->cad) /* racy but no matter */ return; } else { - printk(KERN_ERR "%s: don't know how to wake %s\n", port->name, pd->name); + pr_err("%s: don't know how to wake %s\n", + port->name, pd->name); } } diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index 0144075b11a6..373ea8d4f7a1 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -15,7 +15,6 @@ struct zynqmp_reset_data { struct reset_controller_dev rcdev; - const struct zynqmp_eemi_ops *eemi_ops; }; static inline struct zynqmp_reset_data * @@ -27,28 +26,23 @@ to_zynqmp_reset_data(struct reset_controller_dev *rcdev) static int zynqmp_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); - - return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id, - PM_RESET_ACTION_ASSERT); + return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id, + PM_RESET_ACTION_ASSERT); } static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); - - return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id, - PM_RESET_ACTION_RELEASE); + return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id, + PM_RESET_ACTION_RELEASE); } static int zynqmp_reset_status(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); int val, err; - err = priv->eemi_ops->reset_get_status(ZYNQMP_RESET_ID + id, &val); + err = zynqmp_pm_reset_get_status(ZYNQMP_RESET_ID + id, &val); if (err) return err; @@ -58,10 +52,8 @@ static int zynqmp_reset_status(struct reset_controller_dev *rcdev, static int zynqmp_reset_reset(struct reset_controller_dev *rcdev, unsigned long id) { - struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev); - - return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id, - PM_RESET_ACTION_PULSE); + return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id, + PM_RESET_ACTION_PULSE); } static const struct reset_control_ops zynqmp_reset_ops = { @@ -79,10 +71,6 @@ static int zynqmp_reset_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - priv->eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(priv->eemi_ops)) - return PTR_ERR(priv->eemi_ops); - platform_set_drvdata(pdev, priv); priv->rcdev.ops = &zynqmp_reset_ops; diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c index 526e3215d8fe..ae1e248a8fb8 100644 --- a/drivers/slimbus/core.c +++ b/drivers/slimbus/core.c @@ -162,9 +162,8 @@ static int slim_add_device(struct slim_controller *ctrl, sbdev->ctrl = ctrl; INIT_LIST_HEAD(&sbdev->stream_list); spin_lock_init(&sbdev->stream_list_lock); - - if (node) - sbdev->dev.of_node = of_node_get(node); + sbdev->dev.of_node = of_node_get(node); + sbdev->dev.fwnode = of_fwnode_handle(node); dev_set_name(&sbdev->dev, "%x:%x:%x:%x", sbdev->e_addr.manf_id, @@ -283,6 +282,7 @@ EXPORT_SYMBOL_GPL(slim_register_controller); /* slim_remove_device: Remove the effect of slim_add_device() */ static void slim_remove_device(struct slim_device *sbdev) { + of_node_put(sbdev->dev.of_node); device_unregister(&sbdev->dev); } diff --git a/drivers/slimbus/qcom-ngd-ctrl.c b/drivers/slimbus/qcom-ngd-ctrl.c index fc2575fef51b..743ee7b4e63f 100644 --- a/drivers/slimbus/qcom-ngd-ctrl.c +++ b/drivers/slimbus/qcom-ngd-ctrl.c @@ -1361,12 +1361,10 @@ static int of_qcom_slim_ngd_register(struct device *parent, ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME; ngd->pdev->dev.of_node = node; ctrl->ngd = ngd; - platform_set_drvdata(ngd->pdev, ctrl); platform_device_add(ngd->pdev); ngd->base = ctrl->base + ngd->id * data->offset + (ngd->id - 1) * data->size; - ctrl->ngd = ngd; return 0; } @@ -1376,12 +1374,13 @@ static int of_qcom_slim_ngd_register(struct device *parent, static int qcom_slim_ngd_probe(struct platform_device *pdev) { - struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; + struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent); int ret; ctrl->ctrl.dev = dev; + platform_set_drvdata(pdev, ctrl); pm_runtime_use_autosuspend(dev); pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND); pm_runtime_set_suspended(dev); diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c index 23d90cb12ba9..226d343f0a6a 100644 --- a/drivers/soc/xilinx/zynqmp_pm_domains.c +++ b/drivers/soc/xilinx/zynqmp_pm_domains.c @@ -23,8 +23,6 @@ /* Flag stating if PM nodes mapped to the PM domain has been requested */ #define ZYNQMP_PM_DOMAIN_REQUESTED BIT(0) -static const struct zynqmp_eemi_ops *eemi_ops; - static int min_capability; /** @@ -76,11 +74,8 @@ static int zynqmp_gpd_power_on(struct generic_pm_domain *domain) int ret; struct zynqmp_pm_domain *pd; - if (!eemi_ops->set_requirement) - return -ENXIO; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); - ret = eemi_ops->set_requirement(pd->node_id, + ret = zynqmp_pm_set_requirement(pd->node_id, ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, ZYNQMP_PM_REQUEST_ACK_BLOCKING); @@ -111,9 +106,6 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) u32 capabilities = min_capability; bool may_wakeup; - if (!eemi_ops->set_requirement) - return -ENXIO; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If domain is already released there is nothing to be done */ @@ -134,7 +126,7 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) } } - ret = eemi_ops->set_requirement(pd->node_id, capabilities, 0, + ret = zynqmp_pm_set_requirement(pd->node_id, capabilities, 0, ZYNQMP_PM_REQUEST_ACK_NO); /** * If powering down of any node inside this domain fails, @@ -163,16 +155,13 @@ static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, int ret; struct zynqmp_pm_domain *pd; - if (!eemi_ops->request_node) - return -ENXIO; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If this is not the first device to attach there is nothing to do */ if (domain->device_count) return 0; - ret = eemi_ops->request_node(pd->node_id, 0, 0, + ret = zynqmp_pm_request_node(pd->node_id, 0, 0, ZYNQMP_PM_REQUEST_ACK_BLOCKING); /* If requesting a node fails print and return the error */ if (ret) { @@ -199,16 +188,13 @@ static void zynqmp_gpd_detach_dev(struct generic_pm_domain *domain, int ret; struct zynqmp_pm_domain *pd; - if (!eemi_ops->release_node) - return; - pd = container_of(domain, struct zynqmp_pm_domain, gpd); /* If this is not the last device to detach there is nothing to do */ if (domain->device_count) return; - ret = eemi_ops->release_node(pd->node_id); + ret = zynqmp_pm_release_node(pd->node_id); /* If releasing a node fails print the error and return */ if (ret) { pr_err("%s() %s release failed for node %d: %d\n", @@ -266,10 +252,6 @@ static int zynqmp_gpd_probe(struct platform_device *pdev) struct zynqmp_pm_domain *pd; struct device *dev = &pdev->dev; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - pd = devm_kcalloc(dev, ZYNQMP_NUM_DOMAINS, sizeof(*pd), GFP_KERNEL); if (!pd) return -ENOMEM; diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c index 09227895d216..31ff49fcd078 100644 --- a/drivers/soc/xilinx/zynqmp_power.c +++ b/drivers/soc/xilinx/zynqmp_power.c @@ -30,7 +30,6 @@ struct zynqmp_pm_work_struct { static struct zynqmp_pm_work_struct *zynqmp_pm_init_suspend_work; static struct mbox_chan *rx_chan; -static const struct zynqmp_eemi_ops *eemi_ops; enum pm_suspend_mode { PM_SUSPEND_MODE_FIRST = 0, @@ -155,9 +154,6 @@ static ssize_t suspend_mode_store(struct device *dev, { int md, ret = -EINVAL; - if (!eemi_ops->set_suspend_mode) - return ret; - for (md = PM_SUSPEND_MODE_FIRST; md < ARRAY_SIZE(suspend_modes); md++) if (suspend_modes[md] && sysfs_streq(suspend_modes[md], buf)) { @@ -166,7 +162,7 @@ static ssize_t suspend_mode_store(struct device *dev, } if (!ret && md != suspend_mode) { - ret = eemi_ops->set_suspend_mode(md); + ret = zynqmp_pm_set_suspend_mode(md); if (likely(!ret)) suspend_mode = md; } @@ -182,15 +178,8 @@ static int zynqmp_pm_probe(struct platform_device *pdev) u32 pm_api_version; struct mbox_client *client; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - - if (!eemi_ops->get_api_version || !eemi_ops->init_finalize) - return -ENXIO; - - eemi_ops->init_finalize(); - eemi_ops->get_api_version(&pm_api_version); + zynqmp_pm_init_finalize(); + zynqmp_pm_get_api_version(&pm_api_version); /* Check PM API version number */ if (pm_api_version < ZYNQMP_PM_VERSION) diff --git a/drivers/soundwire/Makefile b/drivers/soundwire/Makefile index e2cdff990e9f..b5871612613b 100644 --- a/drivers/soundwire/Makefile +++ b/drivers/soundwire/Makefile @@ -4,7 +4,8 @@ # #Bus Objs -soundwire-bus-objs := bus_type.o bus.o slave.o mipi_disco.o stream.o +soundwire-bus-objs := bus_type.o bus.o master.o slave.o mipi_disco.o stream.o \ + sysfs_slave.o sysfs_slave_dpn.o obj-$(CONFIG_SOUNDWIRE) += soundwire-bus.o ifdef CONFIG_DEBUG_FS @@ -16,12 +17,9 @@ soundwire-cadence-objs := cadence_master.o obj-$(CONFIG_SOUNDWIRE_CADENCE) += soundwire-cadence.o #Intel driver -soundwire-intel-objs := intel.o +soundwire-intel-objs := intel.o intel_init.o obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel.o -soundwire-intel-init-objs := intel_init.o -obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel-init.o - #Qualcomm driver soundwire-qcom-objs := qcom.o obj-$(CONFIG_SOUNDWIRE_QCOM) += soundwire-qcom.o diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c index 488c3c9e4947..24ba77226376 100644 --- a/drivers/soundwire/bus.c +++ b/drivers/soundwire/bus.c @@ -8,24 +8,54 @@ #include <linux/soundwire/sdw_registers.h> #include <linux/soundwire/sdw.h> #include "bus.h" +#include "sysfs_local.h" + +static DEFINE_IDA(sdw_ida); + +static int sdw_get_id(struct sdw_bus *bus) +{ + int rc = ida_alloc(&sdw_ida, GFP_KERNEL); + + if (rc < 0) + return rc; + + bus->id = rc; + return 0; +} /** - * sdw_add_bus_master() - add a bus Master instance + * sdw_bus_master_add() - add a bus Master instance * @bus: bus instance + * @parent: parent device + * @fwnode: firmware node handle * * Initializes the bus instance, read properties and create child * devices. */ -int sdw_add_bus_master(struct sdw_bus *bus) +int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode) { struct sdw_master_prop *prop = NULL; int ret; - if (!bus->dev) { - pr_err("SoundWire bus has no device\n"); + if (!parent) { + pr_err("SoundWire parent device is not set\n"); return -ENODEV; } + ret = sdw_get_id(bus); + if (ret) { + dev_err(parent, "Failed to get bus id\n"); + return ret; + } + + ret = sdw_master_device_add(bus, parent, fwnode); + if (ret) { + dev_err(parent, "Failed to add master device at link %d\n", + bus->link_id); + return ret; + } + if (!bus->ops) { dev_err(bus->dev, "SoundWire Bus ops are not set\n"); return -EINVAL; @@ -107,7 +137,7 @@ int sdw_add_bus_master(struct sdw_bus *bus) return 0; } -EXPORT_SYMBOL(sdw_add_bus_master); +EXPORT_SYMBOL(sdw_bus_master_add); static int sdw_delete_slave(struct device *dev, void *data) { @@ -131,18 +161,20 @@ static int sdw_delete_slave(struct device *dev, void *data) } /** - * sdw_delete_bus_master() - delete the bus master instance + * sdw_bus_master_delete() - delete the bus master instance * @bus: bus to be deleted * * Remove the instance, delete the child devices. */ -void sdw_delete_bus_master(struct sdw_bus *bus) +void sdw_bus_master_delete(struct sdw_bus *bus) { device_for_each_child(bus->dev, NULL, sdw_delete_slave); + sdw_master_device_del(bus); sdw_bus_debugfs_exit(bus); + ida_free(&sdw_ida, bus->id); } -EXPORT_SYMBOL(sdw_delete_bus_master); +EXPORT_SYMBOL(sdw_bus_master_delete); /* * SDW IO Calls @@ -284,9 +316,10 @@ int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave, msg->flags = flags; msg->buf = buf; - if (addr < SDW_REG_NO_PAGE) { /* no paging area */ + if (addr < SDW_REG_NO_PAGE) /* no paging area */ return 0; - } else if (addr >= SDW_REG_MAX) { /* illegal addr */ + + if (addr >= SDW_REG_MAX) { /* illegal addr */ pr_err("SDW: Invalid address %x passed\n", addr); return -EINVAL; } @@ -306,7 +339,9 @@ int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave, if (!slave) { pr_err("SDW: No slave for paging addr\n"); return -EINVAL; - } else if (!slave->prop.paging_support) { + } + + if (!slave->prop.paging_support) { dev_err(&slave->dev, "address %x needs paging but no support\n", addr); return -EINVAL; @@ -375,8 +410,8 @@ sdw_bread_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr) ret = sdw_transfer(bus, &msg); if (ret < 0) return ret; - else - return buf; + + return buf; } static int @@ -471,8 +506,8 @@ int sdw_read(struct sdw_slave *slave, u32 addr) ret = sdw_nread(slave, addr, 1, &buf); if (ret < 0) return ret; - else - return buf; + + return buf; } EXPORT_SYMBOL(sdw_read); @@ -563,9 +598,9 @@ static int sdw_assign_device_num(struct sdw_slave *slave) } if (!new_device) - dev_info(slave->bus->dev, - "Slave already registered, reusing dev_num:%d\n", - slave->dev_num); + dev_dbg(slave->bus->dev, + "Slave already registered, reusing dev_num:%d\n", + slave->dev_num); /* Clear the slave->dev_num to transfer message on device 0 */ dev_num = slave->dev_num; diff --git a/drivers/soundwire/bus.h b/drivers/soundwire/bus.h index 204204a26db8..82484f741168 100644 --- a/drivers/soundwire/bus.h +++ b/drivers/soundwire/bus.h @@ -19,6 +19,9 @@ static inline int sdw_acpi_find_slaves(struct sdw_bus *bus) int sdw_of_find_slaves(struct sdw_bus *bus); void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id); +int sdw_master_device_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode); +int sdw_master_device_del(struct sdw_bus *bus); #ifdef CONFIG_DEBUG_FS void sdw_bus_debugfs_init(struct sdw_bus *bus); @@ -172,5 +175,6 @@ sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) #define SDW_UNATTACH_REQUEST_MASTER_RESET BIT(0) void sdw_clear_slave_status(struct sdw_bus *bus, u32 request); +int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size); #endif /* __SDW_BUS_H */ diff --git a/drivers/soundwire/bus_type.c b/drivers/soundwire/bus_type.c index 17f096dd6806..de9a671802b8 100644 --- a/drivers/soundwire/bus_type.c +++ b/drivers/soundwire/bus_type.c @@ -7,6 +7,7 @@ #include <linux/soundwire/sdw.h> #include <linux/soundwire/sdw_type.h> #include "bus.h" +#include "sysfs_local.h" /** * sdw_get_device_id - find the matching SoundWire device id @@ -33,10 +34,17 @@ sdw_get_device_id(struct sdw_slave *slave, struct sdw_driver *drv) static int sdw_bus_match(struct device *dev, struct device_driver *ddrv) { - struct sdw_slave *slave = dev_to_sdw_dev(dev); - struct sdw_driver *drv = drv_to_sdw_driver(ddrv); + struct sdw_slave *slave; + struct sdw_driver *drv; + int ret = 0; + + if (is_sdw_slave(dev)) { + slave = dev_to_sdw_dev(dev); + drv = drv_to_sdw_driver(ddrv); - return !!sdw_get_device_id(slave, drv); + ret = !!sdw_get_device_id(slave, drv); + } + return ret; } int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size) @@ -47,7 +55,7 @@ int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size) slave->id.mfg_id, slave->id.part_id); } -static int sdw_uevent(struct device *dev, struct kobj_uevent_env *env) +int sdw_slave_uevent(struct device *dev, struct kobj_uevent_env *env) { struct sdw_slave *slave = dev_to_sdw_dev(dev); char modalias[32]; @@ -63,7 +71,6 @@ static int sdw_uevent(struct device *dev, struct kobj_uevent_env *env) struct bus_type sdw_bus_type = { .name = "soundwire", .match = sdw_bus_match, - .uevent = sdw_uevent, }; EXPORT_SYMBOL_GPL(sdw_bus_type); @@ -98,6 +105,11 @@ static int sdw_drv_probe(struct device *dev) if (slave->ops && slave->ops->read_prop) slave->ops->read_prop(slave); + /* init the sysfs as we have properties now */ + ret = sdw_slave_sysfs_init(slave); + if (ret < 0) + dev_warn(dev, "Slave sysfs init failed:%d\n", ret); + /* * Check for valid clk_stop_timeout, use DisCo worst case value of * 300ms diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c index ecd357d1c63d..9ea87538b9ef 100644 --- a/drivers/soundwire/cadence_master.c +++ b/drivers/soundwire/cadence_master.c @@ -407,7 +407,9 @@ cdns_fill_msg_resp(struct sdw_cdns *cdns, if (nack) { dev_err_ratelimited(cdns->dev, "Msg NACKed for Slave %d\n", msg->dev_num); return SDW_CMD_FAIL; - } else if (no_ack) { + } + + if (no_ack) { dev_dbg_ratelimited(cdns->dev, "Msg ignored for Slave %d\n", msg->dev_num); return SDW_CMD_IGNORED; } @@ -520,7 +522,9 @@ cdns_program_scp_addr(struct sdw_cdns *cdns, struct sdw_msg *msg) dev_err_ratelimited(cdns->dev, "SCP_addrpage NACKed for Slave %d\n", msg->dev_num); return SDW_CMD_FAIL; - } else if (no_ack) { + } + + if (no_ack) { dev_dbg_ratelimited(cdns->dev, "SCP_addrpage ignored for Slave %d\n", msg->dev_num); return SDW_CMD_IGNORED; diff --git a/drivers/soundwire/debugfs.c b/drivers/soundwire/debugfs.c index fb1140e82b86..b6cad0d59b7b 100644 --- a/drivers/soundwire/debugfs.c +++ b/drivers/soundwire/debugfs.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only // Copyright(c) 2017-2019 Intel Corporation. #include <linux/device.h> diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index ed8d576bf5dc..4cfdd074e310 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -1099,7 +1099,6 @@ static int intel_probe(struct platform_device *pdev) sdw->cdns.registers = sdw->link_res->registers; sdw->cdns.instance = sdw->instance; sdw->cdns.msg_count = 0; - sdw->cdns.bus.dev = &pdev->dev; sdw->cdns.bus.link_id = pdev->id; sdw_cdns_probe(&sdw->cdns); @@ -1110,9 +1109,9 @@ static int intel_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sdw); - ret = sdw_add_bus_master(&sdw->cdns.bus); + ret = sdw_bus_master_add(&sdw->cdns.bus, &pdev->dev, pdev->dev.fwnode); if (ret) { - dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret); + dev_err(&pdev->dev, "sdw_bus_master_add fail: %d\n", ret); return ret; } @@ -1173,7 +1172,7 @@ err_interrupt: sdw_cdns_enable_interrupt(&sdw->cdns, false); free_irq(sdw->link_res->irq, sdw); err_init: - sdw_delete_bus_master(&sdw->cdns.bus); + sdw_bus_master_delete(&sdw->cdns.bus); return ret; } @@ -1189,7 +1188,7 @@ static int intel_remove(struct platform_device *pdev) free_irq(sdw->link_res->irq, sdw); snd_soc_unregister_component(sdw->cdns.dev); } - sdw_delete_bus_master(&sdw->cdns.bus); + sdw_bus_master_delete(&sdw->cdns.bus); return 0; } diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c index 4b769409f6f8..d5d42795a48f 100644 --- a/drivers/soundwire/intel_init.c +++ b/drivers/soundwire/intel_init.c @@ -86,7 +86,9 @@ static struct sdw_intel_ctx dev_err(&adev->dev, "Link count %d exceeds max %d\n", count, SDW_MAX_LINKS); return NULL; - } else if (!count) { + } + + if (!count) { dev_warn(&adev->dev, "No SoundWire links detected\n"); return NULL; } diff --git a/drivers/soundwire/master.c b/drivers/soundwire/master.c new file mode 100644 index 000000000000..5f0b2189defe --- /dev/null +++ b/drivers/soundwire/master.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2019-2020 Intel Corporation. + +#include <linux/device.h> +#include <linux/acpi.h> +#include <linux/pm_runtime.h> +#include <linux/soundwire/sdw.h> +#include <linux/soundwire/sdw_type.h> +#include "bus.h" + +/* + * The sysfs for properties reflects the MIPI description as given + * in the MIPI DisCo spec + * + * Base file is: + * sdw-master-N + * |---- revision + * |---- clk_stop_modes + * |---- max_clk_freq + * |---- clk_freq + * |---- clk_gears + * |---- default_row + * |---- default_col + * |---- dynamic_shape + * |---- err_threshold + */ + +#define sdw_master_attr(field, format_string) \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); \ + return sprintf(buf, format_string, md->bus->prop.field); \ +} \ +static DEVICE_ATTR_RO(field) + +sdw_master_attr(revision, "0x%x\n"); +sdw_master_attr(clk_stop_modes, "0x%x\n"); +sdw_master_attr(max_clk_freq, "%d\n"); +sdw_master_attr(default_row, "%d\n"); +sdw_master_attr(default_col, "%d\n"); +sdw_master_attr(default_frame_rate, "%d\n"); +sdw_master_attr(dynamic_frame, "%d\n"); +sdw_master_attr(err_threshold, "%d\n"); + +static ssize_t clock_frequencies_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); + ssize_t size = 0; + int i; + + for (i = 0; i < md->bus->prop.num_clk_freq; i++) + size += sprintf(buf + size, "%8d ", + md->bus->prop.clk_freq[i]); + size += sprintf(buf + size, "\n"); + + return size; +} +static DEVICE_ATTR_RO(clock_frequencies); + +static ssize_t clock_gears_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); + ssize_t size = 0; + int i; + + for (i = 0; i < md->bus->prop.num_clk_gears; i++) + size += sprintf(buf + size, "%8d ", + md->bus->prop.clk_gears[i]); + size += sprintf(buf + size, "\n"); + + return size; +} +static DEVICE_ATTR_RO(clock_gears); + +static struct attribute *master_node_attrs[] = { + &dev_attr_revision.attr, + &dev_attr_clk_stop_modes.attr, + &dev_attr_max_clk_freq.attr, + &dev_attr_default_row.attr, + &dev_attr_default_col.attr, + &dev_attr_default_frame_rate.attr, + &dev_attr_dynamic_frame.attr, + &dev_attr_err_threshold.attr, + &dev_attr_clock_frequencies.attr, + &dev_attr_clock_gears.attr, + NULL, +}; +ATTRIBUTE_GROUPS(master_node); + +static void sdw_master_device_release(struct device *dev) +{ + struct sdw_master_device *md = dev_to_sdw_master_device(dev); + + kfree(md); +} + +static const struct dev_pm_ops master_dev_pm = { + SET_RUNTIME_PM_OPS(pm_generic_runtime_suspend, + pm_generic_runtime_resume, NULL) +}; + +struct device_type sdw_master_type = { + .name = "soundwire_master", + .release = sdw_master_device_release, + .pm = &master_dev_pm, +}; + +/** + * sdw_master_device_add() - create a Linux Master Device representation. + * @bus: SDW bus instance + * @parent: parent device + * @fwnode: firmware node handle + */ +int sdw_master_device_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode) +{ + struct sdw_master_device *md; + int ret; + + if (!parent) + return -EINVAL; + + md = kzalloc(sizeof(*md), GFP_KERNEL); + if (!md) + return -ENOMEM; + + md->dev.bus = &sdw_bus_type; + md->dev.type = &sdw_master_type; + md->dev.parent = parent; + md->dev.groups = master_node_groups; + md->dev.of_node = parent->of_node; + md->dev.fwnode = fwnode; + md->dev.dma_mask = parent->dma_mask; + + dev_set_name(&md->dev, "sdw-master-%d", bus->id); + + ret = device_register(&md->dev); + if (ret) { + dev_err(parent, "Failed to add master: ret %d\n", ret); + /* + * On err, don't free but drop ref as this will be freed + * when release method is invoked. + */ + put_device(&md->dev); + goto device_register_err; + } + + /* add shortcuts to improve code readability/compactness */ + md->bus = bus; + bus->dev = &md->dev; + bus->md = md; + +device_register_err: + return ret; +} + +/** + * sdw_master_device_del() - delete a Linux Master Device representation. + * @bus: bus handle + * + * This function is the dual of sdw_master_device_add() + */ +int sdw_master_device_del(struct sdw_bus *bus) +{ + device_unregister(bus->dev); + + return 0; +} diff --git a/drivers/soundwire/mipi_disco.c b/drivers/soundwire/mipi_disco.c index 844e6b22974f..4ae62b452b8c 100644 --- a/drivers/soundwire/mipi_disco.c +++ b/drivers/soundwire/mipi_disco.c @@ -231,16 +231,17 @@ static int sdw_slave_read_dpn(struct sdw_slave *slave, nval = fwnode_property_count_u32(node, "mipi-sdw-channel-number-list"); if (nval > 0) { - dpn[i].num_ch = nval; - dpn[i].ch = devm_kcalloc(&slave->dev, dpn[i].num_ch, - sizeof(*dpn[i].ch), + dpn[i].num_channels = nval; + dpn[i].channels = devm_kcalloc(&slave->dev, + dpn[i].num_channels, + sizeof(*dpn[i].channels), GFP_KERNEL); - if (!dpn[i].ch) + if (!dpn[i].channels) return -ENOMEM; fwnode_property_read_u32_array(node, "mipi-sdw-channel-number-list", - dpn[i].ch, dpn[i].num_ch); + dpn[i].channels, dpn[i].num_channels); } nval = fwnode_property_count_u32(node, "mipi-sdw-channel-combination-list"); diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index d6c9ad231873..a1c2a44a3b4d 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -765,12 +765,16 @@ static int qcom_swrm_probe(struct platform_device *pdev) } ctrl->irq = of_irq_get(dev->of_node, 0); - if (ctrl->irq < 0) - return ctrl->irq; + if (ctrl->irq < 0) { + ret = ctrl->irq; + goto err_init; + } ctrl->hclk = devm_clk_get(dev, "iface"); - if (IS_ERR(ctrl->hclk)) - return PTR_ERR(ctrl->hclk); + if (IS_ERR(ctrl->hclk)) { + ret = PTR_ERR(ctrl->hclk); + goto err_init; + } clk_prepare_enable(ctrl->hclk); @@ -780,14 +784,13 @@ static int qcom_swrm_probe(struct platform_device *pdev) mutex_init(&ctrl->port_lock); INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq); - ctrl->bus.dev = dev; ctrl->bus.ops = &qcom_swrm_ops; ctrl->bus.port_ops = &qcom_swrm_port_ops; ctrl->bus.compute_params = &qcom_swrm_compute_params; ret = qcom_swrm_get_port_config(ctrl); if (ret) - return ret; + goto err_clk; params = &ctrl->bus.params; params->max_dr_freq = DEFAULT_CLK_FREQ; @@ -810,32 +813,37 @@ static int qcom_swrm_probe(struct platform_device *pdev) ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, qcom_swrm_irq_handler, - IRQF_TRIGGER_RISING, + IRQF_TRIGGER_RISING | + IRQF_ONESHOT, "soundwire", ctrl); if (ret) { dev_err(dev, "Failed to request soundwire irq\n"); - goto err; + goto err_clk; } - ret = sdw_add_bus_master(&ctrl->bus); + ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); if (ret) { dev_err(dev, "Failed to register Soundwire controller (%d)\n", ret); - goto err; + goto err_clk; } qcom_swrm_init(ctrl); ret = qcom_swrm_register_dais(ctrl); if (ret) - goto err; + goto err_master_add; dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, ctrl->version & 0xffff); return 0; -err: + +err_master_add: + sdw_bus_master_delete(&ctrl->bus); +err_clk: clk_disable_unprepare(ctrl->hclk); +err_init: return ret; } @@ -843,7 +851,7 @@ static int qcom_swrm_remove(struct platform_device *pdev) { struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); - sdw_delete_bus_master(&ctrl->bus); + sdw_bus_master_delete(&ctrl->bus); clk_disable_unprepare(ctrl->hclk); return 0; diff --git a/drivers/soundwire/slave.c b/drivers/soundwire/slave.c index aace57fae7f8..0839445ee07b 100644 --- a/drivers/soundwire/slave.c +++ b/drivers/soundwire/slave.c @@ -14,6 +14,12 @@ static void sdw_slave_release(struct device *dev) kfree(slave); } +struct device_type sdw_slave_type = { + .name = "sdw_slave", + .release = sdw_slave_release, + .uevent = sdw_slave_uevent, +}; + static int sdw_slave_add(struct sdw_bus *bus, struct sdw_slave_id *id, struct fwnode_handle *fwnode) { @@ -41,9 +47,9 @@ static int sdw_slave_add(struct sdw_bus *bus, id->class_id, id->unique_id); } - slave->dev.release = sdw_slave_release; slave->dev.bus = &sdw_bus_type; slave->dev.of_node = of_node_get(to_of_node(fwnode)); + slave->dev.type = &sdw_slave_type; slave->bus = bus; slave->status = SDW_SLAVE_UNATTACHED; init_completion(&slave->enumeration_complete); @@ -68,6 +74,8 @@ static int sdw_slave_add(struct sdw_bus *bus, list_del(&slave->node); mutex_unlock(&bus->bus_lock); put_device(&slave->dev); + + return ret; } sdw_slave_debugfs_init(slave); diff --git a/drivers/soundwire/sysfs_local.h b/drivers/soundwire/sysfs_local.h new file mode 100644 index 000000000000..ff60adee3c41 --- /dev/null +++ b/drivers/soundwire/sysfs_local.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright(c) 2015-2020 Intel Corporation. */ + +#ifndef __SDW_SYSFS_LOCAL_H +#define __SDW_SYSFS_LOCAL_H + +/* + * SDW sysfs APIs - + */ + +int sdw_slave_sysfs_init(struct sdw_slave *slave); +int sdw_slave_sysfs_dpn_init(struct sdw_slave *slave); + +#endif /* __SDW_SYSFS_LOCAL_H */ diff --git a/drivers/soundwire/sysfs_slave.c b/drivers/soundwire/sysfs_slave.c new file mode 100644 index 000000000000..f510071b0add --- /dev/null +++ b/drivers/soundwire/sysfs_slave.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2015-2020 Intel Corporation. + +#include <linux/device.h> +#include <linux/mod_devicetable.h> +#include <linux/slab.h> +#include <linux/sysfs.h> +#include <linux/soundwire/sdw.h> +#include <linux/soundwire/sdw_type.h> +#include "bus.h" +#include "sysfs_local.h" + +/* + * Slave sysfs + */ + +/* + * The sysfs for Slave reflects the MIPI description as given + * in the MIPI DisCo spec + * + * Base file is device + * |---- modalias + * |---- dev-properties + * |---- mipi_revision + * |---- wake_capable + * |---- test_mode_capable + * |---- clk_stop_mode1 + * |---- simple_clk_stop_capable + * |---- clk_stop_timeout + * |---- ch_prep_timeout + * |---- reset_behave + * |---- high_PHY_capable + * |---- paging_support + * |---- bank_delay_support + * |---- p15_behave + * |---- master_count + * |---- source_ports + * |---- sink_ports + * |---- dp0 + * |---- max_word + * |---- min_word + * |---- words + * |---- BRA_flow_controlled + * |---- simple_ch_prep_sm + * |---- imp_def_interrupts + * |---- dpN_<sink/src> + * |---- max_word + * |---- min_word + * |---- words + * |---- type + * |---- max_grouping + * |---- simple_ch_prep_sm + * |---- ch_prep_timeout + * |---- imp_def_interrupts + * |---- min_ch + * |---- max_ch + * |---- channels + * |---- ch_combinations + * |---- max_async_buffer + * |---- block_pack_mode + * |---- port_encoding + * + */ + +#define sdw_slave_attr(field, format_string) \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + return sprintf(buf, format_string, slave->prop.field); \ +} \ +static DEVICE_ATTR_RO(field) + +sdw_slave_attr(mipi_revision, "0x%x\n"); +sdw_slave_attr(wake_capable, "%d\n"); +sdw_slave_attr(test_mode_capable, "%d\n"); +sdw_slave_attr(clk_stop_mode1, "%d\n"); +sdw_slave_attr(simple_clk_stop_capable, "%d\n"); +sdw_slave_attr(clk_stop_timeout, "%d\n"); +sdw_slave_attr(ch_prep_timeout, "%d\n"); +sdw_slave_attr(reset_behave, "%d\n"); +sdw_slave_attr(high_PHY_capable, "%d\n"); +sdw_slave_attr(paging_support, "%d\n"); +sdw_slave_attr(bank_delay_support, "%d\n"); +sdw_slave_attr(p15_behave, "%d\n"); +sdw_slave_attr(master_count, "%d\n"); +sdw_slave_attr(source_ports, "0x%x\n"); +sdw_slave_attr(sink_ports, "0x%x\n"); + +static ssize_t modalias_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + + return sdw_slave_modalias(slave, buf, 256); +} +static DEVICE_ATTR_RO(modalias); + +static struct attribute *slave_attrs[] = { + &dev_attr_modalias.attr, + NULL, +}; +ATTRIBUTE_GROUPS(slave); + +static struct attribute *slave_dev_attrs[] = { + &dev_attr_mipi_revision.attr, + &dev_attr_wake_capable.attr, + &dev_attr_test_mode_capable.attr, + &dev_attr_clk_stop_mode1.attr, + &dev_attr_simple_clk_stop_capable.attr, + &dev_attr_clk_stop_timeout.attr, + &dev_attr_ch_prep_timeout.attr, + &dev_attr_reset_behave.attr, + &dev_attr_high_PHY_capable.attr, + &dev_attr_paging_support.attr, + &dev_attr_bank_delay_support.attr, + &dev_attr_p15_behave.attr, + &dev_attr_master_count.attr, + &dev_attr_source_ports.attr, + &dev_attr_sink_ports.attr, + NULL, +}; + +/* + * we don't use ATTRIBUTES_GROUP here since we want to add a subdirectory + * for device-level properties + */ +static struct attribute_group sdw_slave_dev_attr_group = { + .attrs = slave_dev_attrs, + .name = "dev-properties", +}; + +/* + * DP0 sysfs + */ + +#define sdw_dp0_attr(field, format_string) \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + return sprintf(buf, format_string, slave->prop.dp0_prop->field);\ +} \ +static DEVICE_ATTR_RO(field) + +sdw_dp0_attr(max_word, "%d\n"); +sdw_dp0_attr(min_word, "%d\n"); +sdw_dp0_attr(BRA_flow_controlled, "%d\n"); +sdw_dp0_attr(simple_ch_prep_sm, "%d\n"); +sdw_dp0_attr(imp_def_interrupts, "0x%x\n"); + +static ssize_t words_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sdw_slave *slave = dev_to_sdw_dev(dev); + ssize_t size = 0; + int i; + + for (i = 0; i < slave->prop.dp0_prop->num_words; i++) + size += sprintf(buf + size, "%d ", + slave->prop.dp0_prop->words[i]); + size += sprintf(buf + size, "\n"); + + return size; +} +static DEVICE_ATTR_RO(words); + +static struct attribute *dp0_attrs[] = { + &dev_attr_max_word.attr, + &dev_attr_min_word.attr, + &dev_attr_words.attr, + &dev_attr_BRA_flow_controlled.attr, + &dev_attr_simple_ch_prep_sm.attr, + &dev_attr_imp_def_interrupts.attr, + NULL, +}; + +/* + * we don't use ATTRIBUTES_GROUP here since we want to add a subdirectory + * for dp0-level properties + */ +static const struct attribute_group dp0_group = { + .attrs = dp0_attrs, + .name = "dp0", +}; + +int sdw_slave_sysfs_init(struct sdw_slave *slave) +{ + int ret; + + ret = devm_device_add_groups(&slave->dev, slave_groups); + if (ret < 0) + return ret; + + ret = devm_device_add_group(&slave->dev, &sdw_slave_dev_attr_group); + if (ret < 0) + return ret; + + if (slave->prop.dp0_prop) { + ret = devm_device_add_group(&slave->dev, &dp0_group); + if (ret < 0) + return ret; + } + + if (slave->prop.source_ports || slave->prop.sink_ports) { + ret = sdw_slave_sysfs_dpn_init(slave); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/drivers/soundwire/sysfs_slave_dpn.c b/drivers/soundwire/sysfs_slave_dpn.c new file mode 100644 index 000000000000..05a721ea9830 --- /dev/null +++ b/drivers/soundwire/sysfs_slave_dpn.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2015-2020 Intel Corporation. + +#include <linux/device.h> +#include <linux/mod_devicetable.h> +#include <linux/slab.h> +#include <linux/sysfs.h> +#include <linux/soundwire/sdw.h> +#include <linux/soundwire/sdw_type.h> +#include "bus.h" +#include "sysfs_local.h" + +struct dpn_attribute { + struct device_attribute dev_attr; + int N; + int dir; + const char *format_string; +}; + +/* + * Since we can't use ARRAY_SIZE, hard-code number of dpN attributes. + * This needs to be updated when adding new attributes - an error will be + * flagged on a mismatch. + */ +#define SDW_DPN_ATTRIBUTES 15 + +#define sdw_dpn_attribute_alloc(field) \ +static int field##_attribute_alloc(struct device *dev, \ + struct attribute **res, \ + int N, int dir, \ + const char *format_string) \ +{ \ + struct dpn_attribute *dpn_attr; \ + \ + dpn_attr = devm_kzalloc(dev, sizeof(*dpn_attr), GFP_KERNEL); \ + if (!dpn_attr) \ + return -ENOMEM; \ + dpn_attr->N = N; \ + dpn_attr->dir = dir; \ + dpn_attr->format_string = format_string; \ + dpn_attr->dev_attr.attr.name = __stringify(field); \ + dpn_attr->dev_attr.attr.mode = 0444; \ + dpn_attr->dev_attr.show = field##_show; \ + \ + *res = &dpn_attr->dev_attr.attr; \ + \ + return 0; \ +} + +#define sdw_dpn_attr(field) \ + \ +static ssize_t field##_dpn_show(struct sdw_slave *slave, \ + int N, \ + int dir, \ + const char *format_string, \ + char *buf) \ +{ \ + struct sdw_dpn_prop *dpn; \ + unsigned long mask; \ + int bit; \ + int i; \ + \ + if (dir) { \ + dpn = slave->prop.src_dpn_prop; \ + mask = slave->prop.source_ports; \ + } else { \ + dpn = slave->prop.sink_dpn_prop; \ + mask = slave->prop.sink_ports; \ + } \ + \ + i = 0; \ + for_each_set_bit(bit, &mask, 32) { \ + if (bit == N) { \ + return sprintf(buf, format_string, \ + dpn[i].field); \ + } \ + i++; \ + } \ + return -EINVAL; \ +} \ + \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + struct dpn_attribute *dpn_attr = \ + container_of(attr, struct dpn_attribute, dev_attr); \ + \ + return field##_dpn_show(slave, \ + dpn_attr->N, dpn_attr->dir, \ + dpn_attr->format_string, \ + buf); \ +} \ +sdw_dpn_attribute_alloc(field) + +sdw_dpn_attr(imp_def_interrupts); +sdw_dpn_attr(max_word); +sdw_dpn_attr(min_word); +sdw_dpn_attr(type); +sdw_dpn_attr(max_grouping); +sdw_dpn_attr(simple_ch_prep_sm); +sdw_dpn_attr(ch_prep_timeout); +sdw_dpn_attr(max_ch); +sdw_dpn_attr(min_ch); +sdw_dpn_attr(max_async_buffer); +sdw_dpn_attr(block_pack_mode); +sdw_dpn_attr(port_encoding); + +#define sdw_dpn_array_attr(field) \ + \ +static ssize_t field##_dpn_show(struct sdw_slave *slave, \ + int N, \ + int dir, \ + const char *format_string, \ + char *buf) \ +{ \ + struct sdw_dpn_prop *dpn; \ + unsigned long mask; \ + ssize_t size = 0; \ + int bit; \ + int i; \ + int j; \ + \ + if (dir) { \ + dpn = slave->prop.src_dpn_prop; \ + mask = slave->prop.source_ports; \ + } else { \ + dpn = slave->prop.sink_dpn_prop; \ + mask = slave->prop.sink_ports; \ + } \ + \ + i = 0; \ + for_each_set_bit(bit, &mask, 32) { \ + if (bit == N) { \ + for (j = 0; j < dpn[i].num_##field; j++) \ + size += sprintf(buf + size, \ + format_string, \ + dpn[i].field[j]); \ + size += sprintf(buf + size, "\n"); \ + return size; \ + } \ + i++; \ + } \ + return -EINVAL; \ +} \ +static ssize_t field##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct sdw_slave *slave = dev_to_sdw_dev(dev); \ + struct dpn_attribute *dpn_attr = \ + container_of(attr, struct dpn_attribute, dev_attr); \ + \ + return field##_dpn_show(slave, \ + dpn_attr->N, dpn_attr->dir, \ + dpn_attr->format_string, \ + buf); \ +} \ +sdw_dpn_attribute_alloc(field) + +sdw_dpn_array_attr(words); +sdw_dpn_array_attr(ch_combinations); +sdw_dpn_array_attr(channels); + +static int add_all_attributes(struct device *dev, int N, int dir) +{ + struct attribute **dpn_attrs; + struct attribute_group *dpn_group; + int i = 0; + int ret; + + /* allocate attributes, last one is NULL */ + dpn_attrs = devm_kcalloc(dev, SDW_DPN_ATTRIBUTES + 1, + sizeof(struct attribute *), + GFP_KERNEL); + if (!dpn_attrs) + return -ENOMEM; + + ret = max_word_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = min_word_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = words_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = type_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = max_grouping_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = simple_ch_prep_sm_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = ch_prep_timeout_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = imp_def_interrupts_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "0x%x\n"); + if (ret < 0) + return ret; + + ret = min_ch_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = max_ch_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = channels_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = ch_combinations_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = max_async_buffer_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = block_pack_mode_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + ret = port_encoding_attribute_alloc(dev, &dpn_attrs[i++], + N, dir, "%d\n"); + if (ret < 0) + return ret; + + /* paranoia check for editing mistakes */ + if (i != SDW_DPN_ATTRIBUTES) { + dev_err(dev, "mismatch in attributes, allocated %d got %d\n", + SDW_DPN_ATTRIBUTES, i); + return -EINVAL; + } + + dpn_group = devm_kzalloc(dev, sizeof(*dpn_group), GFP_KERNEL); + if (!dpn_group) + return -ENOMEM; + + dpn_group->attrs = dpn_attrs; + dpn_group->name = devm_kasprintf(dev, GFP_KERNEL, "dp%d_%s", + N, dir ? "src" : "sink"); + if (!dpn_group->name) + return -ENOMEM; + + ret = devm_device_add_group(dev, dpn_group); + if (ret < 0) + return ret; + + return 0; +} + +int sdw_slave_sysfs_dpn_init(struct sdw_slave *slave) +{ + unsigned long mask; + int ret; + int i; + + mask = slave->prop.source_ports; + for_each_set_bit(i, &mask, 32) { + ret = add_all_attributes(&slave->dev, i, 1); + if (ret < 0) + return ret; + } + + mask = slave->prop.sink_ports; + for_each_set_bit(i, &mask, 32) { + ret = add_all_attributes(&slave->dev, i, 0); + if (ret < 0) + return ret; + } + + return 0; +} diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 7412a3042a8d..811c97a7c858 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -135,7 +135,6 @@ #define SPI_AUTOSUSPEND_TIMEOUT 3000 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; -static const struct zynqmp_eemi_ops *eemi_ops; /** * struct zynqmp_qspi - Defines qspi driver instance @@ -1015,10 +1014,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) struct zynqmp_qspi *xqspi; struct device *dev = &pdev->dev; - eemi_ops = zynqmp_pm_get_eemi_ops(); - if (IS_ERR(eemi_ops)) - return PTR_ERR(eemi_ops); - master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); if (!master) return -ENOMEM; diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c index 6e725c6c6256..73efb80815db 100644 --- a/drivers/uio/uio.c +++ b/drivers/uio/uio.c @@ -398,7 +398,7 @@ static void uio_dev_del_attributes(struct uio_device *idev) static int uio_get_minor(struct uio_device *idev) { - int retval = -ENOMEM; + int retval; mutex_lock(&minor_lock); retval = idr_alloc(&uio_idr, idev, 0, UIO_MAX_DEVICES, GFP_KERNEL); diff --git a/drivers/uio/uio_dmem_genirq.c b/drivers/uio/uio_dmem_genirq.c index f6ab3f28c838..6e27fe4fcca3 100644 --- a/drivers/uio/uio_dmem_genirq.c +++ b/drivers/uio/uio_dmem_genirq.c @@ -44,7 +44,6 @@ static int uio_dmem_genirq_open(struct uio_info *info, struct inode *inode) { struct uio_dmem_genirq_platdata *priv = info->priv; struct uio_mem *uiomem; - int ret = 0; int dmem_region = priv->dmem_region_start; uiomem = &priv->uioinfo->mem[priv->dmem_region_start]; @@ -68,7 +67,7 @@ static int uio_dmem_genirq_open(struct uio_info *info, struct inode *inode) mutex_unlock(&priv->alloc_lock); /* Wait until the Runtime PM code has woken up the device */ pm_runtime_get_sync(&priv->pdev->dev); - return ret; + return 0; } static int uio_dmem_genirq_release(struct uio_info *info, struct inode *inode) diff --git a/drivers/uio/uio_hv_generic.c b/drivers/uio/uio_hv_generic.c index 3c5169eb23f5..4dae2320b103 100644 --- a/drivers/uio/uio_hv_generic.c +++ b/drivers/uio/uio_hv_generic.c @@ -361,6 +361,7 @@ hv_uio_remove(struct hv_device *dev) if (!pdata) return 0; + sysfs_remove_bin_file(&dev->channel->kobj, &ring_buffer_bin_attr); uio_unregister_device(&pdata->info); hv_uio_cleanup(dev, pdata); hv_set_drvdata(dev, NULL); diff --git a/drivers/visorbus/controlvmchannel.h b/drivers/visorbus/controlvmchannel.h index 8c57562a070a..c87213554427 100644 --- a/drivers/visorbus/controlvmchannel.h +++ b/drivers/visorbus/controlvmchannel.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2010 - 2015 UNISYS CORPORATION * All rights reserved. diff --git a/drivers/visorbus/vbuschannel.h b/drivers/visorbus/vbuschannel.h index b1dce26166bf..4aaf6564eb9f 100644 --- a/drivers/visorbus/vbuschannel.h +++ b/drivers/visorbus/vbuschannel.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2010 - 2015 UNISYS CORPORATION * All rights reserved. diff --git a/drivers/visorbus/visorbus_private.h b/drivers/visorbus/visorbus_private.h index 366380b7f8d9..6956de605827 100644 --- a/drivers/visorbus/visorbus_private.h +++ b/drivers/visorbus/visorbus_private.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2010 - 2015 UNISYS CORPORATION * All rights reserved. diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index aa09f8527776..bf2ec59c1f9d 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c @@ -54,10 +54,10 @@ MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection in HDQ mode"); struct hdq_data { struct device *dev; void __iomem *hdq_base; - /* lock status update */ + /* lock read/write/break operations */ struct mutex hdq_mutex; + /* interrupt status and a lock for it */ u8 hdq_irqstatus; - /* device lock */ spinlock_t hdq_spinlock; /* mode: 0-HDQ 1-W1 */ int mode; @@ -120,13 +120,18 @@ static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset, } /* Clear saved irqstatus after using an interrupt */ -static void hdq_reset_irqstatus(struct hdq_data *hdq_data) +static u8 hdq_reset_irqstatus(struct hdq_data *hdq_data, u8 bits) { unsigned long irqflags; + u8 status; spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); - hdq_data->hdq_irqstatus = 0; + status = hdq_data->hdq_irqstatus; + /* this is a read-modify-write */ + hdq_data->hdq_irqstatus &= ~bits; spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); + + return status; } /* write out a byte and fill *status with HDQ_INT_STATUS */ @@ -135,6 +140,16 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) int ret; u8 tmp_status; + ret = mutex_lock_interruptible(&hdq_data->hdq_mutex); + if (ret < 0) { + ret = -EINTR; + goto rtn; + } + + if (hdq_data->hdq_irqstatus) + dev_err(hdq_data->dev, "TX irqstatus not cleared (%02x)\n", + hdq_data->hdq_irqstatus); + *status = 0; hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val); @@ -144,18 +159,19 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO); /* wait for the TXCOMPLETE bit */ ret = wait_event_timeout(hdq_wait_queue, - hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); + (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE), + OMAP_HDQ_TIMEOUT); + *status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE); if (ret == 0) { dev_dbg(hdq_data->dev, "TX wait elapsed\n"); ret = -ETIMEDOUT; goto out; } - *status = hdq_data->hdq_irqstatus; /* check irqstatus */ if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) { dev_dbg(hdq_data->dev, "timeout waiting for" - " TXCOMPLETE/RXCOMPLETE, %x", *status); + " TXCOMPLETE/RXCOMPLETE, %x\n", *status); ret = -ETIMEDOUT; goto out; } @@ -166,11 +182,12 @@ static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status) OMAP_HDQ_FLAG_CLEAR, &tmp_status); if (ret) { dev_dbg(hdq_data->dev, "timeout waiting GO bit" - " return to zero, %x", tmp_status); + " return to zero, %x\n", tmp_status); } out: - hdq_reset_irqstatus(hdq_data); + mutex_unlock(&hdq_data->hdq_mutex); +rtn: return ret; } @@ -181,9 +198,9 @@ static irqreturn_t hdq_isr(int irq, void *_hdq) unsigned long irqflags; spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags); - hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); + hdq_data->hdq_irqstatus |= hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS); spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags); - dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus); + dev_dbg(hdq_data->dev, "hdq_isr: %x\n", hdq_data->hdq_irqstatus); if (hdq_data->hdq_irqstatus & (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE @@ -230,6 +247,10 @@ static int omap_hdq_break(struct hdq_data *hdq_data) goto rtn; } + if (hdq_data->hdq_irqstatus) + dev_err(hdq_data->dev, "break irqstatus not cleared (%02x)\n", + hdq_data->hdq_irqstatus); + /* set the INIT and GO bit */ hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO, @@ -238,18 +259,19 @@ static int omap_hdq_break(struct hdq_data *hdq_data) /* wait for the TIMEOUT bit */ ret = wait_event_timeout(hdq_wait_queue, - hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT); + (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TIMEOUT), + OMAP_HDQ_TIMEOUT); + tmp_status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TIMEOUT); if (ret == 0) { dev_dbg(hdq_data->dev, "break wait elapsed\n"); ret = -EINTR; goto out; } - tmp_status = hdq_data->hdq_irqstatus; /* check irqstatus */ if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) { - dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x", - tmp_status); + dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x\n", + tmp_status); ret = -ETIMEDOUT; goto out; } @@ -275,10 +297,9 @@ static int omap_hdq_break(struct hdq_data *hdq_data) &tmp_status); if (ret) dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits" - " return to zero, %x", tmp_status); + " return to zero, %x\n", tmp_status); out: - hdq_reset_irqstatus(hdq_data); mutex_unlock(&hdq_data->hdq_mutex); rtn: return ret; @@ -309,12 +330,15 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) */ wait_event_timeout(hdq_wait_queue, (hdq_data->hdq_irqstatus - & OMAP_HDQ_INT_STATUS_RXCOMPLETE), + & (OMAP_HDQ_INT_STATUS_RXCOMPLETE | + OMAP_HDQ_INT_STATUS_TIMEOUT)), OMAP_HDQ_TIMEOUT); - + status = hdq_reset_irqstatus(hdq_data, + OMAP_HDQ_INT_STATUS_RXCOMPLETE | + OMAP_HDQ_INT_STATUS_TIMEOUT); hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0, OMAP_HDQ_CTRL_STATUS_DIR); - status = hdq_data->hdq_irqstatus; + /* check irqstatus */ if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) { dev_dbg(hdq_data->dev, "timeout waiting for" @@ -322,11 +346,12 @@ static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val) ret = -ETIMEDOUT; goto out; } + } else { /* interrupt had occurred before hdq_read_byte was called */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE); } /* the data is ready. Read it in! */ *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA); out: - hdq_reset_irqstatus(hdq_data); mutex_unlock(&hdq_data->hdq_mutex); rtn: return ret; @@ -367,15 +392,15 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE), OMAP_HDQ_TIMEOUT); + /* Must clear irqstatus for another RXCOMPLETE interrupt */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE); + if (err == 0) { dev_dbg(hdq_data->dev, "RX wait elapsed\n"); goto out; } id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01); - /* Must clear irqstatus for another RXCOMPLETE interrupt */ - hdq_reset_irqstatus(hdq_data); - /* read comp_bit */ hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask); @@ -383,6 +408,9 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE), OMAP_HDQ_TIMEOUT); + /* Must clear irqstatus for another RXCOMPLETE interrupt */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE); + if (err == 0) { dev_dbg(hdq_data->dev, "RX wait elapsed\n"); goto out; @@ -409,6 +437,9 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE), OMAP_HDQ_TIMEOUT); + /* Must clear irqstatus for another TXCOMPLETE interrupt */ + hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE); + if (err == 0) { dev_dbg(hdq_data->dev, "TX wait elapsed\n"); goto out; @@ -418,7 +449,6 @@ static u8 omap_w1_triplet(void *_hdq, u8 bdir) OMAP_HDQ_CTRL_STATUS_SINGLE); out: - hdq_reset_irqstatus(hdq_data); mutex_unlock(&hdq_data->hdq_mutex); rtn: pm_runtime_mark_last_busy(hdq_data->dev); @@ -464,7 +494,7 @@ static u8 omap_w1_read_byte(void *_hdq) ret = hdq_read_byte(hdq_data, &val); if (ret) - ret = -1; + val = -1; pm_runtime_mark_last_busy(hdq_data->dev); pm_runtime_put_autosuspend(hdq_data->dev); diff --git a/drivers/w1/slaves/w1_ds2430.c b/drivers/w1/slaves/w1_ds2430.c index 6fb0563fb2ae..75bb8a88620b 100644 --- a/drivers/w1/slaves/w1_ds2430.c +++ b/drivers/w1/slaves/w1_ds2430.c @@ -290,6 +290,6 @@ static struct w1_family w1_family_14 = { module_w1_family(w1_family_14); MODULE_AUTHOR("Angelo Dureghello <angelo.dureghello@timesys.com>"); -MODULE_DESCRIPTION("w1 family 14 driver for DS2430, 256kb EEPROM"); +MODULE_DESCRIPTION("w1 family 14 driver for DS2430, 256b EEPROM"); MODULE_LICENSE("GPL"); MODULE_ALIAS("w1-family-" __stringify(W1_EEPROM_DS2430)); diff --git a/drivers/w1/slaves/w1_therm.c b/drivers/w1/slaves/w1_therm.c index e028e0092799..c1b4eda16719 100644 --- a/drivers/w1/slaves/w1_therm.c +++ b/drivers/w1/slaves/w1_therm.c @@ -16,6 +16,7 @@ #include <linux/slab.h> #include <linux/delay.h> #include <linux/hwmon.h> +#include <linux/string.h> #include <linux/w1.h> @@ -25,7 +26,8 @@ #define W1_THERM_DS1825 0x3B #define W1_THERM_DS28EA00 0x42 -/* Allow the strong pullup to be disabled, but default to enabled. +/* + * Allow the strong pullup to be disabled, but default to enabled. * If it was disabled a parasite powered device might not get the require * current to do a temperature conversion. If it is enabled parasite powered * devices have a better chance of getting the current required. @@ -41,42 +43,211 @@ static int w1_strong_pullup = 1; module_param_named(strong_pullup, w1_strong_pullup, int, 0); +/* Counter for devices supporting bulk reading */ +static u16 bulk_read_device_counter; /* =0 as per C standard */ + +/* This command should be in public header w1.h but is not */ +#define W1_RECALL_EEPROM 0xB8 + +/* Nb of try for an operation */ +#define W1_THERM_MAX_TRY 5 + +/* ms delay to retry bus mutex */ +#define W1_THERM_RETRY_DELAY 20 + +/* delay in ms to write in EEPROM */ +#define W1_THERM_EEPROM_WRITE_DELAY 10 + +#define EEPROM_CMD_WRITE "save" /* cmd for write eeprom sysfs */ +#define EEPROM_CMD_READ "restore" /* cmd for read eeprom sysfs */ +#define BULK_TRIGGER_CMD "trigger" /* cmd to trigger a bulk read */ + +#define MIN_TEMP -55 /* min temperature that can be mesured */ +#define MAX_TEMP 125 /* max temperature that can be mesured */ + +/* Helpers Macros */ + +/* + * return a pointer on the slave w1_therm_family_converter struct: + * always test family data existence before using this macro + */ +#define SLAVE_SPECIFIC_FUNC(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->specific_functions) + +/* + * return the power mode of the sl slave : 1-ext, 0-parasite, <0 unknown + * always test family data existence before using this macro + */ +#define SLAVE_POWERMODE(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->external_powered) + +/* + * return the resolution in bit of the sl slave : <0 unknown + * always test family data existence before using this macro + */ +#define SLAVE_RESOLUTION(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->resolution) + +/* + * return whether or not a converT command has been issued to the slave + * * 0: no bulk read is pending + * * -1: conversion is in progress + * * 1: conversion done, result to be read + */ +#define SLAVE_CONVERT_TRIGGERED(sl) \ + (((struct w1_therm_family_data *)(sl->family_data))->convert_triggered) + +/* return the address of the refcnt in the family data */ +#define THERM_REFCNT(family_data) \ + (&((struct w1_therm_family_data *)family_data)->refcnt) + +/* Structs definition */ + +/** + * struct w1_therm_family_converter - bind device specific functions + * @broken: flag for non-registred families + * @reserved: not used here + * @f: pointer to the device binding structure + * @convert: pointer to the device conversion function + * @get_conversion_time: pointer to the device conversion time function + * @set_resolution: pointer to the device set_resolution function + * @get_resolution: pointer to the device get_resolution function + * @write_data: pointer to the device writing function (2 or 3 bytes) + * @bulk_read: true if device family support bulk read, false otherwise + */ +struct w1_therm_family_converter { + u8 broken; + u16 reserved; + struct w1_family *f; + int (*convert)(u8 rom[9]); + int (*get_conversion_time)(struct w1_slave *sl); + int (*set_resolution)(struct w1_slave *sl, int val); + int (*get_resolution)(struct w1_slave *sl); + int (*write_data)(struct w1_slave *sl, const u8 *data); + bool bulk_read; +}; + +/** + * struct w1_therm_family_data - device data + * @rom: ROM device id (64bit Lasered ROM code + 1 CRC byte) + * @refcnt: ref count + * @external_powered: 1 device powered externally, + * 0 device parasite powered, + * -x error or undefined + * @resolution: current device resolution + * @convert_triggered: conversion state of the device + * @specific_functions: pointer to struct of device specific function + */ struct w1_therm_family_data { uint8_t rom[9]; atomic_t refcnt; + int external_powered; + int resolution; + int convert_triggered; + struct w1_therm_family_converter *specific_functions; }; +/** + * struct therm_info - store temperature reading + * @rom: read device data (8 data bytes + 1 CRC byte) + * @crc: computed crc from rom + * @verdict: 1 crc checked, 0 crc not matching + */ struct therm_info { u8 rom[9]; u8 crc; u8 verdict; }; -/* return the address of the refcnt in the family data */ -#define THERM_REFCNT(family_data) \ - (&((struct w1_therm_family_data *)family_data)->refcnt) +/* Hardware Functions declaration */ -static int w1_therm_add_slave(struct w1_slave *sl) -{ - sl->family_data = kzalloc(sizeof(struct w1_therm_family_data), - GFP_KERNEL); - if (!sl->family_data) - return -ENOMEM; - atomic_set(THERM_REFCNT(sl->family_data), 1); - return 0; -} +/** + * reset_select_slave() - reset and select a slave + * @sl: the slave to select + * + * Resets the bus and select the slave by sending a ROM MATCH cmd + * w1_reset_select_slave() from w1_io.c could not be used here because + * it sent a SKIP ROM command if only one device is on the line. + * At the beginning of the such process, sl->master->slave_count is 1 even if + * more devices are on the line, causing collision on the line. + * + * Context: The w1 master lock must be held. + * + * Return: 0 if success, negative kernel error code otherwise. + */ +static int reset_select_slave(struct w1_slave *sl); -static void w1_therm_remove_slave(struct w1_slave *sl) -{ - int refcnt = atomic_sub_return(1, THERM_REFCNT(sl->family_data)); +/** + * convert_t() - Query the device for temperature conversion and read + * @sl: pointer to the slave to read + * @info: pointer to a structure to store the read results + * + * Return: 0 if success, -kernel error code otherwise + */ +static int convert_t(struct w1_slave *sl, struct therm_info *info); - while (refcnt) { - msleep(1000); - refcnt = atomic_read(THERM_REFCNT(sl->family_data)); - } - kfree(sl->family_data); - sl->family_data = NULL; -} +/** + * read_scratchpad() - read the data in device RAM + * @sl: pointer to the slave to read + * @info: pointer to a structure to store the read results + * + * Return: 0 if success, -kernel error code otherwise + */ +static int read_scratchpad(struct w1_slave *sl, struct therm_info *info); + +/** + * write_scratchpad() - write nb_bytes in the device RAM + * @sl: pointer to the slave to write in + * @data: pointer to an array of 3 bytes, as 3 bytes MUST be written + * @nb_bytes: number of bytes to be written (2 for DS18S20, 3 otherwise) + * + * Return: 0 if success, -kernel error code otherwise + */ +static int write_scratchpad(struct w1_slave *sl, const u8 *data, u8 nb_bytes); + +/** + * copy_scratchpad() - Copy the content of scratchpad in device EEPROM + * @sl: slave involved + * + * Return: 0 if success, -kernel error code otherwise + */ +static int copy_scratchpad(struct w1_slave *sl); + +/** + * recall_eeprom() - Restore EEPROM data to device RAM + * @sl: slave involved + * + * Return: 0 if success, -kernel error code otherwise + */ +static int recall_eeprom(struct w1_slave *sl); + +/** + * read_powermode() - Query the power mode of the slave + * @sl: slave to retrieve the power mode + * + * Ask the device to get its power mode (external or parasite) + * and store the power status in the &struct w1_therm_family_data. + * + * Return: + * * 0 parasite powered device + * * 1 externally powered device + * * <0 kernel error code + */ +static int read_powermode(struct w1_slave *sl); + +/** + * trigger_bulk_read() - function to trigger a bulk read on the bus + * @dev_master: the device master of the bus + * + * Send a SKIP ROM follow by a CONVERT T commmand on the bus. + * It also set the status flag in each slave &struct w1_therm_family_data + * to signal that a conversion is in progress. + * + * Return: 0 if success, -kernel error code otherwise + */ +static int trigger_bulk_read(struct w1_master *dev_master); + +/* Sysfs interface declaration */ static ssize_t w1_slave_show(struct device *device, struct device_attribute *attr, char *buf); @@ -87,21 +258,103 @@ static ssize_t w1_slave_store(struct device *device, static ssize_t w1_seq_show(struct device *device, struct device_attribute *attr, char *buf); +static ssize_t temperature_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t ext_power_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t resolution_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t resolution_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t eeprom_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t alarms_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t alarms_show(struct device *device, + struct device_attribute *attr, char *buf); + +static ssize_t therm_bulk_read_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size); + +static ssize_t therm_bulk_read_show(struct device *device, + struct device_attribute *attr, char *buf); + +/* Attributes declarations */ + static DEVICE_ATTR_RW(w1_slave); static DEVICE_ATTR_RO(w1_seq); +static DEVICE_ATTR_RO(temperature); +static DEVICE_ATTR_RO(ext_power); +static DEVICE_ATTR_RW(resolution); +static DEVICE_ATTR_WO(eeprom); +static DEVICE_ATTR_RW(alarms); + +static DEVICE_ATTR_RW(therm_bulk_read); /* attribut at master level */ + +/* Interface Functions declaration */ + +/** + * w1_therm_add_slave() - Called when a new slave is discovered + * @sl: slave just discovered by the master. + * + * Called by the master when the slave is discovered on the bus. Used to + * initialize slave state before the beginning of any communication. + * + * Return: 0 - If success, negative kernel code otherwise + */ +static int w1_therm_add_slave(struct w1_slave *sl); + +/** + * w1_therm_remove_slave() - Called when a slave is removed + * @sl: slave to be removed. + * + * Called by the master when the slave is considered not to be on the bus + * anymore. Used to free memory. + */ +static void w1_therm_remove_slave(struct w1_slave *sl); + +/* Family attributes */ static struct attribute *w1_therm_attrs[] = { &dev_attr_w1_slave.attr, + &dev_attr_temperature.attr, + &dev_attr_ext_power.attr, + &dev_attr_resolution.attr, + &dev_attr_eeprom.attr, + &dev_attr_alarms.attr, + NULL, +}; + +static struct attribute *w1_ds18s20_attrs[] = { + &dev_attr_w1_slave.attr, + &dev_attr_temperature.attr, + &dev_attr_ext_power.attr, + &dev_attr_eeprom.attr, + &dev_attr_alarms.attr, NULL, }; static struct attribute *w1_ds28ea00_attrs[] = { &dev_attr_w1_slave.attr, &dev_attr_w1_seq.attr, + &dev_attr_temperature.attr, + &dev_attr_ext_power.attr, + &dev_attr_resolution.attr, + &dev_attr_eeprom.attr, + &dev_attr_alarms.attr, NULL, }; +/* Attribute groups */ + ATTRIBUTE_GROUPS(w1_therm); +ATTRIBUTE_GROUPS(w1_ds18s20); ATTRIBUTE_GROUPS(w1_ds28ea00); #if IS_REACHABLE(CONFIG_HWMON) @@ -154,6 +407,8 @@ static const struct hwmon_chip_info w1_chip_info = { #define W1_CHIPINFO NULL #endif +/* Family operations */ + static struct w1_family_ops w1_therm_fops = { .add_slave = w1_therm_add_slave, .remove_slave = w1_therm_remove_slave, @@ -161,6 +416,13 @@ static struct w1_family_ops w1_therm_fops = { .chip_info = W1_CHIPINFO, }; +static struct w1_family_ops w1_ds18s20_fops = { + .add_slave = w1_therm_add_slave, + .remove_slave = w1_therm_remove_slave, + .groups = w1_ds18s20_groups, + .chip_info = W1_CHIPINFO, +}; + static struct w1_family_ops w1_ds28ea00_fops = { .add_slave = w1_therm_add_slave, .remove_slave = w1_therm_remove_slave, @@ -168,9 +430,11 @@ static struct w1_family_ops w1_ds28ea00_fops = { .chip_info = W1_CHIPINFO, }; +/* Family binding operations struct */ + static struct w1_family w1_therm_family_DS18S20 = { .fid = W1_THERM_DS18S20, - .fops = &w1_therm_fops, + .fops = &w1_ds18s20_fops, }; static struct w1_family w1_therm_family_DS18B20 = { @@ -193,377 +457,813 @@ static struct w1_family w1_therm_family_DS1825 = { .fops = &w1_therm_fops, }; -struct w1_therm_family_converter { - u8 broken; - u16 reserved; - struct w1_family *f; - int (*convert)(u8 rom[9]); - int (*precision)(struct device *device, int val); - int (*eeprom)(struct device *device); -}; +/* Device dependent func */ + +static inline int w1_DS18B20_convert_time(struct w1_slave *sl) +{ + int ret; + + if (!sl->family_data) + return -ENODEV; /* device unknown */ + + /* return time in ms for conversion operation */ + switch (SLAVE_RESOLUTION(sl)) { + case 9: + ret = 95; + break; + case 10: + ret = 190; + break; + case 11: + ret = 375; + break; + case 12: + default: + ret = 750; + } + return ret; +} + +static inline int w1_DS18S20_convert_time(struct w1_slave *sl) +{ + (void)(sl); + return 750; /* always 750ms for DS18S20 */ +} + +static inline int w1_DS18B20_write_data(struct w1_slave *sl, + const u8 *data) +{ + return write_scratchpad(sl, data, 3); +} + +static inline int w1_DS18S20_write_data(struct w1_slave *sl, + const u8 *data) +{ + /* No config register */ + return write_scratchpad(sl, data, 2); +} + +static inline int w1_DS18B20_set_resolution(struct w1_slave *sl, int val) +{ + int ret; + u8 new_config_register[3]; /* array of data to be written */ + struct therm_info info; + + /* resolution of DS18B20 is in the range [9..12] bits */ + if (val < 9 || val > 12) + return -EINVAL; + + val -= 9; /* soustract 9 the lowest resolution in bit */ + val = (val << 5); /* shift to position bit 5 & bit 6 */ + + /* + * Read the scratchpad to change only the required bits + * (bit5 & bit 6 from byte 4) + */ + ret = read_scratchpad(sl, &info); + if (!ret) { + new_config_register[0] = info.rom[2]; + new_config_register[1] = info.rom[3]; + /* config register is byte 4 & mask 0b10011111*/ + new_config_register[2] = (info.rom[4] & 0x9F) | + (u8) val; + } else + return ret; + + /* Write data in the device RAM */ + ret = w1_DS18B20_write_data(sl, new_config_register); + + return ret; +} + +static inline int w1_DS18B20_get_resolution(struct w1_slave *sl) +{ + int ret; + u8 config_register; + struct therm_info info; + + ret = read_scratchpad(sl, &info); + + if (!ret) { + config_register = info.rom[4]; /* config register is byte 4 */ + config_register &= 0x60; /* 0b01100000 keep only bit 5 & 6 */ + config_register = (config_register >> 5); /* shift */ + config_register += 9; /* add 9 the lowest resolution in bit */ + ret = (int) config_register; + } + return ret; +} -/* write configuration to eeprom */ -static inline int w1_therm_eeprom(struct device *device); +/** + * w1_DS18B20_convert_temp() - temperature computation for DS18B20 + * @rom: data read from device RAM (8 data bytes + 1 CRC byte) + * + * Can be called for any DS18B20 compliant device. + * + * Return: value in millidegrees Celsius. + */ +static inline int w1_DS18B20_convert_temp(u8 rom[9]) +{ + s16 t = le16_to_cpup((__le16 *)rom); -/* Set precision for conversion */ -static inline int w1_DS18B20_precision(struct device *device, int val); -static inline int w1_DS18S20_precision(struct device *device, int val); + return t*1000/16; +} -/* The return value is millidegrees Centigrade. */ -static inline int w1_DS18B20_convert_temp(u8 rom[9]); -static inline int w1_DS18S20_convert_temp(u8 rom[9]); +/** + * w1_DS18S20_convert_temp() - temperature computation for DS18S20 + * @rom: data read from device RAM (8 data bytes + 1 CRC byte) + * + * Can be called for any DS18S20 compliant device. + * + * Return: value in millidegrees Celsius. + */ +static inline int w1_DS18S20_convert_temp(u8 rom[9]) +{ + int t, h; + + if (!rom[7]) { + pr_debug("%s: Invalid argument for conversion\n", __func__); + return 0; + } + + if (rom[1] == 0) + t = ((s32)rom[0] >> 1)*1000; + else + t = 1000*(-1*(s32)(0x100-rom[0]) >> 1); + + t -= 250; + h = 1000*((s32)rom[7] - (s32)rom[6]); + h /= (s32)rom[7]; + t += h; + + return t; +} + +/* Device capability description */ static struct w1_therm_family_converter w1_therm_families[] = { { - .f = &w1_therm_family_DS18S20, - .convert = w1_DS18S20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom + .f = &w1_therm_family_DS18S20, + .convert = w1_DS18S20_convert_temp, + .get_conversion_time = w1_DS18S20_convert_time, + .set_resolution = NULL, /* no config register */ + .get_resolution = NULL, /* no config register */ + .write_data = w1_DS18S20_write_data, + .bulk_read = true }, { - .f = &w1_therm_family_DS1822, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom + .f = &w1_therm_family_DS1822, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = true }, { - .f = &w1_therm_family_DS18B20, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18B20_precision, - .eeprom = w1_therm_eeprom + .f = &w1_therm_family_DS18B20, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = true }, { - .f = &w1_therm_family_DS28EA00, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom + .f = &w1_therm_family_DS28EA00, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = false }, { - .f = &w1_therm_family_DS1825, - .convert = w1_DS18B20_convert_temp, - .precision = w1_DS18S20_precision, - .eeprom = w1_therm_eeprom + .f = &w1_therm_family_DS1825, + .convert = w1_DS18B20_convert_temp, + .get_conversion_time = w1_DS18B20_convert_time, + .set_resolution = w1_DS18B20_set_resolution, + .get_resolution = w1_DS18B20_get_resolution, + .write_data = w1_DS18B20_write_data, + .bulk_read = true } }; -static inline int w1_therm_eeprom(struct device *device) +/* Helpers Functions */ + +/** + * device_family() - Retrieve a pointer on &struct w1_therm_family_converter + * @sl: slave to retrieve the device specific structure + * + * Return: pointer to the slaves's family converter, NULL if not known + */ +static struct w1_therm_family_converter *device_family(struct w1_slave *sl) { - struct w1_slave *sl = dev_to_w1_slave(device); - struct w1_master *dev = sl->master; - u8 rom[9], external_power; - int ret, max_trying = 10; - u8 *family_data = sl->family_data; + struct w1_therm_family_converter *ret = NULL; + int i; - if (!sl->family_data) { - ret = -ENODEV; - goto error; + for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) { + if (w1_therm_families[i].f->fid == sl->family->fid) { + ret = &w1_therm_families[i]; + break; + } } + return ret; +} - /* prevent the slave from going away in sleep */ - atomic_inc(THERM_REFCNT(family_data)); +/** + * bus_mutex_lock() - Acquire the mutex + * @lock: w1 bus mutex to acquire + * + * It try to acquire the mutex W1_THERM_MAX_TRY times and wait + * W1_THERM_RETRY_DELAY between 2 attempts. + * + * Return: true is mutex is acquired and lock, false otherwise + */ +static inline bool bus_mutex_lock(struct mutex *lock) +{ + int max_trying = W1_THERM_MAX_TRY; - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; + /* try to acquire the mutex, if not, sleep retry_delay before retry) */ + while (mutex_lock_interruptible(lock) != 0 && max_trying > 0) { + unsigned long sleep_rem; - memset(rom, 0, sizeof(rom)); + sleep_rem = msleep_interruptible(W1_THERM_RETRY_DELAY); + if (!sleep_rem) + max_trying--; + } - while (max_trying--) { - if (!w1_reset_select_slave(sl)) { - unsigned int tm = 10; - unsigned long sleep_rem; + if (!max_trying) + return false; /* Didn't acquire the bus mutex */ + + return true; +} - /* check if in parasite mode */ - w1_write_8(dev, W1_READ_PSUPPLY); - external_power = w1_read_8(dev); +/** + * support_bulk_read() - check if slave support bulk read + * @sl: device to check the ability + * + * Return: true if bulk read is supported, false if not or error + */ +static inline bool bulk_read_support(struct w1_slave *sl) +{ + if (SLAVE_SPECIFIC_FUNC(sl)) + return SLAVE_SPECIFIC_FUNC(sl)->bulk_read; + + dev_info(&sl->dev, + "%s: Device not supported by the driver\n", __func__); + + return false; /* No device family */ +} + +/** + * conversion_time() - get the Tconv for the slave + * @sl: device to get the conversion time + * + * On device supporting resolution settings, conversion time depend + * on the resolution setting. This helper function get the slave timing, + * depending on its current setting. + * + * Return: conversion time in ms, negative values are kernel error code + */ +static inline int conversion_time(struct w1_slave *sl) +{ + if (SLAVE_SPECIFIC_FUNC(sl)) + return SLAVE_SPECIFIC_FUNC(sl)->get_conversion_time(sl); + + dev_info(&sl->dev, + "%s: Device not supported by the driver\n", __func__); + + return -ENODEV; /* No device family */ +} + +/** + * temperature_from_RAM() - Convert the read info to temperature + * @sl: device that sent the RAM data + * @rom: read value on the slave device RAM + * + * Device dependent, the function bind the correct computation method. + * + * Return: temperature in 1/1000degC, 0 on error. + */ +static inline int temperature_from_RAM(struct w1_slave *sl, u8 rom[9]) +{ + if (SLAVE_SPECIFIC_FUNC(sl)) + return SLAVE_SPECIFIC_FUNC(sl)->convert(rom); - if (w1_reset_select_slave(sl)) - continue; + dev_info(&sl->dev, + "%s: Device not supported by the driver\n", __func__); - /* 10ms strong pullup/delay after the copy command */ - if (w1_strong_pullup == 2 || - (!external_power && w1_strong_pullup)) - w1_next_pullup(dev, tm); + return 0; /* No device family */ +} + +/** + * int_to_short() - Safe casting of int to short + * + * @i: integer to be converted to short + * + * Device register use 1 byte to store signed integer. + * This helper function convert the int in a signed short, + * using the min/max values that device can measure as limits. + * min/max values are defined by macro. + * + * Return: a short in the range of min/max value + */ +static inline s8 int_to_short(int i) +{ + /* Prepare to cast to short by eliminating out of range values */ + i = i > MAX_TEMP ? MAX_TEMP : i; + i = i < MIN_TEMP ? MIN_TEMP : i; + return (s8) i; +} - w1_write_8(dev, W1_COPY_SCRATCHPAD); +/* Interface Functions */ - if (external_power) { - mutex_unlock(&dev->bus_mutex); +static int w1_therm_add_slave(struct w1_slave *sl) +{ + struct w1_therm_family_converter *sl_family_conv; + + /* Allocate memory */ + sl->family_data = kzalloc(sizeof(struct w1_therm_family_data), + GFP_KERNEL); + if (!sl->family_data) + return -ENOMEM; + + atomic_set(THERM_REFCNT(sl->family_data), 1); + + /* Get a pointer to the device specific function struct */ + sl_family_conv = device_family(sl); + if (!sl_family_conv) { + kfree(sl->family_data); + return -ENODEV; + } + /* save this pointer to the device structure */ + SLAVE_SPECIFIC_FUNC(sl) = sl_family_conv; + + if (bulk_read_support(sl)) { + /* + * add the sys entry to trigger bulk_read + * at master level only the 1st time + */ + if (!bulk_read_device_counter) { + int err = device_create_file(&sl->master->dev, + &dev_attr_therm_bulk_read); + + if (err) + dev_warn(&sl->dev, + "%s: Device has been added, but bulk read is unavailable. err=%d\n", + __func__, err); + } + /* Increment the counter */ + bulk_read_device_counter++; + } + + /* Getting the power mode of the device {external, parasite} */ + SLAVE_POWERMODE(sl) = read_powermode(sl); + + if (SLAVE_POWERMODE(sl) < 0) { + /* no error returned as device has been added */ + dev_warn(&sl->dev, + "%s: Device has been added, but power_mode may be corrupted. err=%d\n", + __func__, SLAVE_POWERMODE(sl)); + } + + /* Getting the resolution of the device */ + if (SLAVE_SPECIFIC_FUNC(sl)->get_resolution) { + SLAVE_RESOLUTION(sl) = + SLAVE_SPECIFIC_FUNC(sl)->get_resolution(sl); + if (SLAVE_RESOLUTION(sl) < 0) { + /* no error returned as device has been added */ + dev_warn(&sl->dev, + "%s:Device has been added, but resolution may be corrupted. err=%d\n", + __func__, SLAVE_RESOLUTION(sl)); + } + } + + /* Finally initialize convert_triggered flag */ + SLAVE_CONVERT_TRIGGERED(sl) = 0; + + return 0; +} + +static void w1_therm_remove_slave(struct w1_slave *sl) +{ + int refcnt = atomic_sub_return(1, THERM_REFCNT(sl->family_data)); + + if (bulk_read_support(sl)) { + bulk_read_device_counter--; + /* Delete the entry if no more device support the feature */ + if (!bulk_read_device_counter) + device_remove_file(&sl->master->dev, + &dev_attr_therm_bulk_read); + } + + while (refcnt) { + msleep(1000); + refcnt = atomic_read(THERM_REFCNT(sl->family_data)); + } + kfree(sl->family_data); + sl->family_data = NULL; +} + +/* Hardware Functions */ + +/* Safe version of reset_select_slave - avoid using the one in w_io.c */ +static int reset_select_slave(struct w1_slave *sl) +{ + u8 match[9] = { W1_MATCH_ROM, }; + u64 rn = le64_to_cpu(*((u64 *)&sl->reg_num)); + + if (w1_reset_bus(sl->master)) + return -ENODEV; + + memcpy(&match[1], &rn, 8); + w1_write_block(sl->master, match, 9); + + return 0; +} + +static int convert_t(struct w1_slave *sl, struct therm_info *info) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int t_conv; + int ret = -ENODEV; + bool strong_pullup; - sleep_rem = msleep_interruptible(tm); + if (!sl->family_data) + goto error; + + strong_pullup = (w1_strong_pullup == 2 || + (!SLAVE_POWERMODE(sl) && + w1_strong_pullup)); + + /* get conversion duration device and id dependent */ + t_conv = conversion_time(sl); + + memset(info->rom, 0, sizeof(info->rom)); + + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while (max_trying-- && ret) { /* ret should be 0 */ + + info->verdict = 0; + info->crc = 0; + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + unsigned long sleep_rem; + + /* 750ms strong pullup (or delay) after the convert */ + if (strong_pullup) + w1_next_pullup(dev_master, t_conv); + + w1_write_8(dev_master, W1_CONVERT_TEMP); + + if (strong_pullup) { /*some device need pullup */ + sleep_rem = msleep_interruptible(t_conv); if (sleep_rem != 0) { ret = -EINTR; - goto dec_refcnt; + goto mt_unlock; } + mutex_unlock(&dev_master->bus_mutex); + } else { /*no device need pullup */ + mutex_unlock(&dev_master->bus_mutex); - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; - } else if (!w1_strong_pullup) { - sleep_rem = msleep_interruptible(tm); + sleep_rem = msleep_interruptible(t_conv); if (sleep_rem != 0) { ret = -EINTR; - goto mt_unlock; + goto dec_refcnt; } } - - break; + ret = read_scratchpad(sl, info); + goto dec_refcnt; } + } mt_unlock: - mutex_unlock(&dev->bus_mutex); + mutex_unlock(&dev_master->bus_mutex); dec_refcnt: - atomic_dec(THERM_REFCNT(family_data)); + atomic_dec(THERM_REFCNT(sl->family_data)); error: return ret; } -/* DS18S20 does not feature configuration register */ -static inline int w1_DS18S20_precision(struct device *device, int val) +static int read_scratchpad(struct w1_slave *sl, struct therm_info *info) { - return 0; -} + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; -static inline int w1_DS18B20_precision(struct device *device, int val) -{ - struct w1_slave *sl = dev_to_w1_slave(device); - struct w1_master *dev = sl->master; - u8 rom[9], crc; - int ret, max_trying = 10; - u8 *family_data = sl->family_data; - uint8_t precision_bits; - uint8_t mask = 0x60; + info->verdict = 0; - if (val > 12 || val < 9) { - pr_warn("Unsupported precision\n"); - ret = -EINVAL; + if (!sl->family_data) goto error; - } - if (!sl->family_data) { - ret = -ENODEV; - goto error; - } + memset(info->rom, 0, sizeof(info->rom)); /* prevent the slave from going away in sleep */ - atomic_inc(THERM_REFCNT(family_data)); + atomic_inc(THERM_REFCNT(sl->family_data)); - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ goto dec_refcnt; + } - memset(rom, 0, sizeof(rom)); + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + u8 nb_bytes_read; + + w1_write_8(dev_master, W1_READ_SCRATCHPAD); + + nb_bytes_read = w1_read_block(dev_master, info->rom, 9); + if (nb_bytes_read != 9) { + dev_warn(&sl->dev, + "w1_read_block(): returned %u instead of 9.\n", + nb_bytes_read); + ret = -EIO; + } + + info->crc = w1_calc_crc8(info->rom, 8); + + if (info->rom[8] == info->crc) { + info->verdict = 1; + ret = 0; + } else + ret = -EIO; /* CRC not checked */ + } - /* translate precision to bitmask (see datasheet page 9) */ - switch (val) { - case 9: - precision_bits = 0x00; - break; - case 10: - precision_bits = 0x20; - break; - case 11: - precision_bits = 0x40; - break; - case 12: - default: - precision_bits = 0x60; - break; } + mutex_unlock(&dev_master->bus_mutex); - while (max_trying--) { - crc = 0; +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; +} - if (!w1_reset_select_slave(sl)) { - int count = 0; +static int write_scratchpad(struct w1_slave *sl, const u8 *data, u8 nb_bytes) +{ + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; - /* read values to only alter precision bits */ - w1_write_8(dev, W1_READ_SCRATCHPAD); - count = w1_read_block(dev, rom, 9); - if (count != 9) - dev_warn(device, "w1_read_block() returned %u instead of 9.\n", count); + if (!sl->family_data) + goto error; - crc = w1_calc_crc8(rom, 8); - if (rom[8] == crc) { - rom[4] = (rom[4] & ~mask) | (precision_bits & mask); + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); - if (!w1_reset_select_slave(sl)) { - w1_write_8(dev, W1_WRITE_SCRATCHPAD); - w1_write_8(dev, rom[2]); - w1_write_8(dev, rom[3]); - w1_write_8(dev, rom[4]); + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } - break; - } - } + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + w1_write_8(dev_master, W1_WRITE_SCRATCHPAD); + w1_write_block(dev_master, data, nb_bytes); + ret = 0; } } + mutex_unlock(&dev_master->bus_mutex); - mutex_unlock(&dev->bus_mutex); dec_refcnt: - atomic_dec(THERM_REFCNT(family_data)); + atomic_dec(THERM_REFCNT(sl->family_data)); error: return ret; } -static inline int w1_DS18B20_convert_temp(u8 rom[9]) +static int copy_scratchpad(struct w1_slave *sl) { - s16 t = le16_to_cpup((__le16 *)rom); + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int t_write, ret = -ENODEV; + bool strong_pullup; - return t*1000/16; -} + if (!sl->family_data) + goto error; -static inline int w1_DS18S20_convert_temp(u8 rom[9]) -{ - int t, h; + t_write = W1_THERM_EEPROM_WRITE_DELAY; + strong_pullup = (w1_strong_pullup == 2 || + (!SLAVE_POWERMODE(sl) && + w1_strong_pullup)); - if (!rom[7]) - return 0; + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); - if (rom[1] == 0) - t = ((s32)rom[0] >> 1)*1000; - else - t = 1000*(-1*(s32)(0x100-rom[0]) >> 1); + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } - t -= 250; - h = 1000*((s32)rom[7] - (s32)rom[6]); - h /= (s32)rom[7]; - t += h; + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + unsigned long sleep_rem; - return t; -} + /* 10ms strong pullup (or delay) after the convert */ + if (strong_pullup) + w1_next_pullup(dev_master, t_write); -static inline int w1_convert_temp(u8 rom[9], u8 fid) -{ - int i; + w1_write_8(dev_master, W1_COPY_SCRATCHPAD); - for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) - if (w1_therm_families[i].f->fid == fid) - return w1_therm_families[i].convert(rom); + if (strong_pullup) { + sleep_rem = msleep_interruptible(t_write); + if (sleep_rem != 0) { + ret = -EINTR; + goto mt_unlock; + } + } + ret = 0; + } - return 0; + } + +mt_unlock: + mutex_unlock(&dev_master->bus_mutex); +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; } -static ssize_t w1_slave_store(struct device *device, - struct device_attribute *attr, const char *buf, - size_t size) +static int recall_eeprom(struct w1_slave *sl) { - int val, ret; - struct w1_slave *sl = dev_to_w1_slave(device); - int i; + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; - ret = kstrtoint(buf, 0, &val); - if (ret) - return ret; + if (!sl->family_data) + goto error; - for (i = 0; i < ARRAY_SIZE(w1_therm_families); ++i) { - if (w1_therm_families[i].f->fid == sl->family->fid) { - /* zero value indicates to write current configuration to eeprom */ - if (val == 0) - ret = w1_therm_families[i].eeprom(device); - else - ret = w1_therm_families[i].precision(device, val); - break; + /* prevent the slave from going away in sleep */ + atomic_inc(THERM_REFCNT(sl->family_data)); + + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto dec_refcnt; + } + + while (max_trying-- && ret) { /* ret should be 0 */ + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + + w1_write_8(dev_master, W1_RECALL_EEPROM); + + ret = 1; /* Slave will pull line to 0 */ + while (ret) + ret = 1 - w1_touch_bit(dev_master, 1); } + } - return ret ? : size; + + mutex_unlock(&dev_master->bus_mutex); + +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; } -static ssize_t read_therm(struct device *device, - struct w1_slave *sl, struct therm_info *info) +static int read_powermode(struct w1_slave *sl) { - struct w1_master *dev = sl->master; - u8 external_power; - int ret, max_trying = 10; - u8 *family_data = sl->family_data; + struct w1_master *dev_master = sl->master; + int max_trying = W1_THERM_MAX_TRY; + int ret = -ENODEV; - if (!family_data) { - ret = -ENODEV; + if (!sl->family_data) goto error; - } /* prevent the slave from going away in sleep */ - atomic_inc(THERM_REFCNT(family_data)); + atomic_inc(THERM_REFCNT(sl->family_data)); - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ goto dec_refcnt; + } - memset(info->rom, 0, sizeof(info->rom)); + while ((max_trying--) && (ret < 0)) { + /* safe version to select slave */ + if (!reset_select_slave(sl)) { + w1_write_8(dev_master, W1_READ_PSUPPLY); + /* + * Emit a read time slot and read only one bit, + * 1 is externally powered, + * 0 is parasite powered + */ + ret = w1_touch_bit(dev_master, 1); + /* ret should be either 1 either 0 */ + } + } + mutex_unlock(&dev_master->bus_mutex); - while (max_trying--) { +dec_refcnt: + atomic_dec(THERM_REFCNT(sl->family_data)); +error: + return ret; +} - info->verdict = 0; - info->crc = 0; +static int trigger_bulk_read(struct w1_master *dev_master) +{ + struct w1_slave *sl = NULL; /* used to iterate through slaves */ + int max_trying = W1_THERM_MAX_TRY; + int t_conv = 0; + int ret = -ENODEV; + bool strong_pullup = false; + + /* + * Check whether there are parasite powered device on the bus, + * and compute duration of conversion for these devices + * so we can apply a strong pullup if required + */ + list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) { + if (!sl->family_data) + goto error; + if (bulk_read_support(sl)) { + int t_cur = conversion_time(sl); + + t_conv = t_cur > t_conv ? t_cur : t_conv; + strong_pullup = strong_pullup || + (w1_strong_pullup == 2 || + (!SLAVE_POWERMODE(sl) && + w1_strong_pullup)); + } + } - if (!w1_reset_select_slave(sl)) { - int count = 0; - unsigned int tm = 750; - unsigned long sleep_rem; + /* + * t_conv is the max conversion time required on the bus + * If its 0, no device support the bulk read feature + */ + if (!t_conv) + goto error; - w1_write_8(dev, W1_READ_PSUPPLY); - external_power = w1_read_8(dev); + if (!bus_mutex_lock(&dev_master->bus_mutex)) { + ret = -EAGAIN; /* Didn't acquire the mutex */ + goto error; + } - if (w1_reset_select_slave(sl)) - continue; + while ((max_trying--) && (ret < 0)) { /* ret should be either 0 */ - /* 750ms strong pullup (or delay) after the convert */ - if (w1_strong_pullup == 2 || - (!external_power && w1_strong_pullup)) - w1_next_pullup(dev, tm); + if (!w1_reset_bus(dev_master)) { /* Just reset the bus */ + unsigned long sleep_rem; - w1_write_8(dev, W1_CONVERT_TEMP); + w1_write_8(dev_master, W1_SKIP_ROM); - if (external_power) { - mutex_unlock(&dev->bus_mutex); + if (strong_pullup) /* Apply pullup if required */ + w1_next_pullup(dev_master, t_conv); - sleep_rem = msleep_interruptible(tm); - if (sleep_rem != 0) { - ret = -EINTR; - goto dec_refcnt; - } + w1_write_8(dev_master, W1_CONVERT_TEMP); - ret = mutex_lock_interruptible(&dev->bus_mutex); - if (ret != 0) - goto dec_refcnt; - } else if (!w1_strong_pullup) { - sleep_rem = msleep_interruptible(tm); + /* set a flag to instruct that converT pending */ + list_for_each_entry(sl, + &dev_master->slist, w1_slave_entry) { + if (bulk_read_support(sl)) + SLAVE_CONVERT_TRIGGERED(sl) = -1; + } + + if (strong_pullup) { /* some device need pullup */ + sleep_rem = msleep_interruptible(t_conv); if (sleep_rem != 0) { ret = -EINTR; goto mt_unlock; } - } - - if (!w1_reset_select_slave(sl)) { - - w1_write_8(dev, W1_READ_SCRATCHPAD); - count = w1_read_block(dev, info->rom, 9); - if (count != 9) { - dev_warn(device, "w1_read_block() " - "returned %u instead of 9.\n", - count); + mutex_unlock(&dev_master->bus_mutex); + } else { + mutex_unlock(&dev_master->bus_mutex); + sleep_rem = msleep_interruptible(t_conv); + if (sleep_rem != 0) { + ret = -EINTR; + goto set_flag; } - - info->crc = w1_calc_crc8(info->rom, 8); - - if (info->rom[8] == info->crc) - info->verdict = 1; } + ret = 0; + goto set_flag; } - - if (info->verdict) - break; } mt_unlock: - mutex_unlock(&dev->bus_mutex); -dec_refcnt: - atomic_dec(THERM_REFCNT(family_data)); + mutex_unlock(&dev_master->bus_mutex); +set_flag: + /* set a flag to register convsersion is done */ + list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) { + if (bulk_read_support(sl)) + SLAVE_CONVERT_TRIGGERED(sl) = 1; + } error: return ret; } +/* Sysfs Interface definition */ + static ssize_t w1_slave_show(struct device *device, struct device_attribute *attr, char *buf) { @@ -572,43 +1272,405 @@ static ssize_t w1_slave_show(struct device *device, u8 *family_data = sl->family_data; int ret, i; ssize_t c = PAGE_SIZE; - u8 fid = sl->family->fid; - ret = read_therm(device, sl, &info); - if (ret) - return ret; + if (bulk_read_support(sl)) { + if (SLAVE_CONVERT_TRIGGERED(sl) < 0) { + dev_dbg(device, + "%s: Conversion in progress, retry later\n", + __func__); + return 0; + } else if (SLAVE_CONVERT_TRIGGERED(sl) > 0) { + /* A bulk read has been issued, read the device RAM */ + ret = read_scratchpad(sl, &info); + SLAVE_CONVERT_TRIGGERED(sl) = 0; + } else + ret = convert_t(sl, &info); + } else + ret = convert_t(sl, &info); + + if (ret < 0) { + dev_dbg(device, + "%s: Temperature data may be corrupted. err=%d\n", + __func__, ret); + return 0; + } for (i = 0; i < 9; ++i) c -= snprintf(buf + PAGE_SIZE - c, c, "%02x ", info.rom[i]); c -= snprintf(buf + PAGE_SIZE - c, c, ": crc=%02x %s\n", info.crc, (info.verdict) ? "YES" : "NO"); + if (info.verdict) memcpy(family_data, info.rom, sizeof(info.rom)); else - dev_warn(device, "Read failed CRC check\n"); + dev_warn(device, "%s:Read failed CRC check\n", __func__); for (i = 0; i < 9; ++i) c -= snprintf(buf + PAGE_SIZE - c, c, "%02x ", ((u8 *)family_data)[i]); c -= snprintf(buf + PAGE_SIZE - c, c, "t=%d\n", - w1_convert_temp(info.rom, fid)); + temperature_from_RAM(sl, info.rom)); + ret = PAGE_SIZE - c; return ret; } +static ssize_t w1_slave_store(struct device *device, + struct device_attribute *attr, const char *buf, + size_t size) +{ + int val, ret = 0; + struct w1_slave *sl = dev_to_w1_slave(device); + + ret = kstrtoint(buf, 10, &val); /* converting user entry to int */ + + if (ret) { /* conversion error */ + dev_info(device, + "%s: conversion error. err= %d\n", __func__, ret); + return size; /* return size to avoid call back again */ + } + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return size; /* No device family */ + } + + if (val == 0) /* val=0 : trigger a EEPROM save */ + ret = copy_scratchpad(sl); + else { + if (SLAVE_SPECIFIC_FUNC(sl)->set_resolution) + ret = SLAVE_SPECIFIC_FUNC(sl)->set_resolution(sl, val); + } + + if (ret) { + dev_info(device, + "%s: writing error %d\n", __func__, ret); + /* return size to avoid call back again */ + } else + SLAVE_RESOLUTION(sl) = val; + + return size; /* always return size to avoid infinite calling */ +} + +static ssize_t temperature_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + struct therm_info info; + int ret = 0; + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return 0; /* No device family */ + } + + if (bulk_read_support(sl)) { + if (SLAVE_CONVERT_TRIGGERED(sl) < 0) { + dev_dbg(device, + "%s: Conversion in progress, retry later\n", + __func__); + return 0; + } else if (SLAVE_CONVERT_TRIGGERED(sl) > 0) { + /* A bulk read has been issued, read the device RAM */ + ret = read_scratchpad(sl, &info); + SLAVE_CONVERT_TRIGGERED(sl) = 0; + } else + ret = convert_t(sl, &info); + } else + ret = convert_t(sl, &info); + + if (ret < 0) { + dev_dbg(device, + "%s: Temperature data may be corrupted. err=%d\n", + __func__, ret); + return 0; + } + + return sprintf(buf, "%d\n", temperature_from_RAM(sl, info.rom)); +} + +static ssize_t ext_power_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + + if (!sl->family_data) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return 0; /* No device family */ + } + + /* Getting the power mode of the device {external, parasite} */ + SLAVE_POWERMODE(sl) = read_powermode(sl); + + if (SLAVE_POWERMODE(sl) < 0) { + dev_dbg(device, + "%s: Power_mode may be corrupted. err=%d\n", + __func__, SLAVE_POWERMODE(sl)); + } + return sprintf(buf, "%d\n", SLAVE_POWERMODE(sl)); +} + +static ssize_t resolution_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return 0; /* No device family */ + } + + /* get the correct function depending on the device */ + SLAVE_RESOLUTION(sl) = SLAVE_SPECIFIC_FUNC(sl)->get_resolution(sl); + if (SLAVE_RESOLUTION(sl) < 0) { + dev_dbg(device, + "%s: Resolution may be corrupted. err=%d\n", + __func__, SLAVE_RESOLUTION(sl)); + } + + return sprintf(buf, "%d\n", SLAVE_RESOLUTION(sl)); +} + +static ssize_t resolution_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + int val; + int ret = 0; + + ret = kstrtoint(buf, 10, &val); /* converting user entry to int */ + + if (ret) { /* conversion error */ + dev_info(device, + "%s: conversion error. err= %d\n", __func__, ret); + return size; /* return size to avoid call back again */ + } + + if ((!sl->family_data) || (!SLAVE_SPECIFIC_FUNC(sl))) { + dev_info(device, + "%s: Device not supported by the driver\n", __func__); + return size; /* No device family */ + } + + /* + * Don't deal with the val enterd by user, + * only device knows what is correct or not + */ + + /* get the correct function depending on the device */ + ret = SLAVE_SPECIFIC_FUNC(sl)->set_resolution(sl, val); + + if (ret) { + dev_info(device, + "%s: writing error %d\n", __func__, ret); + /* return size to avoid call back again */ + } else + SLAVE_RESOLUTION(sl) = val; + + return size; +} + +static ssize_t eeprom_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + int ret = -EINVAL; /* Invalid argument */ + + if (size == sizeof(EEPROM_CMD_WRITE)) { + if (!strncmp(buf, EEPROM_CMD_WRITE, sizeof(EEPROM_CMD_WRITE)-1)) + ret = copy_scratchpad(sl); + } else if (size == sizeof(EEPROM_CMD_READ)) { + if (!strncmp(buf, EEPROM_CMD_READ, sizeof(EEPROM_CMD_READ)-1)) + ret = recall_eeprom(sl); + } + + if (ret) + dev_info(device, "%s: error in process %d\n", __func__, ret); + + return size; +} + +static ssize_t alarms_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + int ret; + s8 th = 0, tl = 0; + struct therm_info scratchpad; + + ret = read_scratchpad(sl, &scratchpad); + + if (!ret) { + th = scratchpad.rom[2]; /* TH is byte 2 */ + tl = scratchpad.rom[3]; /* TL is byte 3 */ + } else { + dev_info(device, + "%s: error reading alarms register %d\n", + __func__, ret); + } + + return sprintf(buf, "%hd %hd\n", tl, th); +} + +static ssize_t alarms_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_slave *sl = dev_to_w1_slave(device); + struct therm_info info; + u8 new_config_register[3]; /* array of data to be written */ + int temp, ret; + char *token = NULL; + s8 tl, th, tt; /* 1 byte per value + temp ring order */ + char *p_args, *orig; + + p_args = orig = kmalloc(size, GFP_KERNEL); + /* Safe string copys as buf is const */ + if (!p_args) { + dev_warn(device, + "%s: error unable to allocate memory %d\n", + __func__, -ENOMEM); + return size; + } + strcpy(p_args, buf); + + /* Split string using space char */ + token = strsep(&p_args, " "); + + if (!token) { + dev_info(device, + "%s: error parsing args %d\n", __func__, -EINVAL); + goto free_m; + } + + /* Convert 1st entry to int */ + ret = kstrtoint (token, 10, &temp); + if (ret) { + dev_info(device, + "%s: error parsing args %d\n", __func__, ret); + goto free_m; + } + + tl = int_to_short(temp); + + /* Split string using space char */ + token = strsep(&p_args, " "); + if (!token) { + dev_info(device, + "%s: error parsing args %d\n", __func__, -EINVAL); + goto free_m; + } + /* Convert 2nd entry to int */ + ret = kstrtoint (token, 10, &temp); + if (ret) { + dev_info(device, + "%s: error parsing args %d\n", __func__, ret); + goto free_m; + } + + /* Prepare to cast to short by eliminating out of range values */ + th = int_to_short(temp); + + /* Reorder if required th and tl */ + if (tl > th) { + tt = tl; tl = th; th = tt; + } + + /* + * Read the scratchpad to change only the required bits + * (th : byte 2 - tl: byte 3) + */ + ret = read_scratchpad(sl, &info); + if (!ret) { + new_config_register[0] = th; /* Byte 2 */ + new_config_register[1] = tl; /* Byte 3 */ + new_config_register[2] = info.rom[4];/* Byte 4 */ + } else { + dev_info(device, + "%s: error reading from the slave device %d\n", + __func__, ret); + goto free_m; + } + + /* Write data in the device RAM */ + if (!SLAVE_SPECIFIC_FUNC(sl)) { + dev_info(device, + "%s: Device not supported by the driver %d\n", + __func__, -ENODEV); + goto free_m; + } + + ret = SLAVE_SPECIFIC_FUNC(sl)->write_data(sl, new_config_register); + if (ret) + dev_info(device, + "%s: error writing to the slave device %d\n", + __func__, ret); + +free_m: + /* free allocated memory */ + kfree(orig); + + return size; +} + +static ssize_t therm_bulk_read_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct w1_master *dev_master = dev_to_w1_master(device); + int ret = -EINVAL; /* Invalid argument */ + + if (size == sizeof(BULK_TRIGGER_CMD)) + if (!strncmp(buf, BULK_TRIGGER_CMD, + sizeof(BULK_TRIGGER_CMD)-1)) + ret = trigger_bulk_read(dev_master); + + if (ret) + dev_info(device, + "%s: unable to trigger a bulk read on the bus. err=%d\n", + __func__, ret); + + return size; +} + +static ssize_t therm_bulk_read_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct w1_master *dev_master = dev_to_w1_master(device); + struct w1_slave *sl = NULL; + int ret = 0; + + list_for_each_entry(sl, &dev_master->slist, w1_slave_entry) { + if (sl->family_data) { + if (bulk_read_support(sl)) { + if (SLAVE_CONVERT_TRIGGERED(sl) == -1) { + ret = -1; + goto show_result; + } + if (SLAVE_CONVERT_TRIGGERED(sl) == 1) + /* continue to check other slaves */ + ret = 1; + } + } + } +show_result: + return sprintf(buf, "%d\n", ret); +} + #if IS_REACHABLE(CONFIG_HWMON) static int w1_read_temp(struct device *device, u32 attr, int channel, long *val) { struct w1_slave *sl = dev_get_drvdata(device); struct therm_info info; - u8 fid = sl->family->fid; int ret; switch (attr) { case hwmon_temp_input: - ret = read_therm(device, sl, &info); + ret = convert_t(sl, &info); if (ret) return ret; @@ -617,7 +1679,7 @@ static int w1_read_temp(struct device *device, u32 attr, int channel, return ret; } - *val = w1_convert_temp(info.rom, fid); + *val = temperature_from_RAM(sl, info.rom); ret = 0; break; default: @@ -666,7 +1728,7 @@ static ssize_t w1_seq_show(struct device *device, if (ack != W1_42_SUCCESS_CONFIRM_BYTE) goto error; - /* In case the bus fails to send 0xFF, limit*/ + /* In case the bus fails to send 0xFF, limit */ for (i = 0; i <= 64; i++) { if (w1_reset_bus(sl->master)) goto error; diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 000000000000..8f10bb06cb59 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon <abailon@baylibre.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */ diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h new file mode 100644 index 000000000000..307b977100b6 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mn.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H + +#define IMX8MN_ICN_NOC 1 +#define IMX8MN_ICS_DRAM 2 +#define IMX8MN_ICS_OCRAM 3 +#define IMX8MN_ICM_A53 4 + +#define IMX8MN_ICM_GPU 5 +#define IMX8MN_ICN_GPU 6 + +#define IMX8MN_ICM_CSI1 7 +#define IMX8MN_ICM_CSI2 8 +#define IMX8MN_ICM_ISI 9 +#define IMX8MN_ICM_LCDIF 10 +#define IMX8MN_ICN_MIPI 11 + +#define IMX8MN_ICM_USB 12 + +#define IMX8MN_ICM_SDMA2 13 +#define IMX8MN_ICM_SDMA3 14 +#define IMX8MN_ICN_AUDIO 15 + +#define IMX8MN_ICN_ENET 16 +#define IMX8MN_ICM_ENET 17 + +#define IMX8MN_ICM_NAND 18 +#define IMX8MN_ICM_SDMA1 19 +#define IMX8MN_ICM_USDHC1 20 +#define IMX8MN_ICM_USDHC2 21 +#define IMX8MN_ICM_USDHC3 22 +#define IMX8MN_ICN_MAIN 23 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ diff --git a/include/dt-bindings/interconnect/imx8mq.h b/include/dt-bindings/interconnect/imx8mq.h new file mode 100644 index 000000000000..1a4cae7f8be2 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mq.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H + +#define IMX8MQ_ICN_NOC 1 +#define IMX8MQ_ICS_DRAM 2 +#define IMX8MQ_ICS_OCRAM 3 +#define IMX8MQ_ICM_A53 4 + +#define IMX8MQ_ICM_VPU 5 +#define IMX8MQ_ICN_VIDEO 6 + +#define IMX8MQ_ICM_GPU 7 +#define IMX8MQ_ICN_GPU 8 + +#define IMX8MQ_ICM_DCSS 9 +#define IMX8MQ_ICN_DCSS 10 + +#define IMX8MQ_ICM_USB1 11 +#define IMX8MQ_ICM_USB2 12 +#define IMX8MQ_ICN_USB 13 + +#define IMX8MQ_ICM_CSI1 14 +#define IMX8MQ_ICM_CSI2 15 +#define IMX8MQ_ICM_LCDIF 16 +#define IMX8MQ_ICN_DISPLAY 17 + +#define IMX8MQ_ICM_SDMA2 18 +#define IMX8MQ_ICN_AUDIO 19 + +#define IMX8MQ_ICN_ENET 20 +#define IMX8MQ_ICM_ENET 21 + +#define IMX8MQ_ICM_SDMA1 22 +#define IMX8MQ_ICM_NAND 23 +#define IMX8MQ_ICM_USDHC1 24 +#define IMX8MQ_ICM_USDHC2 25 +#define IMX8MQ_ICM_PCIE1 26 +#define IMX8MQ_ICM_PCIE2 27 +#define IMX8MQ_ICN_MAIN 28 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 193cc9dbf448..e3e9f0e3a878 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -100,10 +100,12 @@ union coresight_dev_subtype { }; /** - * struct coresight_platform_data - data harvested from the DT specification - * @nr_inport: number of input ports for this component. - * @nr_outport: number of output ports for this component. - * @conns: Array of nr_outport connections from this component + * struct coresight_platform_data - data harvested from the firmware + * specification. + * + * @nr_inport: Number of elements for the input connections. + * @nr_outport: Number of elements for the output connections. + * @conns: Sparse array of nr_outport connections from this component. */ struct coresight_platform_data { int nr_inport; @@ -140,12 +142,28 @@ struct coresight_desc { * @chid_fwnode: remote component's fwnode handle. * @child_dev: a @coresight_device representation of the component connected to @outport. + * @link: Representation of the connection as a sysfs link. */ struct coresight_connection { int outport; int child_port; struct fwnode_handle *child_fwnode; struct coresight_device *child_dev; + struct coresight_sysfs_link *link; +}; + +/** + * struct coresight_sysfs_link - representation of a connection in sysfs. + * @orig: Originating (master) coresight device for the link. + * @orig_name: Name to use for the link orig->target. + * @target: Target (slave) coresight device for the link. + * @target_name: Name to use for the link target->orig. + */ +struct coresight_sysfs_link { + struct coresight_device *orig; + const char *orig_name; + struct coresight_device *target; + const char *target_name; }; /** @@ -165,6 +183,9 @@ struct coresight_connection { * @ea: Device attribute for sink representation under PMU directory. * @ect_dev: Associated cross trigger device. Not part of the trace data * path or connections. + * @nr_links: number of sysfs links created to other components from this + * device. These will appear in the "connections" group. + * @has_conns_grp: Have added a "connections" group for sysfs links. */ struct coresight_device { struct coresight_platform_data *pdata; @@ -180,6 +201,9 @@ struct coresight_device { struct dev_ext_attribute *ea; /* cross trigger handling */ struct coresight_device *ect_dev; + /* sysfs links between components */ + int nr_links; + bool has_conns_grp; }; /* diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 24b3a77810b6..8377afef8806 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -142,6 +142,7 @@ enum cpuhp_state { CPUHP_AP_ARM_XEN_STARTING, CPUHP_AP_ARM_KVMPV_STARTING, CPUHP_AP_ARM_CORESIGHT_STARTING, + CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, CPUHP_AP_ARM64_ISNDEP_STARTING, CPUHP_AP_SMPCFD_DYING, CPUHP_AP_X86_TBOOT_DYING, diff --git a/include/linux/firmware/intel/stratix10-smc.h b/include/linux/firmware/intel/stratix10-smc.h index 013ae4819deb..682dbf694007 100644 --- a/include/linux/firmware/intel/stratix10-smc.h +++ b/include/linux/firmware/intel/stratix10-smc.h @@ -54,32 +54,25 @@ * Secure monitor software doesn't recognize the request. * * INTEL_SIP_SMC_STATUS_OK: - * FPGA configuration completed successfully, - * In case of FPGA configuration write operation, it means secure monitor - * software can accept the next chunk of FPGA configuration data. + * Secure monitor software accepts the service client's request. * - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY: - * In case of FPGA configuration write operation, it means secure monitor - * software is still processing previous data & can't accept the next chunk - * of data. Service driver needs to issue - * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the - * completed block(s). + * INTEL_SIP_SMC_STATUS_BUSY: + * Secure monitor software is still processing service client's request. * - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR: - * There is error during the FPGA configuration process. + * INTEL_SIP_SMC_STATUS_REJECTED: + * Secure monitor software reject the service client's request. * - * INTEL_SIP_SMC_REG_ERROR: - * There is error during a read or write operation of the protected registers. + * INTEL_SIP_SMC_STATUS_ERROR: + * There is error during the process of service request. * * INTEL_SIP_SMC_RSU_ERROR: - * There is error during a remote status update. + * There is error during the process of remote status update request. */ #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF #define INTEL_SIP_SMC_STATUS_OK 0x0 -#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY 0x1 -#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED 0x2 -#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4 -#define INTEL_SIP_SMC_REG_ERROR 0x5 +#define INTEL_SIP_SMC_STATUS_BUSY 0x1 +#define INTEL_SIP_SMC_STATUS_REJECTED 0x2 +#define INTEL_SIP_SMC_STATUS_ERROR 0x4 #define INTEL_SIP_SMC_RSU_ERROR 0x7 /** @@ -95,7 +88,7 @@ * a2-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 @@ -115,8 +108,8 @@ * a3-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. * a1: 64bit physical address of 1st completed memory block if any completed * block, otherwise zero value. * a2: 64bit physical address of 2nd completed memory block if any completed @@ -133,15 +126,15 @@ * * Sync call used by service driver at EL1 to track the completed write * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE - * call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY. + * call returns INTEL_SIP_SMC_STATUS_BUSY. * * Call register usage: * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. * a1: 64bit physical address of 1st completed memory block. * a2: 64bit physical address of 2nd completed memory block if * any completed block, otherwise zero value. @@ -164,8 +157,8 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or - * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or + * INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 @@ -183,7 +176,7 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. * a1: start of physical address of reserved memory block. * a2: size of reserved memory block. * a3: not used. @@ -203,7 +196,7 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * a1-7: not used. * * Return status: - * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR. + * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. * a1-3: not used. */ #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 diff --git a/include/linux/firmware/intel/stratix10-svc-client.h b/include/linux/firmware/intel/stratix10-svc-client.h index 59bc6e2af693..64213c3e82f5 100644 --- a/include/linux/firmware/intel/stratix10-svc-client.h +++ b/include/linux/firmware/intel/stratix10-svc-client.h @@ -18,45 +18,37 @@ /** * Status of the sent command, in bit number * - * SVC_COMMAND_STATUS_RECONFIG_REQUEST_OK: - * Secure firmware accepts the request of FPGA reconfiguration. + * SVC_STATUS_OK: + * Secure firmware accepts the request issued by one of service clients. * - * SVC_STATUS_RECONFIG_BUFFER_SUBMITTED: - * Service client successfully submits FPGA configuration - * data buffer to secure firmware. + * SVC_STATUS_BUFFER_SUBMITTED: + * Service client successfully submits data buffer to secure firmware. * - * SVC_COMMAND_STATUS_RECONFIG_BUFFER_DONE: + * SVC_STATUS_BUFFER_DONE: * Secure firmware completes data process, ready to accept the * next WRITE transaction. * - * SVC_COMMAND_STATUS_RECONFIG_COMPLETED: - * Secure firmware completes FPGA configuration successfully, FPGA should - * be in user mode. + * SVC_STATUS_COMPLETED: + * Secure firmware completes service request successfully. In case of + * FPGA configuration, FPGA should be in user mode. * - * SVC_COMMAND_STATUS_RECONFIG_BUSY: - * FPGA configuration is still in process. + * SVC_COMMAND_STATUS_BUSY: + * Service request is still in process. * - * SVC_COMMAND_STATUS_RECONFIG_ERROR: - * Error encountered during FPGA configuration. + * SVC_COMMAND_STATUS_ERROR: + * Error encountered during the process of the service request. * - * SVC_STATUS_RSU_OK: - * Secure firmware accepts the request of remote status update (RSU). - * - * SVC_STATUS_RSU_ERROR: - * Error encountered during remote system update. - * - * SVC_STATUS_RSU_NO_SUPPORT: - * Secure firmware doesn't support RSU retry or notify feature. + * SVC_STATUS_NO_SUPPORT: + * Secure firmware doesn't support requested features such as RSU retry + * or RSU notify. */ -#define SVC_STATUS_RECONFIG_REQUEST_OK 0 -#define SVC_STATUS_RECONFIG_BUFFER_SUBMITTED 1 -#define SVC_STATUS_RECONFIG_BUFFER_DONE 2 -#define SVC_STATUS_RECONFIG_COMPLETED 3 -#define SVC_STATUS_RECONFIG_BUSY 4 -#define SVC_STATUS_RECONFIG_ERROR 5 -#define SVC_STATUS_RSU_OK 6 -#define SVC_STATUS_RSU_ERROR 7 -#define SVC_STATUS_RSU_NO_SUPPORT 8 +#define SVC_STATUS_OK 0 +#define SVC_STATUS_BUFFER_SUBMITTED 1 +#define SVC_STATUS_BUFFER_DONE 2 +#define SVC_STATUS_COMPLETED 3 +#define SVC_STATUS_BUSY 4 +#define SVC_STATUS_ERROR 5 +#define SVC_STATUS_NO_SUPPORT 6 /** * Flag bit for COMMAND_RECONFIG @@ -84,32 +76,29 @@ struct stratix10_svc_chan; * @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting * * @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status - * is SVC_STATUS_RECONFIG_REQUEST_OK + * is SVC_STATUS_OK * * @COMMAND_RECONFIG_DATA_SUBMIT: submit buffer(s) of bit-stream data for the - * FPGA configuration, return status is SVC_STATUS_RECONFIG_BUFFER_SUBMITTED, - * or SVC_STATUS_RECONFIG_ERROR + * FPGA configuration, return status is SVC_STATUS_SUBMITTED or SVC_STATUS_ERROR * * @COMMAND_RECONFIG_DATA_CLAIM: check the status of the configuration, return - * status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or - * SVC_STATUS_RECONFIG_ERROR + * status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR * * @COMMAND_RECONFIG_STATUS: check the status of the configuration, return - * status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or - * SVC_STATUS_RECONFIG_ERROR + * status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR * * @COMMAND_RSU_STATUS: request remote system update boot log, return status * is log data or SVC_STATUS_RSU_ERROR * * @COMMAND_RSU_UPDATE: set the offset of the bitstream to boot after reboot, - * return status is SVC_STATUS_RSU_OK or SVC_STATUS_RSU_ERROR + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR * * @COMMAND_RSU_NOTIFY: report the status of hard processor system - * software to firmware, return status is SVC_STATUS_RSU_OK or - * SVC_STATUS_RSU_ERROR + * software to firmware, return status is SVC_STATUS_OK or + * SVC_STATUS_ERROR * * @COMMAND_RSU_RETRY: query firmware for the current image's retry counter, - * return status is SVC_STATUS_RSU_OK or SVC_STATUS_RSU_ERROR + * return status is SVC_STATUS_OK or SVC_STATUS_ERROR */ enum stratix10_svc_command_code { COMMAND_NOOP = 0, diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 8efa5ac22d7e..5968df82b991 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -42,6 +42,8 @@ #define ZYNQMP_PM_MAX_QOS 100U +#define GSS_NUM_REGS (4) + /* Node capabilities */ #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U @@ -62,6 +64,7 @@ enum pm_api_id { PM_GET_API_VERSION = 1, + PM_SYSTEM_SHUTDOWN = 12, PM_REQUEST_NODE = 13, PM_RELEASE_NODE, PM_SET_REQUIREMENT, @@ -107,6 +110,12 @@ enum pm_ioctl_id { IOCTL_GET_PLL_FRAC_MODE, IOCTL_SET_PLL_FRAC_DATA, IOCTL_GET_PLL_FRAC_DATA, + IOCTL_WRITE_GGS = 12, + IOCTL_READ_GGS = 13, + IOCTL_WRITE_PGGS = 14, + IOCTL_READ_PGGS = 15, + /* Set healthy bit value */ + IOCTL_SET_BOOT_HEALTH_STATUS = 17, }; enum pm_query_id { @@ -279,6 +288,18 @@ enum dll_reset_type { PM_DLL_RESET_PULSE, }; +enum zynqmp_pm_shutdown_type { + ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN, + ZYNQMP_PM_SHUTDOWN_TYPE_RESET, + ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY, +}; + +enum zynqmp_pm_shutdown_subtype { + ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM, + ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY, + ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM, +}; + /** * struct zynqmp_pm_query_data - PM query data * @qid: query ID @@ -293,49 +314,199 @@ struct zynqmp_pm_query_data { u32 arg3; }; -struct zynqmp_eemi_ops { - int (*get_api_version)(u32 *version); - int (*get_chipid)(u32 *idcode, u32 *version); - int (*fpga_load)(const u64 address, const u32 size, const u32 flags); - int (*fpga_get_status)(u32 *value); - int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); - int (*clock_enable)(u32 clock_id); - int (*clock_disable)(u32 clock_id); - int (*clock_getstate)(u32 clock_id, u32 *state); - int (*clock_setdivider)(u32 clock_id, u32 divider); - int (*clock_getdivider)(u32 clock_id, u32 *divider); - int (*clock_setrate)(u32 clock_id, u64 rate); - int (*clock_getrate)(u32 clock_id, u64 *rate); - int (*clock_setparent)(u32 clock_id, u32 parent_id); - int (*clock_getparent)(u32 clock_id, u32 *parent_id); - int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out); - int (*reset_assert)(const enum zynqmp_pm_reset reset, - const enum zynqmp_pm_reset_action assert_flag); - int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status); - int (*init_finalize)(void); - int (*set_suspend_mode)(u32 mode); - int (*request_node)(const u32 node, - const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack); - int (*release_node)(const u32 node); - int (*set_requirement)(const u32 node, - const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack); - int (*aes)(const u64 address, u32 *out); -}; int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) -const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); +int zynqmp_pm_get_api_version(u32 *version); +int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); +int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); +int zynqmp_pm_clock_enable(u32 clock_id); +int zynqmp_pm_clock_disable(u32 clock_id); +int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); +int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); +int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); +int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate); +int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate); +int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); +int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); +int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); +int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); +int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); +int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); +int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); +int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); +int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, + const enum zynqmp_pm_reset_action assert_flag); +int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); +int zynqmp_pm_init_finalize(void); +int zynqmp_pm_set_suspend_mode(u32 mode); +int zynqmp_pm_request_node(const u32 node, const u32 capabilities, + const u32 qos, const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_release_node(const u32 node); +int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_aes_engine(const u64 address, u32 *out); +int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); +int zynqmp_pm_fpga_get_status(u32 *value); +int zynqmp_pm_write_ggs(u32 index, u32 value); +int zynqmp_pm_read_ggs(u32 index, u32 *value); +int zynqmp_pm_write_pggs(u32 index, u32 value); +int zynqmp_pm_read_pggs(u32 index, u32 *value); +int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); +int zynqmp_pm_set_boot_health_status(u32 value); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { return ERR_PTR(-ENODEV); } +static inline int zynqmp_pm_get_api_version(u32 *version) +{ + return -ENODEV; +} +static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) +{ + return -ENODEV; +} +static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, + u32 *out) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_enable(u32 clock_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_disable(u32 clock_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) +{ + return -ENODEV; +} +static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) +{ + return -ENODEV; +} +static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) +{ + return -ENODEV; +} +static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, + const enum zynqmp_pm_reset_action assert_flag) +{ + return -ENODEV; +} +static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, + u32 *status) +{ + return -ENODEV; +} +static inline int zynqmp_pm_init_finalize(void) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_suspend_mode(u32 mode) +{ + return -ENODEV; +} +static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} +static inline int zynqmp_pm_release_node(const u32 node) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_requirement(const u32 node, + const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} +static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) +{ + return -ENODEV; +} +static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, + const u32 flags) +{ + return -ENODEV; +} +static inline int zynqmp_pm_fpga_get_status(u32 *value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_write_ggs(u32 index, u32 value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_write_pggs(u32 index, u32 value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) +{ + return -ENODEV; +} +static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) +{ + return -ENODEV; +} +static inline int zynqmp_pm_set_boot_health_status(u32 value) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ diff --git a/include/linux/greybus/greybus_protocols.h b/include/linux/greybus/greybus_protocols.h index dfbc6c39a74b..aeb8f9243545 100644 --- a/include/linux/greybus/greybus_protocols.h +++ b/include/linux/greybus/greybus_protocols.h @@ -345,7 +345,7 @@ struct gb_cap_get_ims_certificate_request { struct gb_cap_get_ims_certificate_response { __u8 result_code; - __u8 certificate[0]; + __u8 certificate[]; } __packed; /* CAP authenticate request/response */ @@ -358,7 +358,7 @@ struct gb_cap_authenticate_request { struct gb_cap_authenticate_response { __u8 result_code; __u8 response[64]; - __u8 signature[0]; + __u8 signature[]; } __packed; @@ -642,7 +642,7 @@ struct gb_hid_get_report_request { struct gb_hid_set_report_request { __u8 report_type; __u8 report_id; - __u8 report[0]; + __u8 report[]; } __packed; /* HID input report request, via interrupt pipe */ @@ -680,7 +680,7 @@ struct gb_i2c_transfer_op { struct gb_i2c_transfer_request { __le16 op_count; - struct gb_i2c_transfer_op ops[0]; /* op_count of these */ + struct gb_i2c_transfer_op ops[]; /* op_count of these */ } __packed; struct gb_i2c_transfer_response { __u8 data[0]; /* inbound data */ @@ -908,7 +908,7 @@ struct gb_spi_transfer_request { __u8 chip_select; /* of the spi device */ __u8 mode; /* of the spi device */ __le16 count; - struct gb_spi_transfer transfers[0]; /* count of these */ + struct gb_spi_transfer transfers[]; /* count of these */ } __packed; struct gb_spi_transfer_response { @@ -1188,7 +1188,7 @@ struct gb_svc_pwrmon_rail_count_get_response { struct gb_svc_pwrmon_rail_names_get_response { __u8 status; - __u8 name[0][GB_SVC_PWRMON_RAIL_NAME_BUFSIZE]; + __u8 name[][GB_SVC_PWRMON_RAIL_NAME_BUFSIZE]; } __packed; #define GB_SVC_PWRMON_TYPE_CURR 0x01 @@ -1281,7 +1281,7 @@ struct gb_svc_intf_oops_request { struct gb_raw_send_request { __le32 len; - __u8 data[0]; + __u8 data[]; } __packed; @@ -1300,7 +1300,7 @@ struct gb_raw_send_request { /* Represents data from AP -> Module */ struct gb_uart_send_data_request { __le16 size; - __u8 data[0]; + __u8 data[]; } __packed; /* recv-data-request flags */ @@ -1313,7 +1313,7 @@ struct gb_uart_send_data_request { struct gb_uart_recv_data_request { __le16 size; __u8 flags; - __u8 data[0]; + __u8 data[]; } __packed; struct gb_uart_receive_credits_request { @@ -1382,14 +1382,14 @@ struct gb_loopback_transfer_request { __le32 len; __le32 reserved0; __le32 reserved1; - __u8 data[0]; + __u8 data[]; } __packed; struct gb_loopback_transfer_response { __le32 len; __le32 reserved0; __le32 reserved1; - __u8 data[0]; + __u8 data[]; } __packed; /* SDIO */ @@ -1530,13 +1530,13 @@ struct gb_sdio_transfer_request { __le16 data_blocks; __le16 data_blksz; - __u8 data[0]; + __u8 data[]; } __packed; struct gb_sdio_transfer_response { __le16 data_blocks; __le16 data_blksz; - __u8 data[0]; + __u8 data[]; } __packed; /* event request: generated by module and is defined as unidirectional */ @@ -1572,7 +1572,7 @@ struct gb_camera_configure_streams_request { __u8 flags; #define GB_CAMERA_CONFIGURE_STREAMS_TEST_ONLY 0x01 __le16 padding; - struct gb_camera_stream_config_request config[0]; + struct gb_camera_stream_config_request config[]; } __packed; /* Greybus Camera Configure Streams response payload */ @@ -1593,7 +1593,7 @@ struct gb_camera_configure_streams_response { __u8 flags; __u8 padding[2]; __le32 data_rate; - struct gb_camera_stream_config_response config[0]; + struct gb_camera_stream_config_response config[]; }; /* Greybus Camera Capture request payload - response has no payload */ @@ -1602,7 +1602,7 @@ struct gb_camera_capture_request { __u8 streams; __u8 padding; __le16 num_frames; - __u8 settings[0]; + __u8 settings[]; } __packed; /* Greybus Camera Flush response payload - request has no payload */ @@ -1616,7 +1616,7 @@ struct gb_camera_metadata_request { __le16 frame_number; __u8 stream; __u8 padding; - __u8 metadata[0]; + __u8 metadata[]; } __packed; /* Lights */ @@ -1993,7 +1993,7 @@ struct gb_audio_integer64 { struct gb_audio_enumerated { __le32 items; __le16 names_length; - __u8 names[0]; + __u8 names[]; } __packed; struct gb_audio_ctl_elem_info { /* See snd_ctl_elem_info in Linux source */ @@ -2033,7 +2033,7 @@ struct gb_audio_widget { __u8 type; /* GB_AUDIO_WIDGET_TYPE_* */ __u8 state; /* GB_AUDIO_WIDGET_STATE_* */ __u8 ncontrols; - struct gb_audio_control ctl[0]; /* 'ncontrols' entries */ + struct gb_audio_control ctl[]; /* 'ncontrols' entries */ } __packed; struct gb_audio_route { @@ -2059,7 +2059,7 @@ struct gb_audio_topology { * struct gb_audio_widget widgets[num_widgets]; * struct gb_audio_route routes[num_routes]; */ - __u8 data[0]; + __u8 data[]; } __packed; struct gb_audio_get_topology_size_response { @@ -2157,7 +2157,7 @@ struct gb_audio_streaming_event_request { struct gb_audio_send_data_request { __le64 timestamp; - __u8 data[0]; + __u8 data[]; } __packed; @@ -2171,7 +2171,7 @@ struct gb_audio_send_data_request { struct gb_log_send_log_request { __le16 len; - __u8 msg[0]; + __u8 msg[]; } __packed; #endif /* __GREYBUS_PROTOCOLS_H */ diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h index d70a914cba11..d8c29049f066 100644 --- a/include/linux/interconnect.h +++ b/include/linux/interconnect.h @@ -28,7 +28,11 @@ struct device; struct icc_path *icc_get(struct device *dev, const int src_id, const int dst_id); struct icc_path *of_icc_get(struct device *dev, const char *name); +struct icc_path *devm_of_icc_get(struct device *dev, const char *name); +struct icc_path *of_icc_get_by_index(struct device *dev, int idx); void icc_put(struct icc_path *path); +int icc_enable(struct icc_path *path); +int icc_disable(struct icc_path *path); int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw); void icc_set_tag(struct icc_path *path, u32 tag); @@ -46,10 +50,31 @@ static inline struct icc_path *of_icc_get(struct device *dev, return NULL; } +static inline struct icc_path *devm_of_icc_get(struct device *dev, + const char *name) +{ + return NULL; +} + +static inline struct icc_path *of_icc_get_by_index(struct device *dev, int idx) +{ + return NULL; +} + static inline void icc_put(struct icc_path *path) { } +static inline int icc_enable(struct icc_path *path) +{ + return 0; +} + +static inline int icc_disable(struct icc_path *path) +{ + return 0; +} + static inline int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) { return 0; diff --git a/include/linux/ioport.h b/include/linux/ioport.h index cc9a5b4593ca..6c2b06fe8beb 100644 --- a/include/linux/ioport.h +++ b/include/linux/ioport.h @@ -302,5 +302,11 @@ struct resource *devm_request_free_mem_region(struct device *dev, struct resource *request_free_mem_region(struct resource *base, unsigned long size, const char *name); +#ifdef CONFIG_IO_STRICT_DEVMEM +void revoke_devmem(struct resource *res); +#else +static inline void revoke_devmem(struct resource *res) { }; +#endif + #endif /* __ASSEMBLY__ */ #endif /* _LINUX_IOPORT_H */ diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 3d7c3c26eeb9..c4a940d98912 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -331,8 +331,6 @@ struct mhi_controller_config { * @wlock: Lock for protecting device wakeup * @mhi_link_info: Device bandwidth info * @st_worker: State transition worker - * @fw_worker: Firmware download worker - * @syserr_worker: System error worker * @state_event: State change event * @status_cb: CB function to notify power states of the device (required) * @wake_get: CB function to assert device wake (optional) @@ -412,8 +410,6 @@ struct mhi_controller { spinlock_t wlock; struct mhi_link_info mhi_link_info; struct work_struct st_worker; - struct work_struct fw_worker; - struct work_struct syserr_worker; wait_queue_head_t state_event; void (*status_cb)(struct mhi_controller *mhi_cntrl, @@ -573,6 +569,13 @@ void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state); /** + * mhi_notify - Notify the MHI client driver about client device status + * @mhi_dev: MHI device instance + * @cb_reason: MHI callback reason + */ +void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason); + +/** * mhi_prepare_for_power_up - Do pre-initialization before power up. * This is optional, call this before power up if * the controller does not want bus framework to @@ -609,6 +612,18 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful); void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl); /** + * mhi_pm_suspend - Move MHI into a suspended state + * @mhi_cntrl: MHI controller + */ +int mhi_pm_suspend(struct mhi_controller *mhi_cntrl); + +/** + * mhi_pm_resume - Resume MHI from suspended state + * @mhi_cntrl: MHI controller + */ +int mhi_pm_resume(struct mhi_controller *mhi_cntrl); + +/** * mhi_download_rddm_img - Download ramdump image from device for * debugging purpose. * @mhi_cntrl: MHI controller diff --git a/include/linux/parport.h b/include/linux/parport.h index 13932ce8b37b..1fb508c19e83 100644 --- a/include/linux/parport.h +++ b/include/linux/parport.h @@ -325,18 +325,10 @@ struct pardev_cb { unsigned int flags; }; -/* parport_register_device declares that a device is connected to a - port, and tells the kernel all it needs to know. - - pf is the preemption function (may be NULL for no callback) - - kf is the wake-up function (may be NULL for no callback) - - irq_func is the interrupt handler (may be NULL for no interrupts) - - handle is a user pointer that gets handed to callback functions. */ -struct pardevice *parport_register_device(struct parport *port, - const char *name, - int (*pf)(void *), void (*kf)(void *), - void (*irq_func)(void *), - int flags, void *handle); - +/* + * parport_register_dev_model declares that a device is connected to a + * port, and tells the kernel all it needs to know. + */ struct pardevice * parport_register_dev_model(struct parport *port, const char *name, const struct pardev_cb *par_dev_cb, int cnt); diff --git a/include/linux/rtsx_pci.h b/include/linux/rtsx_pci.h index 65b8142a7fed..e8780d4e4636 100644 --- a/include/linux/rtsx_pci.h +++ b/include/linux/rtsx_pci.h @@ -1080,11 +1080,7 @@ struct pcr_ops { void (*stop_cmd)(struct rtsx_pcr *pcr); void (*set_aspm)(struct rtsx_pcr *pcr, bool enable); - int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency); - int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val); void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active); - void (*full_on)(struct rtsx_pcr *pcr); - void (*power_saving)(struct rtsx_pcr *pcr); void (*enable_ocp)(struct rtsx_pcr *pcr); void (*disable_ocp)(struct rtsx_pcr *pcr); void (*init_ocp)(struct rtsx_pcr *pcr); @@ -1108,13 +1104,6 @@ enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; #define L1_SNOOZE_TEST_EN BIT(5) #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6) -enum dev_aspm_mode { - DEV_ASPM_DYNAMIC, - DEV_ASPM_BACKDOOR, - DEV_ASPM_STATIC, - DEV_ASPM_DISABLE, -}; - /* * struct rtsx_cr_option - card reader option * @dev_flags: device flags @@ -1125,7 +1114,6 @@ enum dev_aspm_mode { * @ltr_active_latency: ltr mode active latency * @ltr_idle_latency: ltr mode idle latency * @ltr_l1off_latency: ltr mode l1off latency - * @dev_aspm_mode: device aspm mode * @l1_snooze_delay: l1 snooze delay * @ltr_l1off_sspwrgate: ltr l1off sspwrgate * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate @@ -1142,7 +1130,6 @@ struct rtsx_cr_option { u32 ltr_active_latency; u32 ltr_idle_latency; u32 ltr_l1off_latency; - enum dev_aspm_mode dev_aspm_mode; u32 l1_snooze_delay; u8 ltr_l1off_sspwrgate; u8 ltr_l1off_snooze_sspwrgate; @@ -1320,18 +1307,6 @@ static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr) return (u8 *)(pcr->host_cmds_ptr); } -static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr, - u8 mask, u8 append) -{ - int err; - u8 val; - - err = pci_read_config_byte(pcr->pci, addr, &val); - if (err < 0) - return err; - return pci_write_config_byte(pcr->pci, addr, (val & mask) | append); -} - static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) { rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 00f5826092e3..9c27a32df9bb 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -291,8 +291,8 @@ struct sdw_dpn_audio_mode { * implementation-defined interrupts * @max_ch: Maximum channels supported * @min_ch: Minimum channels supported - * @num_ch: Number of discrete channels supported - * @ch: Discrete channels supported + * @num_channels: Number of discrete channels supported + * @channels: Discrete channels supported * @num_ch_combinations: Number of channel combinations supported * @ch_combinations: Channel combinations supported * @modes: SDW mode supported @@ -316,8 +316,8 @@ struct sdw_dpn_prop { u32 imp_def_interrupts; u32 max_ch; u32 min_ch; - u32 num_ch; - u32 *ch; + u32 num_channels; + u32 *channels; u32 num_ch_combinations; u32 *ch_combinations; u32 modes; @@ -632,6 +632,19 @@ struct sdw_slave { #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) +/** + * struct sdw_master_device - SoundWire 'Master Device' representation + * @dev: Linux device for this Master + * @bus: Bus handle shortcut + */ +struct sdw_master_device { + struct device dev; + struct sdw_bus *bus; +}; + +#define dev_to_sdw_master_device(d) \ + container_of(d, struct sdw_master_device, dev) + struct sdw_driver { const char *name; @@ -787,8 +800,10 @@ struct sdw_master_ops { /** * struct sdw_bus - SoundWire bus - * @dev: Master linux device + * @dev: Shortcut to &bus->md->dev to avoid changing the entire code. + * @md: Master device * @link_id: Link id number, can be 0 to N, unique for each Master + * @id: bus system-wide unique id * @slaves: list of Slaves on this bus * @assigned: Bitmap for Slave device numbers. * Bit set implies used number, bit clear implies unused number. @@ -812,7 +827,9 @@ struct sdw_master_ops { */ struct sdw_bus { struct device *dev; + struct sdw_master_device *md; unsigned int link_id; + int id; struct list_head slaves; DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); struct mutex bus_lock; @@ -832,8 +849,9 @@ struct sdw_bus { bool multi_link; }; -int sdw_add_bus_master(struct sdw_bus *bus); -void sdw_delete_bus_master(struct sdw_bus *bus); +int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, + struct fwnode_handle *fwnode); +void sdw_bus_master_delete(struct sdw_bus *bus); /** * sdw_port_config: Master or Slave Port configuration diff --git a/include/linux/soundwire/sdw_type.h b/include/linux/soundwire/sdw_type.h index aaa7f4267c14..52eb66cd11bc 100644 --- a/include/linux/soundwire/sdw_type.h +++ b/include/linux/soundwire/sdw_type.h @@ -5,6 +5,13 @@ #define __SOUNDWIRE_TYPES_H extern struct bus_type sdw_bus_type; +extern struct device_type sdw_slave_type; +extern struct device_type sdw_master_type; + +static inline int is_sdw_slave(const struct device *dev) +{ + return dev->type == &sdw_slave_type; +} #define drv_to_sdw_driver(_drv) container_of(_drv, struct sdw_driver, driver) @@ -14,7 +21,7 @@ extern struct bus_type sdw_bus_type; int __sdw_register_driver(struct sdw_driver *drv, struct module *owner); void sdw_unregister_driver(struct sdw_driver *drv); -int sdw_slave_modalias(const struct sdw_slave *slave, char *buf, size_t size); +int sdw_slave_uevent(struct device *dev, struct kobj_uevent_env *env); /** * module_sdw_driver() - Helper macro for registering a Soundwire driver diff --git a/include/uapi/linux/magic.h b/include/uapi/linux/magic.h index d78064007b17..f3956fc11de6 100644 --- a/include/uapi/linux/magic.h +++ b/include/uapi/linux/magic.h @@ -94,6 +94,7 @@ #define BALLOON_KVM_MAGIC 0x13661366 #define ZSMALLOC_MAGIC 0x58295829 #define DMA_BUF_MAGIC 0x444d4142 /* "DMAB" */ +#define DEVMEM_MAGIC 0x454d444d /* "DMEM" */ #define Z3FOLD_MAGIC 0x33 #define PPC_CMM_MAGIC 0xc7571590 diff --git a/include/uapi/misc/habanalabs.h b/include/uapi/misc/habanalabs.h index 4faa2c9767e5..f6267a8d7416 100644 --- a/include/uapi/misc/habanalabs.h +++ b/include/uapi/misc/habanalabs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note * - * Copyright 2016-2019 HabanaLabs, Ltd. + * Copyright 2016-2020 HabanaLabs, Ltd. * All Rights Reserved. * */ @@ -15,10 +15,13 @@ * Defines that are asic-specific but constitutes as ABI between kernel driver * and userspace */ -#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ +#define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ +#define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ +#define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 48 +#define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 24 /* - * Queue Numbering + * Goya queue Numbering * * The external queues (PCI DMA channels) MUST be before the internal queues * and each group (PCI DMA channels and internal) must be contiguous inside @@ -46,6 +49,129 @@ enum goya_queue_id { }; /* + * Gaudi queue Numbering + * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. + * Except one CPU queue, all the rest are internal queues. + */ + +enum gaudi_queue_id { + GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ + GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ + GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ + GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ + GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ + GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ + GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ + GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ + GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ + GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ + GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ + GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ + GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ + GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ + GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ + GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ + GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ + GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ + GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ + GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ + GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ + GAUDI_QUEUE_ID_DMA_5_0 = 21, /* external */ + GAUDI_QUEUE_ID_DMA_5_1 = 22, /* external */ + GAUDI_QUEUE_ID_DMA_5_2 = 23, /* external */ + GAUDI_QUEUE_ID_DMA_5_3 = 24, /* external */ + GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ + GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ + GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ + GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ + GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ + GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ + GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ + GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ + GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ + GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ + GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ + GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ + GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ + GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ + GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ + GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ + GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ + GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ + GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ + GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ + GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ + GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ + GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ + GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ + GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ + GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ + GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ + GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ + GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ + GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ + GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ + GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ + GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ + GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ + GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ + GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ + GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ + GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ + GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ + GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ + GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ + GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ + GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ + GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ + GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ + GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ + GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ + GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ + GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ + GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ + GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ + GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ + GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ + GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ + GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ + GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ + GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ + GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ + GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ + GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ + GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ + GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ + GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ + GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ + GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ + GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ + GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ + GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ + GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ + GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ + GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ + GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ + GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ + GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ + GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ + GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ + GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ + GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ + GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ + GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ + GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ + GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ + GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ + GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ + GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ + GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ + GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ + GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ + GAUDI_QUEUE_ID_SIZE +}; + +/* * Engine Numbering * * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' @@ -69,6 +195,40 @@ enum goya_engine_id { GOYA_ENGINE_ID_SIZE }; +enum gaudi_engine_id { + GAUDI_ENGINE_ID_DMA_0 = 0, + GAUDI_ENGINE_ID_DMA_1, + GAUDI_ENGINE_ID_DMA_2, + GAUDI_ENGINE_ID_DMA_3, + GAUDI_ENGINE_ID_DMA_4, + GAUDI_ENGINE_ID_DMA_5, + GAUDI_ENGINE_ID_DMA_6, + GAUDI_ENGINE_ID_DMA_7, + GAUDI_ENGINE_ID_MME_0, + GAUDI_ENGINE_ID_MME_1, + GAUDI_ENGINE_ID_MME_2, + GAUDI_ENGINE_ID_MME_3, + GAUDI_ENGINE_ID_TPC_0, + GAUDI_ENGINE_ID_TPC_1, + GAUDI_ENGINE_ID_TPC_2, + GAUDI_ENGINE_ID_TPC_3, + GAUDI_ENGINE_ID_TPC_4, + GAUDI_ENGINE_ID_TPC_5, + GAUDI_ENGINE_ID_TPC_6, + GAUDI_ENGINE_ID_TPC_7, + GAUDI_ENGINE_ID_NIC_0, + GAUDI_ENGINE_ID_NIC_1, + GAUDI_ENGINE_ID_NIC_2, + GAUDI_ENGINE_ID_NIC_3, + GAUDI_ENGINE_ID_NIC_4, + GAUDI_ENGINE_ID_NIC_5, + GAUDI_ENGINE_ID_NIC_6, + GAUDI_ENGINE_ID_NIC_7, + GAUDI_ENGINE_ID_NIC_8, + GAUDI_ENGINE_ID_NIC_9, + GAUDI_ENGINE_ID_SIZE +}; + enum hl_device_status { HL_DEVICE_STATUS_OPERATIONAL, HL_DEVICE_STATUS_IN_RESET, @@ -101,6 +261,8 @@ enum hl_device_status { * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset * operations performed on the device since the last * time the driver was loaded. + * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time + * for synchronization. */ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 @@ -111,6 +273,7 @@ enum hl_device_status { #define HL_INFO_HW_EVENTS_AGGREGATE 7 #define HL_INFO_CLK_RATE 8 #define HL_INFO_RESET_COUNT 9 +#define HL_INFO_TIME_SYNC 10 #define HL_INFO_VERSION_MAX_LEN 128 #define HL_INFO_CARD_NAME_MAX_LEN 16 @@ -122,7 +285,8 @@ struct hl_info_hw_ip_info { __u32 sram_size; __u32 num_of_events; __u32 device_id; /* PCI Device ID */ - __u32 reserved[3]; + __u32 module_id; /* For mezzanine cards in servers (From OCP spec.) */ + __u32 reserved[2]; __u32 armcp_cpld_version; __u32 psoc_pci_pll_nr; __u32 psoc_pci_pll_nf; @@ -169,6 +333,11 @@ struct hl_info_reset_count { __u32 soft_reset_cnt; }; +struct hl_info_time_sync { + __u64 device_time; + __u64 host_time; +}; + struct hl_info_args { /* Location of relevant struct in userspace */ __u64 return_pointer; @@ -201,7 +370,8 @@ struct hl_info_args { /* Opcode to destroy previously created command buffer */ #define HL_CB_OP_DESTROY 1 -#define HL_MAX_CB_SIZE 0x200000 /* 2MB */ +/* 2MB minus 32 bytes for 2xMSG_PROT */ +#define HL_MAX_CB_SIZE (0x200000 - 32) struct hl_cb_in { /* Handle of CB or 0 if we want to create one */ @@ -232,52 +402,87 @@ union hl_cb_args { * compatibility */ struct hl_cs_chunk { - /* - * For external queue, this represents a Handle of CB on the Host - * For internal queue, this represents an SRAM or DRAM address of the - * internal CB - */ - __u64 cb_handle; + union { + /* For external queue, this represents a Handle of CB on the + * Host. + * For internal queue in Goya, this represents an SRAM or + * a DRAM address of the internal CB. In Gaudi, this might also + * represent a mapped host address of the CB. + * + * A mapped host address is in the device address space, after + * a host address was mapped by the device MMU. + */ + __u64 cb_handle; + + /* Relevant only when HL_CS_FLAGS_WAIT is set. + * This holds address of array of u64 values that contain + * signal CS sequence numbers. The wait described by this job + * will listen on all those signals (wait event per signal) + */ + __u64 signal_seq_arr; + }; + /* Index of queue to put the CB on */ __u32 queue_index; - /* - * Size of command buffer with valid packets - * Can be smaller then actual CB size - */ - __u32 cb_size; + + union { + /* + * Size of command buffer with valid packets + * Can be smaller then actual CB size + */ + __u32 cb_size; + + /* Relevant only when HL_CS_FLAGS_WAIT is set. + * Number of entries in signal_seq_arr + */ + __u32 num_signal_seq_arr; + }; + /* HL_CS_CHUNK_FLAGS_* */ __u32 cs_chunk_flags; + /* Align structure to 64 bytes */ __u32 pad[11]; }; +/* SIGNAL and WAIT flags are mutually exclusive */ #define HL_CS_FLAGS_FORCE_RESTORE 0x1 +#define HL_CS_FLAGS_SIGNAL 0x2 +#define HL_CS_FLAGS_WAIT 0x4 #define HL_CS_STATUS_SUCCESS 0 #define HL_MAX_JOBS_PER_CS 512 struct hl_cs_in { + /* this holds address of array of hl_cs_chunk for restore phase */ __u64 chunks_restore; - /* this holds address of array of hl_cs_chunk for execution phase */ + + /* holds address of array of hl_cs_chunk for execution phase */ __u64 chunks_execute; + /* this holds address of array of hl_cs_chunk for store phase - * Currently not in use */ __u64 chunks_store; + /* Number of chunks in restore phase array. Maximum number is * HL_MAX_JOBS_PER_CS */ __u32 num_chunks_restore; + /* Number of chunks in execution array. Maximum number is * HL_MAX_JOBS_PER_CS */ __u32 num_chunks_execute; + /* Number of chunks in restore phase array - Currently not in use */ __u32 num_chunks_store; + /* HL_CS_FLAGS_* */ __u32 cs_flags; + /* Context ID - Currently not in use */ __u32 ctx_id; }; @@ -588,8 +793,8 @@ struct hl_debug_args { * For jobs on external queues, the user needs to create command buffers * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on * internal queues, the user needs to prepare a "command buffer" with packets - * on either the SRAM or DRAM, and give the device address of that buffer to - * the CS ioctl. + * on either the device SRAM/DRAM or the host, and give the device address of + * that buffer to the CS ioctl. * * This IOCTL is asynchronous in regard to the actual execution of the CS. This * means it returns immediately after ALL the JOBS were enqueued on their @@ -601,7 +806,7 @@ struct hl_debug_args { * external JOBS have been completed. Note that if the CS has internal JOBS * which can execute AFTER the external JOBS have finished, the driver might * report that the CS has finished executing BEFORE the internal JOBS have - * actually finish executing. + * actually finished executing. * * Even though the sequence number increments per CS, the user can NOT * automatically assume that if CS with sequence number N finished, then CS diff --git a/kernel/resource.c b/kernel/resource.c index 76036a41143b..841737bbda9e 100644 --- a/kernel/resource.c +++ b/kernel/resource.c @@ -1126,6 +1126,7 @@ struct resource * __request_region(struct resource *parent, { DECLARE_WAITQUEUE(wait, current); struct resource *res = alloc_resource(GFP_KERNEL); + struct resource *orig_parent = parent; if (!res) return NULL; @@ -1176,6 +1177,10 @@ struct resource * __request_region(struct resource *parent, break; } write_unlock(&resource_lock); + + if (res && orig_parent == &iomem_resource) + revoke_devmem(res); + return res; } EXPORT_SYMBOL(__request_region); |