diff options
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/pwm-samsung.yaml | 17 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts | 6 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 13 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/tesla/fsd.dtsi | 4 |
6 files changed, 35 insertions, 14 deletions
diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index fe603fb1b2cc..2162f661ed5a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -20,12 +20,17 @@ description: |+ properties: compatible: - enum: - - samsung,s3c2410-pwm # 16-bit, S3C24xx - - samsung,s3c6400-pwm # 32-bit, S3C64xx - - samsung,s5p6440-pwm # 32-bit, S5P64x0 - - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs - - samsung,exynos4210-pwm # 32-bit, Exynos + oneOf: + - enum: + - samsung,s3c2410-pwm # 16-bit, S3C24xx + - samsung,s3c6400-pwm # 32-bit, S3C64xx + - samsung,s5p6440-pwm # 32-bit, S5P64x0 + - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs + - samsung,exynos4210-pwm # 32-bit, Exynos + - items: + - enum: + - samsung,exynosautov9-pwm + - const: samsung,exynos4210-pwm reg: maxItems: 1 diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index e4ed788413fe..d163891cd399 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -137,7 +137,6 @@ /* Receiver */ "RCV", "HPOUT3L", "RCV", "HPOUT3R"; - status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 5ea8bda2bfa6..54ed5167d0f6 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -138,10 +138,10 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x2000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; + reg = <0x11001000 0x1000>, + <0x11002000 0x2000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; }; pdma0: dma-controller@10e10000 { diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index 101f51bf565a..bc1815f6ada2 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -49,6 +49,12 @@ }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_tout3>; + status = "okay"; +}; + &serial_0 { pinctrl-0 = <&uart0_bus_dual>; status = "okay"; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index d3c5cdeff47f..b228cd7e351e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -313,7 +313,7 @@ }; }; - pinctrl_aud: pinctrl@19c60000{ + pinctrl_aud: pinctrl@19c60000 { compatible = "samsung,exynosautov9-pinctrl"; reg = <0x19c60000 0x1000>; }; @@ -1560,6 +1560,17 @@ samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; }; + + pwm: pwm@103f0000 { + compatible = "samsung,exynosautov9-pwm", + "samsung,exynos4210-pwm"; + reg = <0x103f0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&xtcxo>; + clock-names = "timers"; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 1c53c68efd53..bb50a9f7db4a 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -353,8 +353,8 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ - <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ + reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; |