diff options
| -rw-r--r-- | arch/arm64/boot/dts/arm/fvp-base-revc.dts | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 50b5993a2460..755b1407c4dc 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -44,6 +44,30 @@ #address-cells = <2>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + status = "disabled"; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + status = "disabled"; + }; + }; + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; @@ -56,6 +80,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@100 { device_type = "cpu"; @@ -69,6 +94,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@200 { device_type = "cpu"; @@ -82,6 +108,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu3: cpu@300 { device_type = "cpu"; @@ -95,6 +122,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C0_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu4: cpu@10000 { device_type = "cpu"; @@ -108,6 +136,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu5: cpu@10100 { device_type = "cpu"; @@ -121,6 +150,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu6: cpu@10200 { device_type = "cpu"; @@ -134,6 +164,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu7: cpu@10300 { device_type = "cpu"; @@ -147,6 +178,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&C1_L2>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; C0_L2: l2-cache0 { compatible = "cache"; |