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-rw-r--r--Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml86
1 files changed, 45 insertions, 41 deletions
diff --git a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml
index 3ea0e1290dbb..d5bd93ee4dbb 100644
--- a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml
+++ b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml
@@ -4,11 +4,12 @@
$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
+title: TI SoC Ethernet Switch Controller (CPSW)
maintainers:
- - Grygorii Strashko <grygorii.strashko@ti.com>
- - Sekhar Nori <nsekhar@ti.com>
+ - Siddharth Vadapalli <s-vadapalli@ti.com>
+ - Ravi Gunasekaran <r-gunasekaran@ti.com>
+ - Roger Quadros <rogerq@kernel.org>
description:
The 3-port switch gigabit ethernet subsystem provides ethernet packet
@@ -35,7 +36,7 @@ properties:
reg:
maxItems: 1
description:
- The physical base address and size of full the CPSW module IO range
+ The physical base address and size of full the CPSW module IO range
'#address-cells':
const: 1
@@ -62,21 +63,23 @@ properties:
interrupt-names:
items:
- - const: "rx_thresh"
- - const: "rx"
- - const: "tx"
- - const: "misc"
+ - const: rx_thresh
+ - const: rx
+ - const: tx
+ - const: misc
pinctrl-names: true
syscon:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the system control device node which provides access to
efuse IO range with MAC addresses
ethernet-ports:
type: object
+ additionalProperties: false
+
properties:
'#address-cells':
const: 1
@@ -84,40 +87,41 @@ properties:
const: 0
patternProperties:
- "^port@[0-9]+$":
- type: object
- description: CPSW external ports
-
- allOf:
- - $ref: ethernet-controller.yaml#
-
- properties:
- reg:
- items:
- - enum: [1, 2]
- description: CPSW port number
-
- phys:
- maxItems: 1
- description: phandle on phy-gmii-sel PHY
-
- label:
- description: label associated with this port
-
- ti,dual-emac-pvid:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 1
- maximum: 1024
- description:
- Specifies default PORT VID to be used to segregate
- ports. Default value - CPSW port number.
-
- required:
- - reg
- - phys
+ "^port@[12]$":
+ type: object
+ description: CPSW external ports
+
+ $ref: ethernet-controller.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ items:
+ - enum: [1, 2]
+ description: CPSW port number
+
+ phys:
+ maxItems: 1
+ description: phandle on phy-gmii-sel PHY
+
+ label:
+ description: label associated with this port
+
+ ti,dual-emac-pvid:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 1024
+ description:
+ Specifies default PORT VID to be used to segregate
+ ports. Default value - CPSW port number.
+
+ required:
+ - reg
+ - phys
cpts:
type: object
+ unevaluatedProperties: false
description:
The Common Platform Time Sync (CPTS) module
@@ -151,7 +155,7 @@ patternProperties:
type: object
description:
CPSW MDIO bus.
- $ref: "ti,davinci-mdio.yaml#"
+ $ref: ti,davinci-mdio.yaml#
required: