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-rw-r--r--arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts302
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diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
new file mode 100644
index 000000000000..2de047393652
--- /dev/null
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-DB Board
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/pcs-rzn1-miic.h>
+#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
+
+#include "r9a06g032.dtsi"
+
+/ {
+ model = "RZN1D-DB Board";
+ compatible = "renesas,rzn1d400-db", "renesas,r9a06g032";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ keyboard {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ switch-1 {
+ linux,code = <KEY_1>;
+ label = "SW1-1";
+ debounce-interval = <20>;
+ gpios = <&pca9698 8 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-2 {
+ linux,code = <KEY_2>;
+ label = "SW1-2";
+ debounce-interval = <20>;
+ gpios = <&pca9698 9 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-3 {
+ linux,code = <KEY_3>;
+ label = "SW1-3";
+ debounce-interval = <20>;
+ gpios = <&pca9698 10 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-4 {
+ linux,code = <KEY_4>;
+ label = "SW1-4";
+ debounce-interval = <20>;
+ gpios = <&pca9698 11 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-5 {
+ linux,code = <KEY_5>;
+ label = "SW1-5";
+ debounce-interval = <20>;
+ gpios = <&pca9698 12 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-6 {
+ linux,code = <KEY_6>;
+ label = "SW1-6";
+ debounce-interval = <20>;
+ gpios = <&pca9698 13 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-7 {
+ linux,code = <KEY_7>;
+ label = "SW1-7";
+ debounce-interval = <20>;
+ gpios = <&pca9698 14 GPIO_ACTIVE_LOW>;
+ };
+
+ switch-8 {
+ linux,code = <KEY_8>;
+ label = "SW1-8";
+ debounce-interval = <20>;
+ gpios = <&pca9698 15 GPIO_ACTIVE_LOW>;
+ };
+
+ };
+};
+
+&can0 {
+ pinctrl-0 = <&pins_can0>;
+ pinctrl-names = "default";
+
+ /* Assuming CN10/CN11 are wired for CAN1 */
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-0 = <&pins_can1>;
+ pinctrl-names = "default";
+
+ /* Please only enable can0 or can1, depending on CN10/CN11 */
+ /* status = "okay"; */
+};
+
+&eth_miic {
+ status = "okay";
+ renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "gmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&pins_i2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pca9698: gpio@20 {
+ compatible = "nxp,pca9698";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ /* configure the analog switch to let i2c2 access the eeprom */
+ max4662-in1-hog {
+ gpio-hog;
+ gpios = <16 0>;
+ output-high;
+ };
+ max4662-in2-hog {
+ gpio-hog;
+ gpios = <17 0>;
+ output-low;
+ };
+ max4662-in3-hog {
+ gpio-hog;
+ gpios = <18 0>;
+ output-low;
+ };
+ };
+
+ /* Some revisions may have a 24cs64 at address 0x58 */
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ pagesize = <32>;
+ reg = <0x50>;
+ };
+};
+
+&mii_conv4 {
+ renesas,miic-input = <MIIC_SWITCH_PORTB>;
+ status = "okay";
+};
+
+&mii_conv5 {
+ renesas,miic-input = <MIIC_SWITCH_PORTA>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_cpld>;
+
+ pins_can0: pins_can0 {
+ pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */
+ <RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */
+ drive-strength = <6>;
+ };
+
+ pins_can1: pins_can1 {
+ pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>, /* CAN1_TXD */
+ <RZN1_PINMUX(110, RZN1_FUNC_CAN)>; /* CAN1_RXD */
+ drive-strength = <6>;
+ };
+
+ pins_cpld: pins-cpld {
+ pinmux = <RZN1_PINMUX(119, RZN1_FUNC_USB)>,
+ <RZN1_PINMUX(120, RZN1_FUNC_USB)>,
+ <RZN1_PINMUX(121, RZN1_FUNC_USB)>,
+ <RZN1_PINMUX(122, RZN1_FUNC_USB)>;
+ };
+
+ pins_eth3: pins_eth3 {
+ pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ pins_eth4: pins_eth4 {
+ pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ pins_i2c2: pins_i2c2 {
+ pinmux = <RZN1_PINMUX(115, RZN1_FUNC_I2C)>,
+ <RZN1_PINMUX(116, RZN1_FUNC_I2C)>;
+ drive-strength = <12>;
+ };
+
+ pins_mdio1: pins_mdio1 {
+ pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
+ <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
+ };
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;
+
+ dsa,member = <0 0>;
+
+ mdio {
+ clock-frequency = <2500000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy4: ethernet-phy@4 {
+ reg = <4>;
+ micrel,led-mode = <1>;
+ };
+
+ switch0phy5: ethernet-phy@5 {
+ reg = <5>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
+&switch_port0 {
+ label = "lan0";
+ phy-mode = "mii";
+ phy-handle = <&switch0phy5>;
+ status = "okay";
+};
+
+&switch_port1 {
+ label = "lan1";
+ phy-mode = "mii";
+ phy-handle = <&switch0phy4>;
+ status = "okay";
+};
+
+&switch_port4 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&udc {
+ status = "okay";
+};
+
+&wdt0 {
+ timeout-sec = <60>;
+ status = "okay";
+};
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.