diff options
Diffstat (limited to 'arch/mips/pci')
27 files changed, 69 insertions, 893 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index ed0388485a15..a6e9785b537e 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_PCI_DRIVERS_GENERIC)+= pci-generic.o obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o -obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ @@ -42,14 +41,9 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o -obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o -obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o -obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o -obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o -obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o diff --git a/arch/mips/pci/fixup-ath79.c b/arch/mips/pci/fixup-ath79.c index 09a4ce53424f..6a6c4f58f7f4 100644 --- a/arch/mips/pci/fixup-ath79.c +++ b/arch/mips/pci/fixup-ath79.c @@ -9,7 +9,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) { - return PCIBIOS_SUCCESSFUL; + return 0; } int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) diff --git a/arch/mips/pci/fixup-capcella.c b/arch/mips/pci/fixup-capcella.c deleted file mode 100644 index dc8cd98a1761..000000000000 --- a/arch/mips/pci/fixup-capcella.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * fixup-cappcela.c, The ZAO Networks Capcella specific PCI fixups. - * - * Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org> - */ -#include <linux/init.h> -#include <linux/pci.h> - -#include <asm/vr41xx/capcella.h> - -/* - * Shortcuts - */ -#define INT1 RTL8139_1_IRQ -#define INT2 RTL8139_2_IRQ -#define INTA PC104PLUS_INTA_IRQ -#define INTB PC104PLUS_INTB_IRQ -#define INTC PC104PLUS_INTC_IRQ -#define INTD PC104PLUS_INTD_IRQ - -static char irq_tab_capcella[][5] = { - [11] = { -1, INT1, INT1, INT1, INT1 }, - [12] = { -1, INT2, INT2, INT2, INT2 }, - [14] = { -1, INTA, INTB, INTC, INTD } -}; - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_tab_capcella[slot][pin]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-lantiq.c b/arch/mips/pci/fixup-lantiq.c index 105569c1b712..8bcc136976dc 100644 --- a/arch/mips/pci/fixup-lantiq.c +++ b/arch/mips/pci/fixup-lantiq.c @@ -4,20 +4,11 @@ * Copyright (C) 2012 John Crispin <john@phrozen.org> */ -#include <linux/of_irq.h> #include <linux/of_pci.h> - -int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; -int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; +#include <linux/pci.h> int pcibios_plat_dev_init(struct pci_dev *dev) { - if (ltq_pci_plat_arch_init) - return ltq_pci_plat_arch_init(dev); - - if (ltq_pci_plat_dev_init) - return ltq_pci_plat_dev_init(dev); - return 0; } diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c index 632ff2daa338..afafda03ed4e 100644 --- a/arch/mips/pci/fixup-lemote2f.c +++ b/arch/mips/pci/fixup-lemote2f.c @@ -80,7 +80,7 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } return dev->irq; } else { - printk(KERN_INFO " strange pci slot number.\n"); + printk(KERN_INFO "strange PCI slot number.\n"); return 0; } } diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c deleted file mode 100644 index 27c75f268c4c..000000000000 --- a/arch/mips/pci/fixup-mpc30x.c +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * fixup-mpc30x.c, The Victor MP-C303/304 specific PCI fixups. - * - * Copyright (C) 2002,2004 Yoichi Yuasa <yuasa@linux-mips.org> - */ -#include <linux/init.h> -#include <linux/pci.h> - -#include <asm/vr41xx/mpc30x.h> - -static const int internal_func_irqs[] = { - VRC4173_CASCADE_IRQ, - VRC4173_AC97_IRQ, - VRC4173_USB_IRQ, -}; - -static const int irq_tab_mpc30x[] = { - [12] = VRC4173_PCMCIA1_IRQ, - [13] = VRC4173_PCMCIA2_IRQ, - [29] = MQ200_IRQ, -}; - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - if (slot == 30) - return internal_func_irqs[PCI_FUNC(dev->devfn)]; - - return irq_tab_mpc30x[slot]; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c deleted file mode 100644 index 43942998599b..000000000000 --- a/arch/mips/pci/fixup-tb0219.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups. - * - * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp> - * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org> - */ -#include <linux/init.h> -#include <linux/pci.h> - -#include <asm/vr41xx/tb0219.h> - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = -1; - - switch (slot) { - case 12: - irq = TB0219_PCI_SLOT1_IRQ; - break; - case 13: - irq = TB0219_PCI_SLOT2_IRQ; - break; - case 14: - irq = TB0219_PCI_SLOT3_IRQ; - break; - default: - break; - } - - return irq; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c deleted file mode 100644 index a4d1efadfd4a..000000000000 --- a/arch/mips/pci/fixup-tb0226.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups. - * - * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@linux-mips.org> - */ -#include <linux/init.h> -#include <linux/pci.h> - -#include <asm/vr41xx/giu.h> -#include <asm/vr41xx/tb0226.h> - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = -1; - - switch (slot) { - case 12: - vr41xx_set_irq_trigger(GD82559_1_PIN, - IRQ_TRIGGER_LEVEL, - IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW); - irq = GD82559_1_IRQ; - break; - case 13: - vr41xx_set_irq_trigger(GD82559_2_PIN, - IRQ_TRIGGER_LEVEL, - IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW); - irq = GD82559_2_IRQ; - break; - case 14: - switch (pin) { - case 1: - vr41xx_set_irq_trigger(UPD720100_INTA_PIN, - IRQ_TRIGGER_LEVEL, - IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(UPD720100_INTA_PIN, - IRQ_LEVEL_LOW); - irq = UPD720100_INTA_IRQ; - break; - case 2: - vr41xx_set_irq_trigger(UPD720100_INTB_PIN, - IRQ_TRIGGER_LEVEL, - IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(UPD720100_INTB_PIN, - IRQ_LEVEL_LOW); - irq = UPD720100_INTB_IRQ; - break; - case 3: - vr41xx_set_irq_trigger(UPD720100_INTC_PIN, - IRQ_TRIGGER_LEVEL, - IRQ_SIGNAL_THROUGH); - vr41xx_set_irq_level(UPD720100_INTC_PIN, - IRQ_LEVEL_LOW); - irq = UPD720100_INTC_IRQ; - break; - default: - break; - } - break; - default: - break; - } - - return irq; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c deleted file mode 100644 index 721ec9ac1c76..000000000000 --- a/arch/mips/pci/fixup-tb0287.c +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups. - * - * Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org> - */ -#include <linux/init.h> -#include <linux/pci.h> - -#include <asm/vr41xx/tb0287.h> - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - unsigned char bus; - int irq = -1; - - bus = dev->bus->number; - if (bus == 0) { - switch (slot) { - case 16: - irq = TB0287_SM501_IRQ; - break; - case 17: - irq = TB0287_SIL680A_IRQ; - break; - default: - break; - } - } else if (bus == 1) { - switch (PCI_SLOT(dev->devfn)) { - case 0: - irq = TB0287_PCI_SLOT_IRQ; - break; - case 2: - case 3: - irq = TB0287_RTL8110_IRQ; - break; - default: - break; - } - } else if (bus > 1) { - irq = TB0287_PCI_SLOT_IRQ; - } - - return irq; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index c2860ebbd863..abc3b61bff9f 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c @@ -46,16 +46,17 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); static int msi_irq_size; /** - * Called when a driver request MSI interrupts instead of the + * arch_setup_msi_irq() - setup MSI IRQs for a device + * @dev: Device requesting MSI interrupts + * @desc: MSI descriptor + * + * Called when a driver requests MSI interrupts instead of the * legacy INT A-D. This routine will allocate multiple interrupts * for MSI devices that support them. A device can override this by * programming the MSI control bits [6:4] before calling * pci_enable_msi(). * - * @dev: Device requesting MSI interrupts - * @desc: MSI descriptor - * - * Returns 0 on success. + * Return: %0 on success, non-%0 on error. */ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) { @@ -186,10 +187,11 @@ msi_irq_allocated: } /** + * arch_teardown_msi_irq() - release MSI IRQs for a device + * @irq: The devices first irq number. There may be multiple in sequence. + * * Called when a device no longer needs its MSI interrupts. All * MSI interrupts for the device are freed. - * - * @irq: The devices first irq number. There may be multple in sequence. */ void arch_teardown_msi_irq(unsigned int irq) { diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c index dc6dc2741272..b0ea023c47c0 100644 --- a/arch/mips/pci/ops-bcm63xx.c +++ b/arch/mips/pci/ops-bcm63xx.c @@ -413,18 +413,18 @@ struct pci_ops bcm63xx_cb_ops = { static void bcm63xx_fixup(struct pci_dev *dev) { static int io_window = -1; - int i, found, new_io_window; + int found, new_io_window; + struct resource *r; u32 val; /* look for any io resource */ found = 0; - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - if (pci_resource_flags(dev, i) & IORESOURCE_IO) { + pci_dev_for_each_resource(dev, r) { + if (resource_type(r) == IORESOURCE_IO) { found = 1; break; } } - if (!found) return; diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c index 0d1b36ba1c21..068113f5c49d 100644 --- a/arch/mips/pci/ops-loongson2.c +++ b/arch/mips/pci/ops-loongson2.c @@ -49,7 +49,7 @@ static int loongson_pcibios_config_access(unsigned char access_type, */ #ifdef CONFIG_CS5536 /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to - * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO, + * access the registers PCI_MSR_ADDR, PCI_MSR_DATA_LO, * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it * will not go this branch, but the others. so, no calling dead * loop here. diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index f7802f100401..37087f4137ee 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -60,7 +60,7 @@ static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, { if (bus->parent == NULL && devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) - return -1; + return PCIBIOS_DEVICE_NOT_FOUND; __raw_writel(((bus->number & 0xff) << 0x10) | ((devfn & 0xff) << 0x08) | (where & 0xfc) | (bus->parent ? 1 : 0), @@ -69,7 +69,7 @@ static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT << 16), &pcicptr->pcistatus); - return 0; + return PCIBIOS_SUCCESSFUL; } static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) @@ -140,10 +140,12 @@ static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); + int ret; - if (mkaddr(bus, devfn, where, pcicptr)) { - *val = 0xffffffff; - return -1; + ret = mkaddr(bus, devfn, where, pcicptr); + if (ret != PCIBIOS_SUCCESSFUL) { + PCI_SET_ERROR_RESPONSE(val); + return ret; } switch (size) { case 1: @@ -162,9 +164,11 @@ static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); + int ret; - if (mkaddr(bus, devfn, where, pcicptr)) - return -1; + ret = mkaddr(bus, devfn, where, pcicptr); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; switch (size) { case 1: icd_writeb(val, where & 3, pcicptr); diff --git a/arch/mips/pci/ops-vr41xx.c b/arch/mips/pci/ops-vr41xx.c deleted file mode 100644 index 7b7709aa14c7..000000000000 --- a/arch/mips/pci/ops-vr41xx.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series. - * - * Copyright (C) 2001-2003 MontaVista Software Inc. - * Author: Yoichi Yuasa <source@mvista.com> - * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org> - */ -/* - * Changes: - * MontaVista Software Inc. <source@mvista.com> - * - New creation, NEC VR4122 and VR4131 are supported. - */ -#include <linux/pci.h> -#include <linux/types.h> - -#include <asm/io.h> - -#define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14) -#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18) - -static inline int set_pci_configuration_address(unsigned char number, - unsigned int devfn, int where) -{ - if (number == 0) { - /* - * Type 0 configuration - */ - if (PCI_SLOT(devfn) < 11 || where > 0xff) - return -EINVAL; - - writel((1U << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) | - (where & 0xfc), PCICONFAREG); - } else { - /* - * Type 1 configuration - */ - if (where > 0xff) - return -EINVAL; - - writel(((uint32_t)number << 16) | ((devfn & 0xff) << 8) | - (where & 0xfc) | 1U, PCICONFAREG); - } - - return 0; -} - -static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t *val) -{ - uint32_t data; - - *val = 0xffffffffU; - if (set_pci_configuration_address(bus->number, devfn, where) < 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - data = readl(PCICONFDREG); - - switch (size) { - case 1: - *val = (data >> ((where & 3) << 3)) & 0xffU; - break; - case 2: - *val = (data >> ((where & 2) << 3)) & 0xffffU; - break; - case 4: - *val = data; - break; - default: - return PCIBIOS_FUNC_NOT_SUPPORTED; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, uint32_t val) -{ - uint32_t data; - int shift; - - if (set_pci_configuration_address(bus->number, devfn, where) < 0) - return PCIBIOS_DEVICE_NOT_FOUND; - - data = readl(PCICONFDREG); - - switch (size) { - case 1: - shift = (where & 3) << 3; - data &= ~(0xffU << shift); - data |= ((val & 0xffU) << shift); - break; - case 2: - shift = (where & 2) << 3; - data &= ~(0xffffU << shift); - data |= ((val & 0xffffU) << shift); - break; - case 4: - data = val; - break; - default: - return PCIBIOS_FUNC_NOT_SUPPORTED; - } - - writel(data, PCICONFDREG); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops vr41xx_pci_ops = { - .read = pci_config_read, - .write = pci_config_write, -}; diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index 1c722dd0c130..58625d1b6465 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -453,7 +453,7 @@ static int alchemy_pci_probe(struct platform_device *pdev) /* we can't ioremap the entire pci config space because it's too large, * nor can we dynamically ioremap it because some drivers use the - * PCI config routines from within atomic contex and that becomes a + * PCI config routines from within atomic context and that becomes a * problem in get_vm_area(). Instead we use one wired TLB entry to * handle all config accesses for all busses. */ diff --git a/arch/mips/pci/pci-ar2315.c b/arch/mips/pci/pci-ar2315.c index 30e0922f4cea..a925842ee125 100644 --- a/arch/mips/pci/pci-ar2315.c +++ b/arch/mips/pci/pci-ar2315.c @@ -2,7 +2,7 @@ /* */ -/** +/* * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA * and interrupt. PCI interface supports MMIO access method, but does not * seem to support I/O ports. @@ -16,7 +16,7 @@ * the CFG_SEL bit in the PCI_MISC_CONFIG register. * * Devices on the bus can perform DMA requests via chip BAR1. PCI host - * controller BARs are programmend as if an external device is programmed. + * controller BARs are programmed as if an external device is programmed. * Which means that during configuration, IDSEL pin of the chip should be * asserted. * diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index d85cbf84e41c..973faea61cad 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -7,6 +7,9 @@ * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ + +#include <linux/io.h> + #include <asm/sn/addrs.h> #include <asm/sn/types.h> #include <asm/sn/klconfig.h> diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index 1ca42f482130..68a8cefed420 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -9,13 +9,13 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/delay.h> +#include <linux/gpio/consumer.h> #include <linux/mm.h> #include <linux/vmalloc.h> #include <linux/clk.h> -#include <linux/of_platform.h> -#include <linux/of_gpio.h> -#include <linux/of_irq.h> +#include <linux/of.h> #include <linux/of_pci.h> +#include <linux/platform_device.h> #include <asm/addrspace.h> @@ -62,7 +62,7 @@ __iomem void *ltq_pci_mapped_cfg; static __iomem void *ltq_pci_membase; -static int reset_gpio; +static struct gpio_desc *reset_gpio; static struct clk *clk_pci, *clk_external; static struct resource pci_io_resource; static struct resource pci_mem_resource; @@ -95,6 +95,7 @@ static int ltq_pci_startup(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; const __be32 *req_mask, *bus_clk; u32 temp_buffer; + int error; /* get our clocks */ clk_pci = clk_get(&pdev->dev, NULL); @@ -117,23 +118,20 @@ static int ltq_pci_startup(struct platform_device *pdev) /* and enable the clocks */ clk_enable(clk_pci); - if (of_find_property(node, "lantiq,external-clock", NULL)) + if (of_property_read_bool(node, "lantiq,external-clock")) clk_enable(clk_external); else clk_disable(clk_external); /* setup reset gpio used by pci */ - reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); - if (gpio_is_valid(reset_gpio)) { - int ret = devm_gpio_request(&pdev->dev, - reset_gpio, "pci-reset"); - if (ret) { - dev_err(&pdev->dev, - "failed to request gpio %d\n", reset_gpio); - return ret; - } - gpio_direction_output(reset_gpio, 1); + reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", + GPIOD_OUT_LOW); + error = PTR_ERR_OR_ZERO(reset_gpio); + if (error) { + dev_err(&pdev->dev, "failed to request gpio: %d\n", error); + return error; } + gpiod_set_consumer_name(reset_gpio, "pci_reset"); /* enable auto-switching between PCI and EBU */ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); @@ -154,7 +152,7 @@ static int ltq_pci_startup(struct platform_device *pdev) temp_buffer &= ~0xf0000; /* enable internal arbiter */ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); - /* enable internal PCI master reqest */ + /* enable internal PCI master request */ temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); /* enable EBU request */ @@ -195,28 +193,24 @@ static int ltq_pci_startup(struct platform_device *pdev) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); /* toggle reset pin */ - if (gpio_is_valid(reset_gpio)) { - __gpio_set_value(reset_gpio, 0); + if (reset_gpio) { + gpiod_set_value_cansleep(reset_gpio, 1); wmb(); mdelay(1); - __gpio_set_value(reset_gpio, 1); + gpiod_set_value_cansleep(reset_gpio, 0); } return 0; } static int ltq_pci_probe(struct platform_device *pdev) { - struct resource *res_cfg, *res_bridge; - pci_clear_flags(PCI_PROBE_ONLY); - res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1); - ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge); + ltq_pci_membase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); if (IS_ERR(ltq_pci_membase)) return PTR_ERR(ltq_pci_membase); - res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg); + ltq_pci_mapped_cfg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(ltq_pci_mapped_cfg)) return PTR_ERR(ltq_pci_mapped_cfg); diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c index 468722c8a5c6..ec2567f8efd8 100644 --- a/arch/mips/pci/pci-legacy.c +++ b/arch/mips/pci/pci-legacy.c @@ -249,12 +249,11 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask) pci_read_config_word(dev, PCI_COMMAND, &cmd); old_cmd = cmd; - for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) { + pci_dev_for_each_resource(dev, r, idx) { /* Only set up the requested stuff */ if (!(mask & (1<<idx))) continue; - r = &dev->resource[idx]; if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) continue; if ((idx == PCI_ROM_RESOURCE) && diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c index e032932348d6..5c4bdf6919e5 100644 --- a/arch/mips/pci/pci-mt7620.c +++ b/arch/mips/pci/pci-mt7620.c @@ -274,29 +274,22 @@ static int mt7628_pci_hw_init(struct platform_device *pdev) val |= 0x50 << 8; pci_config_write(NULL, 0, 0x70c, 4, val); - pci_config_read(NULL, 0, 0x70c, 4, &val); - dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val); - return 0; } static int mt7620_pci_probe(struct platform_device *pdev) { - struct resource *bridge_res = platform_get_resource(pdev, - IORESOURCE_MEM, 0); - struct resource *pcie_res = platform_get_resource(pdev, - IORESOURCE_MEM, 1); u32 val = 0; rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0"); if (IS_ERR(rstpcie0)) return PTR_ERR(rstpcie0); - bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res); + bridge_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(bridge_base)) return PTR_ERR(bridge_base); - pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res); + pcie_base = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); if (IS_ERR(pcie_base)) return PTR_ERR(pcie_base); @@ -334,7 +327,7 @@ static int mt7620_pci_probe(struct platform_device *pdev) rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); if (ralink_soc == MT762X_SOC_MT7620A) rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV); - dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n"); + dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n"); return -1; } @@ -377,7 +370,7 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) dev->bus->number, slot); return 0; } - dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", + dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n", dev->bus->number, slot, irq); /* configure the cache line size to 0x14 */ diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index e457a18cbdc5..36d12cea3512 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -376,7 +376,7 @@ static void octeon_pci_initialize(void) ctl_status.s.timer = 1; cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); - /* Deassert PCI reset and advertize PCX Host Mode Device Capability + /* Deassert PCI reset and advertise PCX Host Mode Device Capability (64b) */ cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); cvmx_read_csr(CVMX_CIU_SOFT_PRST); @@ -664,7 +664,7 @@ static int __init octeon_pci_setup(void) /* BAR1 movable regions contiguous to cover the swiotlb */ octeon_bar1_pci_phys = - io_tlb_default_mem.start & ~((1ull << 22) - 1); + default_swiotlb_base() & ~((1ull << 22) - 1); for (index = 0; index < 32; index++) { union cvmx_pci_bar1_indexx bar1_index; diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c index e9dd01431f21..1cada09fa5db 100644 --- a/arch/mips/pci/pci-rt2880.c +++ b/arch/mips/pci/pci-rt2880.c @@ -13,9 +13,8 @@ #include <linux/pci.h> #include <linux/io.h> #include <linux/init.h> -#include <linux/of_platform.h> -#include <linux/of_irq.h> -#include <linux/of_pci.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <asm/mach-ralink/rt288x.h> diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c index e07ae098bdd8..4ac68a534e4f 100644 --- a/arch/mips/pci/pci-rt3883.c +++ b/arch/mips/pci/pci-rt3883.c @@ -404,7 +404,6 @@ static int rt3883_pci_probe(struct platform_device *pdev) struct rt3883_pci_controller *rpc; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - struct resource *res; struct device_node *child; u32 val; int err; @@ -414,14 +413,13 @@ static int rt3883_pci_probe(struct platform_device *pdev) if (!rpc) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rpc->base = devm_ioremap_resource(dev, res); + rpc->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rpc->base)) return PTR_ERR(rpc->base); /* find the interrupt controller child node */ for_each_child_of_node(np, child) { - if (of_get_property(child, "interrupt-controller", NULL)) { + if (of_property_read_bool(child, "interrupt-controller")) { rpc->intc_of_node = child; break; } diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c deleted file mode 100644 index 4f250c55b6e6..000000000000 --- a/arch/mips/pci/pci-vr41xx.c +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series. - * - * Copyright (C) 2001-2003 MontaVista Software Inc. - * Author: Yoichi Yuasa <source@mvista.com> - * Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org> - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - */ -/* - * Changes: - * MontaVista Software Inc. <source@mvista.com> - * - New creation, NEC VR4122 and VR4131 are supported. - */ -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/types.h> - -#include <asm/cpu.h> -#include <asm/io.h> -#include <asm/vr41xx/pci.h> -#include <asm/vr41xx/vr41xx.h> - -#include "pci-vr41xx.h" - -extern struct pci_ops vr41xx_pci_ops; - -static void __iomem *pciu_base; - -#define pciu_read(offset) readl(pciu_base + (offset)) -#define pciu_write(offset, value) writel((value), pciu_base + (offset)) - -static struct pci_master_address_conversion pci_master_memory1 = { - .bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS, - .address_mask = PCI_MASTER_MEM1_ADDRESS_MASK, - .pci_base_address = PCI_MASTER_MEM1_PCI_BASE_ADDRESS, -}; - -static struct pci_target_address_conversion pci_target_memory1 = { - .address_mask = PCI_TARGET_MEM1_ADDRESS_MASK, - .bus_base_address = PCI_TARGET_MEM1_BUS_BASE_ADDRESS, -}; - -static struct pci_master_address_conversion pci_master_io = { - .bus_base_address = PCI_MASTER_IO_BUS_BASE_ADDRESS, - .address_mask = PCI_MASTER_IO_ADDRESS_MASK, - .pci_base_address = PCI_MASTER_IO_PCI_BASE_ADDRESS, -}; - -static struct pci_mailbox_address pci_mailbox = { - .base_address = PCI_MAILBOX_BASE_ADDRESS, -}; - -static struct pci_target_address_window pci_target_window1 = { - .base_address = PCI_TARGET_WINDOW1_BASE_ADDRESS, -}; - -static struct resource pci_mem_resource = { - .name = "PCI Memory resources", - .start = PCI_MEM_RESOURCE_START, - .end = PCI_MEM_RESOURCE_END, - .flags = IORESOURCE_MEM, -}; - -static struct resource pci_io_resource = { - .name = "PCI I/O resources", - .start = PCI_IO_RESOURCE_START, - .end = PCI_IO_RESOURCE_END, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { - .master_memory1 = &pci_master_memory1, - .target_memory1 = &pci_target_memory1, - .master_io = &pci_master_io, - .exclusive_access = CANNOT_LOCK_FROM_DEVICE, - .wait_time_limit_from_irdy_to_trdy = 0, - .mailbox = &pci_mailbox, - .target_window1 = &pci_target_window1, - .master_latency_timer = 0x80, - .retry_limit = 0, - .arbiter_priority_control = PCI_ARBITRATION_MODE_FAIR, - .take_away_gnt_mode = PCI_TAKE_AWAY_GNT_DISABLE, -}; - -static struct pci_controller vr41xx_pci_controller = { - .pci_ops = &vr41xx_pci_ops, - .mem_resource = &pci_mem_resource, - .io_resource = &pci_io_resource, -}; - -void __init vr41xx_pciu_setup(struct pci_controller_unit_setup *setup) -{ - vr41xx_pci_controller_unit_setup = *setup; -} - -static int __init vr41xx_pciu_init(void) -{ - struct pci_controller_unit_setup *setup; - struct pci_master_address_conversion *master; - struct pci_target_address_conversion *target; - struct pci_mailbox_address *mailbox; - struct pci_target_address_window *window; - unsigned long vtclock, pci_clock_max; - uint32_t val; - - setup = &vr41xx_pci_controller_unit_setup; - - if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL) - return -EBUSY; - - pciu_base = ioremap(PCIU_BASE, PCIU_SIZE); - if (pciu_base == NULL) { - release_mem_region(PCIU_BASE, PCIU_SIZE); - return -EBUSY; - } - - /* Disable PCI interrupt */ - vr41xx_disable_pciint(); - - /* Supply VTClock to PCIU */ - vr41xx_supply_clock(PCIU_CLOCK); - - /* Dummy write, waiting for supply of VTClock. */ - vr41xx_disable_pciint(); - - /* Select PCI clock */ - if (setup->pci_clock_max != 0) - pci_clock_max = setup->pci_clock_max; - else - pci_clock_max = PCI_CLOCK_MAX; - vtclock = vr41xx_get_vtclock_frequency(); - if (vtclock < pci_clock_max) - pciu_write(PCICLKSELREG, EQUAL_VTCLOCK); - else if ((vtclock / 2) < pci_clock_max) - pciu_write(PCICLKSELREG, HALF_VTCLOCK); - else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 && - (vtclock / 3) < pci_clock_max) - pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK); - else if ((vtclock / 4) < pci_clock_max) - pciu_write(PCICLKSELREG, QUARTER_VTCLOCK); - else { - printk(KERN_ERR "PCI Clock is over 33MHz.\n"); - iounmap(pciu_base); - return -EINVAL; - } - - /* Supply PCI clock by PCI bus */ - vr41xx_supply_clock(PCI_CLOCK); - - if (setup->master_memory1 != NULL) { - master = setup->master_memory1; - val = IBA(master->bus_base_address) | - MASTER_MSK(master->address_mask) | - WINEN | - PCIA(master->pci_base_address); - pciu_write(PCIMMAW1REG, val); - } else { - val = pciu_read(PCIMMAW1REG); - val &= ~WINEN; - pciu_write(PCIMMAW1REG, val); - } - - if (setup->master_memory2 != NULL) { - master = setup->master_memory2; - val = IBA(master->bus_base_address) | - MASTER_MSK(master->address_mask) | - WINEN | - PCIA(master->pci_base_address); - pciu_write(PCIMMAW2REG, val); - } else { - val = pciu_read(PCIMMAW2REG); - val &= ~WINEN; - pciu_write(PCIMMAW2REG, val); - } - - if (setup->target_memory1 != NULL) { - target = setup->target_memory1; - val = TARGET_MSK(target->address_mask) | - WINEN | - ITA(target->bus_base_address); - pciu_write(PCITAW1REG, val); - } else { - val = pciu_read(PCITAW1REG); - val &= ~WINEN; - pciu_write(PCITAW1REG, val); - } - - if (setup->target_memory2 != NULL) { - target = setup->target_memory2; - val = TARGET_MSK(target->address_mask) | - WINEN | - ITA(target->bus_base_address); - pciu_write(PCITAW2REG, val); - } else { - val = pciu_read(PCITAW2REG); - val &= ~WINEN; - pciu_write(PCITAW2REG, val); - } - - if (setup->master_io != NULL) { - master = setup->master_io; - val = IBA(master->bus_base_address) | - MASTER_MSK(master->address_mask) | - WINEN | - PCIIA(master->pci_base_address); - pciu_write(PCIMIOAWREG, val); - } else { - val = pciu_read(PCIMIOAWREG); - val &= ~WINEN; - pciu_write(PCIMIOAWREG, val); - } - - if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE) - pciu_write(PCIEXACCREG, UNLOCK); - else - pciu_write(PCIEXACCREG, 0); - - if (current_cpu_type() == CPU_VR4122) - pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy)); - - pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer)); - - if (setup->mailbox != NULL) { - mailbox = setup->mailbox; - val = MBADD(mailbox->base_address) | TYPE_32BITSPACE | - MSI_MEMORY | PREF_APPROVAL; - pciu_write(MAILBAREG, val); - } - - if (setup->target_window1) { - window = setup->target_window1; - val = PMBA(window->base_address) | TYPE_32BITSPACE | - MSI_MEMORY | PREF_APPROVAL; - pciu_write(PCIMBA1REG, val); - } - - if (setup->target_window2) { - window = setup->target_window2; - val = PMBA(window->base_address) | TYPE_32BITSPACE | - MSI_MEMORY | PREF_APPROVAL; - pciu_write(PCIMBA2REG, val); - } - - val = pciu_read(RETVALREG); - val &= ~RTYVAL_MASK; - val |= RTYVAL(setup->retry_limit); - pciu_write(RETVALREG, val); - - val = pciu_read(PCIAPCNTREG); - val &= ~(TKYGNT | PAPC); - - switch (setup->arbiter_priority_control) { - case PCI_ARBITRATION_MODE_ALTERNATE_0: - val |= PAPC_ALTERNATE_0; - break; - case PCI_ARBITRATION_MODE_ALTERNATE_B: - val |= PAPC_ALTERNATE_B; - break; - default: - val |= PAPC_FAIR; - break; - } - - if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE) - val |= TKYGNT_ENABLE; - - pciu_write(PCIAPCNTREG, val); - - pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | - PCI_COMMAND_SERR); - - /* Clear bus error */ - pciu_read(BUSERRADREG); - - pciu_write(PCIENREG, PCIU_CONFIG_DONE); - - if (setup->mem_resource != NULL) - vr41xx_pci_controller.mem_resource = setup->mem_resource; - - if (setup->io_resource != NULL) { - vr41xx_pci_controller.io_resource = setup->io_resource; - } else { - set_io_port_base(IO_PORT_BASE); - ioport_resource.start = IO_PORT_RESOURCE_START; - ioport_resource.end = IO_PORT_RESOURCE_END; - } - - if (setup->master_io) { - void __iomem *io_map_base; - struct resource *res = vr41xx_pci_controller.io_resource; - master = setup->master_io; - io_map_base = ioremap(master->bus_base_address, - resource_size(res)); - if (!io_map_base) { - iounmap(pciu_base); - return -EBUSY; - } - - vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base; - } - - register_pci_controller(&vr41xx_pci_controller); - - return 0; -} - -arch_initcall(vr41xx_pciu_init); diff --git a/arch/mips/pci/pci-vr41xx.h b/arch/mips/pci/pci-vr41xx.h deleted file mode 100644 index 5595e4a39b2a..000000000000 --- a/arch/mips/pci/pci-vr41xx.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series. - * - * Copyright (C) 2002 MontaVista Software Inc. - * Author: Yoichi Yuasa <source@mvista.com> - * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org> - */ -#ifndef __PCI_VR41XX_H -#define __PCI_VR41XX_H - -#define PCIU_BASE 0x0f000c00UL -#define PCIU_SIZE 0x200UL - -#define PCIMMAW1REG 0x00 -#define PCIMMAW2REG 0x04 -#define PCITAW1REG 0x08 -#define PCITAW2REG 0x0c -#define PCIMIOAWREG 0x10 - #define IBA(addr) ((addr) & 0xff000000U) - #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U) - #define PCIA(addr) (((addr) >> 24) & 0x000000ffU) - #define TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U) - #define ITA(addr) (((addr) >> 24) & 0x000000ffU) - #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU) - #define WINEN 0x1000U -#define PCICONFDREG 0x14 -#define PCICONFAREG 0x18 -#define PCIMAILREG 0x1c -#define BUSERRADREG 0x24 - #define EA(reg) ((reg) &0xfffffffc) - -#define INTCNTSTAREG 0x28 - #define MABTCLR 0x80000000U - #define TRDYCLR 0x40000000U - #define PARCLR 0x20000000U - #define MBCLR 0x10000000U - #define SERRCLR 0x08000000U - #define RTYCLR 0x04000000U - #define MABCLR 0x02000000U - #define TABCLR 0x01000000U - /* RFU */ - #define MABTMSK 0x00008000U - #define TRDYMSK 0x00004000U - #define PARMSK 0x00002000U - #define MBMSK 0x00001000U - #define SERRMSK 0x00000800U - #define RTYMSK 0x00000400U - #define MABMSK 0x00000200U - #define TABMSK 0x00000100U - #define IBAMABT 0x00000080U - #define TRDYRCH 0x00000040U - #define PAR 0x00000020U - #define MB 0x00000010U - #define PCISERR 0x00000008U - #define RTYRCH 0x00000004U - #define MABORT 0x00000002U - #define TABORT 0x00000001U - -#define PCIEXACCREG 0x2c - #define UNLOCK 0x2U - #define EAREQ 0x1U -#define PCIRECONTREG 0x30 - #define RTRYCNT(reg) ((reg) & 0x000000ffU) -#define PCIENREG 0x34 - #define PCIU_CONFIG_DONE 0x4U -#define PCICLKSELREG 0x38 - #define EQUAL_VTCLOCK 0x2U - #define HALF_VTCLOCK 0x0U - #define ONE_THIRD_VTCLOCK 0x3U - #define QUARTER_VTCLOCK 0x1U -#define PCITRDYVREG 0x3c - #define TRDYV(val) ((uint32_t)(val) & 0xffU) -#define PCICLKRUNREG 0x60 - -#define VENDORIDREG 0x100 -#define DEVICEIDREG 0x100 -#define COMMANDREG 0x104 -#define STATUSREG 0x104 -#define REVIDREG 0x108 -#define CLASSREG 0x108 -#define CACHELSREG 0x10c -#define LATTIMEREG 0x10c - #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U) -#define MAILBAREG 0x110 -#define PCIMBA1REG 0x114 -#define PCIMBA2REG 0x118 - #define MBADD(base) ((base) & 0xfffff800U) - #define PMBA(base) ((base) & 0xffe00000U) - #define PREF 0x8U - #define PREF_APPROVAL 0x8U - #define PREF_DISAPPROVAL 0x0U - #define TYPE 0x6U - #define TYPE_32BITSPACE 0x0U - #define MSI 0x1U - #define MSI_MEMORY 0x0U -#define INTLINEREG 0x13c -#define INTPINREG 0x13c -#define RETVALREG 0x140 -#define PCIAPCNTREG 0x140 - #define TKYGNT 0x04000000U - #define TKYGNT_ENABLE 0x04000000U - #define TKYGNT_DISABLE 0x00000000U - #define PAPC 0x03000000U - #define PAPC_ALTERNATE_B 0x02000000U - #define PAPC_ALTERNATE_0 0x01000000U - #define PAPC_FAIR 0x00000000U - #define RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U) - #define RTYVAL_MASK 0xff00U - -#define PCI_CLOCK_MAX 33333333U - -/* - * Default setup - */ -#define PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U -#define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U -#define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U - -#define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U -#define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U - -#define PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U -#define PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U -#define PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U - -#define PCI_MAILBOX_BASE_ADDRESS 0x00000000U - -#define PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U - -#define IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS) -#define IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS -#define IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK) - -#define PCI_IO_RESOURCE_START 0x01000000UL -#define PCI_IO_RESOURCE_END 0x01ffffffUL - -#define PCI_MEM_RESOURCE_START 0x11000000UL -#define PCI_MEM_RESOURCE_END 0x13ffffffUL - -#endif /* __PCI_VR41XX_H */ diff --git a/arch/mips/pci/pci-xtalk-bridge.c b/arch/mips/pci/pci-xtalk-bridge.c index ab9bedb82b28..45ddbaa6c123 100644 --- a/arch/mips/pci/pci-xtalk-bridge.c +++ b/arch/mips/pci/pci-xtalk-bridge.c @@ -114,7 +114,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, * * The function is complicated by the ultimate brokenness of the IOC3 chip * which is used in SGI systems. The IOC3 can only handle 32-bit PCI - * accesses and does only decode parts of it's address space. + * accesses and does only decode parts of its address space. */ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) @@ -733,7 +733,7 @@ err_remove_domain: return err; } -static int bridge_remove(struct platform_device *pdev) +static void bridge_remove(struct platform_device *pdev) { struct pci_bus *bus = platform_get_drvdata(pdev); struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); @@ -745,13 +745,11 @@ static int bridge_remove(struct platform_device *pdev) pci_stop_root_bus(bus); pci_remove_root_bus(bus); pci_unlock_rescan_remove(); - - return 0; } static struct platform_driver bridge_driver = { - .probe = bridge_probe, - .remove = bridge_remove, + .probe = bridge_probe, + .remove_new = bridge_remove, .driver = { .name = "xtalk-bridge", } diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index c9edd3fb380d..2583e318e8c6 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -1037,7 +1037,7 @@ retry: in_fif_p_count = dbg_data.s.data & 0xff; } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff)); - /* Update in_fif_p_count for it's offset with respect to out_p_count */ + /* Update in_fif_p_count for its offset with respect to out_p_count */ in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff; /* Read the OUT_P_COUNT from the debug select */ |