diff options
Diffstat (limited to 'arch/mips/ralink/rt288x.c')
-rw-r--r-- | arch/mips/ralink/rt288x.c | 118 |
1 files changed, 69 insertions, 49 deletions
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index 493335db2fe1..ce8b5b6025bb 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -10,6 +10,8 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/slab.h> +#include <linux/sys_soc.h> #include <asm/mipsregs.h> #include <asm/mach-ralink/ralink_regs.h> @@ -17,74 +19,92 @@ #include "common.h" -void __init ralink_clk_init(void) +static struct ralink_soc_info *soc_info_ptr; + +static unsigned int __init rt2880_get_soc_name0(void) { - unsigned long cpu_rate, wmac_rate = 40000000; - u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); - t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK); - - switch (t) { - case SYSTEM_CONFIG_CPUCLK_250: - cpu_rate = 250000000; - break; - case SYSTEM_CONFIG_CPUCLK_266: - cpu_rate = 266666667; - break; - case SYSTEM_CONFIG_CPUCLK_280: - cpu_rate = 280000000; - break; - case SYSTEM_CONFIG_CPUCLK_300: - cpu_rate = 300000000; - break; - } + return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0); +} - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("300100.timer", cpu_rate / 2); - ralink_clk_add("300120.watchdog", cpu_rate / 2); - ralink_clk_add("300500.uart", cpu_rate / 2); - ralink_clk_add("300900.i2c", cpu_rate / 2); - ralink_clk_add("300c00.uartlite", cpu_rate / 2); - ralink_clk_add("400000.ethernet", cpu_rate / 2); - ralink_clk_add("480000.wmac", wmac_rate); +static unsigned int __init rt2880_get_soc_name1(void) +{ + return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1); } -void __init ralink_of_remap(void) +static bool __init rt2880_soc_valid(void) { - rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc"); - rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc"); + if (rt2880_get_soc_name0() == RT2880_CHIP_NAME0 && + rt2880_get_soc_name1() == RT2880_CHIP_NAME1) + return true; + else + return false; +} - if (!rt_sysc_membase || !rt_memc_membase) - panic("Failed to remap core resources"); +static const char __init *rt2880_get_soc_name(void) +{ + if (rt2880_soc_valid()) + return "RT2880"; + else + return "invalid"; } -void __init prom_soc_init(struct ralink_soc_info *soc_info) +static unsigned int __init rt2880_get_soc_id(void) { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE); - const char *name; - u32 n0; - u32 n1; - u32 id; + return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID); +} - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); - id = __raw_readl(sysc + SYSC_REG_CHIP_ID); +static unsigned int __init rt2880_get_soc_ver(void) +{ + return (rt2880_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK; +} - if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) { - soc_info->compatible = "ralink,r2880-soc"; - name = "RT2880"; - } else { - panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1); +static unsigned int __init rt2880_get_soc_rev(void) +{ + return (rt2880_get_soc_id() & CHIP_ID_REV_MASK); +} + +static int __init rt2880_soc_dev_init(void) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = "Ralink"; + soc_dev_attr->soc_id = rt2880_get_soc_name(); + + soc_dev_attr->data = soc_info_ptr; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr); + return PTR_ERR(soc_dev); } + return 0; +} +device_initcall(rt2880_soc_dev_init); + +void __init prom_soc_init(struct ralink_soc_info *soc_info) +{ + if (rt2880_soc_valid()) + soc_info->compatible = "ralink,r2880-soc"; + else + panic("rt288x: unknown SoC, n0:%08x n1:%08x", + rt2880_get_soc_name0(), rt2880_get_soc_name1()); + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, "Ralink %s id:%u rev:%u", - name, - (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, - (id & CHIP_ID_REV_MASK)); + rt2880_get_soc_name(), + rt2880_get_soc_ver(), + rt2880_get_soc_rev()); soc_info->mem_base = RT2880_SDRAM_BASE; soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; ralink_soc = RT2880_SOC; + soc_info_ptr = soc_info; } |