diff options
Diffstat (limited to 'drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h')
| -rw-r--r-- | drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h | 896 |
1 files changed, 896 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h new file mode 100644 index 000000000000..cd61289a1e8a --- /dev/null +++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/dma_if_e_s_down_ch0_regs.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ +#define ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ + +/* + ***************************************** + * DMA_IF_E_S_DOWN_CH0 (Prototype: RTR_CTRL) + ***************************************** + */ + +#define mmDMA_IF_E_S_DOWN_CH0_PERM_SEL 0x4A1108 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_0 0x4A1114 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_1 0x4A1118 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_2 0x4A111C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_3 0x4A1120 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_4 0x4A1124 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_5 0x4A1128 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_6 0x4A112C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_7 0x4A1130 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_8 0x4A1134 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_9 0x4A1138 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_10 0x4A113C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_11 0x4A1140 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_12 0x4A1144 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_13 0x4A1148 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_14 0x4A114C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_15 0x4A1150 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_16 0x4A1154 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_17 0x4A1158 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_18 0x4A115C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_19 0x4A1160 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_20 0x4A1164 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_21 0x4A1168 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_22 0x4A116C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_23 0x4A1170 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_24 0x4A1174 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_25 0x4A1178 + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_26 0x4A117C + +#define mmDMA_IF_E_S_DOWN_CH0_HBM_POLY_H3_27 0x4A1180 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_0 0x4A1184 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_1 0x4A1188 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_2 0x4A118C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_3 0x4A1190 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_4 0x4A1194 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_5 0x4A1198 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_6 0x4A119C + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_7 0x4A11A0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_8 0x4A11A4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_9 0x4A11A8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_10 0x4A11AC + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_11 0x4A11B0 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_12 0x4A11B4 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_13 0x4A11B8 + +#define mmDMA_IF_E_S_DOWN_CH0_SRAM_POLY_H3_14 0x4A11BC + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_SRAM_EN 0x4A126C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_EN 0x4A1274 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_SAT 0x4A1278 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_RST 0x4A127C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_HBM_TIMEOUT 0x4A1280 + +#define mmDMA_IF_E_S_DOWN_CH0_SCRAM_HBM_EN 0x4A1284 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_EN 0x4A1288 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_SAT 0x4A128C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_RST 0x4A1290 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_PCI_TIMEOUT 0x4A1294 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_EN 0x4A129C + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_SAT 0x4A12A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RST 0x4A12A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4A12AC + +#define mmDMA_IF_E_S_DOWN_CH0_RL_SRAM_RED 0x4A12B4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_EN 0x4A12EC + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_EN 0x4A12F0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4A12F4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4A12F8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x4A1404 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x4A1408 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x4A140C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x4A1410 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x4A1414 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x4A1418 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x4A141C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x4A1420 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x4A1424 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x4A1428 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x4A142C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x4A1430 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x4A1434 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x4A1438 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_0 0x4A1450 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_SEL_1 0x4A1454 + +#define mmDMA_IF_E_S_DOWN_CH0_NON_LIN_EN 0x4A1480 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_0 0x4A1500 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_1 0x4A1504 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_2 0x4A1508 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_3 0x4A150C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_BANK_4 0x4A1510 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x4A1514 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x4A1520 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x4A1524 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x4A1528 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x4A152C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x4A1530 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x4A1534 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x4A1538 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x4A153C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x4A1540 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_0 0x4A1550 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_1 0x4A1554 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_2 0x4A1558 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_3 0x4A155C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_4 0x4A1560 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_5 0x4A1564 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_6 0x4A1568 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_7 0x4A156C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_8 0x4A1570 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_9 0x4A1574 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_10 0x4A1578 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_11 0x4A157C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_12 0x4A1580 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_13 0x4A1584 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_14 0x4A1588 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_15 0x4A158C + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_16 0x4A1590 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_17 0x4A1594 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_OFFSET_18 0x4A1598 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4A15E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4A15E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4A15EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4A15F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4A15F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4A15F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4A15FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x4A1600 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x4A1604 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x4A1608 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x4A160C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x4A1610 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x4A1614 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x4A1618 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x4A161C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x4A1620 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x4A1624 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x4A1628 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x4A162C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x4A1630 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x4A1634 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x4A1638 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x4A163C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x4A1640 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x4A1644 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x4A1648 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x4A164C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x4A1650 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x4A1654 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x4A1658 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x4A165C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x4A1660 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x4A1664 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x4A1668 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x4A166C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x4A1670 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x4A1674 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x4A1678 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x4A167C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x4A1680 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x4A1684 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x4A1688 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x4A168C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x4A1690 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x4A1694 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x4A1698 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x4A169C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4A16A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4A16A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4A16A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4A16AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4A16B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4A16B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4A16B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4A16BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4A16C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4A16C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4A16C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4A16CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4A16D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4A16D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4A16D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4A16DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4A16E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4A16E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4A16E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4A16EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4A16F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4A16F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4A16F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4A16FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x4A1700 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x4A1704 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x4A1708 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x4A170C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x4A1710 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x4A1714 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x4A1718 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x4A171C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x4A1720 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x4A1724 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x4A1728 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x4A172C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x4A1730 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x4A1734 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x4A1738 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x4A173C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x4A1740 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x4A1744 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x4A1748 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x4A174C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x4A1750 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x4A1754 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x4A1758 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x4A175C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x4A1760 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x4A1764 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x4A1768 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x4A176C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x4A1770 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x4A1774 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x4A1778 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x4A177C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x4A1780 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x4A1784 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x4A1788 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x4A178C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x4A1790 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x4A1794 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x4A1798 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x4A179C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4A17A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4A17A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4A17A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4A17AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4A17B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4A17B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4A17B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4A17BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4A17C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4A17C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4A17C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4A17CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4A17D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4A17D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4A17D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4A17DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4A17E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x4A1824 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x4A1828 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x4A182C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x4A1830 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x4A1834 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x4A1838 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x4A183C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x4A1840 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x4A1844 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x4A1848 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x4A184C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x4A1850 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x4A1854 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x4A1858 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x4A185C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x4A1860 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x4A1864 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x4A1868 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x4A186C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x4A1870 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x4A1874 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x4A1878 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x4A187C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x4A1880 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x4A1884 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x4A1888 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x4A188C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x4A1890 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x4A1894 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x4A1898 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x4A189C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4A18A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4A18A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4A18A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4A18AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4A18B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4A18B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4A18B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4A18BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4A18C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4A18C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4A18C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4A18CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4A18D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4A18D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4A18D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4A18DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4A18E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4A18E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4A18E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4A18EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4A18F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4A18F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4A18F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4A18FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x4A1900 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x4A1904 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x4A1908 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x4A190C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x4A1910 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x4A1914 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x4A1918 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x4A191C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x4A1920 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x4A1924 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x4A1928 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x4A192C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x4A1930 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x4A1934 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x4A1938 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x4A193C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x4A1940 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x4A1944 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x4A1948 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x4A194C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x4A1950 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x4A1954 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x4A1958 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x4A195C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x4A1960 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x4A1964 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x4A1968 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x4A196C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x4A1970 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x4A1974 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x4A1978 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x4A197C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x4A1980 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x4A1984 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x4A1988 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x4A198C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x4A1990 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x4A1994 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x4A1998 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x4A199C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4A19A0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4A19A4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4A19A8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4A19AC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4A19B0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4A19B4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4A19B8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4A19BC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4A19C0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4A19C4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4A19C8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4A19CC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4A19D0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4A19D4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4A19D8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4A19DC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4A19E0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4A19E4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4A19E8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4A19EC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4A19F0 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4A19F4 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4A19F8 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4A19FC + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x4A1A00 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x4A1A04 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x4A1A08 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x4A1A0C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x4A1A10 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x4A1A14 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x4A1A18 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x4A1A1C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x4A1A20 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x4A1A64 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x4A1A68 + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x4A1A6C + +#define mmDMA_IF_E_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x4A1A70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_CFG 0x4A1B64 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_SHIFT 0x4A1B68 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x4A1B6C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x4A1B70 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x4A1B74 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x4A1B78 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x4A1B7C + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x4A1B80 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x4A1B84 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x4A1B88 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_0 0x4A1BAC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_1 0x4A1BB0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_2 0x4A1BB4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_3 0x4A1BB8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_4 0x4A1BBC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_5 0x4A1BC0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_6 0x4A1BC4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_TOKEN_7 0x4A1BC8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_0 0x4A1BEC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_1 0x4A1BF0 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_2 0x4A1BF4 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_3 0x4A1BF8 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_4 0x4A1BFC + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_5 0x4A1C00 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_6 0x4A1C04 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_BANK_ID_7 0x4A1C08 + +#define mmDMA_IF_E_S_DOWN_CH0_RGL_WDT 0x4A1C2C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A1C30 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A1C34 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A1C38 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A1C3C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A1C40 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A1C44 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A1C48 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A1C4C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x4A1C50 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x4A1C54 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x4A1C58 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x4A1C5C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x4A1C60 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x4A1C64 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x4A1C68 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x4A1C6C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A1C70 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A1C74 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A1C78 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A1C7C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A1C80 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A1C84 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A1C88 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A1C8C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x4A1C90 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x4A1C94 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x4A1C98 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x4A1C9C + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x4A1CA0 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x4A1CA4 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x4A1CA8 + +#define mmDMA_IF_E_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x4A1CAC + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x4A1CB0 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x4A1CB4 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x4A1CB8 + +#define mmDMA_IF_E_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x4A1CBC + +#endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH0_REGS_H_ */ |