diff options
Diffstat (limited to 'drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h')
| -rw-r--r-- | drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h | 1057 |
1 files changed, 1057 insertions, 0 deletions
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h new file mode 100644 index 000000000000..acb19c1cd4bd --- /dev/null +++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/nic0_qm0_regs.h @@ -0,0 +1,1057 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_NIC0_QM0_REGS_H_ +#define ASIC_REG_NIC0_QM0_REGS_H_ + +/* + ***************************************** + * NIC0_QM0 + * (Prototype: QMAN) + ***************************************** + */ + +#define mmNIC0_QM0_GLBL_CFG0 0x541A000 + +#define mmNIC0_QM0_GLBL_CFG1 0x541A004 + +#define mmNIC0_QM0_GLBL_CFG2 0x541A008 + +#define mmNIC0_QM0_GLBL_ERR_CFG 0x541A00C + +#define mmNIC0_QM0_GLBL_ERR_CFG1 0x541A010 + +#define mmNIC0_QM0_GLBL_ERR_ARC_HALT_EN 0x541A014 + +#define mmNIC0_QM0_GLBL_AXCACHE 0x541A018 + +#define mmNIC0_QM0_GLBL_STS0 0x541A01C + +#define mmNIC0_QM0_GLBL_STS1 0x541A020 + +#define mmNIC0_QM0_GLBL_ERR_STS_0 0x541A024 + +#define mmNIC0_QM0_GLBL_ERR_STS_1 0x541A028 + +#define mmNIC0_QM0_GLBL_ERR_STS_2 0x541A02C + +#define mmNIC0_QM0_GLBL_ERR_STS_3 0x541A030 + +#define mmNIC0_QM0_GLBL_ERR_STS_4 0x541A034 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_0 0x541A038 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_1 0x541A03C + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_2 0x541A040 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_3 0x541A044 + +#define mmNIC0_QM0_GLBL_ERR_MSG_EN_4 0x541A048 + +#define mmNIC0_QM0_GLBL_PROT 0x541A04C + +#define mmNIC0_QM0_PQ_BASE_LO_0 0x541A050 + +#define mmNIC0_QM0_PQ_BASE_LO_1 0x541A054 + +#define mmNIC0_QM0_PQ_BASE_LO_2 0x541A058 + +#define mmNIC0_QM0_PQ_BASE_LO_3 0x541A05C + +#define mmNIC0_QM0_PQ_BASE_HI_0 0x541A060 + +#define mmNIC0_QM0_PQ_BASE_HI_1 0x541A064 + +#define mmNIC0_QM0_PQ_BASE_HI_2 0x541A068 + +#define mmNIC0_QM0_PQ_BASE_HI_3 0x541A06C + +#define mmNIC0_QM0_PQ_SIZE_0 0x541A070 + +#define mmNIC0_QM0_PQ_SIZE_1 0x541A074 + +#define mmNIC0_QM0_PQ_SIZE_2 0x541A078 + +#define mmNIC0_QM0_PQ_SIZE_3 0x541A07C + +#define mmNIC0_QM0_PQ_PI_0 0x541A080 + +#define mmNIC0_QM0_PQ_PI_1 0x541A084 + +#define mmNIC0_QM0_PQ_PI_2 0x541A088 + +#define mmNIC0_QM0_PQ_PI_3 0x541A08C + +#define mmNIC0_QM0_PQ_CI_0 0x541A090 + +#define mmNIC0_QM0_PQ_CI_1 0x541A094 + +#define mmNIC0_QM0_PQ_CI_2 0x541A098 + +#define mmNIC0_QM0_PQ_CI_3 0x541A09C + +#define mmNIC0_QM0_PQ_CFG0_0 0x541A0A0 + +#define mmNIC0_QM0_PQ_CFG0_1 0x541A0A4 + +#define mmNIC0_QM0_PQ_CFG0_2 0x541A0A8 + +#define mmNIC0_QM0_PQ_CFG0_3 0x541A0AC + +#define mmNIC0_QM0_PQ_CFG1_0 0x541A0B0 + +#define mmNIC0_QM0_PQ_CFG1_1 0x541A0B4 + +#define mmNIC0_QM0_PQ_CFG1_2 0x541A0B8 + +#define mmNIC0_QM0_PQ_CFG1_3 0x541A0BC + +#define mmNIC0_QM0_PQ_STS0_0 0x541A0C0 + +#define mmNIC0_QM0_PQ_STS0_1 0x541A0C4 + +#define mmNIC0_QM0_PQ_STS0_2 0x541A0C8 + +#define mmNIC0_QM0_PQ_STS0_3 0x541A0CC + +#define mmNIC0_QM0_PQ_STS1_0 0x541A0D0 + +#define mmNIC0_QM0_PQ_STS1_1 0x541A0D4 + +#define mmNIC0_QM0_PQ_STS1_2 0x541A0D8 + +#define mmNIC0_QM0_PQ_STS1_3 0x541A0DC + +#define mmNIC0_QM0_CQ_CFG0_0 0x541A0E0 + +#define mmNIC0_QM0_CQ_CFG0_1 0x541A0E4 + +#define mmNIC0_QM0_CQ_CFG0_2 0x541A0E8 + +#define mmNIC0_QM0_CQ_CFG0_3 0x541A0EC + +#define mmNIC0_QM0_CQ_CFG0_4 0x541A0F0 + +#define mmNIC0_QM0_CQ_STS0_0 0x541A0F4 + +#define mmNIC0_QM0_CQ_STS0_1 0x541A0F8 + +#define mmNIC0_QM0_CQ_STS0_2 0x541A0FC + +#define mmNIC0_QM0_CQ_STS0_3 0x541A100 + +#define mmNIC0_QM0_CQ_STS0_4 0x541A104 + +#define mmNIC0_QM0_CQ_CFG1_0 0x541A108 + +#define mmNIC0_QM0_CQ_CFG1_1 0x541A10C + +#define mmNIC0_QM0_CQ_CFG1_2 0x541A110 + +#define mmNIC0_QM0_CQ_CFG1_3 0x541A114 + +#define mmNIC0_QM0_CQ_CFG1_4 0x541A118 + +#define mmNIC0_QM0_CQ_STS1_0 0x541A11C + +#define mmNIC0_QM0_CQ_STS1_1 0x541A120 + +#define mmNIC0_QM0_CQ_STS1_2 0x541A124 + +#define mmNIC0_QM0_CQ_STS1_3 0x541A128 + +#define mmNIC0_QM0_CQ_STS1_4 0x541A12C + +#define mmNIC0_QM0_CQ_PTR_LO_0 0x541A150 + +#define mmNIC0_QM0_CQ_PTR_HI_0 0x541A154 + +#define mmNIC0_QM0_CQ_TSIZE_0 0x541A158 + +#define mmNIC0_QM0_CQ_CTL_0 0x541A15C + +#define mmNIC0_QM0_CQ_PTR_LO_1 0x541A160 + +#define mmNIC0_QM0_CQ_PTR_HI_1 0x541A164 + +#define mmNIC0_QM0_CQ_TSIZE_1 0x541A168 + +#define mmNIC0_QM0_CQ_CTL_1 0x541A16C + +#define mmNIC0_QM0_CQ_PTR_LO_2 0x541A170 + +#define mmNIC0_QM0_CQ_PTR_HI_2 0x541A174 + +#define mmNIC0_QM0_CQ_TSIZE_2 0x541A178 + +#define mmNIC0_QM0_CQ_CTL_2 0x541A17C + +#define mmNIC0_QM0_CQ_PTR_LO_3 0x541A180 + +#define mmNIC0_QM0_CQ_PTR_HI_3 0x541A184 + +#define mmNIC0_QM0_CQ_TSIZE_3 0x541A188 + +#define mmNIC0_QM0_CQ_CTL_3 0x541A18C + +#define mmNIC0_QM0_CQ_PTR_LO_4 0x541A190 + +#define mmNIC0_QM0_CQ_PTR_HI_4 0x541A194 + +#define mmNIC0_QM0_CQ_TSIZE_4 0x541A198 + +#define mmNIC0_QM0_CQ_CTL_4 0x541A19C + +#define mmNIC0_QM0_CQ_TSIZE_STS_0 0x541A1A0 + +#define mmNIC0_QM0_CQ_TSIZE_STS_1 0x541A1A4 + +#define mmNIC0_QM0_CQ_TSIZE_STS_2 0x541A1A8 + +#define mmNIC0_QM0_CQ_TSIZE_STS_3 0x541A1AC + +#define mmNIC0_QM0_CQ_TSIZE_STS_4 0x541A1B0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_0 0x541A1B4 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_1 0x541A1B8 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_2 0x541A1BC + +#define mmNIC0_QM0_CQ_PTR_LO_STS_3 0x541A1C0 + +#define mmNIC0_QM0_CQ_PTR_LO_STS_4 0x541A1C4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_0 0x541A1C8 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_1 0x541A1CC + +#define mmNIC0_QM0_CQ_PTR_HI_STS_2 0x541A1D0 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_3 0x541A1D4 + +#define mmNIC0_QM0_CQ_PTR_HI_STS_4 0x541A1D8 + +#define mmNIC0_QM0_CQ_IFIFO_STS_0 0x541A1DC + +#define mmNIC0_QM0_CQ_IFIFO_STS_1 0x541A1E0 + +#define mmNIC0_QM0_CQ_IFIFO_STS_2 0x541A1E4 + +#define mmNIC0_QM0_CQ_IFIFO_STS_3 0x541A1E8 + +#define mmNIC0_QM0_CQ_IFIFO_STS_4 0x541A1EC + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0 0x541A1F0 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1 0x541A1F4 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2 0x541A1F8 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3 0x541A1FC + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4 0x541A200 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0 0x541A204 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1 0x541A208 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2 0x541A20C + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3 0x541A210 + +#define mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4 0x541A214 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0 0x541A218 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1 0x541A21C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2 0x541A220 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3 0x541A224 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4 0x541A228 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0 0x541A22C + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1 0x541A230 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2 0x541A234 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3 0x541A238 + +#define mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4 0x541A23C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0 0x541A240 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1 0x541A244 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2 0x541A248 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3 0x541A24C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4 0x541A250 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0 0x541A254 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1 0x541A258 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2 0x541A25C + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3 0x541A260 + +#define mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4 0x541A264 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0 0x541A268 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1 0x541A26C + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2 0x541A270 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3 0x541A274 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4 0x541A278 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0 0x541A27C + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1 0x541A280 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2 0x541A284 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3 0x541A288 + +#define mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4 0x541A28C + +#define mmNIC0_QM0_CP_FENCE0_RDATA_0 0x541A290 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_1 0x541A294 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_2 0x541A298 + +#define mmNIC0_QM0_CP_FENCE0_RDATA_3 0x541A29C + +#define mmNIC0_QM0_CP_FENCE0_RDATA_4 0x541A2A0 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_0 0x541A2A4 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_1 0x541A2A8 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_2 0x541A2AC + +#define mmNIC0_QM0_CP_FENCE1_RDATA_3 0x541A2B0 + +#define mmNIC0_QM0_CP_FENCE1_RDATA_4 0x541A2B4 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_0 0x541A2B8 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_1 0x541A2BC + +#define mmNIC0_QM0_CP_FENCE2_RDATA_2 0x541A2C0 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_3 0x541A2C4 + +#define mmNIC0_QM0_CP_FENCE2_RDATA_4 0x541A2C8 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_0 0x541A2CC + +#define mmNIC0_QM0_CP_FENCE3_RDATA_1 0x541A2D0 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_2 0x541A2D4 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_3 0x541A2D8 + +#define mmNIC0_QM0_CP_FENCE3_RDATA_4 0x541A2DC + +#define mmNIC0_QM0_CP_FENCE0_CNT_0 0x541A2E0 + +#define mmNIC0_QM0_CP_FENCE0_CNT_1 0x541A2E4 + +#define mmNIC0_QM0_CP_FENCE0_CNT_2 0x541A2E8 + +#define mmNIC0_QM0_CP_FENCE0_CNT_3 0x541A2EC + +#define mmNIC0_QM0_CP_FENCE0_CNT_4 0x541A2F0 + +#define mmNIC0_QM0_CP_FENCE1_CNT_0 0x541A2F4 + +#define mmNIC0_QM0_CP_FENCE1_CNT_1 0x541A2F8 + +#define mmNIC0_QM0_CP_FENCE1_CNT_2 0x541A2FC + +#define mmNIC0_QM0_CP_FENCE1_CNT_3 0x541A300 + +#define mmNIC0_QM0_CP_FENCE1_CNT_4 0x541A304 + +#define mmNIC0_QM0_CP_FENCE2_CNT_0 0x541A308 + +#define mmNIC0_QM0_CP_FENCE2_CNT_1 0x541A30C + +#define mmNIC0_QM0_CP_FENCE2_CNT_2 0x541A310 + +#define mmNIC0_QM0_CP_FENCE2_CNT_3 0x541A314 + +#define mmNIC0_QM0_CP_FENCE2_CNT_4 0x541A318 + +#define mmNIC0_QM0_CP_FENCE3_CNT_0 0x541A31C + +#define mmNIC0_QM0_CP_FENCE3_CNT_1 0x541A320 + +#define mmNIC0_QM0_CP_FENCE3_CNT_2 0x541A324 + +#define mmNIC0_QM0_CP_FENCE3_CNT_3 0x541A328 + +#define mmNIC0_QM0_CP_FENCE3_CNT_4 0x541A32C + +#define mmNIC0_QM0_CP_BARRIER_CFG 0x541A330 + +#define mmNIC0_QM0_CP_LDMA_SRC_BASE_LO_OFFSET 0x541A334 + +#define mmNIC0_QM0_CP_LDMA_DST_BASE_LO_OFFSET 0x541A338 + +#define mmNIC0_QM0_CP_LDMA_TSIZE_OFFSET 0x541A33C + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_0 0x541A340 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_1 0x541A344 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_2 0x541A348 + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_3 0x541A34C + +#define mmNIC0_QM0_CP_CQ_PTR_LO_OFFSET_4 0x541A350 + +#define mmNIC0_QM0_CP_STS_0 0x541A368 + +#define mmNIC0_QM0_CP_STS_1 0x541A36C + +#define mmNIC0_QM0_CP_STS_2 0x541A370 + +#define mmNIC0_QM0_CP_STS_3 0x541A374 + +#define mmNIC0_QM0_CP_STS_4 0x541A378 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_0 0x541A37C + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_1 0x541A380 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_2 0x541A384 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_3 0x541A388 + +#define mmNIC0_QM0_CP_CURRENT_INST_LO_4 0x541A38C + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_0 0x541A390 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_1 0x541A394 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_2 0x541A398 + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_3 0x541A39C + +#define mmNIC0_QM0_CP_CURRENT_INST_HI_4 0x541A3A0 + +#define mmNIC0_QM0_CP_PRED_0 0x541A3A4 + +#define mmNIC0_QM0_CP_PRED_1 0x541A3A8 + +#define mmNIC0_QM0_CP_PRED_2 0x541A3AC + +#define mmNIC0_QM0_CP_PRED_3 0x541A3B0 + +#define mmNIC0_QM0_CP_PRED_4 0x541A3B4 + +#define mmNIC0_QM0_CP_PRED_UPEN_0 0x541A3B8 + +#define mmNIC0_QM0_CP_PRED_UPEN_1 0x541A3BC + +#define mmNIC0_QM0_CP_PRED_UPEN_2 0x541A3C0 + +#define mmNIC0_QM0_CP_PRED_UPEN_3 0x541A3C4 + +#define mmNIC0_QM0_CP_PRED_UPEN_4 0x541A3C8 + +#define mmNIC0_QM0_CP_DBG_0_0 0x541A3CC + +#define mmNIC0_QM0_CP_DBG_0_1 0x541A3D0 + +#define mmNIC0_QM0_CP_DBG_0_2 0x541A3D4 + +#define mmNIC0_QM0_CP_DBG_0_3 0x541A3D8 + +#define mmNIC0_QM0_CP_DBG_0_4 0x541A3DC + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_0 0x541A3E0 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_1 0x541A3E4 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_2 0x541A3E8 + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_3 0x541A3EC + +#define mmNIC0_QM0_CP_CPDMA_UP_CRED_4 0x541A3F0 + +#define mmNIC0_QM0_CP_IN_DATA_LO_0 0x541A3F4 + +#define mmNIC0_QM0_CP_IN_DATA_LO_1 0x541A3F8 + +#define mmNIC0_QM0_CP_IN_DATA_LO_2 0x541A3FC + +#define mmNIC0_QM0_CP_IN_DATA_LO_3 0x541A400 + +#define mmNIC0_QM0_CP_IN_DATA_LO_4 0x541A404 + +#define mmNIC0_QM0_CP_IN_DATA_HI_0 0x541A408 + +#define mmNIC0_QM0_CP_IN_DATA_HI_1 0x541A40C + +#define mmNIC0_QM0_CP_IN_DATA_HI_2 0x541A410 + +#define mmNIC0_QM0_CP_IN_DATA_HI_3 0x541A414 + +#define mmNIC0_QM0_CP_IN_DATA_HI_4 0x541A418 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_0 0x541A41C + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_1 0x541A420 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_2 0x541A424 + +#define mmNIC0_QM0_PQC_HBW_BASE_LO_3 0x541A428 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_0 0x541A42C + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_1 0x541A430 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_2 0x541A434 + +#define mmNIC0_QM0_PQC_HBW_BASE_HI_3 0x541A438 + +#define mmNIC0_QM0_PQC_SIZE_0 0x541A43C + +#define mmNIC0_QM0_PQC_SIZE_1 0x541A440 + +#define mmNIC0_QM0_PQC_SIZE_2 0x541A444 + +#define mmNIC0_QM0_PQC_SIZE_3 0x541A448 + +#define mmNIC0_QM0_PQC_PI_0 0x541A44C + +#define mmNIC0_QM0_PQC_PI_1 0x541A450 + +#define mmNIC0_QM0_PQC_PI_2 0x541A454 + +#define mmNIC0_QM0_PQC_PI_3 0x541A458 + +#define mmNIC0_QM0_PQC_LBW_WDATA_0 0x541A45C + +#define mmNIC0_QM0_PQC_LBW_WDATA_1 0x541A460 + +#define mmNIC0_QM0_PQC_LBW_WDATA_2 0x541A464 + +#define mmNIC0_QM0_PQC_LBW_WDATA_3 0x541A468 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_0 0x541A46C + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_1 0x541A470 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_2 0x541A474 + +#define mmNIC0_QM0_PQC_LBW_BASE_LO_3 0x541A478 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_0 0x541A47C + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_1 0x541A480 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_2 0x541A484 + +#define mmNIC0_QM0_PQC_LBW_BASE_HI_3 0x541A488 + +#define mmNIC0_QM0_PQC_CFG 0x541A48C + +#define mmNIC0_QM0_PQC_SECURE_PUSH_IND 0x541A490 + +#define mmNIC0_QM0_ARB_MASK 0x541A4A0 + +#define mmNIC0_QM0_ARB_CFG_0 0x541A4A4 + +#define mmNIC0_QM0_ARB_CHOICE_Q_PUSH 0x541A4A8 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_0 0x541A4AC + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_1 0x541A4B0 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_2 0x541A4B4 + +#define mmNIC0_QM0_ARB_WRR_WEIGHT_3 0x541A4B8 + +#define mmNIC0_QM0_ARB_CFG_1 0x541A4BC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_0 0x541A4C0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_1 0x541A4C4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_2 0x541A4C8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_3 0x541A4CC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_4 0x541A4D0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_5 0x541A4D4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_6 0x541A4D8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_7 0x541A4DC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_8 0x541A4E0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_9 0x541A4E4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_10 0x541A4E8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_11 0x541A4EC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_12 0x541A4F0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_13 0x541A4F4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_14 0x541A4F8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_15 0x541A4FC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_16 0x541A500 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_17 0x541A504 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_18 0x541A508 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_19 0x541A50C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_20 0x541A510 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_21 0x541A514 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_22 0x541A518 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_23 0x541A51C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_24 0x541A520 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_25 0x541A524 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_26 0x541A528 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_27 0x541A52C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_28 0x541A530 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_29 0x541A534 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_30 0x541A538 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_31 0x541A53C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_32 0x541A540 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_33 0x541A544 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_34 0x541A548 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_35 0x541A54C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_36 0x541A550 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_37 0x541A554 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_38 0x541A558 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_39 0x541A55C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_40 0x541A560 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_41 0x541A564 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_42 0x541A568 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_43 0x541A56C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_44 0x541A570 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_45 0x541A574 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_46 0x541A578 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_47 0x541A57C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_48 0x541A580 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_49 0x541A584 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_50 0x541A588 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_51 0x541A58C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_52 0x541A590 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_53 0x541A594 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_54 0x541A598 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_55 0x541A59C + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_56 0x541A5A0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_57 0x541A5A4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_58 0x541A5A8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_59 0x541A5AC + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_60 0x541A5B0 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_61 0x541A5B4 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_62 0x541A5B8 + +#define mmNIC0_QM0_ARB_MST_AVAIL_CRED_63 0x541A5BC + +#define mmNIC0_QM0_ARB_MST_CRED_INC 0x541A5E0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0 0x541A5E4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1 0x541A5E8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2 0x541A5EC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3 0x541A5F0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4 0x541A5F4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5 0x541A5F8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6 0x541A5FC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7 0x541A600 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8 0x541A604 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9 0x541A608 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10 0x541A60C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11 0x541A610 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12 0x541A614 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13 0x541A618 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14 0x541A61C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15 0x541A620 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16 0x541A624 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17 0x541A628 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18 0x541A62C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19 0x541A630 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20 0x541A634 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21 0x541A638 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22 0x541A63C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23 0x541A640 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24 0x541A644 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25 0x541A648 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26 0x541A64C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27 0x541A650 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28 0x541A654 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29 0x541A658 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30 0x541A65C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31 0x541A660 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32 0x541A664 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33 0x541A668 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34 0x541A66C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35 0x541A670 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36 0x541A674 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37 0x541A678 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38 0x541A67C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39 0x541A680 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40 0x541A684 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41 0x541A688 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42 0x541A68C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43 0x541A690 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44 0x541A694 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45 0x541A698 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46 0x541A69C + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47 0x541A6A0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48 0x541A6A4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49 0x541A6A8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50 0x541A6AC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51 0x541A6B0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52 0x541A6B4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53 0x541A6B8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54 0x541A6BC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55 0x541A6C0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56 0x541A6C4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57 0x541A6C8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58 0x541A6CC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59 0x541A6D0 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60 0x541A6D4 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61 0x541A6D8 + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62 0x541A6DC + +#define mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63 0x541A6E0 + +#define mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0x541A704 + +#define mmNIC0_QM0_ARB_MST_SLAVE_EN 0x541A708 + +#define mmNIC0_QM0_ARB_MST_SLAVE_EN_1 0x541A70C + +#define mmNIC0_QM0_ARB_SLV_CHOICE_WDT 0x541A710 + +#define mmNIC0_QM0_ARB_SLV_ID 0x541A714 + +#define mmNIC0_QM0_ARB_MST_QUIET_PER 0x541A718 + +#define mmNIC0_QM0_ARB_MSG_MAX_INFLIGHT 0x541A744 + +#define mmNIC0_QM0_ARB_BASE_LO 0x541A754 + +#define mmNIC0_QM0_ARB_BASE_HI 0x541A758 + +#define mmNIC0_QM0_ARB_STATE_STS 0x541A780 + +#define mmNIC0_QM0_ARB_CHOICE_FULLNESS_STS 0x541A784 + +#define mmNIC0_QM0_ARB_MSG_STS 0x541A788 + +#define mmNIC0_QM0_ARB_SLV_CHOICE_Q_HEAD 0x541A78C + +#define mmNIC0_QM0_ARB_ERR_CAUSE 0x541A79C + +#define mmNIC0_QM0_ARB_ERR_MSG_EN 0x541A7A0 + +#define mmNIC0_QM0_ARB_ERR_STS_DRP 0x541A7A8 + +#define mmNIC0_QM0_ARB_MST_CRED_STS 0x541A7B0 + +#define mmNIC0_QM0_ARB_MST_CRED_STS_1 0x541A7B4 + +#define mmNIC0_QM0_CSMR_STRICT_PRIO_CFG 0x541A7FC + +#define mmNIC0_QM0_ARC_CQ_CFG0 0x541A800 + +#define mmNIC0_QM0_ARC_CQ_CFG1 0x541A804 + +#define mmNIC0_QM0_ARC_CQ_PTR_LO 0x541A808 + +#define mmNIC0_QM0_ARC_CQ_PTR_HI 0x541A80C + +#define mmNIC0_QM0_ARC_CQ_TSIZE 0x541A810 + +#define mmNIC0_QM0_ARC_CQ_CTL 0x541A814 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_STS 0x541A81C + +#define mmNIC0_QM0_ARC_CQ_STS0 0x541A820 + +#define mmNIC0_QM0_ARC_CQ_STS1 0x541A824 + +#define mmNIC0_QM0_ARC_CQ_TSIZE_STS 0x541A828 + +#define mmNIC0_QM0_ARC_CQ_PTR_LO_STS 0x541A82C + +#define mmNIC0_QM0_ARC_CQ_PTR_HI_STS 0x541A830 + +#define mmNIC0_QM0_CP_WR_ARC_ADDR_HI 0x541A834 + +#define mmNIC0_QM0_CP_WR_ARC_ADDR_LO 0x541A838 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_HI 0x541A83C + +#define mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO 0x541A840 + +#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_HI 0x541A844 + +#define mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO 0x541A848 + +#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_HI 0x541A84C + +#define mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO 0x541A850 + +#define mmNIC0_QM0_CQ_CTL_MSG_BASE_HI 0x541A854 + +#define mmNIC0_QM0_CQ_CTL_MSG_BASE_LO 0x541A858 + +#define mmNIC0_QM0_ADDR_OVRD 0x541A85C + +#define mmNIC0_QM0_CQ_IFIFO_CI_0 0x541A860 + +#define mmNIC0_QM0_CQ_IFIFO_CI_1 0x541A864 + +#define mmNIC0_QM0_CQ_IFIFO_CI_2 0x541A868 + +#define mmNIC0_QM0_CQ_IFIFO_CI_3 0x541A86C + +#define mmNIC0_QM0_CQ_IFIFO_CI_4 0x541A870 + +#define mmNIC0_QM0_ARC_CQ_IFIFO_CI 0x541A874 + +#define mmNIC0_QM0_CQ_CTL_CI_0 0x541A878 + +#define mmNIC0_QM0_CQ_CTL_CI_1 0x541A87C + +#define mmNIC0_QM0_CQ_CTL_CI_2 0x541A880 + +#define mmNIC0_QM0_CQ_CTL_CI_3 0x541A884 + +#define mmNIC0_QM0_CQ_CTL_CI_4 0x541A888 + +#define mmNIC0_QM0_ARC_CQ_CTL_CI 0x541A88C + +#define mmNIC0_QM0_CP_CFG 0x541A890 + +#define mmNIC0_QM0_CP_EXT_SWITCH 0x541A894 + +#define mmNIC0_QM0_CP_SWITCH_WD_SET 0x541A898 + +#define mmNIC0_QM0_CP_SWITCH_WD 0x541A89C + +#define mmNIC0_QM0_ARC_LB_ADDR_BASE_LO 0x541A8A4 + +#define mmNIC0_QM0_ARC_LB_ADDR_BASE_HI 0x541A8A8 + +#define mmNIC0_QM0_ENGINE_BASE_ADDR_HI 0x541A8AC + +#define mmNIC0_QM0_ENGINE_BASE_ADDR_LO 0x541A8B0 + +#define mmNIC0_QM0_ENGINE_ADDR_RANGE_SIZE 0x541A8B4 + +#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_HI 0x541A8B8 + +#define mmNIC0_QM0_QM_ARC_AUX_BASE_ADDR_LO 0x541A8BC + +#define mmNIC0_QM0_QM_BASE_ADDR_HI 0x541A8C0 + +#define mmNIC0_QM0_QM_BASE_ADDR_LO 0x541A8C4 + +#define mmNIC0_QM0_ARC_PQC_SECURE_PUSH_IND 0x541A8C8 + +#define mmNIC0_QM0_PQC_STS_0_0 0x541A8D0 + +#define mmNIC0_QM0_PQC_STS_0_1 0x541A8D4 + +#define mmNIC0_QM0_PQC_STS_0_2 0x541A8D8 + +#define mmNIC0_QM0_PQC_STS_0_3 0x541A8DC + +#define mmNIC0_QM0_PQC_STS_1_0 0x541A8E0 + +#define mmNIC0_QM0_PQC_STS_1_1 0x541A8E4 + +#define mmNIC0_QM0_PQC_STS_1_2 0x541A8E8 + +#define mmNIC0_QM0_PQC_STS_1_3 0x541A8EC + +#define mmNIC0_QM0_SEI_STATUS 0x541A8F0 + +#define mmNIC0_QM0_SEI_MASK 0x541A8F4 + +#define mmNIC0_QM0_GLBL_ERR_ADDR_LO 0x541AD00 + +#define mmNIC0_QM0_GLBL_ERR_ADDR_HI 0x541AD04 + +#define mmNIC0_QM0_GLBL_ERR_WDATA 0x541AD08 + +#define mmNIC0_QM0_L2H_MASK_LO 0x541AD14 + +#define mmNIC0_QM0_L2H_MASK_HI 0x541AD18 + +#define mmNIC0_QM0_L2H_CMPR_LO 0x541AD1C + +#define mmNIC0_QM0_L2H_CMPR_HI 0x541AD20 + +#define mmNIC0_QM0_LOCAL_RANGE_BASE 0x541AD24 + +#define mmNIC0_QM0_LOCAL_RANGE_SIZE 0x541AD28 + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_1 0x541AD30 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_0 0x541AD34 + +#define mmNIC0_QM0_LBW_WR_RATE_LIM_CFG_1 0x541AD38 + +#define mmNIC0_QM0_HBW_RD_RATE_LIM_CFG_0 0x541AD3C + +#define mmNIC0_QM0_IND_GW_APB_CFG 0x541AD40 + +#define mmNIC0_QM0_IND_GW_APB_WDATA 0x541AD44 + +#define mmNIC0_QM0_IND_GW_APB_RDATA 0x541AD48 + +#define mmNIC0_QM0_IND_GW_APB_STATUS 0x541AD4C + +#define mmNIC0_QM0_PERF_CNT_FREE_LO 0x541AD60 + +#define mmNIC0_QM0_PERF_CNT_FREE_HI 0x541AD64 + +#define mmNIC0_QM0_PERF_CNT_IDLE_LO 0x541AD68 + +#define mmNIC0_QM0_PERF_CNT_IDLE_HI 0x541AD6C + +#define mmNIC0_QM0_PERF_CNT_CFG 0x541AD70 + +#endif /* ASIC_REG_NIC0_QM0_REGS_H_ */ |