diff options
Diffstat (limited to 'drivers/media/pci/cx88/cx88-core.c')
| -rw-r--r-- | drivers/media/pci/cx88/cx88-core.c | 420 |
1 files changed, 212 insertions, 208 deletions
diff --git a/drivers/media/pci/cx88/cx88-core.c b/drivers/media/pci/cx88/cx88-core.c index 46fe8c1eb9d4..973a9cd4c635 100644 --- a/drivers/media/pci/cx88/cx88-core.c +++ b/drivers/media/pci/cx88/cx88-core.c @@ -1,5 +1,4 @@ /* - * * device driver for Conexant 2388x based TV cards * driver core * @@ -19,12 +18,10 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include "cx88.h" + #include <linux/init.h> #include <linux/list.h> #include <linux/module.h> @@ -38,7 +35,6 @@ #include <linux/videodev2.h> #include <linux/mutex.h> -#include "cx88.h" #include <media/v4l2-common.h> #include <media/v4l2-ioctl.h> @@ -53,17 +49,22 @@ module_param_named(core_debug, cx88_core_debug, int, 0644); MODULE_PARM_DESC(core_debug, "enable debug messages [core]"); static unsigned int nicam; -module_param(nicam,int,0644); -MODULE_PARM_DESC(nicam,"tv audio is nicam"); +module_param(nicam, int, 0644); +MODULE_PARM_DESC(nicam, "tv audio is nicam"); static unsigned int nocomb; -module_param(nocomb,int,0644); -MODULE_PARM_DESC(nocomb,"disable comb filter"); +module_param(nocomb, int, 0644); +MODULE_PARM_DESC(nocomb, "disable comb filter"); + +#define dprintk0(fmt, arg...) \ + printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \ + __func__, ##arg) \ -#define dprintk(level,fmt, arg...) do { \ - if (cx88_core_debug >= level) \ - printk(KERN_DEBUG "%s: " fmt, core->name , ## arg); \ - } while(0) +#define dprintk(level, fmt, arg...) do { \ + if (cx88_core_debug >= level) \ + printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \ + __func__, ##arg); \ +} while (0) static unsigned int cx88_devcount; static LIST_HEAD(cx88_devlist); @@ -71,15 +72,17 @@ static DEFINE_MUTEX(devlist); #define NO_SYNC_LINE (-1U) -/* @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be - generated _after_ lpi lines are transferred. */ -static __le32* cx88_risc_field(__le32 *rp, struct scatterlist *sglist, - unsigned int offset, u32 sync_line, - unsigned int bpl, unsigned int padding, - unsigned int lines, unsigned int lpi, bool jump) +/* + * @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be + * generated _after_ lpi lines are transferred. + */ +static __le32 *cx88_risc_field(__le32 *rp, struct scatterlist *sglist, + unsigned int offset, u32 sync_line, + unsigned int bpl, unsigned int padding, + unsigned int lines, unsigned int lpi, bool jump) { struct scatterlist *sg; - unsigned int line,todo,sol; + unsigned int line, todo, sol; if (jump) { (*rp++) = cpu_to_le32(RISC_JUMP); @@ -97,33 +100,34 @@ static __le32* cx88_risc_field(__le32 *rp, struct scatterlist *sglist, offset -= sg_dma_len(sg); sg = sg_next(sg); } - if (lpi && line>0 && !(line % lpi)) + if (lpi && line > 0 && !(line % lpi)) sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; else sol = RISC_SOL; - if (bpl <= sg_dma_len(sg)-offset) { + if (bpl <= sg_dma_len(sg) - offset) { /* fits into current chunk */ - *(rp++)=cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl); - *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); - offset+=bpl; + *(rp++) = cpu_to_le32(RISC_WRITE | sol | + RISC_EOL | bpl); + *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); + offset += bpl; } else { /* scanline needs to be split */ todo = bpl; - *(rp++)=cpu_to_le32(RISC_WRITE|sol| - (sg_dma_len(sg)-offset)); - *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); - todo -= (sg_dma_len(sg)-offset); + *(rp++) = cpu_to_le32(RISC_WRITE | sol | + (sg_dma_len(sg) - offset)); + *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset); + todo -= (sg_dma_len(sg) - offset); offset = 0; sg = sg_next(sg); while (todo > sg_dma_len(sg)) { - *(rp++)=cpu_to_le32(RISC_WRITE| - sg_dma_len(sg)); - *(rp++)=cpu_to_le32(sg_dma_address(sg)); + *(rp++) = cpu_to_le32(RISC_WRITE | + sg_dma_len(sg)); + *(rp++) = cpu_to_le32(sg_dma_address(sg)); todo -= sg_dma_len(sg); sg = sg_next(sg); } - *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo); - *(rp++)=cpu_to_le32(sg_dma_address(sg)); + *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo); + *(rp++) = cpu_to_le32(sg_dma_address(sg)); offset += todo; } offset += padding; @@ -137,41 +141,46 @@ int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, unsigned int top_offset, unsigned int bottom_offset, unsigned int bpl, unsigned int padding, unsigned int lines) { - u32 instructions,fields; + u32 instructions, fields; __le32 *rp; fields = 0; - if (UNSET != top_offset) + if (top_offset != UNSET) fields++; - if (UNSET != bottom_offset) + if (bottom_offset != UNSET) fields++; - /* estimate risc mem: worst case is one write per page border + - one write per scan line + syncs + jump (all 2 dwords). Padding - can cause next bpl to start close to a page border. First DMA - region may be smaller than PAGE_SIZE */ - instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines); + /* + * estimate risc mem: worst case is one write per page border + + * one write per scan line + syncs + jump (all 2 dwords). Padding + * can cause next bpl to start close to a page border. First DMA + * region may be smaller than PAGE_SIZE + */ + instructions = fields * (1 + ((bpl + padding) * lines) / + PAGE_SIZE + lines); instructions += 4; risc->size = instructions * 8; risc->dma = 0; risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma); - if (NULL == risc->cpu) + if (!risc->cpu) return -ENOMEM; /* write risc instructions */ rp = risc->cpu; - if (UNSET != top_offset) + if (top_offset != UNSET) rp = cx88_risc_field(rp, sglist, top_offset, 0, bpl, padding, lines, 0, true); - if (UNSET != bottom_offset) + if (bottom_offset != UNSET) rp = cx88_risc_field(rp, sglist, bottom_offset, 0x200, - bpl, padding, lines, 0, top_offset == UNSET); + bpl, padding, lines, 0, + top_offset == UNSET); /* save pointer to jmp instruction address */ risc->jmp = rp; - BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size); + WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); return 0; } +EXPORT_SYMBOL(cx88_risc_buffer); int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc, struct scatterlist *sglist, unsigned int bpl, @@ -180,32 +189,38 @@ int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc, u32 instructions; __le32 *rp; - /* estimate risc mem: worst case is one write per page border + - one write per scan line + syncs + jump (all 2 dwords). Here - there is no padding and no sync. First DMA region may be smaller - than PAGE_SIZE */ + /* + * estimate risc mem: worst case is one write per page border + + * one write per scan line + syncs + jump (all 2 dwords). Here + * there is no padding and no sync. First DMA region may be smaller + * than PAGE_SIZE + */ instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; instructions += 3; risc->size = instructions * 8; risc->dma = 0; risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma); - if (NULL == risc->cpu) + if (!risc->cpu) return -ENOMEM; /* write risc instructions */ rp = risc->cpu; - rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines, lpi, !lpi); + rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, + lines, lpi, !lpi); /* save pointer to jmp instruction address */ risc->jmp = rp; - BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size); + WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); return 0; } +EXPORT_SYMBOL(cx88_risc_databuffer); -/* ------------------------------------------------------------------ */ -/* our SRAM memory layout */ +/* + * our SRAM memory layout + */ -/* we are going to put all thr risc programs into host memory, so we +/* + * we are going to put all thr risc programs into host memory, so we * can use the whole SDRAM for the DMA fifos. To simplify things, we * use a static memory layout. That surely will waste memory in case * we don't use all DMA channels at the same time (which will be the @@ -329,12 +344,13 @@ const struct sram_channel cx88_sram_channels[] = { .cnt2_reg = MO_DMA27_CNT2, }, }; +EXPORT_SYMBOL(cx88_sram_channels); int cx88_sram_channel_setup(struct cx88_core *core, const struct sram_channel *ch, unsigned int bpl, u32 risc) { - unsigned int i,lines; + unsigned int i, lines; u32 cdt; bpl = (bpl + 7) & ~7; /* alignment */ @@ -342,16 +358,16 @@ int cx88_sram_channel_setup(struct cx88_core *core, lines = ch->fifo_size / bpl; if (lines > 6) lines = 6; - BUG_ON(lines < 2); + WARN_ON(lines < 2); /* write CDT */ for (i = 0; i < lines; i++) - cx_write(cdt + 16*i, ch->fifo_start + bpl*i); + cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); /* write CMDS */ cx_write(ch->cmds_start + 0, risc); cx_write(ch->cmds_start + 4, cdt); - cx_write(ch->cmds_start + 8, (lines*16) >> 3); + cx_write(ch->cmds_start + 8, (lines * 16) >> 3); cx_write(ch->cmds_start + 12, ch->ctrl_start); cx_write(ch->cmds_start + 16, 64 >> 2); for (i = 20; i < 64; i += 4) @@ -360,12 +376,13 @@ int cx88_sram_channel_setup(struct cx88_core *core, /* fill registers */ cx_write(ch->ptr1_reg, ch->fifo_start); cx_write(ch->ptr2_reg, cdt); - cx_write(ch->cnt1_reg, (bpl >> 3) -1); - cx_write(ch->cnt2_reg, (lines*16) >> 3); + cx_write(ch->cnt1_reg, (bpl >> 3) - 1); + cx_write(ch->cnt2_reg, (lines * 16) >> 3); - dprintk(2,"sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines); + dprintk(2, "sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines); return 0; } +EXPORT_SYMBOL(cx88_sram_channel_setup); /* ------------------------------------------------------------------ */ /* debug helper code */ @@ -373,23 +390,23 @@ int cx88_sram_channel_setup(struct cx88_core *core, static int cx88_risc_decode(u32 risc) { static const char * const instr[16] = { - [ RISC_SYNC >> 28 ] = "sync", - [ RISC_WRITE >> 28 ] = "write", - [ RISC_WRITEC >> 28 ] = "writec", - [ RISC_READ >> 28 ] = "read", - [ RISC_READC >> 28 ] = "readc", - [ RISC_JUMP >> 28 ] = "jump", - [ RISC_SKIP >> 28 ] = "skip", - [ RISC_WRITERM >> 28 ] = "writerm", - [ RISC_WRITECM >> 28 ] = "writecm", - [ RISC_WRITECR >> 28 ] = "writecr", + [RISC_SYNC >> 28] = "sync", + [RISC_WRITE >> 28] = "write", + [RISC_WRITEC >> 28] = "writec", + [RISC_READ >> 28] = "read", + [RISC_READC >> 28] = "readc", + [RISC_JUMP >> 28] = "jump", + [RISC_SKIP >> 28] = "skip", + [RISC_WRITERM >> 28] = "writerm", + [RISC_WRITECM >> 28] = "writecm", + [RISC_WRITECR >> 28] = "writecr", }; static int const incr[16] = { - [ RISC_WRITE >> 28 ] = 2, - [ RISC_JUMP >> 28 ] = 2, - [ RISC_WRITERM >> 28 ] = 3, - [ RISC_WRITECM >> 28 ] = 3, - [ RISC_WRITECR >> 28 ] = 4, + [RISC_WRITE >> 28] = 2, + [RISC_JUMP >> 28] = 2, + [RISC_WRITERM >> 28] = 3, + [RISC_WRITECM >> 28] = 3, + [RISC_WRITECR >> 28] = 4, }; static const char * const bits[] = { "12", "13", "14", "resync", @@ -399,16 +416,15 @@ static int cx88_risc_decode(u32 risc) }; int i; - printk("0x%08x [ %s", risc, - instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); - for (i = ARRAY_SIZE(bits)-1; i >= 0; i--) + dprintk0("0x%08x [ %s", risc, + instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); + for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) if (risc & (1 << (i + 12))) - printk(" %s",bits[i]); - printk(" count=%d ]\n", risc & 0xfff); + pr_cont(" %s", bits[i]); + pr_cont(" count=%d ]\n", risc & 0xfff); return incr[risc >> 28] ? incr[risc >> 28] : 1; } - void cx88_sram_channel_dump(struct cx88_core *core, const struct sram_channel *ch) { @@ -426,46 +442,41 @@ void cx88_sram_channel_dump(struct cx88_core *core, "line / byte", }; u32 risc; - unsigned int i,j,n; + unsigned int i, j, n; - printk("%s: %s - dma channel status dump\n", - core->name,ch->name); + dprintk0("%s - dma channel status dump\n", ch->name); for (i = 0; i < ARRAY_SIZE(name); i++) - printk("%s: cmds: %-12s: 0x%08x\n", - core->name,name[i], - cx_read(ch->cmds_start + 4*i)); + dprintk0(" cmds: %-12s: 0x%08x\n", + name[i], cx_read(ch->cmds_start + 4 * i)); for (n = 1, i = 0; i < 4; i++) { - risc = cx_read(ch->cmds_start + 4 * (i+11)); - printk("%s: risc%d: ", core->name, i); + risc = cx_read(ch->cmds_start + 4 * (i + 11)); + pr_cont(" risc%d: ", i); if (--n) - printk("0x%08x [ arg #%d ]\n", risc, n); + pr_cont("0x%08x [ arg #%d ]\n", risc, n); else n = cx88_risc_decode(risc); } for (i = 0; i < 16; i += n) { risc = cx_read(ch->ctrl_start + 4 * i); - printk("%s: iq %x: ", core->name, i); + dprintk0(" iq %x: ", i); n = cx88_risc_decode(risc); for (j = 1; j < n; j++) { - risc = cx_read(ch->ctrl_start + 4 * (i+j)); - printk("%s: iq %x: 0x%08x [ arg #%d ]\n", - core->name, i+j, risc, j); + risc = cx_read(ch->ctrl_start + 4 * (i + j)); + pr_cont(" iq %x: 0x%08x [ arg #%d ]\n", + i + j, risc, j); } } - printk("%s: fifo: 0x%08x -> 0x%x\n", - core->name, ch->fifo_start, ch->fifo_start+ch->fifo_size); - printk("%s: ctrl: 0x%08x -> 0x%x\n", - core->name, ch->ctrl_start, ch->ctrl_start+6*16); - printk("%s: ptr1_reg: 0x%08x\n", - core->name,cx_read(ch->ptr1_reg)); - printk("%s: ptr2_reg: 0x%08x\n", - core->name,cx_read(ch->ptr2_reg)); - printk("%s: cnt1_reg: 0x%08x\n", - core->name,cx_read(ch->cnt1_reg)); - printk("%s: cnt2_reg: 0x%08x\n", - core->name,cx_read(ch->cnt2_reg)); + dprintk0("fifo: 0x%08x -> 0x%x\n", + ch->fifo_start, ch->fifo_start + ch->fifo_size); + dprintk0("ctrl: 0x%08x -> 0x%x\n", + ch->ctrl_start, ch->ctrl_start + 6 * 16); + dprintk0(" ptr1_reg: 0x%08x\n", cx_read(ch->ptr1_reg)); + dprintk0(" ptr2_reg: 0x%08x\n", cx_read(ch->ptr2_reg)); + dprintk0(" cnt1_reg: 0x%08x\n", cx_read(ch->cnt1_reg)); + dprintk0(" cnt2_reg: 0x%08x\n", cx_read(ch->cnt2_reg)); } +EXPORT_SYMBOL(cx88_sram_channel_dump); static const char *cx88_pci_irqs[32] = { "vid", "aud", "ts", "vip", "hst", "5", "6", "tm1", @@ -474,25 +485,26 @@ static const char *cx88_pci_irqs[32] = { "i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1" }; -void cx88_print_irqbits(const char *name, const char *tag, const char *strings[], +void cx88_print_irqbits(const char *tag, const char *strings[], int len, u32 bits, u32 mask) { unsigned int i; - printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits); + dprintk0("%s [0x%x]", tag, bits); for (i = 0; i < len; i++) { if (!(bits & (1 << i))) continue; if (strings[i]) - printk(" %s", strings[i]); + pr_cont(" %s", strings[i]); else - printk(" %d", i); + pr_cont(" %d", i); if (!(mask & (1 << i))) continue; - printk("*"); + pr_cont("*"); } - printk("\n"); + pr_cont("\n"); } +EXPORT_SYMBOL(cx88_print_irqbits); /* ------------------------------------------------------------------ */ @@ -505,11 +517,12 @@ int cx88_core_irq(struct cx88_core *core, u32 status) handled++; } if (!handled) - cx88_print_irqbits(core->name, "irq pci", + cx88_print_irqbits("irq pci", cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs), status, core->pci_irqmask); return handled; } +EXPORT_SYMBOL(cx88_core_irq); void cx88_wakeup(struct cx88_core *core, struct cx88_dmaqueue *q, u32 count) @@ -524,6 +537,7 @@ void cx88_wakeup(struct cx88_core *core, list_del(&buf->list); vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); } +EXPORT_SYMBOL(cx88_wakeup); void cx88_shutdown(struct cx88_core *core) { @@ -548,10 +562,11 @@ void cx88_shutdown(struct cx88_core *core) /* stop capturing */ cx_write(VID_CAPTURE_CONTROL, 0); } +EXPORT_SYMBOL(cx88_shutdown); int cx88_reset(struct cx88_core *core) { - dprintk(1,"%s\n",__func__); + dprintk(1, ""); cx88_shutdown(core); /* clear irq status */ @@ -563,13 +578,15 @@ int cx88_reset(struct cx88_core *core) msleep(100); /* init sram */ - cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], 720*4, 0); + cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], + 720 * 4, 0); cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0); cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0); cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0); cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0); cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0); - cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], 188*4, 0); + cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], + 188 * 4, 0); cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0); /* misc init ... */ @@ -597,11 +614,12 @@ int cx88_reset(struct cx88_core *core) /* Reset on-board parts */ cx_write(MO_SRST_IO, 0); - msleep(10); + usleep_range(10000, 20000); cx_write(MO_SRST_IO, 1); return 0; } +EXPORT_SYMBOL(cx88_reset); /* ------------------------------------------------------------------ */ @@ -631,10 +649,11 @@ static inline unsigned int norm_fsc8(v4l2_std_id norm) if (norm & V4L2_STD_NTSC) // All NTSC/M and variants return 28636360; // 3.57954545 MHz +/- 10 Hz - /* SECAM have also different sub carrier for chroma, - but step_db and step_dr, at cx88_set_tvnorm already handles that. - - The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N + /* + * SECAM have also different sub carrier for chroma, + * but step_db and step_dr, at cx88_set_tvnorm already handles that. + * + * The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N */ return 35468950; // 4.43361875 MHz +/- 5 Hz @@ -642,13 +661,12 @@ static inline unsigned int norm_fsc8(v4l2_std_id norm) static inline unsigned int norm_htotal(v4l2_std_id norm) { - - unsigned int fsc4=norm_fsc8(norm)/2; + unsigned int fsc4 = norm_fsc8(norm) / 2; /* returns 4*FSC / vtotal / frames per seconds */ return (norm & V4L2_STD_625_50) ? - ((fsc4+312)/625+12)/25 : - ((fsc4+262)/525*1001+15000)/30000; + ((fsc4 + 312) / 625 + 12) / 25 : + ((fsc4 + 262) / 525 * 1001 + 15000) / 30000; } static inline unsigned int norm_vbipack(v4l2_std_id norm) @@ -656,14 +674,14 @@ static inline unsigned int norm_vbipack(v4l2_std_id norm) return (norm & V4L2_STD_625_50) ? 511 : 400; } -int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int height, - enum v4l2_field field) +int cx88_set_scale(struct cx88_core *core, unsigned int width, + unsigned int height, enum v4l2_field field) { unsigned int swidth = norm_swidth(core->tvnorm); unsigned int sheight = norm_maxh(core->tvnorm); u32 value; - dprintk(1,"set_scale: %dx%d [%s%s,%s]\n", width, height, + dprintk(1, "set_scale: %dx%d [%s%s,%s]\n", width, height, V4L2_FIELD_HAS_TOP(field) ? "T" : "", V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "", v4l2_norm_to_name(core->tvnorm)); @@ -675,30 +693,30 @@ int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int heig value &= 0x3fe; cx_write(MO_HDELAY_EVEN, value); cx_write(MO_HDELAY_ODD, value); - dprintk(1,"set_scale: hdelay 0x%04x (width %d)\n", value,swidth); + dprintk(1, "set_scale: hdelay 0x%04x (width %d)\n", value, swidth); value = (swidth * 4096 / width) - 4096; cx_write(MO_HSCALE_EVEN, value); cx_write(MO_HSCALE_ODD, value); - dprintk(1,"set_scale: hscale 0x%04x\n", value); + dprintk(1, "set_scale: hscale 0x%04x\n", value); cx_write(MO_HACTIVE_EVEN, width); cx_write(MO_HACTIVE_ODD, width); - dprintk(1,"set_scale: hactive 0x%04x\n", width); + dprintk(1, "set_scale: hactive 0x%04x\n", width); // recalc V scale Register (delay is constant) cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm)); cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm)); - dprintk(1,"set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm)); + dprintk(1, "set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm)); value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff; cx_write(MO_VSCALE_EVEN, value); cx_write(MO_VSCALE_ODD, value); - dprintk(1,"set_scale: vscale 0x%04x\n", value); + dprintk(1, "set_scale: vscale 0x%04x\n", value); cx_write(MO_VACTIVE_EVEN, sheight); cx_write(MO_VACTIVE_ODD, sheight); - dprintk(1,"set_scale: vactive 0x%04x\n", sheight); + dprintk(1, "set_scale: vactive 0x%04x\n", sheight); // setup filters value = 0; @@ -709,7 +727,7 @@ int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int heig } if (INPUT(core->input).type == CX88_VMUX_SVIDEO) value |= (1 << 13) | (1 << 5); - if (V4L2_FIELD_INTERLACED == field) + if (field == V4L2_FIELD_INTERLACED) value |= (1 << 3); // VINT (interlaced vertical scaling) if (width < 385) value |= (1 << 0); // 3-tap interpolation @@ -720,10 +738,11 @@ int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int heig cx_andor(MO_FILTER_EVEN, 0x7ffc7f, value); /* preserve PEAKEN, PSEL */ cx_andor(MO_FILTER_ODD, 0x7ffc7f, value); - dprintk(1,"set_scale: filter 0x%04x\n", value); + dprintk(1, "set_scale: filter 0x%04x\n", value); return 0; } +EXPORT_SYMBOL(cx88_set_scale); static const u32 xtal = 28636363; @@ -740,36 +759,36 @@ static int set_pll(struct cx88_core *core, int prescale, u32 ofreq) prescale = 5; pll = ofreq * 8 * prescale * (u64)(1 << 20); - do_div(pll,xtal); + do_div(pll, xtal); reg = (pll & 0x3ffffff) | (pre[prescale] << 26); if (((reg >> 20) & 0x3f) < 14) { - printk("%s/0: pll out of range\n",core->name); + pr_err("pll out of range\n"); return -1; } - dprintk(1,"set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n", + dprintk(1, "set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n", reg, cx_read(MO_PLL_REG), ofreq); cx_write(MO_PLL_REG, reg); for (i = 0; i < 100; i++) { reg = cx_read(MO_DEVICE_STATUS); - if (reg & (1<<2)) { - dprintk(1,"pll locked [pre=%d,ofreq=%d]\n", - prescale,ofreq); + if (reg & (1 << 2)) { + dprintk(1, "pll locked [pre=%d,ofreq=%d]\n", + prescale, ofreq); return 0; } - dprintk(1,"pll not locked yet, waiting ...\n"); - msleep(10); + dprintk(1, "pll not locked yet, waiting ...\n"); + usleep_range(10000, 20000); } - dprintk(1,"pll NOT locked [pre=%d,ofreq=%d]\n",prescale,ofreq); + dprintk(1, "pll NOT locked [pre=%d,ofreq=%d]\n", prescale, ofreq); return -1; } int cx88_start_audio_dma(struct cx88_core *core) { /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */ - int bpl = cx88_sram_channels[SRAM_CH25].fifo_size/4; + int bpl = cx88_sram_channels[SRAM_CH25].fifo_size / 4; - int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size/AUD_RDS_LINES; + int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size / AUD_RDS_LINES; /* If downstream RISC is enabled, bail out; ALSA is managing DMA */ if (cx_read(MO_AUD_DMACNTRL) & 0x10) @@ -806,8 +825,8 @@ static int set_tvaudio(struct cx88_core *core) { v4l2_std_id norm = core->tvnorm; - if (CX88_VMUX_TELEVISION != INPUT(core->input).type && - CX88_VMUX_CABLE != INPUT(core->input).type) + if (INPUT(core->input).type != CX88_VMUX_TELEVISION && + INPUT(core->input).type != CX88_VMUX_CABLE) return 0; if (V4L2_STD_PAL_BG & norm) { @@ -822,7 +841,8 @@ static int set_tvaudio(struct cx88_core *core) } else if (V4L2_STD_SECAM_L & norm) { core->tvaudio = WW_L; - } else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) & norm) { + } else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) & + norm) { core->tvaudio = WW_BG; } else if (V4L2_STD_SECAM_DK & norm) { @@ -836,8 +856,8 @@ static int set_tvaudio(struct cx88_core *core) core->tvaudio = WW_EIAJ; } else { - printk("%s/0: tvaudio support needs work for this tv norm [%s], sorry\n", - core->name, v4l2_norm_to_name(core->tvnorm)); + pr_info("tvaudio support needs work for this tv norm [%s], sorry\n", + v4l2_norm_to_name(core->tvnorm)); core->tvaudio = WW_NONE; return 0; } @@ -847,23 +867,21 @@ static int set_tvaudio(struct cx88_core *core) /* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */ /* - This should be needed only on cx88-alsa. It seems that some cx88 chips have - bugs and does require DMA enabled for it to work. + * This should be needed only on cx88-alsa. It seems that some cx88 chips have + * bugs and does require DMA enabled for it to work. */ cx88_start_audio_dma(core); return 0; } - - int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm) { u32 fsc8; u32 adc_clock; u32 vdec_clock; - u32 step_db,step_dr; + u32 step_db, step_dr; u64 tmp64; - u32 bdelay,agcdelay,htotal; + u32 bdelay, agcdelay, htotal; u32 cxiformat, cxoformat; if (norm == core->tvnorm) @@ -912,62 +930,67 @@ int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm) cxoformat = 0x181f0008; } - dprintk(1,"set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n", + dprintk(1, "set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n", v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock, step_db, step_dr); - set_pll(core,2,vdec_clock); + set_pll(core, 2, vdec_clock); - dprintk(1,"set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n", + dprintk(1, "set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n", cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f); - /* Chroma AGC must be disabled if SECAM is used, we enable it - by default on PAL and NTSC */ + /* + * Chroma AGC must be disabled if SECAM is used, we enable it + * by default on PAL and NTSC + */ cx_andor(MO_INPUT_FORMAT, 0x40f, norm & V4L2_STD_SECAM ? cxiformat : cxiformat | 0x400); // FIXME: as-is from DScaler - dprintk(1,"set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n", + dprintk(1, "set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n", cxoformat, cx_read(MO_OUTPUT_FORMAT)); cx_write(MO_OUTPUT_FORMAT, cxoformat); // MO_SCONV_REG = adc clock / video dec clock * 2^17 tmp64 = adc_clock * (u64)(1 << 17); do_div(tmp64, vdec_clock); - dprintk(1,"set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n", + dprintk(1, "set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n", (u32)tmp64, cx_read(MO_SCONV_REG)); cx_write(MO_SCONV_REG, (u32)tmp64); // MO_SUB_STEP = 8 * fsc / video dec clock * 2^22 tmp64 = step_db * (u64)(1 << 22); do_div(tmp64, vdec_clock); - dprintk(1,"set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n", + dprintk(1, "set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n", (u32)tmp64, cx_read(MO_SUB_STEP)); cx_write(MO_SUB_STEP, (u32)tmp64); // MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22 tmp64 = step_dr * (u64)(1 << 22); do_div(tmp64, vdec_clock); - dprintk(1,"set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n", + dprintk(1, "set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n", (u32)tmp64, cx_read(MO_SUB_STEP_DR)); cx_write(MO_SUB_STEP_DR, (u32)tmp64); // bdelay + agcdelay bdelay = vdec_clock * 65 / 20000000 + 21; agcdelay = vdec_clock * 68 / 20000000 + 15; - dprintk(1,"set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n", - (bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST), bdelay, agcdelay); + dprintk(1, + "set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n", + (bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST), + bdelay, agcdelay); cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay); // htotal tmp64 = norm_htotal(norm) * (u64)vdec_clock; do_div(tmp64, fsc8); htotal = (u32)tmp64; - dprintk(1,"set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n", + dprintk(1, + "set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n", htotal, cx_read(MO_HTOTAL), (u32)tmp64); cx_andor(MO_HTOTAL, 0x07ff, htotal); // vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes // the effective vbi offset ~244 samples, the same as the Bt8x8 - cx_write(MO_VBI_PACKET, (10<<11) | norm_vbipack(norm)); + cx_write(MO_VBI_PACKET, (10 << 11) | norm_vbipack(norm)); // this is needed as well to set all tvnorm parameter cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED); @@ -978,12 +1001,16 @@ int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm) // tell i2c chips call_all(core, video, s_std, norm); - /* The chroma_agc control should be inaccessible if the video format is SECAM */ + /* + * The chroma_agc control should be inaccessible + * if the video format is SECAM + */ v4l2_ctrl_grab(core->chroma_agc, cxiformat == VideoFormatSECAM); // done return 0; } +EXPORT_SYMBOL(cx88_set_tvnorm); /* ------------------------------------------------------------------ */ @@ -1008,8 +1035,9 @@ void cx88_vdev_init(struct cx88_core *core, snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", core->name, type, core->board.name); } +EXPORT_SYMBOL(cx88_vdev_init); -struct cx88_core* cx88_core_get(struct pci_dev *pci) +struct cx88_core *cx88_core_get(struct pci_dev *pci) { struct cx88_core *core; @@ -1020,7 +1048,7 @@ struct cx88_core* cx88_core_get(struct pci_dev *pci) if (PCI_SLOT(pci->devfn) != core->pci_slot) continue; - if (0 != cx88_get_resources(core, pci)) { + if (cx88_get_resources(core, pci) != 0) { mutex_unlock(&devlist); return NULL; } @@ -1030,7 +1058,7 @@ struct cx88_core* cx88_core_get(struct pci_dev *pci) } core = cx88_core_create(pci, cx88_devcount); - if (NULL != core) { + if (core) { cx88_devcount++; list_add_tail(&core->devlist, &cx88_devlist); } @@ -1038,18 +1066,19 @@ struct cx88_core* cx88_core_get(struct pci_dev *pci) mutex_unlock(&devlist); return core; } +EXPORT_SYMBOL(cx88_core_get); void cx88_core_put(struct cx88_core *core, struct pci_dev *pci) { - release_mem_region(pci_resource_start(pci,0), - pci_resource_len(pci,0)); + release_mem_region(pci_resource_start(pci, 0), + pci_resource_len(pci, 0)); if (!atomic_dec_and_test(&core->refcount)) return; mutex_lock(&devlist); cx88_ir_fini(core); - if (0 == core->i2c_rc) { + if (core->i2c_rc == 0) { if (core->i2c_rtc) i2c_unregister_device(core->i2c_rtc); i2c_del_adapter(&core->i2c_adap); @@ -1063,29 +1092,4 @@ void cx88_core_put(struct cx88_core *core, struct pci_dev *pci) v4l2_device_unregister(&core->v4l2_dev); kfree(core); } - -/* ------------------------------------------------------------------ */ - -EXPORT_SYMBOL(cx88_print_irqbits); - -EXPORT_SYMBOL(cx88_core_irq); -EXPORT_SYMBOL(cx88_wakeup); -EXPORT_SYMBOL(cx88_reset); -EXPORT_SYMBOL(cx88_shutdown); - -EXPORT_SYMBOL(cx88_risc_buffer); -EXPORT_SYMBOL(cx88_risc_databuffer); - -EXPORT_SYMBOL(cx88_sram_channels); -EXPORT_SYMBOL(cx88_sram_channel_setup); -EXPORT_SYMBOL(cx88_sram_channel_dump); - -EXPORT_SYMBOL(cx88_set_tvnorm); -EXPORT_SYMBOL(cx88_set_scale); - -EXPORT_SYMBOL(cx88_vdev_init); -EXPORT_SYMBOL(cx88_core_get); EXPORT_SYMBOL(cx88_core_put); - -EXPORT_SYMBOL(cx88_ir_start); -EXPORT_SYMBOL(cx88_ir_stop); |