diff options
Diffstat (limited to 'drivers/net/ethernet/pensando/ionic')
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_dev.c | 14 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_dev.h | 17 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_ethtool.c | 20 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_if.h | 1089 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_lif.c | 158 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_lif.h | 28 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_main.c | 7 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_stats.c | 136 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_stats.h | 6 | ||||
| -rw-r--r-- | drivers/net/ethernet/pensando/ionic/ionic_txrx.c | 49 |
10 files changed, 1058 insertions, 466 deletions
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/ethernet/pensando/ionic/ionic_dev.c index f4ae40ae1e53..d83eff0ae0ac 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_dev.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.c @@ -388,6 +388,19 @@ int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data) } /* LIF commands */ +void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, + u16 lif_type, u8 qtype, u8 qver) +{ + union ionic_dev_cmd cmd = { + .q_identify.opcode = IONIC_CMD_Q_IDENTIFY, + .q_identify.lif_type = lif_type, + .q_identify.type = qtype, + .q_identify.ver = qver, + }; + + ionic_dev_cmd_go(idev, &cmd); +} + void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) { union ionic_dev_cmd cmd = { @@ -431,6 +444,7 @@ void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, .q_init.opcode = IONIC_CMD_Q_INIT, .q_init.lif_index = cpu_to_le16(lif_index), .q_init.type = q->type, + .q_init.ver = qcq->q.lif->qtype_info[q->type].version, .q_init.index = cpu_to_le32(q->index), .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA), diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h index 587398b01997..525434f10025 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h @@ -12,7 +12,8 @@ #define IONIC_MIN_MTU ETH_MIN_MTU #define IONIC_MAX_MTU 9194 -#define IONIC_MAX_TXRX_DESC 16384 +#define IONIC_MAX_TX_DESC 8192 +#define IONIC_MAX_RX_DESC 16384 #define IONIC_MIN_TXRX_DESC 16 #define IONIC_DEF_TXRX_DESC 4096 #define IONIC_LIFS_MAX 1024 @@ -83,6 +84,8 @@ static_assert(sizeof(struct ionic_q_init_cmd) == 64); static_assert(sizeof(struct ionic_q_init_comp) == 16); static_assert(sizeof(struct ionic_q_control_cmd) == 64); static_assert(sizeof(ionic_q_control_comp) == 16); +static_assert(sizeof(struct ionic_q_identify_cmd) == 64); +static_assert(sizeof(struct ionic_q_identify_comp) == 16); static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64); static_assert(sizeof(ionic_rx_mode_set_comp) == 16); @@ -179,7 +182,7 @@ struct ionic_desc_info { void *cb_arg; }; -#define QUEUE_NAME_MAX_SZ 32 +#define IONIC_QUEUE_NAME_MAX_SZ 32 struct ionic_queue { u64 dbell_count; @@ -204,14 +207,14 @@ struct ionic_queue { unsigned int desc_size; unsigned int sg_desc_size; unsigned int pid; - char name[QUEUE_NAME_MAX_SZ]; + char name[IONIC_QUEUE_NAME_MAX_SZ]; }; -#define INTR_INDEX_NOT_ASSIGNED -1 -#define INTR_NAME_MAX_SZ 32 +#define IONIC_INTR_INDEX_NOT_ASSIGNED -1 +#define IONIC_INTR_NAME_MAX_SZ 32 struct ionic_intr_info { - char name[INTR_NAME_MAX_SZ]; + char name[IONIC_INTR_NAME_MAX_SZ]; unsigned int index; unsigned int vector; u64 rearm_count; @@ -283,6 +286,8 @@ void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type); void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type); int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data); +void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, + u16 lif_type, u8 qtype, u8 qver); void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver); void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, dma_addr_t addr); diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c index 6996229facfd..f7e3ce3de04d 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c @@ -12,10 +12,11 @@ #include "ionic_stats.h" static const char ionic_priv_flags_strings[][ETH_GSTRING_LEN] = { -#define PRIV_F_SW_DBG_STATS BIT(0) +#define IONIC_PRIV_F_SW_DBG_STATS BIT(0) "sw-dbg-stats", }; -#define PRIV_FLAGS_COUNT ARRAY_SIZE(ionic_priv_flags_strings) + +#define IONIC_PRIV_FLAGS_COUNT ARRAY_SIZE(ionic_priv_flags_strings) static void ionic_get_stats_strings(struct ionic_lif *lif, u8 *buf) { @@ -58,7 +59,7 @@ static int ionic_get_sset_count(struct net_device *netdev, int sset) count = ionic_get_stats_count(lif); break; case ETH_SS_PRIV_FLAGS: - count = PRIV_FLAGS_COUNT; + count = IONIC_PRIV_FLAGS_COUNT; break; } return count; @@ -75,7 +76,7 @@ static void ionic_get_strings(struct net_device *netdev, break; case ETH_SS_PRIV_FLAGS: memcpy(buf, ionic_priv_flags_strings, - PRIV_FLAGS_COUNT * ETH_GSTRING_LEN); + IONIC_PRIV_FLAGS_COUNT * ETH_GSTRING_LEN); break; } } @@ -159,6 +160,8 @@ static int ionic_get_link_ksettings(struct net_device *netdev, ethtool_link_ksettings_add_link_mode(ks, supported, 100000baseSR4_Full); break; + case IONIC_XCVR_PID_QSFP_100G_CWDM4: + case IONIC_XCVR_PID_QSFP_100G_PSM4: case IONIC_XCVR_PID_QSFP_100G_LR4: ethtool_link_ksettings_add_link_mode(ks, supported, 100000baseLR4_ER4_Full); @@ -178,6 +181,7 @@ static int ionic_get_link_ksettings(struct net_device *netdev, break; case IONIC_XCVR_PID_SFP_25GBASE_SR: case IONIC_XCVR_PID_SFP_25GBASE_AOC: + case IONIC_XCVR_PID_SFP_25GBASE_ACC: ethtool_link_ksettings_add_link_mode(ks, supported, 25000baseSR_Full); break; @@ -458,9 +462,9 @@ static void ionic_get_ringparam(struct net_device *netdev, { struct ionic_lif *lif = netdev_priv(netdev); - ring->tx_max_pending = IONIC_MAX_TXRX_DESC; + ring->tx_max_pending = IONIC_MAX_TX_DESC; ring->tx_pending = lif->ntxq_descs; - ring->rx_max_pending = IONIC_MAX_TXRX_DESC; + ring->rx_max_pending = IONIC_MAX_RX_DESC; ring->rx_pending = lif->nrxq_descs; } @@ -554,7 +558,7 @@ static u32 ionic_get_priv_flags(struct net_device *netdev) u32 priv_flags = 0; if (test_bit(IONIC_LIF_F_SW_DEBUG_STATS, lif->state)) - priv_flags |= PRIV_F_SW_DBG_STATS; + priv_flags |= IONIC_PRIV_F_SW_DBG_STATS; return priv_flags; } @@ -564,7 +568,7 @@ static int ionic_set_priv_flags(struct net_device *netdev, u32 priv_flags) struct ionic_lif *lif = netdev_priv(netdev); clear_bit(IONIC_LIF_F_SW_DEBUG_STATS, lif->state); - if (priv_flags & PRIV_F_SW_DBG_STATS) + if (priv_flags & IONIC_PRIV_F_SW_DBG_STATS) set_bit(IONIC_LIF_F_SW_DEBUG_STATS, lif->state); return 0; diff --git a/drivers/net/ethernet/pensando/ionic/ionic_if.h b/drivers/net/ethernet/pensando/ionic/ionic_if.h index ceeb7629e7a0..7e22ba4ed915 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_if.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_if.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ -/* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */ +/* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ #ifndef _IONIC_IF_H_ #define _IONIC_IF_H_ @@ -9,7 +9,7 @@ #define IONIC_IFNAMSIZ 16 /** - * Commands + * enum ionic_cmd_opcode - Device commands */ enum ionic_cmd_opcode { IONIC_CMD_NOP = 0, @@ -40,6 +40,7 @@ enum ionic_cmd_opcode { IONIC_CMD_RX_FILTER_DEL = 32, /* Queue commands */ + IONIC_CMD_Q_IDENTIFY = 39, IONIC_CMD_Q_INIT = 40, IONIC_CMD_Q_CONTROL = 41, @@ -57,6 +58,7 @@ enum ionic_cmd_opcode { IONIC_CMD_QOS_CLASS_IDENTIFY = 240, IONIC_CMD_QOS_CLASS_INIT = 241, IONIC_CMD_QOS_CLASS_RESET = 242, + IONIC_CMD_QOS_CLASS_UPDATE = 243, /* Firmware commands */ IONIC_CMD_FW_DOWNLOAD = 254, @@ -64,7 +66,7 @@ enum ionic_cmd_opcode { }; /** - * Command Return codes + * enum ionic_status_code - Device command return codes */ enum ionic_status_code { IONIC_RC_SUCCESS = 0, /* Success */ @@ -97,6 +99,7 @@ enum ionic_notifyq_opcode { IONIC_EVENT_RESET = 2, IONIC_EVENT_HEARTBEAT = 3, IONIC_EVENT_LOG = 4, + IONIC_EVENT_XCVR = 5, }; /** @@ -114,12 +117,11 @@ struct ionic_admin_cmd { /** * struct ionic_admin_comp - General admin command completion format - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. - * @cmd_data: Command-specific bytes. - * @color: Color bit. (Always 0 for commands issued to the - * Device Cmd Registers.) + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @cmd_data: Command-specific bytes + * @color: Color bit (Always 0 for commands issued to the + * Device Cmd Registers) */ struct ionic_admin_comp { u8 status; @@ -146,7 +148,7 @@ struct ionic_nop_cmd { /** * struct ionic_nop_comp - NOP command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_nop_comp { u8 status; @@ -156,7 +158,7 @@ struct ionic_nop_comp { /** * struct ionic_dev_init_cmd - Device init command * @opcode: opcode - * @type: device type + * @type: Device type */ struct ionic_dev_init_cmd { u8 opcode; @@ -166,7 +168,7 @@ struct ionic_dev_init_cmd { /** * struct init_comp - Device init command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_dev_init_comp { u8 status; @@ -184,7 +186,7 @@ struct ionic_dev_reset_cmd { /** * struct reset_comp - Reset command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_dev_reset_comp { u8 status; @@ -205,8 +207,8 @@ struct ionic_dev_identify_cmd { }; /** - * struct dev_identify_comp - Driver/device identify command completion - * @status: The status of the command (enum status_code) + * struct ionic_dev_identify_comp - Driver/device identify command completion + * @status: Status of the command (enum ionic_status_code) * @ver: Version of identify returned by device */ struct ionic_dev_identify_comp { @@ -225,8 +227,8 @@ enum ionic_os_type { }; /** - * union drv_identity - driver identity information - * @os_type: OS type (see enum os_type) + * union ionic_drv_identity - driver identity information + * @os_type: OS type (see enum ionic_os_type) * @os_dist: OS distribution, numeric format * @os_dist_str: OS distribution, string format * @kernel_ver: Kernel version, numeric format @@ -242,26 +244,26 @@ union ionic_drv_identity { char kernel_ver_str[32]; char driver_ver_str[32]; }; - __le32 words[512]; + __le32 words[478]; }; /** - * union dev_identity - device identity information + * union ionic_dev_identity - device identity information * @version: Version of device identify * @type: Identify type (0 for now) * @nports: Number of ports provisioned * @nlifs: Number of LIFs provisioned * @nintrs: Number of interrupts provisioned * @ndbpgs_per_lif: Number of doorbell pages per LIF - * @intr_coal_mult: Interrupt coalescing multiplication factor. + * @intr_coal_mult: Interrupt coalescing multiplication factor * Scale user-supplied interrupt coalescing * value in usecs to device units using: * device units = usecs * mult / div - * @intr_coal_div: Interrupt coalescing division factor. + * @intr_coal_div: Interrupt coalescing division factor * Scale user-supplied interrupt coalescing * value in usecs to device units using: * device units = usecs * mult / div - * + * @eq_count: Number of shared event queues */ union ionic_dev_identity { struct { @@ -275,8 +277,9 @@ union ionic_dev_identity { __le32 ndbpgs_per_lif; __le32 intr_coal_mult; __le32 intr_coal_div; + __le32 eq_count; }; - __le32 words[512]; + __le32 words[478]; }; enum ionic_lif_type { @@ -286,10 +289,10 @@ enum ionic_lif_type { }; /** - * struct ionic_lif_identify_cmd - lif identify command + * struct ionic_lif_identify_cmd - LIF identify command * @opcode: opcode - * @type: lif type (enum lif_type) - * @ver: version of identify returned by device + * @type: LIF type (enum ionic_lif_type) + * @ver: Version of identify returned by device */ struct ionic_lif_identify_cmd { u8 opcode; @@ -299,9 +302,9 @@ struct ionic_lif_identify_cmd { }; /** - * struct ionic_lif_identify_comp - lif identify command completion - * @status: status of the command (enum status_code) - * @ver: version of identify returned by device + * struct ionic_lif_identify_comp - LIF identify command completion + * @status: Status of the command (enum ionic_status_code) + * @ver: Version of identify returned by device */ struct ionic_lif_identify_comp { u8 status; @@ -309,13 +312,24 @@ struct ionic_lif_identify_comp { u8 rsvd2[14]; }; +/** + * enum ionic_lif_capability - LIF capabilities + * @IONIC_LIF_CAP_ETH: LIF supports Ethernet + * @IONIC_LIF_CAP_RDMA: LIF support RDMA + */ enum ionic_lif_capability { IONIC_LIF_CAP_ETH = BIT(0), IONIC_LIF_CAP_RDMA = BIT(1), }; /** - * Logical Queue Types + * enum ionic_logical_qtype - Logical Queue Types + * @IONIC_QTYPE_ADMINQ: Administrative Queue + * @IONIC_QTYPE_NOTIFYQ: Notify Queue + * @IONIC_QTYPE_RXQ: Receive Queue + * @IONIC_QTYPE_TXQ: Transmit Queue + * @IONIC_QTYPE_EQ: Event Queue + * @IONIC_QTYPE_MAX: Max queue type supported */ enum ionic_logical_qtype { IONIC_QTYPE_ADMINQ = 0, @@ -327,10 +341,10 @@ enum ionic_logical_qtype { }; /** - * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue type. - * @qtype: Hardware Queue Type. - * @qid_count: Number of Queue IDs of the logical type. - * @qid_base: Minimum Queue ID of the logical type. + * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type + * @qtype: Hardware Queue Type + * @qid_count: Number of Queue IDs of the logical type + * @qid_base: Minimum Queue ID of the logical type */ struct ionic_lif_logical_qtype { u8 qtype; @@ -339,6 +353,12 @@ struct ionic_lif_logical_qtype { __le32 qid_base; }; +/** + * enum ionic_lif_state - LIF state + * @IONIC_LIF_DISABLE: LIF disabled + * @IONIC_LIF_ENABLE: LIF enabled + * @IONIC_LIF_HANG_RESET: LIF hung, being reset + */ enum ionic_lif_state { IONIC_LIF_DISABLE = 0, IONIC_LIF_ENABLE = 1, @@ -346,13 +366,13 @@ enum ionic_lif_state { }; /** - * LIF configuration - * @state: lif state (enum lif_state) - * @name: lif name - * @mtu: mtu - * @mac: station mac address - * @features: features (enum ionic_eth_hw_features) - * @queue_count: queue counts per queue-type + * union ionic_lif_config - LIF configuration + * @state: LIF state (enum ionic_lif_state) + * @name: LIF name + * @mtu: MTU + * @mac: Station MAC address + * @features: Features (enum ionic_eth_hw_features) + * @queue_count: Queue counts per queue-type */ union ionic_lif_config { struct { @@ -369,37 +389,36 @@ union ionic_lif_config { }; /** - * struct ionic_lif_identity - lif identity information (type-specific) + * struct ionic_lif_identity - LIF identity information (type-specific) * - * @capabilities LIF capabilities + * @capabilities: LIF capabilities * - * Ethernet: - * @version: Ethernet identify structure version. - * @features: Ethernet features supported on this lif type. - * @max_ucast_filters: Number of perfect unicast addresses supported. - * @max_mcast_filters: Number of perfect multicast addresses supported. - * @min_frame_size: Minimum size of frames to be sent - * @max_frame_size: Maximim size of frames to be sent - * @config: LIF config struct with features, mtu, mac, q counts + * @eth: Ethernet identify structure + * @version: Ethernet identify structure version + * @max_ucast_filters: Number of perfect unicast addresses supported + * @max_mcast_filters: Number of perfect multicast addresses supported + * @min_frame_size: Minimum size of frames to be sent + * @max_frame_size: Maximim size of frames to be sent + * @config: LIF config struct with features, mtu, mac, q counts * - * RDMA: - * @version: RDMA version of opcodes and queue descriptors. - * @qp_opcodes: Number of rdma queue pair opcodes supported. - * @admin_opcodes: Number of rdma admin opcodes supported. - * @npts_per_lif: Page table size per lif - * @nmrs_per_lif: Number of memory regions per lif - * @nahs_per_lif: Number of address handles per lif - * @max_stride: Max work request stride. - * @cl_stride: Cache line stride. - * @pte_stride: Page table entry stride. - * @rrq_stride: Remote RQ work request stride. - * @rsq_stride: Remote SQ work request stride. + * @rdma: RDMA identify structure + * @version: RDMA version of opcodes and queue descriptors + * @qp_opcodes: Number of RDMA queue pair opcodes supported + * @admin_opcodes: Number of RDMA admin opcodes supported + * @npts_per_lif: Page table size per LIF + * @nmrs_per_lif: Number of memory regions per LIF + * @nahs_per_lif: Number of address handles per LIF + * @max_stride: Max work request stride + * @cl_stride: Cache line stride + * @pte_stride: Page table entry stride + * @rrq_stride: Remote RQ work request stride + * @rsq_stride: Remote SQ work request stride * @dcqcn_profiles: Number of DCQCN profiles - * @aq_qtype: RDMA Admin Qtype. - * @sq_qtype: RDMA Send Qtype. - * @rq_qtype: RDMA Receive Qtype. - * @cq_qtype: RDMA Completion Qtype. - * @eq_qtype: RDMA Event Qtype. + * @aq_qtype: RDMA Admin Qtype + * @sq_qtype: RDMA Send Qtype + * @rq_qtype: RDMA Receive Qtype + * @cq_qtype: RDMA Completion Qtype + * @eq_qtype: RDMA Event Qtype */ union ionic_lif_identity { struct { @@ -439,15 +458,15 @@ union ionic_lif_identity { struct ionic_lif_logical_qtype eq_qtype; } __packed rdma; } __packed; - __le32 words[512]; + __le32 words[478]; }; /** * struct ionic_lif_init_cmd - LIF init command - * @opcode: opcode - * @type: LIF type (enum lif_type) + * @opcode: Opcode + * @type: LIF type (enum ionic_lif_type) * @index: LIF index - * @info_pa: destination address for lif info (struct ionic_lif_info) + * @info_pa: Destination address for LIF info (struct ionic_lif_info) */ struct ionic_lif_init_cmd { u8 opcode; @@ -460,7 +479,8 @@ struct ionic_lif_init_cmd { /** * struct ionic_lif_init_comp - LIF init command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) + * @hw_index: Hardware index of the initialized LIF */ struct ionic_lif_init_comp { u8 status; @@ -469,14 +489,74 @@ struct ionic_lif_init_comp { u8 rsvd2[12]; }; + /** + * struct ionic_q_identify_cmd - queue identify command + * @opcode: opcode + * @lif_type: LIF type (enum ionic_lif_type) + * @type: Logical queue type (enum ionic_logical_qtype) + * @ver: Highest queue type version that the driver supports + */ +struct ionic_q_identify_cmd { + u8 opcode; + u8 rsvd; + __le16 lif_type; + u8 type; + u8 ver; + u8 rsvd2[58]; +}; + +/** + * struct ionic_q_identify_comp - queue identify command completion + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @ver: Queue type version that can be used with FW + */ +struct ionic_q_identify_comp { + u8 status; + u8 rsvd; + __le16 comp_index; + u8 ver; + u8 rsvd2[11]; +}; + +/** + * union ionic_q_identity - queue identity information + * @version: Queue type version that can be used with FW + * @supported: Bitfield of queue versions, first bit = ver 0 + * @features: Queue features + * @desc_sz: Descriptor size + * @comp_sz: Completion descriptor size + * @sg_desc_sz: Scatter/Gather descriptor size + * @max_sg_elems: Maximum number of Scatter/Gather elements + * @sg_desc_stride: Number of Scatter/Gather elements per descriptor + */ +union ionic_q_identity { + struct { + u8 version; + u8 supported; + u8 rsvd[6]; +#define IONIC_QIDENT_F_CQ 0x01 /* queue has completion ring */ +#define IONIC_QIDENT_F_SG 0x02 /* queue has scatter/gather ring */ +#define IONIC_QIDENT_F_EQ 0x04 /* queue can use event queue */ +#define IONIC_QIDENT_F_CMB 0x08 /* queue is in cmb bar */ + __le64 features; + __le16 desc_sz; + __le16 comp_sz; + __le16 sg_desc_sz; + __le16 max_sg_elems; + __le16 sg_desc_stride; + }; + __le32 words[478]; +}; + /** * struct ionic_q_init_cmd - Queue init command * @opcode: opcode * @type: Logical queue type - * @ver: Queue version (defines opcode/descriptor scope) + * @ver: Queue type version * @lif_index: LIF index - * @index: (lif, qtype) relative admin queue index - * @intr_index: Interrupt control register index + * @index: (LIF, qtype) relative admin queue index + * @intr_index: Interrupt control register index, or Event queue index * @pid: Process ID * @flags: * IRQ: Interrupt requested on completion @@ -494,12 +574,11 @@ struct ionic_lif_init_comp { * descriptors. Values of ring_size <2 and >16 are * reserved. * EQ: Enable the Event Queue - * @cos: Class of service for this queue. + * @cos: Class of service for this queue * @ring_size: Queue ring size, encoded as a log2(size) * @ring_base: Queue ring base address * @cq_ring_base: Completion queue ring base address * @sg_ring_base: Scatter/Gather ring base address - * @eq_index: Event queue index */ struct ionic_q_init_cmd { u8 opcode; @@ -516,29 +595,27 @@ struct ionic_q_init_cmd { #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ -#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ +#define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ +#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ u8 cos; u8 ring_size; __le64 ring_base; __le64 cq_ring_base; __le64 sg_ring_base; - __le32 eq_index; - u8 rsvd2[16]; + u8 rsvd2[20]; } __packed; /** * struct ionic_q_init_comp - Queue init command completion - * @status: The status of the command (enum status_code) - * @ver: Queue version (defines opcode/descriptor scope) - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion * @hw_index: Hardware Queue ID * @hw_type: Hardware Queue type * @color: Color */ struct ionic_q_init_comp { u8 status; - u8 ver; + u8 rsvd; __le16 comp_index; __le32 hw_index; u8 hw_type; @@ -559,10 +636,9 @@ enum ionic_txq_desc_opcode { /** * struct ionic_txq_desc - Ethernet Tx queue descriptor format - * @opcode: Tx operation, see TXQ_DESC_OPCODE_*: + * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: * * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: - * * Non-offload send. No segmentation, * fragmentation or checksum calc/insertion is * performed by device; packet is prepared @@ -570,7 +646,6 @@ enum ionic_txq_desc_opcode { * no further manipulation from device. * * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: - * * Offload 16-bit L4 checksum * calculation/insertion. The device will * calculate the L4 checksum value and @@ -579,14 +654,16 @@ enum ionic_txq_desc_opcode { * is calculated starting at @csum_start bytes * into the packet to the end of the packet. * The checksum insertion position is given - * in @csum_offset. This feature is only - * applicable to protocols such as TCP, UDP - * and ICMP where a standard (i.e. the - * 'IP-style' checksum) one's complement - * 16-bit checksum is used, using an IP - * pseudo-header to seed the calculation. - * Software will preload the L4 checksum - * field with the IP pseudo-header checksum. + * in @csum_offset, which is the offset from + * @csum_start to the checksum field in the L4 + * header. This feature is only applicable to + * protocols such as TCP, UDP and ICMP where a + * standard (i.e. the 'IP-style' checksum) + * one's complement 16-bit checksum is used, + * using an IP pseudo-header to seed the + * calculation. Software will preload the L4 + * checksum field with the IP pseudo-header + * checksum. * * For tunnel encapsulation, @csum_start and * @csum_offset refer to the inner L4 @@ -602,7 +679,6 @@ enum ionic_txq_desc_opcode { * for more info). * * IONIC_TXQ_DESC_OPCODE_CSUM_HW: - * * Offload 16-bit checksum computation to hardware. * If @csum_l3 is set then the packet's L3 checksum is * updated. Similarly, if @csum_l4 is set the the L4 @@ -610,7 +686,6 @@ enum ionic_txq_desc_opcode { * checksums are also updated. * * IONIC_TXQ_DESC_OPCODE_TSO: - * * Device preforms TCP segmentation offload * (TSO). @hdr_len is the number of bytes * to the end of TCP header (the offset to @@ -637,40 +712,41 @@ enum ionic_txq_desc_opcode { * clear CWR in remaining segments. * @flags: * vlan: - * Insert an L2 VLAN header using @vlan_tci. + * Insert an L2 VLAN header using @vlan_tci * encap: - * Calculate encap header checksum. + * Calculate encap header checksum * csum_l3: - * Compute L3 header checksum. + * Compute L3 header checksum * csum_l4: - * Compute L4 header checksum. + * Compute L4 header checksum * tso_sot: * TSO start * tso_eot: * TSO end * @num_sg_elems: Number of scatter-gather elements in SG * descriptor - * @addr: First data buffer's DMA address. - * (Subsequent data buffers are on txq_sg_desc). + * @addr: First data buffer's DMA address + * (Subsequent data buffers are on txq_sg_desc) * @len: First data buffer's length, in bytes * @vlan_tci: VLAN tag to insert in the packet (if requested * by @V-bit). Includes .1p and .1q tags * @hdr_len: Length of packet headers, including - * encapsulating outer header, if applicable. - * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and - * TXQ_DESC_OPCODE_TSO. Should be set to zero for + * encapsulating outer header, if applicable + * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and + * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for * all other modes. For - * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length + * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length * of headers up to inner-most L4 header. For - * TXQ_DESC_OPCODE_TSO, @hdr_len is up to + * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to * inner-most L4 payload, so inclusive of * inner-most L4 header. - * @mss: Desired MSS value for TSO. Only applicable for - * TXQ_DESC_OPCODE_TSO. - * @csum_start: Offset into inner-most L3 header of checksum - * @csum_offset: Offset into inner-most L4 header of checksum + * @mss: Desired MSS value for TSO; only applicable for + * IONIC_TXQ_DESC_OPCODE_TSO + * @csum_start: Offset from packet to first byte checked in L4 checksum + * @csum_offset: Offset from csum_start to L4 checksum field */ - +struct ionic_txq_desc { + __le64 cmd; #define IONIC_TXQ_DESC_OPCODE_MASK 0xf #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf @@ -692,8 +768,6 @@ enum ionic_txq_desc_opcode { #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 -struct ionic_txq_desc { - __le64 cmd; __le16 len; union { __le16 vlan_tci; @@ -733,28 +807,38 @@ static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; }; -#define IONIC_TX_MAX_SG_ELEMS 8 -#define IONIC_RX_MAX_SG_ELEMS 8 - /** - * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list + * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element * @addr: DMA address of SG element data buffer * @len: Length of SG element data buffer, in bytes */ +struct ionic_txq_sg_elem { + __le64 addr; + __le16 len; + __le16 rsvd[3]; +}; + +/** + * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list + * @elems: Scatter-gather elements + */ struct ionic_txq_sg_desc { - struct ionic_txq_sg_elem { - __le64 addr; - __le16 len; - __le16 rsvd[3]; - } elems[IONIC_TX_MAX_SG_ELEMS]; +#define IONIC_TX_MAX_SG_ELEMS 8 +#define IONIC_TX_SG_DESC_STRIDE 8 + struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; +}; + +struct ionic_txq_sg_desc_v1 { +#define IONIC_TX_MAX_SG_ELEMS_V1 15 +#define IONIC_TX_SG_DESC_STRIDE_V1 16 + struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; }; /** * struct ionic_txq_comp - Ethernet transmit queue completion descriptor - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. - * @color: Color bit. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @color: Color bit */ struct ionic_txq_comp { u8 status; @@ -771,16 +855,15 @@ enum ionic_rxq_desc_opcode { /** * struct ionic_rxq_desc - Ethernet Rx queue descriptor format - * @opcode: Rx operation, see RXQ_DESC_OPCODE_*: - * - * RXQ_DESC_OPCODE_SIMPLE: + * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: * + * IONIC_RXQ_DESC_OPCODE_SIMPLE: * Receive full packet into data buffer * starting at @addr. Results of * receive, including actual bytes received, * are recorded in Rx completion descriptor. * - * @len: Data buffer's length, in bytes. + * @len: Data buffer's length, in bytes * @addr: Data buffer's DMA address */ struct ionic_rxq_desc { @@ -791,26 +874,33 @@ struct ionic_rxq_desc { }; /** - * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list + * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element * @addr: DMA address of SG element data buffer * @len: Length of SG element data buffer, in bytes */ +struct ionic_rxq_sg_elem { + __le64 addr; + __le16 len; + __le16 rsvd[3]; +}; + +/** + * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list + * @elems: Scatter-gather elements + */ struct ionic_rxq_sg_desc { - struct ionic_rxq_sg_elem { - __le64 addr; - __le16 len; - __le16 rsvd[3]; - } elems[IONIC_RX_MAX_SG_ELEMS]; +#define IONIC_RX_MAX_SG_ELEMS 8 +#define IONIC_RX_SG_DESC_STRIDE 8 + struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; }; /** * struct ionic_rxq_comp - Ethernet receive queue completion descriptor - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @num_sg_elems: Number of SG elements used by this descriptor - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @comp_index: Index in the descriptor ring for which this is the completion * @rss_hash: 32-bit RSS hash - * @csum: 16-bit sum of the packet's L2 payload. + * @csum: 16-bit sum of the packet's L2 payload * If the packet's L2 payload is odd length, an extra * zero-value byte is included in the @csum calculation but * not included in @len. @@ -818,33 +908,51 @@ struct ionic_rxq_sg_desc { * set. Includes .1p and .1q tags. * @len: Received packet length, in bytes. Excludes FCS. * @csum_calc L2 payload checksum is computed or not - * @csum_tcp_ok: The TCP checksum calculated by the device - * matched the checksum in the receive packet's - * TCP header - * @csum_tcp_bad: The TCP checksum calculated by the device did - * not match the checksum in the receive packet's - * TCP header. - * @csum_udp_ok: The UDP checksum calculated by the device - * matched the checksum in the receive packet's - * UDP header - * @csum_udp_bad: The UDP checksum calculated by the device did - * not match the checksum in the receive packet's - * UDP header. - * @csum_ip_ok: The IPv4 checksum calculated by the device - * matched the checksum in the receive packet's - * first IPv4 header. If the receive packet - * contains both a tunnel IPv4 header and a - * transport IPv4 header, the device validates the - * checksum for the both IPv4 headers. - * @csum_ip_bad: The IPv4 checksum calculated by the device did - * not match the checksum in the receive packet's - * first IPv4 header. If the receive packet - * contains both a tunnel IPv4 header and a - * transport IPv4 header, the device validates the - * checksum for both IP headers. - * @VLAN: VLAN header was stripped and placed in @vlan_tci. - * @pkt_type: Packet type - * @color: Color bit. + * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: + * + * IONIC_RXQ_COMP_CSUM_F_TCP_OK: + * The TCP checksum calculated by the device + * matched the checksum in the receive packet's + * TCP header. + * + * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: + * The TCP checksum calculated by the device did + * not match the checksum in the receive packet's + * TCP header. + * + * IONIC_RXQ_COMP_CSUM_F_UDP_OK: + * The UDP checksum calculated by the device + * matched the checksum in the receive packet's + * UDP header + * + * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: + * The UDP checksum calculated by the device did + * not match the checksum in the receive packet's + * UDP header. + * + * IONIC_RXQ_COMP_CSUM_F_IP_OK: + * The IPv4 checksum calculated by the device + * matched the checksum in the receive packet's + * first IPv4 header. If the receive packet + * contains both a tunnel IPv4 header and a + * transport IPv4 header, the device validates the + * checksum for the both IPv4 headers. + * + * IONIC_RXQ_COMP_CSUM_F_IP_BAD: + * The IPv4 checksum calculated by the device did + * not match the checksum in the receive packet's + * first IPv4 header. If the receive packet + * contains both a tunnel IPv4 header and a + * transport IPv4 header, the device validates the + * checksum for both IP headers. + * + * IONIC_RXQ_COMP_CSUM_F_VLAN: + * The VLAN header was stripped and placed in @vlan_tci. + * + * IONIC_RXQ_COMP_CSUM_F_CALC: + * The checksum was calculated by the device. + * + * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK */ struct ionic_rxq_comp { u8 status; @@ -891,8 +999,8 @@ enum ionic_eth_hw_features { IONIC_ETH_HW_TSO_ECN = BIT(10), IONIC_ETH_HW_TSO_GRE = BIT(11), IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), - IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), - IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), + IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), + IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), IONIC_ETH_HW_TSO_UDP = BIT(15), IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), }; @@ -923,7 +1031,10 @@ enum q_control_oper { }; /** - * Physical connection type + * enum ionic_phy_type - Physical connection type + * @IONIC_PHY_TYPE_NONE: No PHY installed + * @IONIC_PHY_TYPE_COPPER: Copper PHY + * @IONIC_PHY_TYPE_FIBER: Fiber PHY */ enum ionic_phy_type { IONIC_PHY_TYPE_NONE = 0, @@ -932,18 +1043,23 @@ enum ionic_phy_type { }; /** - * Transceiver status + * enum ionic_xcvr_state - Transceiver status + * @IONIC_XCVR_STATE_REMOVED: Transceiver removed + * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted + * @IONIC_XCVR_STATE_PENDING: Transceiver pending + * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read + * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error */ enum ionic_xcvr_state { IONIC_XCVR_STATE_REMOVED = 0, IONIC_XCVR_STATE_INSERTED = 1, IONIC_XCVR_STATE_PENDING = 2, IONIC_XCVR_STATE_SPROM_READ = 3, - IONIC_XCVR_STATE_SPROM_READ_ERR = 4, + IONIC_XCVR_STATE_SPROM_READ_ERR = 4, }; /** - * Supported link modes + * enum ionic_xcvr_pid - Supported link modes */ enum ionic_xcvr_pid { IONIC_XCVR_PID_UNKNOWN = 0, @@ -977,64 +1093,83 @@ enum ionic_xcvr_pid { IONIC_XCVR_PID_SFP_10GBASE_CU = 68, IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, + IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, }; /** - * Port types + * enum ionic_port_type - Port types + * @IONIC_PORT_TYPE_NONE: Port type not configured + * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) + * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) */ enum ionic_port_type { - IONIC_PORT_TYPE_NONE = 0, /* port type not configured */ - IONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */ - IONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */ + IONIC_PORT_TYPE_NONE = 0, + IONIC_PORT_TYPE_ETH = 1, + IONIC_PORT_TYPE_MGMT = 2, }; /** - * Port config state + * enum ionic_port_admin_state - Port config state + * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured + * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled + * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled */ enum ionic_port_admin_state { - IONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */ - IONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */ - IONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */ + IONIC_PORT_ADMIN_STATE_NONE = 0, + IONIC_PORT_ADMIN_STATE_DOWN = 1, + IONIC_PORT_ADMIN_STATE_UP = 2, }; /** - * Port operational status + * enum ionic_port_oper_status - Port operational status + * @IONIC_PORT_OPER_STATUS_NONE: Port disabled + * @IONIC_PORT_OPER_STATUS_UP: Port link status up + * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down */ enum ionic_port_oper_status { - IONIC_PORT_OPER_STATUS_NONE = 0, /* port is disabled */ - IONIC_PORT_OPER_STATUS_UP = 1, /* port is linked up */ - IONIC_PORT_OPER_STATUS_DOWN = 2, /* port link status is down */ + IONIC_PORT_OPER_STATUS_NONE = 0, + IONIC_PORT_OPER_STATUS_UP = 1, + IONIC_PORT_OPER_STATUS_DOWN = 2, }; /** - * Ethernet Forward error correction (fec) modes + * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes + * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled + * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC + * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC */ enum ionic_port_fec_type { - IONIC_PORT_FEC_TYPE_NONE = 0, /* Disabled */ - IONIC_PORT_FEC_TYPE_FC = 1, /* FireCode */ - IONIC_PORT_FEC_TYPE_RS = 2, /* ReedSolomon */ + IONIC_PORT_FEC_TYPE_NONE = 0, + IONIC_PORT_FEC_TYPE_FC = 1, + IONIC_PORT_FEC_TYPE_RS = 2, }; /** - * Ethernet pause (flow control) modes + * enum ionic_port_pause_type - Ethernet pause (flow control) modes + * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause + * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause + * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control */ enum ionic_port_pause_type { - IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */ - IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */ - IONIC_PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */ + IONIC_PORT_PAUSE_TYPE_NONE = 0, + IONIC_PORT_PAUSE_TYPE_LINK = 1, + IONIC_PORT_PAUSE_TYPE_PFC = 2, }; /** - * Loopback modes + * enum ionic_port_loopback_mode - Loopback modes + * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback + * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback + * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback */ enum ionic_port_loopback_mode { - IONIC_PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */ - IONIC_PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */ - IONIC_PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */ + IONIC_PORT_LOOPBACK_MODE_NONE = 0, + IONIC_PORT_LOOPBACK_MODE_MAC = 1, + IONIC_PORT_LOOPBACK_MODE_PHY = 2, }; /** - * Transceiver Status information + * struct ionic_xcvr_status - Transceiver Status information * @state: Transceiver status (enum ionic_xcvr_state) * @phy: Physical connection type (enum ionic_phy_type) * @pid: Transceiver link mode (enum pid) @@ -1048,7 +1183,7 @@ struct ionic_xcvr_status { }; /** - * Port configuration + * union ionic_port_config - Port configuration * @speed: port speed (in Mbps) * @mtu: mtu * @state: port admin state (enum port_admin_state) @@ -1081,17 +1216,21 @@ union ionic_port_config { }; /** - * Port Status information + * struct ionic_port_status - Port Status information * @status: link status (enum ionic_port_oper_status) * @id: port id * @speed: link speed (in Mbps) + * @link_down_count: number of times link went from from up to down + * @fec_type: fec type (enum ionic_port_fec_type) * @xcvr: tranceiver status */ struct ionic_port_status { __le32 id; __le32 speed; u8 status; - u8 rsvd[51]; + __le16 link_down_count; + u8 fec_type; + u8 rsvd[48]; struct ionic_xcvr_status xcvr; } __packed; @@ -1110,7 +1249,7 @@ struct ionic_port_identify_cmd { /** * struct ionic_port_identify_comp - Port identify command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @ver: Version of identify returned by device */ struct ionic_port_identify_comp { @@ -1135,7 +1274,7 @@ struct ionic_port_init_cmd { /** * struct ionic_port_init_comp - Port initialization command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_port_init_comp { u8 status; @@ -1155,7 +1294,7 @@ struct ionic_port_reset_cmd { /** * struct ionic_port_reset_comp - Port reset command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) */ struct ionic_port_reset_comp { u8 status; @@ -1163,15 +1302,23 @@ struct ionic_port_reset_comp { }; /** - * enum stats_ctl_cmd - List of commands for stats control + * enum ionic_stats_ctl_cmd - List of commands for stats control + * @IONIC_STATS_CTL_RESET: Reset statistics */ enum ionic_stats_ctl_cmd { IONIC_STATS_CTL_RESET = 0, }; - /** * enum ionic_port_attr - List of device attributes + * @IONIC_PORT_ATTR_STATE: Port state attribute + * @IONIC_PORT_ATTR_SPEED: Port speed attribute + * @IONIC_PORT_ATTR_MTU: Port MTU attribute + * @IONIC_PORT_ATTR_AUTONEG: Port autonegotation attribute + * @IONIC_PORT_ATTR_FEC: Port FEC attribute + * @IONIC_PORT_ATTR_PAUSE: Port pause attribute + * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute + * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute */ enum ionic_port_attr { IONIC_PORT_ATTR_STATE = 0, @@ -1186,9 +1333,17 @@ enum ionic_port_attr { /** * struct ionic_port_setattr_cmd - Set port attributes on the NIC - * @opcode: Opcode - * @index: port index - * @attr: Attribute type (enum ionic_port_attr) + * @opcode: Opcode + * @index: Port index + * @attr: Attribute type (enum ionic_port_attr) + * @state: Port state + * @speed: Port speed + * @mtu: Port MTU + * @an_enable: Port autonegotiation setting + * @fec_type: Port FEC type setting + * @pause_type: Port pause type setting + * @loopback_mode: Port loopback mode + * @stats_ctl: Port stats setting */ struct ionic_port_setattr_cmd { u8 opcode; @@ -1203,14 +1358,14 @@ struct ionic_port_setattr_cmd { u8 fec_type; u8 pause_type; u8 loopback_mode; - u8 stats_ctl; + u8 stats_ctl; u8 rsvd2[60]; }; }; /** * struct ionic_port_setattr_comp - Port set attr command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @color: Color bit */ struct ionic_port_setattr_comp { @@ -1234,8 +1389,15 @@ struct ionic_port_getattr_cmd { /** * struct ionic_port_getattr_comp - Port get attr command completion - * @status: The status of the command (enum status_code) - * @color: Color bit + * @status: Status of the command (enum ionic_status_code) + * @state: Port state + * @speed: Port speed + * @mtu: Port MTU + * @an_enable: Port autonegotiation setting + * @fec_type: Port FEC type setting + * @pause_type: Port pause type setting + * @loopback_mode: Port loopback mode + * @color: Color bit */ struct ionic_port_getattr_comp { u8 status; @@ -1254,12 +1416,12 @@ struct ionic_port_getattr_comp { }; /** - * struct ionic_lif_status - Lif status register + * struct ionic_lif_status - LIF status register * @eid: most recent NotifyQ event id - * @port_num: port the lif is connected to + * @port_num: port the LIF is connected to * @link_status: port status (enum ionic_port_oper_status) * @link_speed: speed of link in Mbps - * @link_down_count: number of times link status changes + * @link_down_count: number of times link went from up to down */ struct ionic_lif_status { __le64 eid; @@ -1293,6 +1455,9 @@ enum ionic_dev_state { /** * enum ionic_dev_attr - List of device attributes + * @IONIC_DEV_ATTR_STATE: Device state attribute + * @IONIC_DEV_ATTR_NAME: Device name attribute + * @IONIC_DEV_ATTR_FEATURES: Device feature attributes */ enum ionic_dev_attr { IONIC_DEV_ATTR_STATE = 0, @@ -1322,7 +1487,7 @@ struct ionic_dev_setattr_cmd { /** * struct ionic_dev_setattr_comp - Device set attr command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @features: Device features * @color: Color bit */ @@ -1349,7 +1514,7 @@ struct ionic_dev_getattr_cmd { /** * struct ionic_dev_setattr_comp - Device set attr command completion - * @status: The status of the command (enum status_code) + * @status: Status of the command (enum ionic_status_code) * @features: Device features * @color: Color bit */ @@ -1379,6 +1544,13 @@ enum ionic_rss_hash_types { /** * enum ionic_lif_attr - List of LIF attributes + * @IONIC_LIF_ATTR_STATE: LIF state attribute + * @IONIC_LIF_ATTR_NAME: LIF name attribute + * @IONIC_LIF_ATTR_MTU: LIF MTU attribute + * @IONIC_LIF_ATTR_MAC: LIF MAC attribute + * @IONIC_LIF_ATTR_FEATURES: LIF features attribute + * @IONIC_LIF_ATTR_RSS: LIF RSS attribute + * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute */ enum ionic_lif_attr { IONIC_LIF_ATTR_STATE = 0, @@ -1393,18 +1565,18 @@ enum ionic_lif_attr { /** * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC * @opcode: Opcode - * @type: Attribute type (enum ionic_lif_attr) + * @attr: Attribute type (enum ionic_lif_attr) * @index: LIF index - * @state: lif state (enum lif_state) + * @state: LIF state (enum ionic_lif_state) * @name: The netdev name string, 0 terminated * @mtu: Mtu * @mac: Station mac * @features: Features (enum ionic_eth_hw_features) * @rss: RSS properties - * @types: The hash types to enable (see rss_hash_types). - * @key: The hash secret key. - * @addr: Address for the indirection table shared memory. - * @stats_ctl: stats control commands (enum stats_ctl_cmd) + * @types: The hash types to enable (see rss_hash_types) + * @key: The hash secret key + * @addr: Address for the indirection table shared memory + * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) */ struct ionic_lif_setattr_cmd { u8 opcode; @@ -1422,16 +1594,15 @@ struct ionic_lif_setattr_cmd { u8 rsvd[6]; __le64 addr; } rss; - u8 stats_ctl; + u8 stats_ctl; u8 rsvd[60]; } __packed; }; /** * struct ionic_lif_setattr_comp - LIF set attr command completion - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion * @features: features (enum ionic_eth_hw_features) * @color: Color bit */ @@ -1461,10 +1632,9 @@ struct ionic_lif_getattr_cmd { /** * struct ionic_lif_getattr_comp - LIF get attr command completion - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. - * @state: lif state (enum lif_state) + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @state: LIF state (enum ionic_lif_state) * @name: The netdev name string, 0 terminated * @mtu: Mtu * @mac: Station mac @@ -1486,11 +1656,12 @@ struct ionic_lif_getattr_comp { }; enum ionic_rx_mode { - IONIC_RX_MODE_F_UNICAST = BIT(0), - IONIC_RX_MODE_F_MULTICAST = BIT(1), - IONIC_RX_MODE_F_BROADCAST = BIT(2), - IONIC_RX_MODE_F_PROMISC = BIT(3), - IONIC_RX_MODE_F_ALLMULTI = BIT(4), + IONIC_RX_MODE_F_UNICAST = BIT(0), + IONIC_RX_MODE_F_MULTICAST = BIT(1), + IONIC_RX_MODE_F_BROADCAST = BIT(2), + IONIC_RX_MODE_F_PROMISC = BIT(3), + IONIC_RX_MODE_F_ALLMULTI = BIT(4), + IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), }; /** @@ -1498,11 +1669,12 @@ enum ionic_rx_mode { * @opcode: opcode * @lif_index: LIF index * @rx_mode: Rx mode flags: - * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets. - * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets. - * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets. - * IONIC_RX_MODE_F_PROMISC: Accept any packets. - * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets. + * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets + * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets + * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets + * IONIC_RX_MODE_F_PROMISC: Accept any packets + * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets + * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets */ struct ionic_rx_mode_set_cmd { u8 opcode; @@ -1526,9 +1698,14 @@ enum ionic_rx_filter_match_type { * @qtype: Queue type * @lif_index: LIF index * @qid: Queue ID - * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx) - * @vlan: VLAN ID - * @addr: MAC address (network-byte order) + * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) + * @vlan: VLAN filter + * @vlan: VLAN ID + * @mac: MAC filter + * @addr: MAC address (network-byte order) + * @mac_vlan: MACVLAN filter + * @vlan: VLAN ID + * @addr: MAC address (network-byte order) */ struct ionic_rx_filter_add_cmd { u8 opcode; @@ -1553,11 +1730,10 @@ struct ionic_rx_filter_add_cmd { /** * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion - * @status: The status of the command (enum status_code) - * @comp_index: The index in the descriptor ring for which this - * is the completion. + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion * @filter_id: Filter ID - * @color: Color bit. + * @color: Color bit */ struct ionic_rx_filter_add_comp { u8 status; @@ -1584,63 +1760,6 @@ struct ionic_rx_filter_del_cmd { typedef struct ionic_admin_comp ionic_rx_filter_del_comp; -/** - * struct ionic_qos_identify_cmd - QoS identify command - * @opcode: opcode - * @ver: Highest version of identify supported by driver - * - */ -struct ionic_qos_identify_cmd { - u8 opcode; - u8 ver; - u8 rsvd[62]; -}; - -/** - * struct ionic_qos_identify_comp - QoS identify command completion - * @status: The status of the command (enum status_code) - * @ver: Version of identify returned by device - */ -struct ionic_qos_identify_comp { - u8 status; - u8 ver; - u8 rsvd[14]; -}; - -#define IONIC_QOS_CLASS_MAX 7 -#define IONIC_QOS_CLASS_NAME_SZ 32 -#define IONIC_QOS_DSCP_MAX_VALUES 64 - -/** - * enum ionic_qos_class - */ -enum ionic_qos_class { - IONIC_QOS_CLASS_DEFAULT = 0, - IONIC_QOS_CLASS_USER_DEFINED_1 = 1, - IONIC_QOS_CLASS_USER_DEFINED_2 = 2, - IONIC_QOS_CLASS_USER_DEFINED_3 = 3, - IONIC_QOS_CLASS_USER_DEFINED_4 = 4, - IONIC_QOS_CLASS_USER_DEFINED_5 = 5, - IONIC_QOS_CLASS_USER_DEFINED_6 = 6, -}; - -/** - * enum ionic_qos_class_type - Traffic classification criteria - */ -enum ionic_qos_class_type { - IONIC_QOS_CLASS_TYPE_NONE = 0, - IONIC_QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */ - IONIC_QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */ -}; - -/** - * enum ionic_qos_sched_type - Qos class scheduling type - */ -enum ionic_qos_sched_type { - IONIC_QOS_SCHED_TYPE_STRICT = 0, /* Strict priority */ - IONIC_QOS_SCHED_TYPE_DWRR = 1, /* Deficit weighted round-robin */ -}; - enum ionic_vf_attr { IONIC_VF_ATTR_SPOOFCHK = 1, IONIC_VF_ATTR_TRUST = 2, @@ -1652,26 +1771,29 @@ enum ionic_vf_attr { }; /** - * VF link status + * enum ionic_vf_link_status - Virtual Function link status + * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink + * @IONIC_VF_LINK_STATUS_UP: Link always up + * @IONIC_VF_LINK_STATUS_DOWN: Link always down */ enum ionic_vf_link_status { - IONIC_VF_LINK_STATUS_AUTO = 0, /* link state of the uplink */ - IONIC_VF_LINK_STATUS_UP = 1, /* link is always up */ - IONIC_VF_LINK_STATUS_DOWN = 2, /* link is always down */ + IONIC_VF_LINK_STATUS_AUTO = 0, + IONIC_VF_LINK_STATUS_UP = 1, + IONIC_VF_LINK_STATUS_DOWN = 2, }; /** * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC * @opcode: Opcode - * @index: VF index * @attr: Attribute type (enum ionic_vf_attr) - * macaddr mac address - * vlanid vlan ID - * maxrate max Tx rate in Mbps - * spoofchk enable address spoof checking - * trust enable VF trust - * linkstate set link up or down - * stats_pa set DMA address for VF stats + * @vf_index: VF index + * @macaddr: mac address + * @vlanid: vlan ID + * @maxrate: max Tx rate in Mbps + * @spoofchk: enable address spoof checking + * @trust: enable VF trust + * @linkstate: set link up or down + * @stats_pa: set DMA address for VF stats */ struct ionic_vf_setattr_cmd { u8 opcode; @@ -1701,8 +1823,8 @@ struct ionic_vf_setattr_comp { /** * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC * @opcode: Opcode - * @index: VF index * @attr: Attribute type (enum ionic_vf_attr) + * @vf_index: VF index */ struct ionic_vf_getattr_cmd { u8 opcode; @@ -1729,19 +1851,85 @@ struct ionic_vf_getattr_comp { }; /** - * union ionic_qos_config - Qos configuration structure + * struct ionic_qos_identify_cmd - QoS identify command + * @opcode: opcode + * @ver: Highest version of identify supported by driver + * + */ +struct ionic_qos_identify_cmd { + u8 opcode; + u8 ver; + u8 rsvd[62]; +}; + +/** + * struct ionic_qos_identify_comp - QoS identify command completion + * @status: Status of the command (enum ionic_status_code) + * @ver: Version of identify returned by device + */ +struct ionic_qos_identify_comp { + u8 status; + u8 ver; + u8 rsvd[14]; +}; + +#define IONIC_QOS_TC_MAX 8 +/* Capri max supported, should be renamed. */ +#define IONIC_QOS_CLASS_MAX 7 +#define IONIC_QOS_PCP_MAX 8 +#define IONIC_QOS_CLASS_NAME_SZ 32 +#define IONIC_QOS_DSCP_MAX 64 +#define IONIC_QOS_ALL_PCP 0xFF + +/** + * enum ionic_qos_class + */ +enum ionic_qos_class { + IONIC_QOS_CLASS_DEFAULT = 0, + IONIC_QOS_CLASS_USER_DEFINED_1 = 1, + IONIC_QOS_CLASS_USER_DEFINED_2 = 2, + IONIC_QOS_CLASS_USER_DEFINED_3 = 3, + IONIC_QOS_CLASS_USER_DEFINED_4 = 4, + IONIC_QOS_CLASS_USER_DEFINED_5 = 5, + IONIC_QOS_CLASS_USER_DEFINED_6 = 6, +}; + +/** + * enum ionic_qos_class_type - Traffic classification criteria + * @IONIC_QOS_CLASS_TYPE_NONE: No QoS + * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP + * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP + */ +enum ionic_qos_class_type { + IONIC_QOS_CLASS_TYPE_NONE = 0, + IONIC_QOS_CLASS_TYPE_PCP = 1, + IONIC_QOS_CLASS_TYPE_DSCP = 2, +}; + +/** + * enum ionic_qos_sched_type - QoS class scheduling type + * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority + * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin + */ +enum ionic_qos_sched_type { + IONIC_QOS_SCHED_TYPE_STRICT = 0, + IONIC_QOS_SCHED_TYPE_DWRR = 1, +}; + +/** + * union ionic_qos_config - QoS configuration structure * @flags: Configuration flags * IONIC_QOS_CONFIG_F_ENABLE enable - * IONIC_QOS_CONFIG_F_DROP drop/nodrop + * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite - * @sched_type: Qos class scheduling type (enum ionic_qos_sched_type) - * @class_type: Qos class type (enum ionic_qos_class_type) - * @pause_type: Qos pause type (enum ionic_qos_pause_type) - * @name: Qos class name + * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) + * @class_type: QoS class type (enum ionic_qos_class_type) + * @pause_type: QoS pause type (enum ionic_qos_pause_type) + * @name: QoS class name * @mtu: MTU of the class - * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP) - * @dwrr_weight: Qos class scheduling weight + * @pfc_cos: Priority-Flow Control class of service + * @dwrr_weight: QoS class scheduling weight * @strict_rlmt: Rate limit for strict priority scheduling * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP) * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP) @@ -1752,7 +1940,8 @@ struct ionic_vf_getattr_comp { union ionic_qos_config { struct { #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) -#define IONIC_QOS_CONFIG_F_DROP BIT(1) +#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) +/* Used to rewrite PCP or DSCP value. */ #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) u8 flags; @@ -1769,6 +1958,7 @@ union ionic_qos_config { __le64 strict_rlmt; }; /* marking */ + /* Used to rewrite PCP or DSCP value. */ union { u8 rw_dot1q_pcp; u8 rw_ip_dscp; @@ -1778,7 +1968,7 @@ union ionic_qos_config { u8 dot1q_pcp; struct { u8 ndscp; - u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES]; + u8 ip_dscp[IONIC_QOS_DSCP_MAX]; }; }; }; @@ -1797,15 +1987,15 @@ union ionic_qos_identity { u8 version; u8 type; u8 rsvd[62]; - union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; + union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; }; - __le32 words[512]; + __le32 words[478]; }; /** - * struct qos_init_cmd - QoS config init command + * struct ionic_qos_init_cmd - QoS config init command * @opcode: Opcode - * @group: Qos class id + * @group: QoS class id * @info_pa: destination address for qos info */ struct ionic_qos_init_cmd { @@ -1819,8 +2009,9 @@ struct ionic_qos_init_cmd { typedef struct ionic_admin_comp ionic_qos_init_comp; /** - * struct ionic_qos_reset_cmd - Qos config reset command + * struct ionic_qos_reset_cmd - QoS config reset command * @opcode: Opcode + * @group: QoS class id */ struct ionic_qos_reset_cmd { u8 opcode; @@ -1847,10 +2038,16 @@ struct ionic_fw_download_cmd { typedef struct ionic_admin_comp ionic_fw_download_comp; +/** + * enum ionic_fw_control_oper - FW control operations + * @IONIC_FW_RESET: Reset firmware + * @IONIC_FW_INSTALL: Install firmware + * @IONIC_FW_ACTIVATE: Activate firmware + */ enum ionic_fw_control_oper { - IONIC_FW_RESET = 0, /* Reset firmware */ - IONIC_FW_INSTALL = 1, /* Install firmware */ - IONIC_FW_ACTIVATE = 2, /* Activate firmware */ + IONIC_FW_RESET = 0, + IONIC_FW_INSTALL = 1, + IONIC_FW_ACTIVATE = 2, }; /** @@ -1869,8 +2066,10 @@ struct ionic_fw_control_cmd { /** * struct ionic_fw_control_comp - Firmware control copletion - * @opcode: opcode - * @slot: slot where the firmware was installed + * @status: Status of the command (enum ionic_status_code) + * @comp_index: Index in the descriptor ring for which this is the completion + * @slot: Slot where the firmware was installed + * @color: Color bit */ struct ionic_fw_control_comp { u8 status; @@ -1888,11 +2087,11 @@ struct ionic_fw_control_comp { /** * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd * @opcode: opcode - * @lif_index: lif index + * @lif_index: LIF index * - * There is no rdma specific dev command completion struct. Completion uses + * There is no RDMA specific dev command completion struct. Completion uses * the common struct ionic_admin_comp. Only the status is indicated. - * Nonzero status means the LIF does not support rdma. + * Nonzero status means the LIF does not support RDMA. **/ struct ionic_rdma_reset_cmd { u8 opcode; @@ -1904,30 +2103,29 @@ struct ionic_rdma_reset_cmd { /** * struct ionic_rdma_queue_cmd - Create RDMA Queue command * @opcode: opcode, 52, 53 - * @lif_index lif index - * @qid_ver: (qid | (rdma version << 24)) + * @lif_index: LIF index + * @qid_ver: (qid | (RDMA version << 24)) * @cid: intr, eq_id, or cq_id * @dbid: doorbell page id * @depth_log2: log base two of queue depth * @stride_log2: log base two of queue stride * @dma_addr: address of the queue memory - * @xxx_table_index: temporary, but should not need pgtbl for contig. queues. * - * The same command struct is used to create an rdma event queue, completion - * queue, or rdma admin queue. The cid is an interrupt number for an event + * The same command struct is used to create an RDMA event queue, completion + * queue, or RDMA admin queue. The cid is an interrupt number for an event * queue, an event queue id for a completion queue, or a completion queue id - * for an rdma admin queue. + * for an RDMA admin queue. * * The queue created via a dev command must be contiguous in dma space. * * The dev commands are intended only to be used during driver initialization, - * to create queues supporting the rdma admin queue. Other queues, and other - * types of rdma resources like memory regions, will be created and registered - * via the rdma admin queue, and will support a more complete interface + * to create queues supporting the RDMA admin queue. Other queues, and other + * types of RDMA resources like memory regions, will be created and registered + * via the RDMA admin queue, and will support a more complete interface * providing scatter gather lists for larger, scattered queue buffers and * memory registration. * - * There is no rdma specific dev command completion struct. Completion uses + * There is no RDMA specific dev command completion struct. Completion uses * the common struct ionic_admin_comp. Only the status is indicated. **/ struct ionic_rdma_queue_cmd { @@ -1940,8 +2138,7 @@ struct ionic_rdma_queue_cmd { u8 depth_log2; u8 stride_log2; __le64 dma_addr; - u8 rsvd2[36]; - __le32 xxx_table_index; + u8 rsvd2[40]; }; /****************************************************************** @@ -1949,7 +2146,7 @@ struct ionic_rdma_queue_cmd { ******************************************************************/ /** - * struct ionic_notifyq_event + * struct ionic_notifyq_event - Generic event reporting structure * @eid: event number * @ecode: event code * @data: unspecified data about the event @@ -1964,9 +2161,9 @@ struct ionic_notifyq_event { }; /** - * struct ionic_link_change_event + * struct ionic_link_change_event - Link change event notification * @eid: event number - * @ecode: event code = EVENT_OPCODE_LINK_CHANGE + * @ecode: event code = IONIC_EVENT_LINK_CHANGE * @link_status: link up or down, with error bits (enum port_status) * @link_speed: speed of the network link * @@ -1981,9 +2178,9 @@ struct ionic_link_change_event { }; /** - * struct ionic_reset_event + * struct ionic_reset_event - Reset event notification * @eid: event number - * @ecode: event code = EVENT_OPCODE_RESET + * @ecode: event code = IONIC_EVENT_RESET * @reset_code: reset type * @state: 0=pending, 1=complete, 2=error * @@ -1999,11 +2196,9 @@ struct ionic_reset_event { }; /** - * struct ionic_heartbeat_event + * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health * @eid: event number - * @ecode: event code = EVENT_OPCODE_HEARTBEAT - * - * Sent periodically by the NIC to indicate continued health + * @ecode: event code = IONIC_EVENT_HEARTBEAT */ struct ionic_heartbeat_event { __le64 eid; @@ -2012,12 +2207,10 @@ struct ionic_heartbeat_event { }; /** - * struct ionic_log_event + * struct ionic_log_event - Sent to notify the driver of an internal error * @eid: event number - * @ecode: event code = EVENT_OPCODE_LOG + * @ecode: event code = IONIC_EVENT_LOG * @data: log data - * - * Sent to notify the driver of an internal error. */ struct ionic_log_event { __le64 eid; @@ -2026,7 +2219,18 @@ struct ionic_log_event { }; /** - * struct ionic_port_stats + * struct ionic_xcvr_event - Transceiver change event + * @eid: event number + * @ecode: event code = IONIC_EVENT_XCVR + */ +struct ionic_xcvr_event { + __le64 eid; + __le16 ecode; + u8 rsvd[54]; +}; + +/** + * struct ionic_port_stats - Port statistics structure */ struct ionic_port_stats { __le64 frames_rx_ok; @@ -2131,28 +2335,61 @@ struct ionic_mgmt_port_stats { __le64 frames_rx_multicast; __le64 frames_rx_broadcast; __le64 frames_rx_pause; - __le64 frames_rx_bad_length0; - __le64 frames_rx_undersized1; - __le64 frames_rx_oversized2; - __le64 frames_rx_fragments3; - __le64 frames_rx_jabber4; - __le64 frames_rx_64b5; - __le64 frames_rx_65b_127b6; - __le64 frames_rx_128b_255b7; - __le64 frames_rx_256b_511b8; - __le64 frames_rx_512b_1023b9; - __le64 frames_rx_1024b_1518b0; - __le64 frames_rx_gt_1518b1; - __le64 frames_rx_fifo_full2; - __le64 frames_tx_ok3; - __le64 frames_tx_all4; - __le64 frames_tx_bad5; - __le64 octets_tx_ok6; - __le64 octets_tx_total7; - __le64 frames_tx_unicast8; - __le64 frames_tx_multicast9; - __le64 frames_tx_broadcast0; - __le64 frames_tx_pause1; + __le64 frames_rx_bad_length; + __le64 frames_rx_undersized; + __le64 frames_rx_oversized; + __le64 frames_rx_fragments; + __le64 frames_rx_jabber; + __le64 frames_rx_64b; + __le64 frames_rx_65b_127b; + __le64 frames_rx_128b_255b; + __le64 frames_rx_256b_511b; + __le64 frames_rx_512b_1023b; + __le64 frames_rx_1024b_1518b; + __le64 frames_rx_gt_1518b; + __le64 frames_rx_fifo_full; + __le64 frames_tx_ok; + __le64 frames_tx_all; + __le64 frames_tx_bad; + __le64 octets_tx_ok; + __le64 octets_tx_total; + __le64 frames_tx_unicast; + __le64 frames_tx_multicast; + __le64 frames_tx_broadcast; + __le64 frames_tx_pause; +}; + +enum ionic_pb_buffer_drop_stats { + IONIC_BUFFER_INTRINSIC_DROP = 0, + IONIC_BUFFER_DISCARDED, + IONIC_BUFFER_ADMITTED, + IONIC_BUFFER_OUT_OF_CELLS_DROP, + IONIC_BUFFER_OUT_OF_CELLS_DROP_2, + IONIC_BUFFER_OUT_OF_CREDIT_DROP, + IONIC_BUFFER_TRUNCATION_DROP, + IONIC_BUFFER_PORT_DISABLED_DROP, + IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, + IONIC_BUFFER_SPAN_TAIL_DROP, + IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, + IONIC_BUFFER_ENQUEUE_ERROR_DROP, + IONIC_BUFFER_INVALID_PORT_DROP, + IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, + IONIC_BUFFER_DROP_MAX, +}; + +/** + * struct port_pb_stats - packet buffers system stats + * uses ionic_pb_buffer_drop_stats for drop_counts[] + */ +struct ionic_port_pb_stats { + __le64 sop_count_in; + __le64 eop_count_in; + __le64 sop_count_out; + __le64 eop_count_out; + __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; + __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; + __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; + __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; }; /** @@ -2184,22 +2421,31 @@ union ionic_port_identity { u8 rsvd2[44]; union ionic_port_config config; }; - __le32 words[512]; + __le32 words[478]; }; /** * struct ionic_port_info - port info structure - * @port_status: port status - * @port_stats: port stats + * @config: Port configuration data + * @status: Port status data + * @stats: Port statistics data + * @mgmt_stats: Port management statistics data + * @port_pb_drop_stats: uplink pb drop stats */ struct ionic_port_info { union ionic_port_config config; struct ionic_port_status status; - struct ionic_port_stats stats; + union { + struct ionic_port_stats stats; + struct ionic_mgmt_port_stats mgmt_stats; + }; + /* room for pb_stats to start at 2k offset */ + u8 rsvd[760]; + struct ionic_port_pb_stats pb_stats; }; /** - * struct ionic_lif_stats + * struct ionic_lif_stats - LIF statistics structure */ struct ionic_lif_stats { /* RX */ @@ -2252,7 +2498,7 @@ struct ionic_lif_stats { __le64 tx_queue_error; __le64 tx_desc_fetch_error; __le64 tx_desc_data_error; - __le64 rsvd9; + __le64 tx_queue_empty; __le64 rsvd10; __le64 rsvd11; __le64 rsvd12; @@ -2353,7 +2599,10 @@ struct ionic_lif_stats { }; /** - * struct ionic_lif_info - lif info structure + * struct ionic_lif_info - LIF info structure + * @config: LIF configuration structure + * @status: LIF status structure + * @stats: LIF statistics structure */ struct ionic_lif_info { union ionic_lif_config config; @@ -2389,7 +2638,9 @@ union ionic_dev_cmd { struct ionic_qos_init_cmd qos_init; struct ionic_qos_reset_cmd qos_reset; + struct ionic_q_identify_cmd q_identify; struct ionic_q_init_cmd q_init; + struct ionic_q_control_cmd q_control; }; union ionic_dev_cmd_comp { @@ -2421,19 +2672,20 @@ union ionic_dev_cmd_comp { ionic_qos_init_comp qos_init; ionic_qos_reset_comp qos_reset; + struct ionic_q_identify_comp q_identify; struct ionic_q_init_comp q_init; }; /** - * union dev_info - Device info register format (read-only) - * @signature: Signature value of 0x44455649 ('DEVI'). - * @version: Current version of info. - * @asic_type: Asic type. - * @asic_rev: Asic revision. - * @fw_status: Firmware status. - * @fw_heartbeat: Firmware heartbeat counter. - * @serial_num: Serial number. - * @fw_version: Firmware version. + * union ionic_dev_info_regs - Device info register format (read-only) + * @signature: Signature value of 0x44455649 ('DEVI') + * @version: Current version of info + * @asic_type: Asic type + * @asic_rev: Asic revision + * @fw_status: Firmware status + * @fw_heartbeat: Firmware heartbeat counter + * @serial_num: Serial number + * @fw_version: Firmware version */ union ionic_dev_info_regs { #define IONIC_DEVINFO_FWVERS_BUFLEN 32 @@ -2454,10 +2706,10 @@ union ionic_dev_info_regs { /** * union ionic_dev_cmd_regs - Device command register format (read-write) - * @doorbell: Device Cmd Doorbell, write-only. + * @doorbell: Device Cmd Doorbell, write-only * Write a 1 to signal device to process cmd, * poll done for completion. - * @done: Done indicator, bit 0 == 1 when command is complete. + * @done: Done indicator, bit 0 == 1 when command is complete * @cmd: Opcode-specific command bytes * @comp: Opcode-specific response bytes * @data: Opcode-specific side-data @@ -2475,7 +2727,7 @@ union ionic_dev_cmd_regs { }; /** - * union ionic_dev_regs - Device register format in for bar 0 page 0 + * union ionic_dev_regs - Device register format for bar 0 page 0 * @info: Device info registers * @devcmd: Device command registers */ @@ -2490,6 +2742,7 @@ union ionic_dev_regs { union ionic_adminq_cmd { struct ionic_admin_cmd cmd; struct ionic_nop_cmd nop; + struct ionic_q_identify_cmd q_identify; struct ionic_q_init_cmd q_init; struct ionic_q_control_cmd q_control; struct ionic_lif_setattr_cmd lif_setattr; @@ -2506,6 +2759,7 @@ union ionic_adminq_cmd { union ionic_adminq_comp { struct ionic_admin_comp comp; struct ionic_nop_comp nop; + struct ionic_q_identify_comp q_identify; struct ionic_q_init_comp q_init; struct ionic_lif_setattr_comp lif_setattr; struct ionic_lif_getattr_comp lif_getattr; @@ -2531,14 +2785,14 @@ union ionic_adminq_comp { /** * struct ionic_doorbell - Doorbell register layout * @p_index: Producer index - * @ring: Selects the specific ring of the queue to update. + * @ring: Selects the specific ring of the queue to update * Type-specific meaning: - * ring=0: Default producer/consumer queue. + * ring=0: Default producer/consumer queue * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs * send events to EQs when armed. EQs send * interrupts when armed. - * @qid: The queue id selects the queue destination for the - * producer index and flags. + * @qid_lo: Queue destination for the producer index and flags (low bits) + * @qid_hi: Queue destination for the producer index and flags (high bits) */ struct ionic_doorbell { __le16 p_index; @@ -2571,6 +2825,7 @@ struct ionic_identity { union ionic_lif_identity lif; union ionic_port_identity port; union ionic_qos_identity qos; + union ionic_q_identity txq; }; #endif /* _IONIC_IF_H_ */ diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c index f8a9c1bcffc9..7321a92f8395 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c @@ -17,6 +17,16 @@ #include "ionic_ethtool.h" #include "ionic_debugfs.h" +/* queuetype support level */ +static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { + [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ + [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ + [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ + [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support + * 1 = ... with Tx SG version 1 + */ +}; + static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode); static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr); static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr); @@ -27,6 +37,7 @@ static void ionic_lif_set_netdev_info(struct ionic_lif *lif); static int ionic_start_queues(struct ionic_lif *lif); static void ionic_stop_queues(struct ionic_lif *lif); +static void ionic_lif_queue_identify(struct ionic_lif *lif); static void ionic_lif_deferred_work(struct work_struct *work) { @@ -186,10 +197,10 @@ static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) return 0; } -static void ionic_intr_free(struct ionic_lif *lif, int index) +static void ionic_intr_free(struct ionic *ionic, int index) { - if (index != INTR_INDEX_NOT_ASSIGNED && index < lif->ionic->nintrs) - clear_bit(index, lif->ionic->intrs); + if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) + clear_bit(index, ionic->intrs); } static int ionic_qcq_enable(struct ionic_qcq *qcq) @@ -299,7 +310,7 @@ static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) irq_set_affinity_hint(qcq->intr.vector, NULL); devm_free_irq(dev, qcq->intr.vector, &qcq->napi); qcq->intr.vector = 0; - ionic_intr_free(lif, qcq->intr.index); + ionic_intr_free(lif->ionic, qcq->intr.index); } devm_kfree(dev, qcq->cq.info); @@ -345,7 +356,7 @@ static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, struct ionic_qcq *n_qcq) { if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { - ionic_intr_free(n_qcq->cq.lif, n_qcq->intr.index); + ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); n_qcq->flags &= ~IONIC_QCQ_F_INTR; } @@ -444,7 +455,7 @@ static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, cpumask_set_cpu(new->intr.cpu, &new->intr.affinity_mask); } else { - new->intr.index = INTR_INDEX_NOT_ASSIGNED; + new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; } new->cq.info = devm_kzalloc(dev, sizeof(*new->cq.info) * num_descs, @@ -497,7 +508,7 @@ err_out_free_irq: devm_free_irq(dev, new->intr.vector, &new->napi); err_out_free_intr: if (flags & IONIC_QCQ_F_INTR) - ionic_intr_free(lif, new->intr.index); + ionic_intr_free(lif->ionic, new->intr.index); err_out: dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); return err; @@ -597,6 +608,7 @@ static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) .opcode = IONIC_CMD_Q_INIT, .lif_index = cpu_to_le16(lif->index), .type = q->type, + .ver = lif->qtype_info[q->type].version, .index = cpu_to_le32(q->index), .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | IONIC_QINIT_F_SG), @@ -614,6 +626,8 @@ static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); + dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); + dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); q->tail = q->info; q->head = q->tail; @@ -646,6 +660,7 @@ static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) .opcode = IONIC_CMD_Q_INIT, .lif_index = cpu_to_le16(lif->index), .type = q->type, + .ver = lif->qtype_info[q->type].version, .index = cpu_to_le32(q->index), .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | IONIC_QINIT_F_SG), @@ -663,6 +678,8 @@ static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); + dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); + dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); q->tail = q->info; q->head = q->tail; @@ -726,7 +743,7 @@ static bool ionic_notifyq_service(struct ionic_cq *cq, } break; default: - netdev_warn(netdev, "Notifyq unknown event ecode=%d eid=%lld\n", + netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", comp->event.ecode, eid); break; } @@ -775,8 +792,8 @@ static int ionic_adminq_napi(struct napi_struct *napi, int budget) return max(n_work, a_work); } -static void ionic_get_stats64(struct net_device *netdev, - struct rtnl_link_stats64 *ns) +void ionic_get_stats64(struct net_device *netdev, + struct rtnl_link_stats64 *ns) { struct ionic_lif *lif = netdev_priv(netdev); struct ionic_lif_stats *ls; @@ -1509,17 +1526,25 @@ static void ionic_txrx_free(struct ionic_lif *lif) static int ionic_txrx_alloc(struct ionic_lif *lif) { + unsigned int sg_desc_sz; unsigned int flags; unsigned int i; int err = 0; + if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && + lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == + sizeof(struct ionic_txq_sg_desc_v1)) + sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); + else + sg_desc_sz = sizeof(struct ionic_txq_sg_desc); + flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; for (i = 0; i < lif->nxqs; i++) { err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, lif->ntxq_descs, sizeof(struct ionic_txq_desc), sizeof(struct ionic_txq_comp), - sizeof(struct ionic_txq_sg_desc), + sg_desc_sz, lif->kern_pid, &lif->txqcqs[i].qcq); if (err) goto err_out; @@ -1682,7 +1707,7 @@ int ionic_stop(struct net_device *netdev) { struct ionic_lif *lif = netdev_priv(netdev); - if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) + if (!netif_device_present(netdev)) return 0; ionic_stop_queues(lif); @@ -1699,6 +1724,9 @@ static int ionic_get_vf_config(struct net_device *netdev, struct ionic *ionic = lif->ionic; int ret = 0; + if (!netif_device_present(netdev)) + return -EBUSY; + down_read(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -1726,6 +1754,9 @@ static int ionic_get_vf_stats(struct net_device *netdev, int vf, struct ionic_lif_stats *vs; int ret = 0; + if (!netif_device_present(netdev)) + return -EBUSY; + down_read(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -1761,6 +1792,9 @@ static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) return -EINVAL; + if (!netif_device_present(netdev)) + return -EBUSY; + down_write(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -1792,6 +1826,9 @@ static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, if (proto != htons(ETH_P_8021Q)) return -EPROTONOSUPPORT; + if (!netif_device_present(netdev)) + return -EBUSY; + down_write(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -1818,6 +1855,9 @@ static int ionic_set_vf_rate(struct net_device *netdev, int vf, if (tx_min) return -EINVAL; + if (!netif_device_present(netdev)) + return -EBUSY; + down_write(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -1840,6 +1880,9 @@ static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) u8 data = set; /* convert to u8 for config */ int ret; + if (!netif_device_present(netdev)) + return -EBUSY; + down_write(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -1862,6 +1905,9 @@ static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) u8 data = set; /* convert to u8 for config */ int ret; + if (!netif_device_present(netdev)) + return -EBUSY; + down_write(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -1898,6 +1944,9 @@ static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) return -EINVAL; } + if (!netif_device_present(netdev)) + return -EBUSY; + down_write(&ionic->vf_op_lock); if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { @@ -2065,9 +2114,17 @@ int ionic_lifs_alloc(struct ionic *ionic) /* only build the first lif, others are for later features */ set_bit(0, ionic->lifbits); + lif = ionic_lif_alloc(ionic, 0); + if (IS_ERR_OR_NULL(lif)) { + clear_bit(0, ionic->lifbits); + return -ENOMEM; + } - return PTR_ERR_OR_ZERO(lif); + lif->lif_type = IONIC_LIF_TYPE_CLASSIC; + ionic_lif_queue_identify(lif); + + return 0; } static void ionic_lif_reset(struct ionic_lif *lif) @@ -2292,6 +2349,7 @@ static int ionic_lif_notifyq_init(struct ionic_lif *lif) .opcode = IONIC_CMD_Q_INIT, .lif_index = cpu_to_le16(lif->index), .type = q->type, + .ver = lif->qtype_info[q->type].version, .index = cpu_to_le32(q->index), .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA), @@ -2578,6 +2636,80 @@ void ionic_lifs_unregister(struct ionic *ionic) unregister_netdev(ionic->master_lif->netdev); } +static void ionic_lif_queue_identify(struct ionic_lif *lif) +{ + struct ionic *ionic = lif->ionic; + union ionic_q_identity *q_ident; + struct ionic_dev *idev; + int qtype; + int err; + + idev = &lif->ionic->idev; + q_ident = (union ionic_q_identity *)&idev->dev_cmd_regs->data; + + for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { + struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; + + /* filter out the ones we know about */ + switch (qtype) { + case IONIC_QTYPE_ADMINQ: + case IONIC_QTYPE_NOTIFYQ: + case IONIC_QTYPE_RXQ: + case IONIC_QTYPE_TXQ: + break; + default: + continue; + } + + memset(qti, 0, sizeof(*qti)); + + mutex_lock(&ionic->dev_cmd_lock); + ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, + ionic_qtype_versions[qtype]); + err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); + if (!err) { + qti->version = q_ident->version; + qti->supported = q_ident->supported; + qti->features = le64_to_cpu(q_ident->features); + qti->desc_sz = le16_to_cpu(q_ident->desc_sz); + qti->comp_sz = le16_to_cpu(q_ident->comp_sz); + qti->sg_desc_sz = le16_to_cpu(q_ident->sg_desc_sz); + qti->max_sg_elems = le16_to_cpu(q_ident->max_sg_elems); + qti->sg_desc_stride = le16_to_cpu(q_ident->sg_desc_stride); + } + mutex_unlock(&ionic->dev_cmd_lock); + + if (err == -EINVAL) { + dev_err(ionic->dev, "qtype %d not supported\n", qtype); + continue; + } else if (err == -EIO) { + dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); + return; + } else if (err) { + dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", + qtype, err); + return; + } + + dev_dbg(ionic->dev, " qtype[%d].version = %d\n", + qtype, qti->version); + dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", + qtype, qti->supported); + dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", + qtype, qti->features); + dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", + qtype, qti->desc_sz); + dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", + qtype, qti->comp_sz); + dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", + qtype, qti->sg_desc_sz); + dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", + qtype, qti->max_sg_elems); + dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", + qtype, qti->sg_desc_stride); + } +} + int ionic_lif_identify(struct ionic *ionic, u8 lif_type, union ionic_lif_identity *lid) { diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h index 5d4ffda5c05f..c3428034a17b 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h @@ -20,11 +20,13 @@ struct ionic_tx_stats { u64 bytes; u64 clean; u64 linearize; - u64 no_csum; + u64 csum_none; u64 csum; u64 crc32_csum; u64 tso; + u64 tso_bytes; u64 frags; + u64 vlan_inserted; u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR]; }; @@ -38,6 +40,7 @@ struct ionic_rx_stats { u64 csum_error; u64 buffers_posted; u64 dropped; + u64 vlan_stripped; }; #define IONIC_QCQ_F_INITED BIT(0) @@ -114,11 +117,17 @@ struct ionic_lif_sw_stats { u64 rx_packets; u64 rx_bytes; u64 tx_tso; - u64 tx_no_csum; + u64 tx_tso_bytes; + u64 tx_csum_none; u64 tx_csum; u64 rx_csum_none; u64 rx_csum_complete; u64 rx_csum_error; + u64 hw_tx_dropped; + u64 hw_rx_dropped; + u64 hw_rx_over_errors; + u64 hw_rx_missed_errors; + u64 hw_tx_aborted_errors; }; enum ionic_lif_state_flags { @@ -133,6 +142,17 @@ enum ionic_lif_state_flags { IONIC_LIF_F_STATE_SIZE }; +struct ionic_qtype_info { + u8 version; + u8 supported; + u64 features; + u16 desc_sz; + u16 comp_sz; + u16 sg_desc_sz; + u16 max_sg_elems; + u16 sg_desc_stride; +}; + #define IONIC_LIF_NAME_MAX_SZ 32 struct ionic_lif { char name[IONIC_LIF_NAME_MAX_SZ]; @@ -161,11 +181,13 @@ struct ionic_lif { bool mc_overflow; unsigned int nmcast; bool uc_overflow; + u16 lif_type; unsigned int nucast; struct ionic_lif_info *info; dma_addr_t info_pa; u32 info_sz; + struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; u16 rss_types; u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; @@ -227,6 +249,8 @@ static inline u32 ionic_coal_hw_to_usec(struct ionic *ionic, u32 units) } void ionic_link_status_check_request(struct ionic_lif *lif); +void ionic_get_stats64(struct net_device *netdev, + struct rtnl_link_stats64 *ns); void ionic_lif_deferred_enqueue(struct ionic_deferred *def, struct ionic_deferred_work *work); int ionic_lifs_alloc(struct ionic *ionic); diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c index 3344bc1f7671..df5b9bcc3aba 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_main.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_main.c @@ -6,7 +6,7 @@ #include <linux/module.h> #include <linux/netdevice.h> #include <linux/utsname.h> -#include <linux/vermagic.h> +#include <generated/utsrelease.h> #include "ionic.h" #include "ionic_bus.h" @@ -152,6 +152,8 @@ static const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode) return "IONIC_CMD_RX_FILTER_ADD"; case IONIC_CMD_RX_FILTER_DEL: return "IONIC_CMD_RX_FILTER_DEL"; + case IONIC_CMD_Q_IDENTIFY: + return "IONIC_CMD_Q_IDENTIFY"; case IONIC_CMD_Q_INIT: return "IONIC_CMD_Q_INIT"; case IONIC_CMD_Q_CONTROL: @@ -356,7 +358,7 @@ try_again: done = ionic_dev_cmd_done(idev); if (done) break; - msleep(20); + msleep(5); hb = ionic_heartbeat_check(ionic); } while (!done && !hb && time_before(jiffies, max_wait)); duration = jiffies - start_time; @@ -413,6 +415,7 @@ int ionic_setup(struct ionic *ionic) err = ionic_dev_setup(ionic); if (err) return err; + ionic_reset(ionic); return 0; } diff --git a/drivers/net/ethernet/pensando/ionic/ionic_stats.c b/drivers/net/ethernet/pensando/ionic/ionic_stats.c index 8f2a8fb029f1..2a1885da58a6 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_stats.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_stats.c @@ -15,11 +15,109 @@ static const struct ionic_stat_desc ionic_lif_stats_desc[] = { IONIC_LIF_STAT_DESC(rx_packets), IONIC_LIF_STAT_DESC(rx_bytes), IONIC_LIF_STAT_DESC(tx_tso), - IONIC_LIF_STAT_DESC(tx_no_csum), + IONIC_LIF_STAT_DESC(tx_tso_bytes), + IONIC_LIF_STAT_DESC(tx_csum_none), IONIC_LIF_STAT_DESC(tx_csum), IONIC_LIF_STAT_DESC(rx_csum_none), IONIC_LIF_STAT_DESC(rx_csum_complete), IONIC_LIF_STAT_DESC(rx_csum_error), + IONIC_LIF_STAT_DESC(hw_tx_dropped), + IONIC_LIF_STAT_DESC(hw_rx_dropped), + IONIC_LIF_STAT_DESC(hw_rx_over_errors), + IONIC_LIF_STAT_DESC(hw_rx_missed_errors), + IONIC_LIF_STAT_DESC(hw_tx_aborted_errors), +}; + +static const struct ionic_stat_desc ionic_port_stats_desc[] = { + IONIC_PORT_STAT_DESC(frames_rx_ok), + IONIC_PORT_STAT_DESC(frames_rx_all), + IONIC_PORT_STAT_DESC(frames_rx_bad_fcs), + IONIC_PORT_STAT_DESC(frames_rx_bad_all), + IONIC_PORT_STAT_DESC(octets_rx_ok), + IONIC_PORT_STAT_DESC(octets_rx_all), + IONIC_PORT_STAT_DESC(frames_rx_unicast), + IONIC_PORT_STAT_DESC(frames_rx_multicast), + IONIC_PORT_STAT_DESC(frames_rx_broadcast), + IONIC_PORT_STAT_DESC(frames_rx_pause), + IONIC_PORT_STAT_DESC(frames_rx_bad_length), + IONIC_PORT_STAT_DESC(frames_rx_undersized), + IONIC_PORT_STAT_DESC(frames_rx_oversized), + IONIC_PORT_STAT_DESC(frames_rx_fragments), + IONIC_PORT_STAT_DESC(frames_rx_jabber), + IONIC_PORT_STAT_DESC(frames_rx_pripause), + IONIC_PORT_STAT_DESC(frames_rx_stomped_crc), + IONIC_PORT_STAT_DESC(frames_rx_too_long), + IONIC_PORT_STAT_DESC(frames_rx_vlan_good), + IONIC_PORT_STAT_DESC(frames_rx_dropped), + IONIC_PORT_STAT_DESC(frames_rx_less_than_64b), + IONIC_PORT_STAT_DESC(frames_rx_64b), + IONIC_PORT_STAT_DESC(frames_rx_65b_127b), + IONIC_PORT_STAT_DESC(frames_rx_128b_255b), + IONIC_PORT_STAT_DESC(frames_rx_256b_511b), + IONIC_PORT_STAT_DESC(frames_rx_512b_1023b), + IONIC_PORT_STAT_DESC(frames_rx_1024b_1518b), + IONIC_PORT_STAT_DESC(frames_rx_1519b_2047b), + IONIC_PORT_STAT_DESC(frames_rx_2048b_4095b), + IONIC_PORT_STAT_DESC(frames_rx_4096b_8191b), + IONIC_PORT_STAT_DESC(frames_rx_8192b_9215b), + IONIC_PORT_STAT_DESC(frames_rx_other), + IONIC_PORT_STAT_DESC(frames_tx_ok), + IONIC_PORT_STAT_DESC(frames_tx_all), + IONIC_PORT_STAT_DESC(frames_tx_bad), + IONIC_PORT_STAT_DESC(octets_tx_ok), + IONIC_PORT_STAT_DESC(octets_tx_total), + IONIC_PORT_STAT_DESC(frames_tx_unicast), + IONIC_PORT_STAT_DESC(frames_tx_multicast), + IONIC_PORT_STAT_DESC(frames_tx_broadcast), + IONIC_PORT_STAT_DESC(frames_tx_pause), + IONIC_PORT_STAT_DESC(frames_tx_pripause), + IONIC_PORT_STAT_DESC(frames_tx_vlan), + IONIC_PORT_STAT_DESC(frames_tx_less_than_64b), + IONIC_PORT_STAT_DESC(frames_tx_64b), + IONIC_PORT_STAT_DESC(frames_tx_65b_127b), + IONIC_PORT_STAT_DESC(frames_tx_128b_255b), + IONIC_PORT_STAT_DESC(frames_tx_256b_511b), + IONIC_PORT_STAT_DESC(frames_tx_512b_1023b), + IONIC_PORT_STAT_DESC(frames_tx_1024b_1518b), + IONIC_PORT_STAT_DESC(frames_tx_1519b_2047b), + IONIC_PORT_STAT_DESC(frames_tx_2048b_4095b), + IONIC_PORT_STAT_DESC(frames_tx_4096b_8191b), + IONIC_PORT_STAT_DESC(frames_tx_8192b_9215b), + IONIC_PORT_STAT_DESC(frames_tx_other), + IONIC_PORT_STAT_DESC(frames_tx_pri_0), + IONIC_PORT_STAT_DESC(frames_tx_pri_1), + IONIC_PORT_STAT_DESC(frames_tx_pri_2), + IONIC_PORT_STAT_DESC(frames_tx_pri_3), + IONIC_PORT_STAT_DESC(frames_tx_pri_4), + IONIC_PORT_STAT_DESC(frames_tx_pri_5), + IONIC_PORT_STAT_DESC(frames_tx_pri_6), + IONIC_PORT_STAT_DESC(frames_tx_pri_7), + IONIC_PORT_STAT_DESC(frames_rx_pri_0), + IONIC_PORT_STAT_DESC(frames_rx_pri_1), + IONIC_PORT_STAT_DESC(frames_rx_pri_2), + IONIC_PORT_STAT_DESC(frames_rx_pri_3), + IONIC_PORT_STAT_DESC(frames_rx_pri_4), + IONIC_PORT_STAT_DESC(frames_rx_pri_5), + IONIC_PORT_STAT_DESC(frames_rx_pri_6), + IONIC_PORT_STAT_DESC(frames_rx_pri_7), + IONIC_PORT_STAT_DESC(tx_pripause_0_1us_count), + IONIC_PORT_STAT_DESC(tx_pripause_1_1us_count), + IONIC_PORT_STAT_DESC(tx_pripause_2_1us_count), + IONIC_PORT_STAT_DESC(tx_pripause_3_1us_count), + IONIC_PORT_STAT_DESC(tx_pripause_4_1us_count), + IONIC_PORT_STAT_DESC(tx_pripause_5_1us_count), + IONIC_PORT_STAT_DESC(tx_pripause_6_1us_count), + IONIC_PORT_STAT_DESC(tx_pripause_7_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_0_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_1_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_2_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_3_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_4_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_5_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_6_1us_count), + IONIC_PORT_STAT_DESC(rx_pripause_7_1us_count), + IONIC_PORT_STAT_DESC(rx_pause_1us_count), + IONIC_PORT_STAT_DESC(frames_tx_truncated), }; static const struct ionic_stat_desc ionic_tx_stats_desc[] = { @@ -29,6 +127,11 @@ static const struct ionic_stat_desc ionic_tx_stats_desc[] = { IONIC_TX_STAT_DESC(dma_map_err), IONIC_TX_STAT_DESC(linearize), IONIC_TX_STAT_DESC(frags), + IONIC_TX_STAT_DESC(tso), + IONIC_TX_STAT_DESC(tso_bytes), + IONIC_TX_STAT_DESC(csum_none), + IONIC_TX_STAT_DESC(csum), + IONIC_TX_STAT_DESC(vlan_inserted), }; static const struct ionic_stat_desc ionic_rx_stats_desc[] = { @@ -40,6 +143,7 @@ static const struct ionic_stat_desc ionic_rx_stats_desc[] = { IONIC_RX_STAT_DESC(csum_complete), IONIC_RX_STAT_DESC(csum_error), IONIC_RX_STAT_DESC(dropped), + IONIC_RX_STAT_DESC(vlan_stripped), }; static const struct ionic_stat_desc ionic_txq_stats_desc[] = { @@ -62,6 +166,7 @@ static const struct ionic_stat_desc ionic_dbg_napi_stats_desc[] = { }; #define IONIC_NUM_LIF_STATS ARRAY_SIZE(ionic_lif_stats_desc) +#define IONIC_NUM_PORT_STATS ARRAY_SIZE(ionic_port_stats_desc) #define IONIC_NUM_TX_STATS ARRAY_SIZE(ionic_tx_stats_desc) #define IONIC_NUM_RX_STATS ARRAY_SIZE(ionic_rx_stats_desc) #define IONIC_NUM_TX_Q_STATS ARRAY_SIZE(ionic_txq_stats_desc) @@ -76,6 +181,7 @@ static void ionic_get_lif_stats(struct ionic_lif *lif, { struct ionic_tx_stats *tstats; struct ionic_rx_stats *rstats; + struct rtnl_link_stats64 ns; struct ionic_qcq *txqcq; struct ionic_qcq *rxqcq; int q_num; @@ -89,7 +195,8 @@ static void ionic_get_lif_stats(struct ionic_lif *lif, stats->tx_packets += tstats->pkts; stats->tx_bytes += tstats->bytes; stats->tx_tso += tstats->tso; - stats->tx_no_csum += tstats->no_csum; + stats->tx_tso_bytes += tstats->tso_bytes; + stats->tx_csum_none += tstats->csum_none; stats->tx_csum += tstats->csum; } @@ -103,6 +210,13 @@ static void ionic_get_lif_stats(struct ionic_lif *lif, stats->rx_csum_error += rstats->csum_error; } } + + ionic_get_stats64(lif->netdev, &ns); + stats->hw_tx_dropped = ns.tx_dropped; + stats->hw_rx_dropped = ns.rx_dropped; + stats->hw_rx_over_errors = ns.rx_over_errors; + stats->hw_rx_missed_errors = ns.rx_missed_errors; + stats->hw_tx_aborted_errors = ns.tx_aborted_errors; } static u64 ionic_sw_stats_get_count(struct ionic_lif *lif) @@ -118,6 +232,9 @@ static u64 ionic_sw_stats_get_count(struct ionic_lif *lif) /* rx stats */ total += MAX_Q(lif) * IONIC_NUM_RX_STATS; + /* port stats */ + total += IONIC_NUM_PORT_STATS; + if (test_bit(IONIC_LIF_F_UP, lif->state) && test_bit(IONIC_LIF_F_SW_DEBUG_STATS, lif->state)) { /* tx debug stats */ @@ -144,6 +261,13 @@ static void ionic_sw_stats_get_strings(struct ionic_lif *lif, u8 **buf) snprintf(*buf, ETH_GSTRING_LEN, ionic_lif_stats_desc[i].name); *buf += ETH_GSTRING_LEN; } + + for (i = 0; i < IONIC_NUM_PORT_STATS; i++) { + snprintf(*buf, ETH_GSTRING_LEN, + ionic_port_stats_desc[i].name); + *buf += ETH_GSTRING_LEN; + } + for (q_num = 0; q_num < MAX_Q(lif); q_num++) { for (i = 0; i < IONIC_NUM_TX_STATS; i++) { snprintf(*buf, ETH_GSTRING_LEN, "tx_%d_%s", @@ -225,6 +349,7 @@ static void ionic_sw_stats_get_strings(struct ionic_lif *lif, u8 **buf) static void ionic_sw_stats_get_values(struct ionic_lif *lif, u64 **buf) { + struct ionic_port_stats *port_stats; struct ionic_lif_sw_stats lif_stats; struct ionic_qcq *txqcq, *rxqcq; struct ionic_tx_stats *txstats; @@ -238,6 +363,13 @@ static void ionic_sw_stats_get_values(struct ionic_lif *lif, u64 **buf) (*buf)++; } + port_stats = &lif->ionic->idev.port_info->stats; + for (i = 0; i < IONIC_NUM_PORT_STATS; i++) { + **buf = IONIC_READ_STAT_LE64(port_stats, + &ionic_port_stats_desc[i]); + (*buf)++; + } + for (q_num = 0; q_num < MAX_Q(lif); q_num++) { txstats = &lif_to_txstats(lif, q_num); diff --git a/drivers/net/ethernet/pensando/ionic/ionic_stats.h b/drivers/net/ethernet/pensando/ionic/ionic_stats.h index d2c1122a2c6e..3f543512616e 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_stats.h +++ b/drivers/net/ethernet/pensando/ionic/ionic_stats.h @@ -11,6 +11,9 @@ .offset = IONIC_STAT_TO_OFFSET(type, stat_name) \ } +#define IONIC_PORT_STAT_DESC(stat_name) \ + IONIC_STAT_DESC(struct ionic_port_stats, stat_name) + #define IONIC_LIF_STAT_DESC(stat_name) \ IONIC_STAT_DESC(struct ionic_lif_sw_stats, stat_name) @@ -45,6 +48,9 @@ extern const int ionic_num_stats_grps; #define IONIC_READ_STAT64(base_ptr, desc_ptr) \ (*((u64 *)(((u8 *)(base_ptr)) + (desc_ptr)->offset))) +#define IONIC_READ_STAT_LE64(base_ptr, desc_ptr) \ + __le64_to_cpu(*((u64 *)(((u8 *)(base_ptr)) + (desc_ptr)->offset))) + struct ionic_stat_desc { char name[ETH_GSTRING_LEN]; u64 offset; diff --git a/drivers/net/ethernet/pensando/ionic/ionic_txrx.c b/drivers/net/ethernet/pensando/ionic/ionic_txrx.c index d233b6e77b1e..b7f900c11834 100644 --- a/drivers/net/ethernet/pensando/ionic/ionic_txrx.c +++ b/drivers/net/ethernet/pensando/ionic/ionic_txrx.c @@ -10,8 +10,10 @@ #include "ionic_lif.h" #include "ionic_txrx.h" -static void ionic_rx_clean(struct ionic_queue *q, struct ionic_desc_info *desc_info, - struct ionic_cq_info *cq_info, void *cb_arg); +static void ionic_rx_clean(struct ionic_queue *q, + struct ionic_desc_info *desc_info, + struct ionic_cq_info *cq_info, + void *cb_arg); static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell, ionic_desc_cb cb_func, void *cb_arg) @@ -140,8 +142,10 @@ static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q, return skb; } -static void ionic_rx_clean(struct ionic_queue *q, struct ionic_desc_info *desc_info, - struct ionic_cq_info *cq_info, void *cb_arg) +static void ionic_rx_clean(struct ionic_queue *q, + struct ionic_desc_info *desc_info, + struct ionic_cq_info *cq_info, + void *cb_arg) { struct ionic_rxq_comp *comp = cq_info->cq_desc; struct ionic_qcq *qcq = q_to_qcq(q); @@ -210,10 +214,11 @@ static void ionic_rx_clean(struct ionic_queue *q, struct ionic_desc_info *desc_i (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD))) stats->csum_error++; - if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) { - if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), - le16_to_cpu(comp->vlan_tci)); + if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && + (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) { + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), + le16_to_cpu(comp->vlan_tci)); + stats->vlan_stripped++; } if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) @@ -475,7 +480,8 @@ int ionic_rx_napi(struct napi_struct *napi, int budget) return work_done; } -static dma_addr_t ionic_tx_map_single(struct ionic_queue *q, void *data, size_t len) +static dma_addr_t ionic_tx_map_single(struct ionic_queue *q, + void *data, size_t len) { struct ionic_tx_stats *stats = q_to_tx_stats(q); struct device *dev = q->lif->ionic->dev; @@ -491,7 +497,8 @@ static dma_addr_t ionic_tx_map_single(struct ionic_queue *q, void *data, size_t return dma_addr; } -static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q, const skb_frag_t *frag, +static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q, + const skb_frag_t *frag, size_t offset, size_t len) { struct ionic_tx_stats *stats = q_to_tx_stats(q); @@ -507,8 +514,10 @@ static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q, const skb_frag_t *fra return dma_addr; } -static void ionic_tx_clean(struct ionic_queue *q, struct ionic_desc_info *desc_info, - struct ionic_cq_info *cq_info, void *cb_arg) +static void ionic_tx_clean(struct ionic_queue *q, + struct ionic_desc_info *desc_info, + struct ionic_cq_info *cq_info, + void *cb_arg) { struct ionic_txq_sg_desc *sg_desc = desc_info->sg_desc; struct ionic_txq_sg_elem *elem = sg_desc->elems; @@ -852,6 +861,7 @@ static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb) stats->pkts += total_pkts; stats->bytes += total_bytes; stats->tso++; + stats->tso_bytes += total_bytes; return 0; @@ -890,9 +900,12 @@ static int ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb) flags, skb_shinfo(skb)->nr_frags, dma_addr); desc->cmd = cpu_to_le64(cmd); desc->len = cpu_to_le16(skb_headlen(skb)); - desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb)); desc->csum_offset = cpu_to_le16(skb->csum_offset); + if (has_vlan) { + desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); + stats->vlan_inserted++; + } if (skb->csum_not_inet) stats->crc32_csum++; @@ -927,9 +940,12 @@ static int ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb) flags, skb_shinfo(skb)->nr_frags, dma_addr); desc->cmd = cpu_to_le64(cmd); desc->len = cpu_to_le16(skb_headlen(skb)); - desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); + if (has_vlan) { + desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); + stats->vlan_inserted++; + } - stats->no_csum++; + stats->csum_none++; return 0; } @@ -989,6 +1005,7 @@ static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb) static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb) { + int sg_elems = q->lif->qtype_info[IONIC_QTYPE_TXQ].max_sg_elems; struct ionic_tx_stats *stats = q_to_tx_stats(q); int err; @@ -997,7 +1014,7 @@ static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb) return (skb->len / skb_shinfo(skb)->gso_size) + 1; /* If non-TSO, just need 1 desc and nr_frags sg elems */ - if (skb_shinfo(skb)->nr_frags <= IONIC_TX_MAX_SG_ELEMS) + if (skb_shinfo(skb)->nr_frags <= sg_elems) return 1; /* Too many frags, so linearize */ |