diff options
Diffstat (limited to 'drivers/regulator/qcom_spmi-regulator.c')
| -rw-r--r-- | drivers/regulator/qcom_spmi-regulator.c | 378 |
1 files changed, 281 insertions, 97 deletions
diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c index a2d0292a92fd..3e312729741e 100644 --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -99,6 +99,9 @@ enum spmi_regulator_logical_type { SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, SPMI_REGULATOR_LOGICAL_TYPE_HFS430, + SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3, + SPMI_REGULATOR_LOGICAL_TYPE_LDO_510, + SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS, }; enum spmi_regulator_type { @@ -166,6 +169,17 @@ enum spmi_regulator_subtype { SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d, + SPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0a, + SPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 0x0b, + SPMI_REGULATOR_SUBTYPE_LV_P150_510 = 0x71, + SPMI_REGULATOR_SUBTYPE_LV_P300_510 = 0x72, + SPMI_REGULATOR_SUBTYPE_LV_P600_510 = 0x73, + SPMI_REGULATOR_SUBTYPE_N300_510 = 0x6a, + SPMI_REGULATOR_SUBTYPE_N600_510 = 0x6b, + SPMI_REGULATOR_SUBTYPE_N1200_510 = 0x6c, + SPMI_REGULATOR_SUBTYPE_MV_P50_510 = 0x7a, + SPMI_REGULATOR_SUBTYPE_MV_P150_510 = 0x7b, + SPMI_REGULATOR_SUBTYPE_MV_P600_510 = 0x7d, }; enum spmi_common_regulator_registers { @@ -193,6 +207,14 @@ enum spmi_ftsmps426_regulator_registers { SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69, }; +/* + * Third common register layout + */ +enum spmi_hfsmps_regulator_registers { + SPMI_HFSMPS_REG_STEP_CTRL = 0x3c, + SPMI_HFSMPS_REG_PULL_DOWN = 0xa0, +}; + enum spmi_vs_registers { SPMI_VS_REG_OCP = 0x4a, SPMI_VS_REG_SOFT_START = 0x4c, @@ -260,6 +282,15 @@ enum spmi_common_control_register_index { #define SPMI_FTSMPS426_MODE_MASK 0x07 +/* Third common regulator mode register values */ +#define SPMI_HFSMPS_MODE_BYPASS_MASK 2 +#define SPMI_HFSMPS_MODE_RETENTION_MASK 3 +#define SPMI_HFSMPS_MODE_LPM_MASK 4 +#define SPMI_HFSMPS_MODE_AUTO_MASK 6 +#define SPMI_HFSMPS_MODE_HPM_MASK 7 + +#define SPMI_HFSMPS_MODE_MASK 0x07 + /* Common regulator pull down control register layout */ #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 @@ -305,6 +336,9 @@ enum spmi_common_control_register_index { #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 +/* slew_rate has units of uV/us. */ +#define SPMI_HFSMPS_SLEW_RATE_38p4 38400 + #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03 #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0 @@ -554,6 +588,14 @@ static struct spmi_voltage_range ht_p600_ranges[] = { SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000), }; +static struct spmi_voltage_range nldo_510_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), +}; + +static struct spmi_voltage_range ftsmps510_ranges[] = { + SPMI_VOLTAGE_RANGE(0, 300000, 300000, 1372000, 1372000, 4000), +}; + static DEFINE_SPMI_SET_POINTS(pldo); static DEFINE_SPMI_SET_POINTS(nldo1); static DEFINE_SPMI_SET_POINTS(nldo2); @@ -576,6 +618,8 @@ static DEFINE_SPMI_SET_POINTS(ht_nldo); static DEFINE_SPMI_SET_POINTS(hfs430); static DEFINE_SPMI_SET_POINTS(ht_p150); static DEFINE_SPMI_SET_POINTS(ht_p600); +static DEFINE_SPMI_SET_POINTS(nldo_510); +static DEFINE_SPMI_SET_POINTS(ftsmps510); static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, int len) @@ -1062,6 +1106,23 @@ static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev } } +static unsigned int spmi_regulator_hfsmps_get_mode(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 reg; + + spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); + + switch (reg) { + case SPMI_HFSMPS_MODE_HPM_MASK: + return REGULATOR_MODE_NORMAL; + case SPMI_HFSMPS_MODE_AUTO_MASK: + return REGULATOR_MODE_FAST; + default: + return REGULATOR_MODE_IDLE; + } +} + static int spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) { @@ -1109,6 +1170,33 @@ spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode) } static int +spmi_regulator_hfsmps_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + u8 mask = SPMI_HFSMPS_MODE_MASK; + u8 val; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + val = SPMI_HFSMPS_MODE_HPM_MASK; + break; + case REGULATOR_MODE_FAST: + val = SPMI_HFSMPS_MODE_AUTO_MASK; + break; + case REGULATOR_MODE_IDLE: + val = vreg->logical_type == + SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3 ? + SPMI_HFSMPS_MODE_RETENTION_MASK : + SPMI_HFSMPS_MODE_LPM_MASK; + break; + default: + return -EINVAL; + } + + return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); +} + +static int spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) { struct spmi_regulator *vreg = rdev_get_drvdata(rdev); @@ -1131,6 +1219,15 @@ static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev) mask, mask); } +static int spmi_regulator_hfsmps_set_pull_down(struct regulator_dev *rdev) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; + + return spmi_vreg_update_bits(vreg, SPMI_HFSMPS_REG_PULL_DOWN, + mask, mask); +} + static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev) { struct spmi_regulator *vreg = rdev_get_drvdata(rdev); @@ -1465,6 +1562,21 @@ static const struct regulator_ops spmi_hfs430_ops = { .get_mode = spmi_regulator_ftsmps426_get_mode, }; +static const struct regulator_ops spmi_hfsmps_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, + .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, + .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, + .map_voltage = spmi_regulator_single_map_voltage, + .list_voltage = spmi_regulator_common_list_voltage, + .set_mode = spmi_regulator_hfsmps_set_mode, + .get_mode = spmi_regulator_hfsmps_get_mode, + .set_load = spmi_regulator_common_set_load, + .set_pull_down = spmi_regulator_hfsmps_set_pull_down, +}; + /* Maximum possible digital major revision value */ #define INF 0xFF @@ -1473,7 +1585,8 @@ static const struct spmi_regulator_mapping supported_regulators[] = { SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000), SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000), SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), - SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000), + SPMI_VREG(BUCK, HFS430, 0, 3, HFS430, hfs430, hfs430, 10000), + SPMI_VREG(BUCK, HFSMPS_510, 4, INF, HFSMPS, hfsmps, hfs430, 100000), SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), @@ -1549,6 +1662,16 @@ static const struct spmi_regulator_mapping supported_regulators[] = { SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), + SPMI_VREG(LDO, LV_P150_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), + SPMI_VREG(LDO, LV_P300_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), + SPMI_VREG(LDO, LV_P600_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), + SPMI_VREG(LDO, MV_P50_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), + SPMI_VREG(LDO, MV_P150_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), + SPMI_VREG(LDO, MV_P600_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), + SPMI_VREG(LDO, N300_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), + SPMI_VREG(LDO, N600_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), + SPMI_VREG(LDO, N1200_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), + SPMI_VREG(FTS, FTSMPS_510, 0, INF, FTSMPS3, hfsmps, ftsmps510, 100000), }; static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) @@ -1696,6 +1819,26 @@ static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg, return ret; } +static int spmi_regulator_init_slew_rate_hfsmps(struct spmi_regulator *vreg) +{ + int ret; + u8 reg = 0; + int delay; + + ret = spmi_vreg_read(vreg, SPMI_HFSMPS_REG_STEP_CTRL, ®, 1); + if (ret) { + dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); + return ret; + } + + delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; + delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; + + vreg->slew_rate = SPMI_HFSMPS_SLEW_RATE_38p4 >> delay; + + return ret; +} + static int spmi_regulator_init_registers(struct spmi_regulator *vreg, const struct spmi_regulator_init_data *data) { @@ -1846,6 +1989,12 @@ static int spmi_regulator_of_parse(struct device_node *node, if (ret) return ret; break; + case SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS: + case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3: + ret = spmi_regulator_init_slew_rate_hfsmps(vreg); + if (ret) + return ret; + break; default: break; } @@ -1872,40 +2021,100 @@ static int spmi_regulator_of_parse(struct device_node *node, return 0; } -static const struct spmi_regulator_data pm8941_regulators[] = { +static const struct spmi_regulator_data pm6125_regulators[] = { + { "s1", 0x1400, "vdd_s1" }, + { "s2", 0x1700, "vdd_s2" }, + { "s3", 0x1a00, "vdd_s3" }, + { "s4", 0x1d00, "vdd_s4" }, + { "s5", 0x2000, "vdd_s5" }, + { "s6", 0x2300, "vdd_s6" }, + { "s7", 0x2600, "vdd_s7" }, + { "s8", 0x2900, "vdd_s8" }, + { "l1", 0x4000, "vdd_l1_l7_l17_l18" }, + { "l2", 0x4100, "vdd_l2_l3_l4" }, + { "l3", 0x4200, "vdd_l2_l3_l4" }, + { "l4", 0x4300, "vdd_l2_l3_l4" }, + { "l5", 0x4400, "vdd_l5_l15_l19_l20_l21_l22" }, + { "l6", 0x4500, "vdd_l6_l8" }, + { "l7", 0x4600, "vdd_l1_l7_l17_l18" }, + { "l8", 0x4700, "vdd_l6_l8" }, + { "l9", 0x4800, "vdd_l9_l11" }, + { "l10", 0x4900, "vdd_l10_l13_l14" }, + { "l11", 0x4a00, "vdd_l9_l11" }, + { "l12", 0x4b00, "vdd_l12_l16" }, + { "l13", 0x4c00, "vdd_l10_l13_l14" }, + { "l14", 0x4d00, "vdd_l10_l13_l14" }, + { "l15", 0x4e00, "vdd_l5_l15_l19_l20_l21_l22" }, + { "l16", 0x4f00, "vdd_l12_l16" }, + { "l17", 0x5000, "vdd_l1_l7_l17_l18" }, + { "l18", 0x5100, "vdd_l1_l7_l17_l18" }, + { "l19", 0x5200, "vdd_l5_l15_l19_l20_l21_l22" }, + { "l20", 0x5300, "vdd_l5_l15_l19_l20_l21_l22" }, + { "l21", 0x5400, "vdd_l5_l15_l19_l20_l21_l22" }, + { "l22", 0x5500, "vdd_l5_l15_l19_l20_l21_l22" }, + { "l23", 0x5600, "vdd_l23_l24" }, + { "l24", 0x5700, "vdd_l23_l24" }, +}; + +static const struct spmi_regulator_data pm660_regulators[] = { { "s1", 0x1400, "vdd_s1", }, { "s2", 0x1700, "vdd_s2", }, { "s3", 0x1a00, "vdd_s3", }, - { "s4", 0xa000, }, - { "l1", 0x4000, "vdd_l1_l3", }, - { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, - { "l3", 0x4200, "vdd_l1_l3", }, - { "l4", 0x4300, "vdd_l4_l11", }, - { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, - { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, - { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, - { "l8", 0x4700, "vdd_l8_l16_l18_19", }, - { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, - { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, - { "l11", 0x4a00, "vdd_l4_l11", }, - { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, - { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, - { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, - { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, - { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, - { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, - { "l18", 0x5100, "vdd_l8_l16_l18_19", }, - { "l19", 0x5200, "vdd_l8_l16_l18_19", }, - { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, - { "l21", 0x5400, "vdd_l21", }, - { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, - { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, - { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, - { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, - { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, - { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, - { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, - { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, + { "s4", 0x1d00, "vdd_s3", }, + { "s5", 0x2000, "vdd_s5", }, + { "s6", 0x2300, "vdd_s6", }, + { "l1", 0x4000, "vdd_l1_l6_l7", }, + { "l2", 0x4100, "vdd_l2_l3", }, + { "l3", 0x4200, "vdd_l2_l3", }, + /* l4 is unaccessible on PM660 */ + { "l5", 0x4400, "vdd_l5", }, + { "l6", 0x4500, "vdd_l1_l6_l7", }, + { "l7", 0x4600, "vdd_l1_l6_l7", }, + { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, + { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, + { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, + { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, + { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, + { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, + { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, + { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, + { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, + { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, + { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, + { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, + { } +}; + +static const struct spmi_regulator_data pm660l_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", }, + { "s3", 0x1a00, "vdd_s3", }, + { "s4", 0x1d00, "vdd_s4", }, + { "s5", 0x2000, "vdd_s5", }, + { "l1", 0x4000, "vdd_l1_l9_l10", }, + { "l2", 0x4100, "vdd_l2", }, + { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, + { "l4", 0x4300, "vdd_l4_l6", }, + { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, + { "l6", 0x4500, "vdd_l4_l6", }, + { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, + { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, + { "l9", 0x4800, "vdd_l1_l9_l10", }, + { "l10", 0x4900, "vdd_l1_l9_l10", }, + { } +}; + +static const struct spmi_regulator_data pm8004_regulators[] = { + { "s2", 0x1700, "vdd_s2", }, + { "s5", 0x2000, "vdd_s5", }, + { } +}; + +static const struct spmi_regulator_data pm8005_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", }, + { "s3", 0x1a00, "vdd_s3", }, + { "s4", 0x1d00, "vdd_s4", }, { } }; @@ -1985,6 +2194,43 @@ static const struct spmi_regulator_data pm8916_regulators[] = { { } }; +static const struct spmi_regulator_data pm8941_regulators[] = { + { "s1", 0x1400, "vdd_s1", }, + { "s2", 0x1700, "vdd_s2", }, + { "s3", 0x1a00, "vdd_s3", }, + { "s4", 0xa000, }, + { "l1", 0x4000, "vdd_l1_l3", }, + { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, + { "l3", 0x4200, "vdd_l1_l3", }, + { "l4", 0x4300, "vdd_l4_l11", }, + { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, + { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, + { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, + { "l8", 0x4700, "vdd_l8_l16_l18_19", }, + { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, + { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, + { "l11", 0x4a00, "vdd_l4_l11", }, + { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, + { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, + { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, + { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, + { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, + { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, + { "l18", 0x5100, "vdd_l8_l16_l18_19", }, + { "l19", 0x5200, "vdd_l8_l16_l18_19", }, + { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, + { "l21", 0x5400, "vdd_l21", }, + { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, + { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, + { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, + { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, + { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, + { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, + { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, + { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, + { } +}; + static const struct spmi_regulator_data pm8950_regulators[] = { { "s1", 0x1400, "vdd_s1", }, { "s2", 0x1700, "vdd_s2", }, @@ -2076,69 +2322,6 @@ static const struct spmi_regulator_data pmi8994_regulators[] = { { } }; -static const struct spmi_regulator_data pm660_regulators[] = { - { "s1", 0x1400, "vdd_s1", }, - { "s2", 0x1700, "vdd_s2", }, - { "s3", 0x1a00, "vdd_s3", }, - { "s4", 0x1d00, "vdd_s3", }, - { "s5", 0x2000, "vdd_s5", }, - { "s6", 0x2300, "vdd_s6", }, - { "l1", 0x4000, "vdd_l1_l6_l7", }, - { "l2", 0x4100, "vdd_l2_l3", }, - { "l3", 0x4200, "vdd_l2_l3", }, - /* l4 is unaccessible on PM660 */ - { "l5", 0x4400, "vdd_l5", }, - { "l6", 0x4500, "vdd_l1_l6_l7", }, - { "l7", 0x4600, "vdd_l1_l6_l7", }, - { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, - { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, - { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, - { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, - { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, - { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, - { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, - { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, - { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, - { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, - { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, - { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, - { } -}; - -static const struct spmi_regulator_data pm660l_regulators[] = { - { "s1", 0x1400, "vdd_s1", }, - { "s2", 0x1700, "vdd_s2", }, - { "s3", 0x1a00, "vdd_s3", }, - { "s4", 0x1d00, "vdd_s4", }, - { "s5", 0x2000, "vdd_s5", }, - { "l1", 0x4000, "vdd_l1_l9_l10", }, - { "l2", 0x4100, "vdd_l2", }, - { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, - { "l4", 0x4300, "vdd_l4_l6", }, - { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, - { "l6", 0x4500, "vdd_l4_l6", }, - { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, - { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, - { "l9", 0x4800, "vdd_l1_l9_l10", }, - { "l10", 0x4900, "vdd_l1_l9_l10", }, - { } -}; - - -static const struct spmi_regulator_data pm8004_regulators[] = { - { "s2", 0x1700, "vdd_s2", }, - { "s5", 0x2000, "vdd_s5", }, - { } -}; - -static const struct spmi_regulator_data pm8005_regulators[] = { - { "s1", 0x1400, "vdd_s1", }, - { "s2", 0x1700, "vdd_s2", }, - { "s3", 0x1a00, "vdd_s3", }, - { "s4", 0x1d00, "vdd_s4", }, - { } -}; - static const struct spmi_regulator_data pmp8074_regulators[] = { { "s1", 0x1400, "vdd_s1"}, { "s2", 0x1700, "vdd_s2"}, @@ -2167,6 +2350,9 @@ static const struct spmi_regulator_data pms405_regulators[] = { }; static const struct of_device_id qcom_spmi_regulator_match[] = { + { .compatible = "qcom,pm6125-regulators", .data = &pm6125_regulators }, + { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, + { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, { .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators }, @@ -2176,8 +2362,6 @@ static const struct of_device_id qcom_spmi_regulator_match[] = { { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators }, { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, - { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, - { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators }, { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, { } |