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path: root/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c
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Diffstat (limited to 'drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c')
-rw-r--r--drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c55
1 files changed, 27 insertions, 28 deletions
diff --git a/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c b/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c
index a4a792f00b11..8661a3cc1e6b 100644
--- a/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c
+++ b/drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c
@@ -13,7 +13,6 @@
*/
#include <media/v4l2-mem2mem.h>
-#include <media/vp8-ctrls.h>
#include "hantro_hw.h"
#include "hantro.h"
@@ -274,17 +273,17 @@ static const struct hantro_reg vp8_dec_start_dec = {
};
static void cfg_lf(struct hantro_ctx *ctx,
- const struct v4l2_ctrl_vp8_frame_header *hdr)
+ const struct v4l2_ctrl_vp8_frame *hdr)
{
- const struct v4l2_vp8_segment_header *seg = &hdr->segment_header;
- const struct v4l2_vp8_loopfilter_header *lf = &hdr->lf_header;
+ const struct v4l2_vp8_segment *seg = &hdr->segment;
+ const struct v4l2_vp8_loop_filter *lf = &hdr->lf;
struct hantro_dev *vpu = ctx->dev;
unsigned int i;
u32 reg;
- if (!(seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED)) {
+ if (!(seg->flags & V4L2_VP8_SEGMENT_FLAG_ENABLED)) {
hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level);
- } else if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE) {
+ } else if (seg->flags & V4L2_VP8_SEGMENT_FLAG_DELTA_VALUE_MODE) {
for (i = 0; i < 4; i++) {
u32 lf_level = clamp(lf->level + seg->lf_update[i],
0, 63);
@@ -302,7 +301,7 @@ static void cfg_lf(struct hantro_ctx *ctx,
reg |= VDPU_REG_REF_PIC_FILT_TYPE_E;
vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ);
- if (lf->flags & V4L2_VP8_LF_HEADER_ADJ_ENABLE) {
+ if (lf->flags & V4L2_VP8_LF_ADJ_ENABLE) {
for (i = 0; i < 4; i++) {
hantro_reg_write(vpu, &vp8_dec_mb_adj[i],
lf->mb_mode_delta[i]);
@@ -313,16 +312,16 @@ static void cfg_lf(struct hantro_ctx *ctx,
}
static void cfg_qp(struct hantro_ctx *ctx,
- const struct v4l2_ctrl_vp8_frame_header *hdr)
+ const struct v4l2_ctrl_vp8_frame *hdr)
{
- const struct v4l2_vp8_quantization_header *q = &hdr->quant_header;
- const struct v4l2_vp8_segment_header *seg = &hdr->segment_header;
+ const struct v4l2_vp8_quantization *q = &hdr->quant;
+ const struct v4l2_vp8_segment *seg = &hdr->segment;
struct hantro_dev *vpu = ctx->dev;
unsigned int i;
- if (!(seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED)) {
+ if (!(seg->flags & V4L2_VP8_SEGMENT_FLAG_ENABLED)) {
hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi);
- } else if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE) {
+ } else if (seg->flags & V4L2_VP8_SEGMENT_FLAG_DELTA_VALUE_MODE) {
for (i = 0; i < 4; i++) {
u32 quant = clamp(q->y_ac_qi + seg->quant_update[i],
0, 127);
@@ -343,11 +342,11 @@ static void cfg_qp(struct hantro_ctx *ctx,
}
static void cfg_parts(struct hantro_ctx *ctx,
- const struct v4l2_ctrl_vp8_frame_header *hdr)
+ const struct v4l2_ctrl_vp8_frame *hdr)
{
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *vb2_src;
- u32 first_part_offset = VP8_FRAME_IS_KEY_FRAME(hdr) ? 10 : 3;
+ u32 first_part_offset = V4L2_VP8_FRAME_IS_KEY_FRAME(hdr) ? 10 : 3;
u32 mb_size, mb_offset_bytes, mb_offset_bits, mb_start_bits;
u32 dct_size_part_size, dct_part_offset;
dma_addr_t src_dma;
@@ -426,7 +425,7 @@ static void cfg_parts(struct hantro_ctx *ctx,
* normal 6-tap filters
*/
static void cfg_tap(struct hantro_ctx *ctx,
- const struct v4l2_ctrl_vp8_frame_header *hdr)
+ const struct v4l2_ctrl_vp8_frame *hdr)
{
struct hantro_dev *vpu = ctx->dev;
int i, j;
@@ -445,7 +444,7 @@ static void cfg_tap(struct hantro_ctx *ctx,
}
static void cfg_ref(struct hantro_ctx *ctx,
- const struct v4l2_ctrl_vp8_frame_header *hdr)
+ const struct v4l2_ctrl_vp8_frame *hdr)
{
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *vb2_dst;
@@ -462,7 +461,7 @@ static void cfg_ref(struct hantro_ctx *ctx,
WARN_ON(!ref && hdr->golden_frame_ts);
if (!ref)
ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
- if (hdr->flags & V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN)
+ if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN)
ref |= VDPU_REG_VP8_GREF_SIGN_BIAS;
vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(2));
@@ -470,15 +469,15 @@ static void cfg_ref(struct hantro_ctx *ctx,
WARN_ON(!ref && hdr->alt_frame_ts);
if (!ref)
ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0);
- if (hdr->flags & V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT)
+ if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT)
ref |= VDPU_REG_VP8_AREF_SIGN_BIAS;
vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(3));
}
static void cfg_buffers(struct hantro_ctx *ctx,
- const struct v4l2_ctrl_vp8_frame_header *hdr)
+ const struct v4l2_ctrl_vp8_frame *hdr)
{
- const struct v4l2_vp8_segment_header *seg = &hdr->segment_header;
+ const struct v4l2_vp8_segment *seg = &hdr->segment;
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *vb2_dst;
dma_addr_t dst_dma;
@@ -492,9 +491,9 @@ static void cfg_buffers(struct hantro_ctx *ctx,
/* Set segment map address */
reg = VDPU_REG_FWD_PIC1_SEGMENT_BASE(ctx->vp8_dec.segment_map.dma);
- if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED) {
+ if (seg->flags & V4L2_VP8_SEGMENT_FLAG_ENABLED) {
reg |= VDPU_REG_FWD_PIC1_SEGMENT_E;
- if (seg->flags & V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP)
+ if (seg->flags & V4L2_VP8_SEGMENT_FLAG_UPDATE_MAP)
reg |= VDPU_REG_FWD_PIC1_SEGMENT_UPD_E;
}
vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_SEGMENT_VAL);
@@ -506,7 +505,7 @@ static void cfg_buffers(struct hantro_ctx *ctx,
void rk3399_vpu_vp8_dec_run(struct hantro_ctx *ctx)
{
- const struct v4l2_ctrl_vp8_frame_header *hdr;
+ const struct v4l2_ctrl_vp8_frame *hdr;
struct hantro_dev *vpu = ctx->dev;
size_t height = ctx->dst_fmt.height;
size_t width = ctx->dst_fmt.width;
@@ -515,12 +514,12 @@ void rk3399_vpu_vp8_dec_run(struct hantro_ctx *ctx)
hantro_start_prepare_run(ctx);
- hdr = hantro_get_ctrl(ctx, V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER);
+ hdr = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_VP8_FRAME);
if (WARN_ON(!hdr))
return;
/* Reset segment_map buffer in keyframe */
- if (VP8_FRAME_IS_KEY_FRAME(hdr) && ctx->vp8_dec.segment_map.cpu)
+ if (V4L2_VP8_FRAME_IS_KEY_FRAME(hdr) && ctx->vp8_dec.segment_map.cpu)
memset(ctx->vp8_dec.segment_map.cpu, 0,
ctx->vp8_dec.segment_map.size);
@@ -537,7 +536,7 @@ void rk3399_vpu_vp8_dec_run(struct hantro_ctx *ctx)
reg = VDPU_REG_CONFIG_DEC_TIMEOUT_E
| VDPU_REG_CONFIG_DEC_CLK_GATE_E;
- if (!VP8_FRAME_IS_KEY_FRAME(hdr))
+ if (!V4L2_VP8_FRAME_IS_KEY_FRAME(hdr))
reg |= VDPU_REG_DEC_CTRL0_PIC_INTER_E;
vdpu_write_relaxed(vpu, reg, VDPU_REG_EN_FLAGS);
@@ -555,9 +554,9 @@ void rk3399_vpu_vp8_dec_run(struct hantro_ctx *ctx)
reg = VDPU_REG_DEC_CTRL0_DEC_MODE(10);
vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_FORMAT);
- if (!(hdr->flags & V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF))
+ if (!(hdr->flags & V4L2_VP8_FRAME_FLAG_MB_NO_SKIP_COEFF))
hantro_reg_write(vpu, &vp8_dec_skip_mode, 1);
- if (hdr->lf_header.level == 0)
+ if (hdr->lf.level == 0)
hantro_reg_write(vpu, &vp8_dec_filter_disable, 1);
/* Frame dimensions */
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.