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path: root/drivers/staging/qlge/qlge_mpi.c
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Diffstat (limited to 'drivers/staging/qlge/qlge_mpi.c')
-rw-r--r--drivers/staging/qlge/qlge_mpi.c59
1 files changed, 30 insertions, 29 deletions
diff --git a/drivers/staging/qlge/qlge_mpi.c b/drivers/staging/qlge/qlge_mpi.c
index 60c08d9cc034..e85c6ab538df 100644
--- a/drivers/staging/qlge/qlge_mpi.c
+++ b/drivers/staging/qlge/qlge_mpi.c
@@ -17,36 +17,34 @@ int ql_unpause_mpi_risc(struct ql_adapter *qdev)
int ql_pause_mpi_risc(struct ql_adapter *qdev)
{
u32 tmp;
- int count = UDELAY_COUNT;
+ int count;
/* Pause the RISC */
ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE);
- do {
+ for (count = UDELAY_COUNT; count; count--) {
tmp = ql_read32(qdev, CSR);
if (tmp & CSR_RP)
break;
mdelay(UDELAY_DELAY);
- count--;
- } while (count);
+ }
return (count == 0) ? -ETIMEDOUT : 0;
}
int ql_hard_reset_mpi_risc(struct ql_adapter *qdev)
{
u32 tmp;
- int count = UDELAY_COUNT;
+ int count;
/* Reset the RISC */
ql_write32(qdev, CSR, CSR_CMD_SET_RST);
- do {
+ for (count = UDELAY_COUNT; count; count--) {
tmp = ql_read32(qdev, CSR);
if (tmp & CSR_RR) {
ql_write32(qdev, CSR, CSR_CMD_CLR_RST);
break;
}
mdelay(UDELAY_DELAY);
- count--;
- } while (count);
+ }
return (count == 0) ? -ETIMEDOUT : 0;
}
@@ -147,15 +145,15 @@ static int ql_get_mb_sts(struct ql_adapter *qdev, struct mbox_params *mbcp)
*/
static int ql_wait_mbx_cmd_cmplt(struct ql_adapter *qdev)
{
- int count = 100;
+ int count;
u32 value;
- do {
+ for (count = 100; count; count--) {
value = ql_read32(qdev, STS);
if (value & STS_PI)
return 0;
mdelay(UDELAY_DELAY); /* 100ms */
- } while (--count);
+ }
return -ETIMEDOUT;
}
@@ -276,8 +274,8 @@ static void ql_link_up(struct ql_adapter *qdev, struct mbox_params *mbcp)
netif_err(qdev, ifup, qdev->ndev,
"Failed to init CAM/Routing tables.\n");
return;
- } else
- clear_bit(QL_CAM_RT_SET, &qdev->flags);
+ }
+ clear_bit(QL_CAM_RT_SET, &qdev->flags);
}
/* Queue up a worker to check the frame
@@ -389,7 +387,8 @@ static void ql_init_fw_done(struct ql_adapter *qdev, struct mbox_params *mbcp)
* This can get called iteratively from the mpi_work thread
* when events arrive via an interrupt.
* It also gets called when a mailbox command is polling for
- * it's completion. */
+ * it's completion.
+ */
static int ql_mpi_handler(struct ql_adapter *qdev, struct mbox_params *mbcp)
{
int status;
@@ -520,7 +519,7 @@ end:
* changed when a mailbox command is waiting
* for a response and an AEN arrives and
* is handled.
- * */
+ */
mbcp->out_count = orig_count;
return status;
}
@@ -555,7 +554,8 @@ static int ql_mailbox_command(struct ql_adapter *qdev, struct mbox_params *mbcp)
* here because some AEN might arrive while
* we're waiting for the mailbox command to
* complete. If more than 5 seconds expire we can
- * assume something is wrong. */
+ * assume something is wrong.
+ */
count = jiffies + HZ * MAILBOX_TIMEOUT;
do {
/* Wait for the interrupt to come in. */
@@ -786,8 +786,9 @@ int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
char *my_buf;
dma_addr_t buf_dma;
- my_buf = pci_alloc_consistent(qdev->pdev, word_count * sizeof(u32),
- &buf_dma);
+ my_buf = dma_alloc_coherent(&qdev->pdev->dev,
+ word_count * sizeof(u32), &buf_dma,
+ GFP_ATOMIC);
if (!my_buf)
return -EIO;
@@ -795,8 +796,8 @@ int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
if (!status)
memcpy(buf, my_buf, word_count * sizeof(u32));
- pci_free_consistent(qdev->pdev, word_count * sizeof(u32), my_buf,
- buf_dma);
+ dma_free_coherent(&qdev->pdev->dev, word_count * sizeof(u32), my_buf,
+ buf_dma);
return status;
}
@@ -911,10 +912,10 @@ int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol)
static int ql_idc_wait(struct ql_adapter *qdev)
{
int status = -ETIMEDOUT;
- long wait_time = 1 * HZ;
struct mbox_params *mbcp = &qdev->idc_mbc;
+ long wait_time;
- do {
+ for (wait_time = 1 * HZ; wait_time;) {
/* Wait here for the command to complete
* via the IDC process.
*/
@@ -944,7 +945,7 @@ static int ql_idc_wait(struct ql_adapter *qdev)
status = -EIO;
break;
}
- } while (wait_time);
+ }
return status;
}
@@ -1077,18 +1078,18 @@ static int ql_mb_get_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 *control)
int ql_wait_fifo_empty(struct ql_adapter *qdev)
{
- int count = 5;
+ int count;
u32 mgmnt_fifo_empty;
u32 nic_fifo_empty;
- do {
+ for (count = 6; count; count--) {
nic_fifo_empty = ql_read32(qdev, STS) & STS_NFE;
ql_mb_get_mgmnt_traffic_ctl(qdev, &mgmnt_fifo_empty);
mgmnt_fifo_empty &= MB_GET_MPI_TFK_FIFO_EMPTY;
if (nic_fifo_empty && mgmnt_fifo_empty)
return 0;
msleep(100);
- } while (count-- > 0);
+ }
return -ETIMEDOUT;
}
@@ -1173,12 +1174,12 @@ void ql_mpi_idc_work(struct work_struct *work)
case MB_CMD_PORT_RESET:
case MB_CMD_STOP_FW:
ql_link_off(qdev);
- /* Fall through */
+ fallthrough;
case MB_CMD_SET_PORT_CFG:
/* Signal the resulting link up AEN
* that the frame routing and mac addr
* needs to be set.
- * */
+ */
set_bit(QL_CAM_RT_SET, &qdev->flags);
/* Do ACK if required */
if (timeout) {
@@ -1206,7 +1207,7 @@ void ql_mpi_idc_work(struct work_struct *work)
*/
ql_link_off(qdev);
set_bit(QL_CAM_RT_SET, &qdev->flags);
- /* Fall through. */
+ fallthrough;
case MB_CMD_IOP_DVR_START:
case MB_CMD_IOP_FLASH_ACC:
case MB_CMD_IOP_CORE_DUMP_MPI: