diff options
Diffstat (limited to 'include/dt-bindings')
58 files changed, 3175 insertions, 156 deletions
diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h new file mode 100644 index 000000000000..61e7bdf8ea6e --- /dev/null +++ b/include/dt-bindings/arm/coresight-cti-dt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the defined trigger signal + * types on CoreSight CTI. + */ + +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H + +#define GEN_IO 0 +#define GEN_INTREQ 1 +#define GEN_INTACK 2 +#define GEN_HALTREQ 3 +#define GEN_RESTARTREQ 4 +#define PE_EDBGREQ 5 +#define PE_DBGRESTART 6 +#define PE_CTIIRQ 7 +#define PE_PMUIRQ 8 +#define PE_DBGTRIGGER 9 +#define ETM_EXTOUT 10 +#define ETM_EXTIN 11 +#define SNK_FULL 12 +#define SNK_ACQCOMP 13 +#define SNK_FLUSHCOMP 14 +#define SNK_FLUSHIN 15 +#define SNK_TRIGIN 16 +#define STM_ASYNCOUT 17 +#define STM_TOUT_SPTE 18 +#define STM_TOUT_SW 19 +#define STM_TOUT_HETE 20 +#define STM_HWEVENT 21 +#define ELA_TSTART 22 +#define ELA_TSTOP 23 +#define ELA_DBGREQ 24 +#define CTI_TRIG_MAX 25 + +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h index babd08a1d226..76b07826ed05 100644 --- a/include/dt-bindings/bus/ti-sysc.h +++ b/include/dt-bindings/bus/ti-sysc.h @@ -18,6 +18,10 @@ #define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) +/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ +#define SYSC_PRUSS_SUB_MWAIT (1 << 5) +#define SYSC_PRUSS_STANDBY_INIT (1 << 4) + /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ #define SYSC_IDLE_FORCE 0 #define SYSC_IDLE_NO 1 diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h index f0f04e0a249e..33b8826d936b 100644 --- a/include/dt-bindings/clock/dm814.h +++ b/include/dt-bindings/clock/dm814.h @@ -34,4 +34,9 @@ #define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220) #define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224) +/* alwon_ethernet clocks */ +#define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4 +#define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET) +#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4) + #endif diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index 72f2e8411523..8cec5a1e1806 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -29,6 +29,16 @@ #define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) #define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) +/* vip clocks */ +#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) + +/* vpe clocks */ +#define DRA7_VPE_CLKCTRL_OFFSET 0x60 +#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) +#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) + /* coreaon clocks */ #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) @@ -78,6 +88,9 @@ #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +/* gpu clocks */ +#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + /* l3init clocks */ #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) @@ -192,6 +205,16 @@ /* rtc clocks */ #define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) +/* vip clocks */ +#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) + +/* vpe clocks */ +#define DRA7_VPE_CLKCTRL_OFFSET 0x60 +#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) +#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) + /* coreaon clocks */ #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 0837c1a7ae49..b0d65d73db96 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -143,5 +143,7 @@ #define CLKID_CPU1_CLK 253 #define CLKID_CPU2_CLK 254 #define CLKID_CPU3_CLK 255 +#define CLKID_SPICC0_SCLK 258 +#define CLKID_SPICC1_SCLK 261 #endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index db0763e96173..4073eb7a9da1 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -146,5 +146,6 @@ #define CLKID_CTS_VDAC 201 #define CLKID_HDMI_TX 202 #define CLKID_HDMI 205 +#define CLKID_ACODEC 206 #endif /* __GXBB_CLKC_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index e6a670e1a3f8..1d4c0dfe0202 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -451,5 +451,6 @@ #define IMX7D_SNVS_CLK 442 #define IMX7D_CAAM_CLK 443 #define IMX7D_KPP_ROOT_CLK 444 -#define IMX7D_CLK_END 445 +#define IMX7D_PXP_CLK 445 +#define IMX7D_CLK_END 446 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index edeece2289f0..e63a5530aed7 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -265,6 +265,15 @@ #define IMX8MM_SYS_PLL2_333M_CG 244 #define IMX8MM_SYS_PLL2_500M_CG 245 -#define IMX8MM_CLK_END 246 +#define IMX8MM_CLK_M4_CORE 246 +#define IMX8MM_CLK_VPU_CORE 247 +#define IMX8MM_CLK_GPU3D_CORE 248 +#define IMX8MM_CLK_GPU2D_CORE 249 + +#define IMX8MM_CLK_CLKO2 250 + +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_END 252 #endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index 0f2b8423ce1d..621ea0e87c67 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -122,8 +122,8 @@ #define IMX8MN_CLK_I2C1 105 #define IMX8MN_CLK_I2C2 106 #define IMX8MN_CLK_I2C3 107 -#define IMX8MN_CLK_I2C4 118 -#define IMX8MN_CLK_UART1 119 +#define IMX8MN_CLK_I2C4 108 +#define IMX8MN_CLK_UART1 109 #define IMX8MN_CLK_UART2 110 #define IMX8MN_CLK_UART3 111 #define IMX8MN_CLK_UART4 112 @@ -228,6 +228,12 @@ #define IMX8MN_SYS_PLL2_333M_CG 209 #define IMX8MN_SYS_PLL2_500M_CG 210 -#define IMX8MN_CLK_END 211 +#define IMX8MN_CLK_SNVS_ROOT 211 +#define IMX8MN_CLK_GPU_CORE 212 +#define IMX8MN_CLK_GPU_SHADER 213 + +#define IMX8MN_CLK_A53_CORE 214 + +#define IMX8MN_CLK_END 215 #endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h new file mode 100644 index 000000000000..47ab082238b4 --- /dev/null +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H +#define __DT_BINDINGS_CLOCK_IMX8MP_H + +#define IMX8MP_CLK_DUMMY 0 +#define IMX8MP_CLK_32K 1 +#define IMX8MP_CLK_24M 2 +#define IMX8MP_OSC_HDMI_CLK 3 +#define IMX8MP_CLK_EXT1 4 +#define IMX8MP_CLK_EXT2 5 +#define IMX8MP_CLK_EXT3 6 +#define IMX8MP_CLK_EXT4 7 +#define IMX8MP_AUDIO_PLL1_REF_SEL 8 +#define IMX8MP_AUDIO_PLL2_REF_SEL 9 +#define IMX8MP_VIDEO_PLL1_REF_SEL 10 +#define IMX8MP_DRAM_PLL_REF_SEL 11 +#define IMX8MP_GPU_PLL_REF_SEL 12 +#define IMX8MP_VPU_PLL_REF_SEL 13 +#define IMX8MP_ARM_PLL_REF_SEL 14 +#define IMX8MP_SYS_PLL1_REF_SEL 15 +#define IMX8MP_SYS_PLL2_REF_SEL 16 +#define IMX8MP_SYS_PLL3_REF_SEL 17 +#define IMX8MP_AUDIO_PLL1 18 +#define IMX8MP_AUDIO_PLL2 19 +#define IMX8MP_VIDEO_PLL1 20 +#define IMX8MP_DRAM_PLL 21 +#define IMX8MP_GPU_PLL 22 +#define IMX8MP_VPU_PLL 23 +#define IMX8MP_ARM_PLL 24 +#define IMX8MP_SYS_PLL1 25 +#define IMX8MP_SYS_PLL2 26 +#define IMX8MP_SYS_PLL3 27 +#define IMX8MP_AUDIO_PLL1_BYPASS 28 +#define IMX8MP_AUDIO_PLL2_BYPASS 29 +#define IMX8MP_VIDEO_PLL1_BYPASS 30 +#define IMX8MP_DRAM_PLL_BYPASS 31 +#define IMX8MP_GPU_PLL_BYPASS 32 +#define IMX8MP_VPU_PLL_BYPASS 33 +#define IMX8MP_ARM_PLL_BYPASS 34 +#define IMX8MP_SYS_PLL1_BYPASS 35 +#define IMX8MP_SYS_PLL2_BYPASS 36 +#define IMX8MP_SYS_PLL3_BYPASS 37 +#define IMX8MP_AUDIO_PLL1_OUT 38 +#define IMX8MP_AUDIO_PLL2_OUT 39 +#define IMX8MP_VIDEO_PLL1_OUT 40 +#define IMX8MP_DRAM_PLL_OUT 41 +#define IMX8MP_GPU_PLL_OUT 42 +#define IMX8MP_VPU_PLL_OUT 43 +#define IMX8MP_ARM_PLL_OUT 44 +#define IMX8MP_SYS_PLL1_OUT 45 +#define IMX8MP_SYS_PLL2_OUT 46 +#define IMX8MP_SYS_PLL3_OUT 47 +#define IMX8MP_SYS_PLL1_40M 48 +#define IMX8MP_SYS_PLL1_80M 49 +#define IMX8MP_SYS_PLL1_100M 50 +#define IMX8MP_SYS_PLL1_133M 51 +#define IMX8MP_SYS_PLL1_160M 52 +#define IMX8MP_SYS_PLL1_200M 53 +#define IMX8MP_SYS_PLL1_266M 54 +#define IMX8MP_SYS_PLL1_400M 55 +#define IMX8MP_SYS_PLL1_800M 56 +#define IMX8MP_SYS_PLL2_50M 57 +#define IMX8MP_SYS_PLL2_100M 58 +#define IMX8MP_SYS_PLL2_125M 59 +#define IMX8MP_SYS_PLL2_166M 60 +#define IMX8MP_SYS_PLL2_200M 61 +#define IMX8MP_SYS_PLL2_250M 62 +#define IMX8MP_SYS_PLL2_333M 63 +#define IMX8MP_SYS_PLL2_500M 64 +#define IMX8MP_SYS_PLL2_1000M 65 +#define IMX8MP_CLK_A53_SRC 66 +#define IMX8MP_CLK_M7_SRC 67 +#define IMX8MP_CLK_ML_SRC 68 +#define IMX8MP_CLK_GPU3D_CORE_SRC 69 +#define IMX8MP_CLK_GPU3D_SHADER_SRC 70 +#define IMX8MP_CLK_GPU2D_SRC 71 +#define IMX8MP_CLK_AUDIO_AXI_SRC 72 +#define IMX8MP_CLK_HSIO_AXI_SRC 73 +#define IMX8MP_CLK_MEDIA_ISP_SRC 74 +#define IMX8MP_CLK_A53_CG 75 +#define IMX8MP_CLK_M4_CG 76 +#define IMX8MP_CLK_ML_CG 77 +#define IMX8MP_CLK_GPU3D_CORE_CG 78 +#define IMX8MP_CLK_GPU3D_SHADER_CG 79 +#define IMX8MP_CLK_GPU2D_CG 80 +#define IMX8MP_CLK_AUDIO_AXI_CG 81 +#define IMX8MP_CLK_HSIO_AXI_CG 82 +#define IMX8MP_CLK_MEDIA_ISP_CG 83 +#define IMX8MP_CLK_A53_DIV 84 +#define IMX8MP_CLK_M7_DIV 85 +#define IMX8MP_CLK_ML_DIV 86 +#define IMX8MP_CLK_GPU3D_CORE_DIV 87 +#define IMX8MP_CLK_GPU3D_SHADER_DIV 88 +#define IMX8MP_CLK_GPU2D_DIV 89 +#define IMX8MP_CLK_AUDIO_AXI_DIV 90 +#define IMX8MP_CLK_HSIO_AXI_DIV 91 +#define IMX8MP_CLK_MEDIA_ISP_DIV 92 +#define IMX8MP_CLK_MAIN_AXI 93 +#define IMX8MP_CLK_ENET_AXI 94 +#define IMX8MP_CLK_NAND_USDHC_BUS 95 +#define IMX8MP_CLK_VPU_BUS 96 +#define IMX8MP_CLK_MEDIA_AXI 97 +#define IMX8MP_CLK_MEDIA_APB 98 +#define IMX8MP_CLK_HDMI_APB 99 +#define IMX8MP_CLK_HDMI_AXI 100 +#define IMX8MP_CLK_GPU_AXI 101 +#define IMX8MP_CLK_GPU_AHB 102 +#define IMX8MP_CLK_NOC 103 +#define IMX8MP_CLK_NOC_IO 104 +#define IMX8MP_CLK_ML_AXI 105 +#define IMX8MP_CLK_ML_AHB 106 +#define IMX8MP_CLK_AHB 107 +#define IMX8MP_CLK_AUDIO_AHB 108 +#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109 +#define IMX8MP_CLK_IPG_ROOT 110 +#define IMX8MP_CLK_IPG_AUDIO_ROOT 111 +#define IMX8MP_CLK_DRAM_ALT 112 +#define IMX8MP_CLK_DRAM_APB 113 +#define IMX8MP_CLK_VPU_G1 114 +#define IMX8MP_CLK_VPU_G2 115 +#define IMX8MP_CLK_CAN1 116 +#define IMX8MP_CLK_CAN2 117 +#define IMX8MP_CLK_MEMREPAIR 118 +#define IMX8MP_CLK_PCIE_PHY 119 +#define IMX8MP_CLK_PCIE_AUX 120 +#define IMX8MP_CLK_I2C5 121 +#define IMX8MP_CLK_I2C6 122 +#define IMX8MP_CLK_SAI1 123 +#define IMX8MP_CLK_SAI2 124 +#define IMX8MP_CLK_SAI3 125 +#define IMX8MP_CLK_SAI4 126 +#define IMX8MP_CLK_SAI5 127 +#define IMX8MP_CLK_SAI6 128 +#define IMX8MP_CLK_ENET_QOS 129 +#define IMX8MP_CLK_ENET_QOS_TIMER 130 +#define IMX8MP_CLK_ENET_REF 131 +#define IMX8MP_CLK_ENET_TIMER 132 +#define IMX8MP_CLK_ENET_PHY_REF 133 +#define IMX8MP_CLK_NAND 134 +#define IMX8MP_CLK_QSPI 135 +#define IMX8MP_CLK_USDHC1 136 +#define IMX8MP_CLK_USDHC2 137 +#define IMX8MP_CLK_I2C1 138 +#define IMX8MP_CLK_I2C2 139 +#define IMX8MP_CLK_I2C3 140 +#define IMX8MP_CLK_I2C4 141 +#define IMX8MP_CLK_UART1 142 +#define IMX8MP_CLK_UART2 143 +#define IMX8MP_CLK_UART3 144 +#define IMX8MP_CLK_UART4 145 +#define IMX8MP_CLK_USB_CORE_REF 146 +#define IMX8MP_CLK_USB_PHY_REF 147 +#define IMX8MP_CLK_GIC 148 +#define IMX8MP_CLK_ECSPI1 149 +#define IMX8MP_CLK_ECSPI2 150 +#define IMX8MP_CLK_PWM1 151 +#define IMX8MP_CLK_PWM2 152 +#define IMX8MP_CLK_PWM3 153 +#define IMX8MP_CLK_PWM4 154 +#define IMX8MP_CLK_GPT1 155 +#define IMX8MP_CLK_GPT2 156 +#define IMX8MP_CLK_GPT3 157 +#define IMX8MP_CLK_GPT4 158 +#define IMX8MP_CLK_GPT5 159 +#define IMX8MP_CLK_GPT6 160 +#define IMX8MP_CLK_TRACE 161 +#define IMX8MP_CLK_WDOG 162 +#define IMX8MP_CLK_WRCLK 163 +#define IMX8MP_CLK_IPP_DO_CLKO1 164 +#define IMX8MP_CLK_IPP_DO_CLKO2 165 +#define IMX8MP_CLK_HDMI_FDCC_TST 166 +#define IMX8MP_CLK_HDMI_24M 167 +#define IMX8MP_CLK_HDMI_REF_266M 168 +#define IMX8MP_CLK_USDHC3 169 +#define IMX8MP_CLK_MEDIA_CAM1_PIX 170 +#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171 +#define IMX8MP_CLK_MEDIA_DISP1_PIX 172 +#define IMX8MP_CLK_MEDIA_CAM2_PIX 173 +#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174 +#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175 +#define IMX8MP_CLK_PCIE2_CTRL 176 +#define IMX8MP_CLK_PCIE2_PHY 177 +#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178 +#define IMX8MP_CLK_ECSPI3 179 +#define IMX8MP_CLK_PDM 180 +#define IMX8MP_CLK_VPU_VC8000E 181 +#define IMX8MP_CLK_SAI7 182 +#define IMX8MP_CLK_GPC_ROOT 183 +#define IMX8MP_CLK_ANAMIX_ROOT 184 +#define IMX8MP_CLK_CPU_ROOT 185 +#define IMX8MP_CLK_CSU_ROOT 186 +#define IMX8MP_CLK_DEBUG_ROOT 187 +#define IMX8MP_CLK_DRAM1_ROOT 188 +#define IMX8MP_CLK_ECSPI1_ROOT 189 +#define IMX8MP_CLK_ECSPI2_ROOT 190 +#define IMX8MP_CLK_ECSPI3_ROOT 191 +#define IMX8MP_CLK_ENET1_ROOT 192 +#define IMX8MP_CLK_GPIO1_ROOT 193 +#define IMX8MP_CLK_GPIO2_ROOT 194 +#define IMX8MP_CLK_GPIO3_ROOT 195 +#define IMX8MP_CLK_GPIO4_ROOT 196 +#define IMX8MP_CLK_GPIO5_ROOT 197 +#define IMX8MP_CLK_GPT1_ROOT 198 +#define IMX8MP_CLK_GPT2_ROOT 199 +#define IMX8MP_CLK_GPT3_ROOT 200 +#define IMX8MP_CLK_GPT4_ROOT 201 +#define IMX8MP_CLK_GPT5_ROOT 202 +#define IMX8MP_CLK_GPT6_ROOT 203 +#define IMX8MP_CLK_HS_ROOT 204 +#define IMX8MP_CLK_I2C1_ROOT 205 +#define IMX8MP_CLK_I2C2_ROOT 206 +#define IMX8MP_CLK_I2C3_ROOT 207 +#define IMX8MP_CLK_I2C4_ROOT 208 +#define IMX8MP_CLK_IOMUX_ROOT 209 +#define IMX8MP_CLK_IPMUX1_ROOT 210 +#define IMX8MP_CLK_IPMUX2_ROOT 211 +#define IMX8MP_CLK_IPMUX3_ROOT 212 +#define IMX8MP_CLK_MU_ROOT 213 +#define IMX8MP_CLK_OCOTP_ROOT 214 +#define IMX8MP_CLK_OCRAM_ROOT 215 +#define IMX8MP_CLK_OCRAM_S_ROOT 216 +#define IMX8MP_CLK_PCIE_ROOT 217 +#define IMX8MP_CLK_PERFMON1_ROOT 218 +#define IMX8MP_CLK_PERFMON2_ROOT 219 +#define IMX8MP_CLK_PWM1_ROOT 220 +#define IMX8MP_CLK_PWM2_ROOT 221 +#define IMX8MP_CLK_PWM3_ROOT 222 +#define IMX8MP_CLK_PWM4_ROOT 223 +#define IMX8MP_CLK_QOS_ROOT 224 +#define IMX8MP_CLK_QOS_ENET_ROOT 225 +#define IMX8MP_CLK_QSPI_ROOT 226 +#define IMX8MP_CLK_NAND_ROOT 227 +#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228 +#define IMX8MP_CLK_RDC_ROOT 229 +#define IMX8MP_CLK_ROM_ROOT 230 +#define IMX8MP_CLK_I2C5_ROOT 231 +#define IMX8MP_CLK_I2C6_ROOT 232 +#define IMX8MP_CLK_CAN1_ROOT 233 +#define IMX8MP_CLK_CAN2_ROOT 234 +#define IMX8MP_CLK_SCTR_ROOT 235 +#define IMX8MP_CLK_SDMA1_ROOT 236 +#define IMX8MP_CLK_ENET_QOS_ROOT 237 +#define IMX8MP_CLK_SEC_DEBUG_ROOT 238 +#define IMX8MP_CLK_SEMA1_ROOT 239 +#define IMX8MP_CLK_SEMA2_ROOT 240 +#define IMX8MP_CLK_IRQ_STEER_ROOT 241 +#define IMX8MP_CLK_SIM_ENET_ROOT 242 +#define IMX8MP_CLK_SIM_M_ROOT 243 +#define IMX8MP_CLK_SIM_MAIN_ROOT 244 +#define IMX8MP_CLK_SIM_S_ROOT 245 +#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246 +#define IMX8MP_CLK_GPU2D_ROOT 247 +#define IMX8MP_CLK_GPU3D_ROOT 248 +#define IMX8MP_CLK_SNVS_ROOT 249 +#define IMX8MP_CLK_TRACE_ROOT 250 +#define IMX8MP_CLK_UART1_ROOT 251 +#define IMX8MP_CLK_UART2_ROOT 252 +#define IMX8MP_CLK_UART3_ROOT 253 +#define IMX8MP_CLK_UART4_ROOT 254 +#define IMX8MP_CLK_USB_ROOT 255 +#define IMX8MP_CLK_USB_PHY_ROOT 256 +#define IMX8MP_CLK_USDHC1_ROOT 257 +#define IMX8MP_CLK_USDHC2_ROOT 258 +#define IMX8MP_CLK_WDOG1_ROOT 259 +#define IMX8MP_CLK_WDOG2_ROOT 260 +#define IMX8MP_CLK_WDOG3_ROOT 261 +#define IMX8MP_CLK_VPU_G1_ROOT 262 +#define IMX8MP_CLK_GPU_ROOT 263 +#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264 +#define IMX8MP_CLK_VPU_VC8KE_ROOT 265 +#define IMX8MP_CLK_VPU_G2_ROOT 266 +#define IMX8MP_CLK_NPU_ROOT 267 +#define IMX8MP_CLK_HSIO_ROOT 268 +#define IMX8MP_CLK_MEDIA_APB_ROOT 269 +#define IMX8MP_CLK_MEDIA_AXI_ROOT 270 +#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271 +#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272 +#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273 +#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274 +#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275 +#define IMX8MP_CLK_MEDIA_ISP_ROOT 276 +#define IMX8MP_CLK_USDHC3_ROOT 277 +#define IMX8MP_CLK_HDMI_ROOT 278 +#define IMX8MP_CLK_XTAL_ROOT 279 +#define IMX8MP_CLK_PLL_ROOT 280 +#define IMX8MP_CLK_TSENSOR_ROOT 281 +#define IMX8MP_CLK_VPU_ROOT 282 +#define IMX8MP_CLK_MRPR_ROOT 283 +#define IMX8MP_CLK_AUDIO_ROOT 284 +#define IMX8MP_CLK_DRAM_ALT_ROOT 285 +#define IMX8MP_CLK_DRAM_CORE 286 +#define IMX8MP_CLK_ARM 287 +#define IMX8MP_CLK_A53_CORE 288 + +#define IMX8MP_CLK_END 289 + +#endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 3bab9b21c8d7..9b8045d75b8b 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -424,6 +424,13 @@ #define IMX8MQ_SYS2_PLL_500M_CG 283 #define IMX8MQ_SYS2_PLL_1000M_CG 284 -#define IMX8MQ_CLK_END 285 +#define IMX8MQ_CLK_GPU_CORE 285 +#define IMX8MQ_CLK_GPU_SHADER 286 +#define IMX8MQ_CLK_M4_CORE 287 +#define IMX8MQ_CLK_VPU_CORE 288 + +#define IMX8MQ_CLK_A53_CORE 289 + +#define IMX8MQ_CLK_END 290 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h new file mode 100644 index 000000000000..5a2fd64d1a49 --- /dev/null +++ b/include/dt-bindings/clock/k210-clk.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef K210_CLK_H +#define K210_CLK_H + +/* + * Arbitrary identifiers for clocks. + * The structure is: in0 -> pll0 -> aclk -> cpu + * + * Since we use the hardware defaults for now, set all these to the same clock. + */ +#define K210_CLK_PLL0 0 +#define K210_CLK_PLL1 0 +#define K210_CLK_ACLK 0 +#define K210_CLK_CPU 0 + +#endif /* K210_CLK_H */ diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h index e785c6eb3561..06bb7fe4c62f 100644 --- a/include/dt-bindings/clock/marvell,mmp2.h +++ b/include/dt-bindings/clock/marvell,mmp2.h @@ -26,6 +26,9 @@ #define MMP2_CLK_VCTCXO_4 25 #define MMP2_CLK_UART_PLL 26 #define MMP2_CLK_USB_PLL 27 +#define MMP3_CLK_PLL1_P 28 +#define MMP3_CLK_PLL2_P 29 +#define MMP3_CLK_PLL3 30 /* apb periphrals */ #define MMP2_CLK_TWSI0 60 @@ -50,6 +53,10 @@ #define MMP2_CLK_SSP2 79 #define MMP2_CLK_SSP3 80 #define MMP2_CLK_TIMER 81 +#define MMP2_CLK_THERMAL0 82 +#define MMP3_CLK_THERMAL1 83 +#define MMP3_CLK_THERMAL2 84 +#define MMP3_CLK_THERMAL3 85 /* axi periphrals */ #define MMP2_CLK_SDH0 101 @@ -72,6 +79,14 @@ #define MMP2_CLK_CCIC1_PHY 118 #define MMP2_CLK_CCIC1_SPHY 119 #define MMP2_CLK_DISP0_LCDC 120 +#define MMP2_CLK_USBHSIC0 121 +#define MMP2_CLK_USBHSIC1 122 +#define MMP2_CLK_GPU_BUS 123 +#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS +#define MMP2_CLK_GPU_3D 124 +#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D +#define MMP3_CLK_GPU_2D 125 +#define MMP3_CLK_SDH4 126 #define MMP2_NR_CLKS 200 #endif diff --git a/include/dt-bindings/clock/meson8-ddr-clkc.h b/include/dt-bindings/clock/meson8-ddr-clkc.h new file mode 100644 index 000000000000..a8e0fa2987ab --- /dev/null +++ b/include/dt-bindings/clock/meson8-ddr-clkc.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#define DDR_CLKID_DDR_PLL_DCO 0 +#define DDR_CLKID_DDR_PLL 1 diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h index 5167b2d93ac3..88d73be84b94 100644 --- a/include/dt-bindings/clock/omap4.h +++ b/include/dt-bindings/clock/omap4.h @@ -124,6 +124,17 @@ #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) +/* l4_secure clocks */ +#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) + /* l4_wkup clocks */ #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index ba672064ccb4..41775272fd27 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -16,6 +16,7 @@ /* abe clocks */ #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) @@ -86,6 +87,17 @@ #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) +/* l4_secure clocks */ +#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 +#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) +#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) +#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) +#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) +#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) +#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) +#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) +#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) + /* iva clocks */ #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/include/dt-bindings/clock/qcom,dispcc-sc7180.h new file mode 100644 index 000000000000..b9b51617a335 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sc7180.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H + +#define DISP_CC_PLL0 0 +#define DISP_CC_PLL0_OUT_EVEN 1 +#define DISP_CC_MDSS_AHB_CLK 2 +#define DISP_CC_MDSS_AHB_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_CLK 4 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 +#define DISP_CC_MDSS_DP_AUX_CLK 8 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 10 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11 +#define DISP_CC_MDSS_DP_LINK_CLK 12 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15 +#define DISP_CC_MDSS_DP_PIXEL_CLK 16 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17 +#define DISP_CC_MDSS_ESC0_CLK 18 +#define DISP_CC_MDSS_ESC0_CLK_SRC 19 +#define DISP_CC_MDSS_MDP_CLK 20 +#define DISP_CC_MDSS_MDP_CLK_SRC 21 +#define DISP_CC_MDSS_MDP_LUT_CLK 22 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23 +#define DISP_CC_MDSS_PCLK0_CLK 24 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 25 +#define DISP_CC_MDSS_ROT_CLK 26 +#define DISP_CC_MDSS_ROT_CLK_SRC 27 +#define DISP_CC_MDSS_RSCC_AHB_CLK 28 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29 +#define DISP_CC_MDSS_VSYNC_CLK 30 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 31 +#define DISP_CC_XO_CLK 32 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h index 11eed4bc9646..4016fd1d5b46 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h +++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H @@ -35,6 +35,17 @@ #define DISP_CC_PLL0 25 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 +#define DISP_CC_MDSS_DP_AUX_CLK 28 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 +#define DISP_CC_MDSS_DP_LINK_CLK 32 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 +#define DISP_CC_MDSS_DP_PIXEL_CLK 37 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 /* DISP_CC Reset */ #define DISP_CC_MDSS_RSCC_BCR 0 diff --git a/include/dt-bindings/clock/qcom,gcc-ipq6018.h b/include/dt-bindings/clock/qcom,gcc-ipq6018.h new file mode 100644 index 000000000000..6f4be3aa0acf --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq6018.h @@ -0,0 +1,262 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H + +#define GPLL0 0 +#define UBI32_PLL 1 +#define GPLL6 2 +#define GPLL4 3 +#define PCNOC_BFDCD_CLK_SRC 4 +#define GPLL2 5 +#define NSS_CRYPTO_PLL 6 +#define NSS_PPE_CLK_SRC 7 +#define GCC_XO_CLK_SRC 8 +#define NSS_CE_CLK_SRC 9 +#define GCC_SLEEP_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define NSS_PORT5_RX_CLK_SRC 12 +#define NSS_PORT5_TX_CLK_SRC 13 +#define PCIE0_AXI_CLK_SRC 14 +#define USB0_MASTER_CLK_SRC 15 +#define APSS_AHB_POSTDIV_CLK_SRC 16 +#define NSS_PORT1_RX_CLK_SRC 17 +#define NSS_PORT1_TX_CLK_SRC 18 +#define NSS_PORT2_RX_CLK_SRC 19 +#define NSS_PORT2_TX_CLK_SRC 20 +#define NSS_PORT3_RX_CLK_SRC 21 +#define NSS_PORT3_TX_CLK_SRC 22 +#define NSS_PORT4_RX_CLK_SRC 23 +#define NSS_PORT4_TX_CLK_SRC 24 +#define NSS_PORT5_RX_DIV_CLK_SRC 25 +#define NSS_PORT5_TX_DIV_CLK_SRC 26 +#define APSS_AXI_CLK_SRC 27 +#define NSS_CRYPTO_CLK_SRC 28 +#define NSS_PORT1_RX_DIV_CLK_SRC 29 +#define NSS_PORT1_TX_DIV_CLK_SRC 30 +#define NSS_PORT2_RX_DIV_CLK_SRC 31 +#define NSS_PORT2_TX_DIV_CLK_SRC 32 +#define NSS_PORT3_RX_DIV_CLK_SRC 33 +#define NSS_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_PORT4_RX_DIV_CLK_SRC 35 +#define NSS_PORT4_TX_DIV_CLK_SRC 36 +#define NSS_UBI0_CLK_SRC 37 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49 +#define BLSP1_UART1_APPS_CLK_SRC 50 +#define BLSP1_UART2_APPS_CLK_SRC 51 +#define BLSP1_UART3_APPS_CLK_SRC 52 +#define BLSP1_UART4_APPS_CLK_SRC 53 +#define BLSP1_UART5_APPS_CLK_SRC 54 +#define BLSP1_UART6_APPS_CLK_SRC 55 +#define CRYPTO_CLK_SRC 56 +#define NSS_UBI0_DIV_CLK_SRC 57 +#define PCIE0_AUX_CLK_SRC 58 +#define PCIE0_PIPE_CLK_SRC 59 +#define SDCC1_APPS_CLK_SRC 60 +#define USB0_AUX_CLK_SRC 61 +#define USB0_MOCK_UTMI_CLK_SRC 62 +#define USB0_PIPE_CLK_SRC 63 +#define USB1_MOCK_UTMI_CLK_SRC 64 +#define GCC_APSS_AHB_CLK 65 +#define GCC_APSS_AXI_CLK 66 +#define GCC_BLSP1_AHB_CLK 67 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79 +#define GCC_BLSP1_UART1_APPS_CLK 80 +#define GCC_BLSP1_UART2_APPS_CLK 81 +#define GCC_BLSP1_UART3_APPS_CLK 82 +#define GCC_BLSP1_UART4_APPS_CLK 83 +#define GCC_BLSP1_UART5_APPS_CLK 84 +#define GCC_BLSP1_UART6_APPS_CLK 85 +#define GCC_CRYPTO_AHB_CLK 86 +#define GCC_CRYPTO_AXI_CLK 87 +#define GCC_CRYPTO_CLK 88 +#define GCC_XO_CLK 89 +#define GCC_XO_DIV4_CLK 90 +#define GCC_MDIO_AHB_CLK 91 +#define GCC_CRYPTO_PPE_CLK 92 +#define GCC_NSS_CE_APB_CLK 93 +#define GCC_NSS_CE_AXI_CLK 94 +#define GCC_NSS_CFG_CLK 95 +#define GCC_NSS_CRYPTO_CLK 96 +#define GCC_NSS_CSR_CLK 97 +#define GCC_NSS_EDMA_CFG_CLK 98 +#define GCC_NSS_EDMA_CLK 99 +#define GCC_NSS_NOC_CLK 100 +#define GCC_NSS_PORT1_RX_CLK 101 +#define GCC_NSS_PORT1_TX_CLK 102 +#define GCC_NSS_PORT2_RX_CLK 103 +#define GCC_NSS_PORT2_TX_CLK 104 +#define GCC_NSS_PORT3_RX_CLK 105 +#define GCC_NSS_PORT3_TX_CLK 106 +#define GCC_NSS_PORT4_RX_CLK 107 +#define GCC_NSS_PORT4_TX_CLK 108 +#define GCC_NSS_PORT5_RX_CLK 109 +#define GCC_NSS_PORT5_TX_CLK 110 +#define GCC_NSS_PPE_CFG_CLK 111 +#define GCC_NSS_PPE_CLK 112 +#define GCC_NSS_PPE_IPE_CLK 113 +#define GCC_NSS_PTP_REF_CLK 114 +#define GCC_NSSNOC_CE_APB_CLK 115 +#define GCC_NSSNOC_CE_AXI_CLK 116 +#define GCC_NSSNOC_CRYPTO_CLK 117 +#define GCC_NSSNOC_PPE_CFG_CLK 118 +#define GCC_NSSNOC_PPE_CLK 119 +#define GCC_NSSNOC_QOSGEN_REF_CLK 120 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 121 +#define GCC_NSSNOC_UBI0_AHB_CLK 122 +#define GCC_PORT1_MAC_CLK 123 +#define GCC_PORT2_MAC_CLK 124 +#define GCC_PORT3_MAC_CLK 125 +#define GCC_PORT4_MAC_CLK 126 +#define GCC_PORT5_MAC_CLK 127 +#define GCC_UBI0_AHB_CLK 128 +#define GCC_UBI0_AXI_CLK 129 +#define GCC_UBI0_CORE_CLK 130 +#define GCC_PCIE0_AHB_CLK 131 +#define GCC_PCIE0_AUX_CLK 132 +#define GCC_PCIE0_AXI_M_CLK 133 +#define GCC_PCIE0_AXI_S_CLK 134 +#define GCC_PCIE0_PIPE_CLK 135 +#define GCC_PRNG_AHB_CLK 136 +#define GCC_QPIC_AHB_CLK 137 +#define GCC_QPIC_CLK 138 +#define GCC_SDCC1_AHB_CLK 139 +#define GCC_SDCC1_APPS_CLK 140 +#define GCC_UNIPHY0_AHB_CLK 141 +#define GCC_UNIPHY0_PORT1_RX_CLK 142 +#define GCC_UNIPHY0_PORT1_TX_CLK 143 +#define GCC_UNIPHY0_PORT2_RX_CLK 144 +#define GCC_UNIPHY0_PORT2_TX_CLK 145 +#define GCC_UNIPHY0_PORT3_RX_CLK 146 +#define GCC_UNIPHY0_PORT3_TX_CLK 147 +#define GCC_UNIPHY0_PORT4_RX_CLK 148 +#define GCC_UNIPHY0_PORT4_TX_CLK 149 +#define GCC_UNIPHY0_PORT5_RX_CLK 150 +#define GCC_UNIPHY0_PORT5_TX_CLK 151 +#define GCC_UNIPHY0_SYS_CLK 152 +#define GCC_UNIPHY1_AHB_CLK 153 +#define GCC_UNIPHY1_PORT5_RX_CLK 154 +#define GCC_UNIPHY1_PORT5_TX_CLK 155 +#define GCC_UNIPHY1_SYS_CLK 156 +#define GCC_USB0_AUX_CLK 157 +#define GCC_USB0_MASTER_CLK 158 +#define GCC_USB0_MOCK_UTMI_CLK 159 +#define GCC_USB0_PHY_CFG_AHB_CLK 160 +#define GCC_USB0_PIPE_CLK 161 +#define GCC_USB0_SLEEP_CLK 162 +#define GCC_USB1_MASTER_CLK 163 +#define GCC_USB1_MOCK_UTMI_CLK 164 +#define GCC_USB1_PHY_CFG_AHB_CLK 165 +#define GCC_USB1_SLEEP_CLK 166 +#define GP1_CLK_SRC 167 +#define GP2_CLK_SRC 168 +#define GP3_CLK_SRC 169 +#define GCC_GP1_CLK 170 +#define GCC_GP2_CLK 171 +#define GCC_GP3_CLK 172 +#define SYSTEM_NOC_BFDCD_CLK_SRC 173 +#define GCC_NSSNOC_SNOC_CLK 174 +#define GCC_UBI0_NC_AXI_CLK 175 +#define GCC_UBI1_NC_AXI_CLK 176 +#define GPLL0_MAIN 177 +#define UBI32_PLL_MAIN 178 +#define GPLL6_MAIN 179 +#define GPLL4_MAIN 180 +#define GPLL2_MAIN 181 +#define NSS_CRYPTO_PLL_MAIN 182 +#define GCC_CMN_12GPLL_AHB_CLK 183 +#define GCC_CMN_12GPLL_SYS_CLK 184 +#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185 +#define GCC_SYS_NOC_USB0_AXI_CLK 186 +#define GCC_SYS_NOC_PCIE0_AXI_CLK 187 +#define QDSS_TSCTR_CLK_SRC 188 +#define QDSS_AT_CLK_SRC 189 +#define GCC_QDSS_AT_CLK 190 +#define GCC_QDSS_DAP_CLK 191 +#define ADSS_PWM_CLK_SRC 192 +#define GCC_ADSS_PWM_CLK 193 +#define SDCC1_ICE_CORE_CLK_SRC 194 +#define GCC_SDCC1_ICE_CORE_CLK 195 +#define GCC_DCC_CLK 196 +#define PCIE0_RCHNG_CLK_SRC 197 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198 +#define PCIE0_RCHNG_CLK 199 +#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200 +#define WCSS_AHB_CLK_SRC 201 +#define Q6_AXI_CLK_SRC 202 +#define GCC_Q6SS_PCLKDBG_CLK 203 +#define GCC_Q6_TSCTR_1TO2_CLK 204 +#define GCC_WCSS_CORE_TBU_CLK 205 +#define GCC_WCSS_AXI_M_CLK 206 +#define GCC_SYS_NOC_WCSS_AHB_CLK 207 +#define GCC_Q6_AXIM_CLK 208 +#define GCC_Q6SS_ATBM_CLK 209 +#define GCC_WCSS_Q6_TBU_CLK 210 +#define GCC_Q6_AXIM2_CLK 211 +#define GCC_Q6_AHB_CLK 212 +#define GCC_Q6_AHB_S_CLK 213 +#define GCC_WCSS_DBG_IFC_APB_CLK 214 +#define GCC_WCSS_DBG_IFC_ATB_CLK 215 +#define GCC_WCSS_DBG_IFC_NTS_CLK 216 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220 +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221 +#define GCC_WCSS_ECAHB_CLK 222 +#define GCC_WCSS_ACMT_CLK 223 +#define GCC_WCSS_AHB_S_CLK 224 +#define GCC_RBCPR_WCSS_CLK 225 +#define RBCPR_WCSS_CLK_SRC 226 +#define GCC_RBCPR_WCSS_AHB_CLK 227 +#define GCC_LPASS_CORE_AXIM_CLK 228 +#define GCC_LPASS_SNOC_CFG_CLK 229 +#define GCC_LPASS_Q6_AXIM_CLK 230 +#define GCC_LPASS_Q6_ATBM_AT_CLK 231 +#define GCC_LPASS_Q6_PCLKDBG_CLK 232 +#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233 +#define GCC_LPASS_Q6SS_TRIG_CLK 234 +#define GCC_LPASS_TBU_CLK 235 +#define LPASS_CORE_AXIM_CLK_SRC 236 +#define LPASS_SNOC_CFG_CLK_SRC 237 +#define LPASS_Q6_AXIM_CLK_SRC 238 +#define GCC_PCNOC_LPASS_CLK 239 +#define GCC_UBI0_UTCM_CLK 240 +#define SNOC_NSSNOC_BFDCD_CLK_SRC 241 +#define GCC_SNOC_NSSNOC_CLK 242 +#define GCC_MEM_NOC_Q6_AXI_CLK 243 +#define GCC_MEM_NOC_UBI32_CLK 244 +#define GCC_MEM_NOC_LPASS_CLK 245 +#define GCC_SNOC_LPASS_CFG_CLK 246 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247 +#define GCC_QDSS_STM_CLK 248 +#define GCC_QDSS_TRACECLKIN_CLK 249 +#define QDSS_STM_CLK_SRC 250 +#define QDSS_TRACECLKIN_CLK_SRC 251 +#define GCC_NSSNOC_ATB_CLK 252 +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index de1d8a1f5966..63e02dc32a0b 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -182,6 +182,7 @@ #define GCC_MSS_GPLL0_DIV_CLK_SRC 173 #define GCC_MSS_SNOC_AXI_CLK 174 #define GCC_MSS_MNOC_BIMC_AXI_CLK 175 +#define GCC_BIMC_GFX_CLK 176 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h index e8029b2e92d7..1258fd05db68 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc7180.h +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H @@ -132,6 +132,11 @@ #define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 #define GCC_VIDEO_THROTTLE_AXI_CLK 123 #define GCC_VIDEO_XO_CLK 124 +#define GCC_MSS_CFG_AHB_CLK 125 +#define GCC_MSS_MFAB_AXIS_CLK 126 +#define GCC_MSS_NAV_AXI_CLK 127 +#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 +#define GCC_MSS_SNOC_AXI_CLK 129 /* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 90d60ef94c64..3e1a91876610 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -240,4 +240,8 @@ #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +/* GCC GDSCRs */ +#define USB30_PRIM_GDSC 4 +#define USB30_SEC_GDSC 5 + #endif diff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h new file mode 100644 index 000000000000..7b7abe327e37 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL4 2 +#define GPLL9 3 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 5 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 6 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 8 +#define GCC_BOOT_ROM_AHB_CLK 9 +#define GCC_CAMERA_AHB_CLK 10 +#define GCC_CAMERA_HF_AXI_CLK 11 +#define GCC_CAMERA_SF_AXI_CLK 12 +#define GCC_CAMERA_XO_CLK 13 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15 +#define GCC_CPUSS_AHB_CLK 16 +#define GCC_CPUSS_AHB_CLK_SRC 17 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18 +#define GCC_CPUSS_DVM_BUS_CLK 19 +#define GCC_CPUSS_RBCPR_CLK 20 +#define GCC_DDRSS_GPU_AXI_CLK 21 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 22 +#define GCC_DISP_AHB_CLK 23 +#define GCC_DISP_HF_AXI_CLK 24 +#define GCC_DISP_SF_AXI_CLK 25 +#define GCC_DISP_XO_CLK 26 +#define GCC_GP1_CLK 27 +#define GCC_GP1_CLK_SRC 28 +#define GCC_GP2_CLK 29 +#define GCC_GP2_CLK_SRC 30 +#define GCC_GP3_CLK 31 +#define GCC_GP3_CLK_SRC 32 +#define GCC_GPU_CFG_AHB_CLK 33 +#define GCC_GPU_GPLL0_CLK_SRC 34 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 35 +#define GCC_GPU_IREF_EN 36 +#define GCC_GPU_MEMNOC_GFX_CLK 37 +#define GCC_GPU_SNOC_DVM_GFX_CLK 38 +#define GCC_NPU_AXI_CLK 39 +#define GCC_NPU_BWMON_AXI_CLK 40 +#define GCC_NPU_BWMON_CFG_AHB_CLK 41 +#define GCC_NPU_CFG_AHB_CLK 42 +#define GCC_NPU_DMA_CLK 43 +#define GCC_NPU_GPLL0_CLK_SRC 44 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 45 +#define GCC_PCIE0_PHY_REFGEN_CLK 46 +#define GCC_PCIE1_PHY_REFGEN_CLK 47 +#define GCC_PCIE2_PHY_REFGEN_CLK 48 +#define GCC_PCIE_0_AUX_CLK 49 +#define GCC_PCIE_0_AUX_CLK_SRC 50 +#define GCC_PCIE_0_CFG_AHB_CLK 51 +#define GCC_PCIE_0_MSTR_AXI_CLK 52 +#define GCC_PCIE_0_PIPE_CLK 53 +#define GCC_PCIE_0_SLV_AXI_CLK 54 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 +#define GCC_PCIE_1_AUX_CLK 56 +#define GCC_PCIE_1_AUX_CLK_SRC 57 +#define GCC_PCIE_1_CFG_AHB_CLK 58 +#define GCC_PCIE_1_MSTR_AXI_CLK 59 +#define GCC_PCIE_1_PIPE_CLK 60 +#define GCC_PCIE_1_SLV_AXI_CLK 61 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62 +#define GCC_PCIE_2_AUX_CLK 63 +#define GCC_PCIE_2_AUX_CLK_SRC 64 +#define GCC_PCIE_2_CFG_AHB_CLK 65 +#define GCC_PCIE_2_MSTR_AXI_CLK 66 +#define GCC_PCIE_2_PIPE_CLK 67 +#define GCC_PCIE_2_SLV_AXI_CLK 68 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69 +#define GCC_PCIE_MDM_CLKREF_EN 70 +#define GCC_PCIE_PHY_AUX_CLK 71 +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72 +#define GCC_PCIE_WIFI_CLKREF_EN 73 +#define GCC_PCIE_WIGIG_CLKREF_EN 74 +#define GCC_PDM2_CLK 75 +#define GCC_PDM2_CLK_SRC 76 +#define GCC_PDM_AHB_CLK 77 +#define GCC_PDM_XO4_CLK 78 +#define GCC_PRNG_AHB_CLK 79 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 81 +#define GCC_QMIP_DISP_AHB_CLK 82 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85 +#define GCC_QUPV3_WRAP0_CORE_CLK 86 +#define GCC_QUPV3_WRAP0_S0_CLK 87 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88 +#define GCC_QUPV3_WRAP0_S1_CLK 89 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90 +#define GCC_QUPV3_WRAP0_S2_CLK 91 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92 +#define GCC_QUPV3_WRAP0_S3_CLK 93 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94 +#define GCC_QUPV3_WRAP0_S4_CLK 95 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96 +#define GCC_QUPV3_WRAP0_S5_CLK 97 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98 +#define GCC_QUPV3_WRAP0_S6_CLK 99 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100 +#define GCC_QUPV3_WRAP0_S7_CLK 101 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103 +#define GCC_QUPV3_WRAP1_CORE_CLK 104 +#define GCC_QUPV3_WRAP1_S0_CLK 105 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106 +#define GCC_QUPV3_WRAP1_S1_CLK 107 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108 +#define GCC_QUPV3_WRAP1_S2_CLK 109 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110 +#define GCC_QUPV3_WRAP1_S3_CLK 111 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112 +#define GCC_QUPV3_WRAP1_S4_CLK 113 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114 +#define GCC_QUPV3_WRAP1_S5_CLK 115 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117 +#define GCC_QUPV3_WRAP2_CORE_CLK 118 +#define GCC_QUPV3_WRAP2_S0_CLK 119 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120 +#define GCC_QUPV3_WRAP2_S1_CLK 121 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122 +#define GCC_QUPV3_WRAP2_S2_CLK 123 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124 +#define GCC_QUPV3_WRAP2_S3_CLK 125 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126 +#define GCC_QUPV3_WRAP2_S4_CLK 127 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128 +#define GCC_QUPV3_WRAP2_S5_CLK 129 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136 +#define GCC_SDCC2_AHB_CLK 137 +#define GCC_SDCC2_APPS_CLK 138 +#define GCC_SDCC2_APPS_CLK_SRC 139 +#define GCC_SDCC4_AHB_CLK 140 +#define GCC_SDCC4_APPS_CLK 141 +#define GCC_SDCC4_APPS_CLK_SRC 142 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 143 +#define GCC_TSIF_AHB_CLK 144 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145 +#define GCC_TSIF_REF_CLK 146 +#define GCC_TSIF_REF_CLK_SRC 147 +#define GCC_UFS_1X_CLKREF_EN 148 +#define GCC_UFS_CARD_AHB_CLK 149 +#define GCC_UFS_CARD_AXI_CLK 150 +#define GCC_UFS_CARD_AXI_CLK_SRC 151 +#define GCC_UFS_CARD_ICE_CORE_CLK 152 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153 +#define GCC_UFS_CARD_PHY_AUX_CLK 154 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160 +#define GCC_UFS_PHY_AHB_CLK 161 +#define GCC_UFS_PHY_AXI_CLK 162 +#define GCC_UFS_PHY_AXI_CLK_SRC 163 +#define GCC_UFS_PHY_ICE_CORE_CLK 164 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165 +#define GCC_UFS_PHY_PHY_AUX_CLK 166 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172 +#define GCC_USB30_PRIM_MASTER_CLK 173 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 174 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177 +#define GCC_USB30_PRIM_SLEEP_CLK 178 +#define GCC_USB30_SEC_MASTER_CLK 179 +#define GCC_USB30_SEC_MASTER_CLK_SRC 180 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 181 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183 +#define GCC_USB30_SEC_SLEEP_CLK 184 +#define GCC_USB3_PRIM_PHY_AUX_CLK 185 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 188 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189 +#define GCC_USB3_SEC_CLKREF_EN 190 +#define GCC_USB3_SEC_PHY_AUX_CLK 191 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193 +#define GCC_USB3_SEC_PHY_PIPE_CLK 194 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195 +#define GCC_VIDEO_AHB_CLK 196 +#define GCC_VIDEO_AXI0_CLK 197 +#define GCC_VIDEO_AXI1_CLK 198 +#define GCC_VIDEO_XO_CLK 199 + +/* GCC resets */ +#define GCC_GPU_BCR 0 +#define GCC_MMSS_BCR 1 +#define GCC_NPU_BWMON_BCR 2 +#define GCC_NPU_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_2_BCR 14 +#define GCC_PCIE_2_LINK_DOWN_BCR 15 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_2_PHY_BCR 17 +#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18 +#define GCC_PCIE_PHY_BCR 19 +#define GCC_PCIE_PHY_CFG_AHB_BCR 20 +#define GCC_PCIE_PHY_COM_BCR 21 +#define GCC_PDM_BCR 22 +#define GCC_PRNG_BCR 23 +#define GCC_QUPV3_WRAPPER_0_BCR 24 +#define GCC_QUPV3_WRAPPER_1_BCR 25 +#define GCC_QUPV3_WRAPPER_2_BCR 26 +#define GCC_QUSB2PHY_PRIM_BCR 27 +#define GCC_QUSB2PHY_SEC_BCR 28 +#define GCC_SDCC2_BCR 29 +#define GCC_SDCC4_BCR 30 +#define GCC_TSIF_BCR 31 +#define GCC_UFS_CARD_BCR 32 +#define GCC_UFS_PHY_BCR 33 +#define GCC_USB30_PRIM_BCR 34 +#define GCC_USB30_SEC_BCR 35 +#define GCC_USB3_DP_PHY_PRIM_BCR 36 +#define GCC_USB3_DP_PHY_SEC_BCR 37 +#define GCC_USB3_PHY_PRIM_BCR 38 +#define GCC_USB3_PHY_SEC_BCR 39 +#define GCC_USB3PHY_PHY_PRIM_BCR 40 +#define GCC_USB3PHY_PHY_SEC_BCR 41 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42 +#define GCC_VIDEO_AXI0_CLK_ARES 43 +#define GCC_VIDEO_AXI1_CLK_ARES 44 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define PCIE_2_GDSC 2 +#define UFS_CARD_GDSC 3 +#define UFS_PHY_GDSC 4 +#define USB30_PRIM_GDSC 5 +#define USB30_SEC_GDSC 6 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7180.h b/include/dt-bindings/clock/qcom,gpucc-sc7180.h new file mode 100644 index 000000000000..65e706d7d9c6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sc7180.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H + +#define GPU_CC_PLL1 0 +#define GPU_CC_AHB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 + +/* GPU_CC GDSCRs */ +#define CX_GDSC 0 +#define GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8998.h b/include/dt-bindings/clock/qcom,mmcc-msm8998.h new file mode 100644 index 000000000000..ecbafdb930aa --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-msm8998.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H +#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H + +#define MMPLL0 0 +#define MMPLL0_OUT_EVEN 1 +#define MMPLL1 2 +#define MMPLL1_OUT_EVEN 3 +#define MMPLL3 4 +#define MMPLL3_OUT_EVEN 5 +#define MMPLL4 6 +#define MMPLL4_OUT_EVEN 7 +#define MMPLL5 8 +#define MMPLL5_OUT_EVEN 9 +#define MMPLL6 10 +#define MMPLL6_OUT_EVEN 11 +#define MMPLL7 12 +#define MMPLL7_OUT_EVEN 13 +#define MMPLL10 14 +#define MMPLL10_OUT_EVEN 15 +#define BYTE0_CLK_SRC 16 +#define BYTE1_CLK_SRC 17 +#define CCI_CLK_SRC 18 +#define CPP_CLK_SRC 19 +#define CSI0_CLK_SRC 20 +#define CSI1_CLK_SRC 21 +#define CSI2_CLK_SRC 22 +#define CSI3_CLK_SRC 23 +#define CSIPHY_CLK_SRC 24 +#define CSI0PHYTIMER_CLK_SRC 25 +#define CSI1PHYTIMER_CLK_SRC 26 +#define CSI2PHYTIMER_CLK_SRC 27 +#define DP_AUX_CLK_SRC 28 +#define DP_CRYPTO_CLK_SRC 29 +#define DP_LINK_CLK_SRC 30 +#define DP_PIXEL_CLK_SRC 31 +#define ESC0_CLK_SRC 32 +#define ESC1_CLK_SRC 33 +#define EXTPCLK_CLK_SRC 34 +#define FD_CORE_CLK_SRC 35 +#define HDMI_CLK_SRC 36 +#define JPEG0_CLK_SRC 37 +#define MAXI_CLK_SRC 38 +#define MCLK0_CLK_SRC 39 +#define MCLK1_CLK_SRC 40 +#define MCLK2_CLK_SRC 41 +#define MCLK3_CLK_SRC 42 +#define MDP_CLK_SRC 43 +#define VSYNC_CLK_SRC 44 +#define AHB_CLK_SRC 45 +#define AXI_CLK_SRC 46 +#define PCLK0_CLK_SRC 47 +#define PCLK1_CLK_SRC 48 +#define ROT_CLK_SRC 49 +#define VIDEO_CORE_CLK_SRC 50 +#define VIDEO_SUBCORE0_CLK_SRC 51 +#define VIDEO_SUBCORE1_CLK_SRC 52 +#define VFE0_CLK_SRC 53 +#define VFE1_CLK_SRC 54 +#define MISC_AHB_CLK 55 +#define VIDEO_CORE_CLK 56 +#define VIDEO_AHB_CLK 57 +#define VIDEO_AXI_CLK 58 +#define VIDEO_MAXI_CLK 59 +#define VIDEO_SUBCORE0_CLK 60 +#define VIDEO_SUBCORE1_CLK 61 +#define MDSS_AHB_CLK 62 +#define MDSS_HDMI_DP_AHB_CLK 63 +#define MDSS_AXI_CLK 64 +#define MDSS_PCLK0_CLK 65 +#define MDSS_PCLK1_CLK 66 +#define MDSS_MDP_CLK 67 +#define MDSS_MDP_LUT_CLK 68 +#define MDSS_EXTPCLK_CLK 69 +#define MDSS_VSYNC_CLK 70 +#define MDSS_HDMI_CLK 71 +#define MDSS_BYTE0_CLK 72 +#define MDSS_BYTE1_CLK 73 +#define MDSS_ESC0_CLK 74 +#define MDSS_ESC1_CLK 75 +#define MDSS_ROT_CLK 76 +#define MDSS_DP_LINK_CLK 77 +#define MDSS_DP_LINK_INTF_CLK 78 +#define MDSS_DP_CRYPTO_CLK 79 +#define MDSS_DP_PIXEL_CLK 80 +#define MDSS_DP_AUX_CLK 81 +#define MDSS_BYTE0_INTF_CLK 82 +#define MDSS_BYTE1_INTF_CLK 83 +#define CAMSS_CSI0PHYTIMER_CLK 84 +#define CAMSS_CSI1PHYTIMER_CLK 85 +#define CAMSS_CSI2PHYTIMER_CLK 86 +#define CAMSS_CSI0_CLK 87 +#define CAMSS_CSI0_AHB_CLK 88 +#define CAMSS_CSI0RDI_CLK 89 +#define CAMSS_CSI0PIX_CLK 90 +#define CAMSS_CSI1_CLK 91 +#define CAMSS_CSI1_AHB_CLK 92 +#define CAMSS_CSI1RDI_CLK 93 +#define CAMSS_CSI1PIX_CLK 94 +#define CAMSS_CSI2_CLK 95 +#define CAMSS_CSI2_AHB_CLK 96 +#define CAMSS_CSI2RDI_CLK 97 +#define CAMSS_CSI2PIX_CLK 98 +#define CAMSS_CSI3_CLK 99 +#define CAMSS_CSI3_AHB_CLK 100 +#define CAMSS_CSI3RDI_CLK 101 +#define CAMSS_CSI3PIX_CLK 102 +#define CAMSS_ISPIF_AHB_CLK 103 +#define CAMSS_CCI_CLK 104 +#define CAMSS_CCI_AHB_CLK 105 +#define CAMSS_MCLK0_CLK 106 +#define CAMSS_MCLK1_CLK 107 +#define CAMSS_MCLK2_CLK 108 +#define CAMSS_MCLK3_CLK 109 +#define CAMSS_TOP_AHB_CLK 110 +#define CAMSS_AHB_CLK 111 +#define CAMSS_MICRO_AHB_CLK 112 +#define CAMSS_JPEG0_CLK 113 +#define CAMSS_JPEG_AHB_CLK 114 +#define CAMSS_JPEG_AXI_CLK 115 +#define CAMSS_VFE0_AHB_CLK 116 +#define CAMSS_VFE1_AHB_CLK 117 +#define CAMSS_VFE0_CLK 118 +#define CAMSS_VFE1_CLK 119 +#define CAMSS_CPP_CLK 120 +#define CAMSS_CPP_AHB_CLK 121 +#define CAMSS_VFE_VBIF_AHB_CLK 122 +#define CAMSS_VFE_VBIF_AXI_CLK 123 +#define CAMSS_CPP_AXI_CLK 124 +#define CAMSS_CPP_VBIF_AHB_CLK 125 +#define CAMSS_CSI_VFE0_CLK 126 +#define CAMSS_CSI_VFE1_CLK 127 +#define CAMSS_VFE0_STREAM_CLK 128 +#define CAMSS_VFE1_STREAM_CLK 129 +#define CAMSS_CPHY_CSID0_CLK 130 +#define CAMSS_CPHY_CSID1_CLK 131 +#define CAMSS_CPHY_CSID2_CLK 132 +#define CAMSS_CPHY_CSID3_CLK 133 +#define CAMSS_CSIPHY0_CLK 134 +#define CAMSS_CSIPHY1_CLK 135 +#define CAMSS_CSIPHY2_CLK 136 +#define FD_CORE_CLK 137 +#define FD_CORE_UAR_CLK 138 +#define FD_AHB_CLK 139 +#define MNOC_AHB_CLK 140 +#define BIMC_SMMU_AHB_CLK 141 +#define BIMC_SMMU_AXI_CLK 142 +#define MNOC_MAXI_CLK 143 +#define VMEM_MAXI_CLK 144 +#define VMEM_AHB_CLK 145 + +#define SPDM_BCR 0 +#define SPDM_RM_BCR 1 +#define MISC_BCR 2 +#define VIDEO_TOP_BCR 3 +#define THROTTLE_VIDEO_BCR 4 +#define MDSS_BCR 5 +#define THROTTLE_MDSS_BCR 6 +#define CAMSS_PHY0_BCR 7 +#define CAMSS_PHY1_BCR 8 +#define CAMSS_PHY2_BCR 9 +#define CAMSS_CSI0_BCR 10 +#define CAMSS_CSI0RDI_BCR 11 +#define CAMSS_CSI0PIX_BCR 12 +#define CAMSS_CSI1_BCR 13 +#define CAMSS_CSI1RDI_BCR 14 +#define CAMSS_CSI1PIX_BCR 15 +#define CAMSS_CSI2_BCR 16 +#define CAMSS_CSI2RDI_BCR 17 +#define CAMSS_CSI2PIX_BCR 18 +#define CAMSS_CSI3_BCR 19 +#define CAMSS_CSI3RDI_BCR 20 +#define CAMSS_CSI3PIX_BCR 21 +#define CAMSS_ISPIF_BCR 22 +#define CAMSS_CCI_BCR 23 +#define CAMSS_TOP_BCR 24 +#define CAMSS_AHB_BCR 25 +#define CAMSS_MICRO_BCR 26 +#define CAMSS_JPEG_BCR 27 +#define CAMSS_VFE0_BCR 28 +#define CAMSS_VFE1_BCR 29 +#define CAMSS_VFE_VBIF_BCR 30 +#define CAMSS_CPP_TOP_BCR 31 +#define CAMSS_CPP_BCR 32 +#define CAMSS_CSI_VFE0_BCR 33 +#define CAMSS_CSI_VFE1_BCR 34 +#define CAMSS_FD_BCR 35 +#define THROTTLE_CAMSS_BCR 36 +#define MNOCAHB_BCR 37 +#define MNOCAXI_BCR 38 +#define BMIC_SMMU_BCR 39 +#define MNOC_MAXI_BCR 40 +#define VMEM_BCR 41 +#define BTO_BCR 42 + +#define VIDEO_TOP_GDSC 1 +#define VIDEO_SUBCORE0_GDSC 2 +#define VIDEO_SUBCORE1_GDSC 3 +#define MDSS_GDSC 4 +#define CAMSS_TOP_GDSC 5 +#define CAMSS_VFE0_GDSC 6 +#define CAMSS_VFE1_GDSC 7 +#define CAMSS_CPP_GDSC 8 +#define BIMC_SMMU_GDSC 9 + +#endif diff --git a/include/dt-bindings/clock/qcom,mss-sc7180.h b/include/dt-bindings/clock/qcom,mss-sc7180.h new file mode 100644 index 000000000000..f15a9ded2961 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mss-sc7180.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H + +#define MSS_AXI_CRYPTO_CLK 0 +#define MSS_AXI_NAV_CLK 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 8e3095720552..ae74c43c485d 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -37,6 +37,10 @@ #define RPM_XO_A0 27 #define RPM_XO_A1 28 #define RPM_XO_A2 29 +#define RPM_NSS_FABRIC_0_CLK 30 +#define RPM_NSS_FABRIC_0_A_CLK 31 +#define RPM_NSS_FABRIC_1_CLK 32 +#define RPM_NSS_FABRIC_1_A_CLK 33 /* SMD RPM clocks */ #define RPM_SMD_XO_CLK_SRC 0 diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h index edcab3f7b7d3..2e6c54e65455 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MSM_RPMH_H @@ -19,5 +19,7 @@ #define RPMH_RF_CLK3 10 #define RPMH_RF_CLK3_A 11 #define RPMH_IPA_CLK 12 +#define RPMH_LN_BB_CLK1 13 +#define RPMH_LN_BB_CLK1_A 14 #endif diff --git a/include/dt-bindings/clock/qcom,videocc-sc7180.h b/include/dt-bindings/clock/qcom,videocc-sc7180.h new file mode 100644 index 000000000000..7acaf1366b13 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sc7180.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H + +/* VIDEO_CC clocks */ +#define VIDEO_PLL0 0 +#define VIDEO_CC_VCODEC0_AXI_CLK 1 +#define VIDEO_CC_VCODEC0_CORE_CLK 2 +#define VIDEO_CC_VENUS_AHB_CLK 3 +#define VIDEO_CC_VENUS_CLK_SRC 4 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 5 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 6 +#define VIDEO_CC_XO_CLK 7 + +/* VIDEO_CC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/sprd,sc9863a-clk.h b/include/dt-bindings/clock/sprd,sc9863a-clk.h new file mode 100644 index 000000000000..901ba59676c2 --- /dev/null +++ b/include/dt-bindings/clock/sprd,sc9863a-clk.h @@ -0,0 +1,334 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Unisoc SC9863A platform clocks + * + * Copyright (C) 2019, Unisoc Communications Inc. + */ + +#ifndef _DT_BINDINGS_CLK_SC9863A_H_ +#define _DT_BINDINGS_CLK_SC9863A_H_ + +#define CLK_MPLL0_GATE 0 +#define CLK_DPLL0_GATE 1 +#define CLK_LPLL_GATE 2 +#define CLK_GPLL_GATE 3 +#define CLK_DPLL1_GATE 4 +#define CLK_MPLL1_GATE 5 +#define CLK_MPLL2_GATE 6 +#define CLK_ISPPLL_GATE 7 +#define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1) + +#define CLK_AUDIO_GATE 0 +#define CLK_RPLL 1 +#define CLK_RPLL_390M 2 +#define CLK_RPLL_260M 3 +#define CLK_RPLL_195M 4 +#define CLK_RPLL_26M 5 +#define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1) + +#define CLK_TWPLL 0 +#define CLK_TWPLL_768M 1 +#define CLK_TWPLL_384M 2 +#define CLK_TWPLL_192M 3 +#define CLK_TWPLL_96M 4 +#define CLK_TWPLL_48M 5 +#define CLK_TWPLL_24M 6 +#define CLK_TWPLL_12M 7 +#define CLK_TWPLL_512M 8 +#define CLK_TWPLL_256M 9 +#define CLK_TWPLL_128M 10 +#define CLK_TWPLL_64M 11 +#define CLK_TWPLL_307M2 12 +#define CLK_TWPLL_219M4 13 +#define CLK_TWPLL_170M6 14 +#define CLK_TWPLL_153M6 15 +#define CLK_TWPLL_76M8 16 +#define CLK_TWPLL_51M2 17 +#define CLK_TWPLL_38M4 18 +#define CLK_TWPLL_19M2 19 +#define CLK_LPLL 20 +#define CLK_LPLL_409M6 21 +#define CLK_LPLL_245M76 22 +#define CLK_GPLL 23 +#define CLK_ISPPLL 24 +#define CLK_ISPPLL_468M 25 +#define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1) + +#define CLK_DPLL0 0 +#define CLK_DPLL1 1 +#define CLK_DPLL0_933M 2 +#define CLK_DPLL0_622M3 3 +#define CLK_DPLL0_400M 4 +#define CLK_DPLL0_266M7 5 +#define CLK_DPLL0_123M1 6 +#define CLK_DPLL0_50M 7 +#define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1) + +#define CLK_MPLL0 0 +#define CLK_MPLL1 1 +#define CLK_MPLL2 2 +#define CLK_MPLL2_675M 3 +#define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1) + +#define CLK_AP_APB 0 +#define CLK_AP_CE 1 +#define CLK_NANDC_ECC 2 +#define CLK_NANDC_26M 3 +#define CLK_EMMC_32K 4 +#define CLK_SDIO0_32K 5 +#define CLK_SDIO1_32K 6 +#define CLK_SDIO2_32K 7 +#define CLK_OTG_UTMI 8 +#define CLK_AP_UART0 9 +#define CLK_AP_UART1 10 +#define CLK_AP_UART2 11 +#define CLK_AP_UART3 12 +#define CLK_AP_UART4 13 +#define CLK_AP_I2C0 14 +#define CLK_AP_I2C1 15 +#define CLK_AP_I2C2 16 +#define CLK_AP_I2C3 17 +#define CLK_AP_I2C4 18 +#define CLK_AP_I2C5 19 +#define CLK_AP_I2C6 20 +#define CLK_AP_SPI0 21 +#define CLK_AP_SPI1 22 +#define CLK_AP_SPI2 23 +#define CLK_AP_SPI3 24 +#define CLK_AP_IIS0 25 +#define CLK_AP_IIS1 26 +#define CLK_AP_IIS2 27 +#define CLK_SIM0 28 +#define CLK_SIM0_32K 29 +#define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1) + +#define CLK_13M 0 +#define CLK_6M5 1 +#define CLK_4M3 2 +#define CLK_2M 3 +#define CLK_250K 4 +#define CLK_RCO_25M 5 +#define CLK_RCO_4M 6 +#define CLK_RCO_2M 7 +#define CLK_EMC 8 +#define CLK_AON_APB 9 +#define CLK_ADI 10 +#define CLK_AUX0 11 +#define CLK_AUX1 12 +#define CLK_AUX2 13 +#define CLK_PROBE 14 +#define CLK_PWM0 15 +#define CLK_PWM1 16 +#define CLK_PWM2 17 +#define CLK_AON_THM 18 +#define CLK_AUDIF 19 +#define CLK_CPU_DAP 20 +#define CLK_CPU_TS 21 +#define CLK_DJTAG_TCK 22 +#define CLK_EMC_REF 23 +#define CLK_CSSYS 24 +#define CLK_AON_PMU 25 +#define CLK_PMU_26M 26 +#define CLK_AON_TMR 27 +#define CLK_POWER_CPU 28 +#define CLK_AP_AXI 29 +#define CLK_SDIO0_2X 30 +#define CLK_SDIO1_2X 31 +#define CLK_SDIO2_2X 32 +#define CLK_EMMC_2X 33 +#define CLK_DPU 34 +#define CLK_DPU_DPI 35 +#define CLK_OTG_REF 36 +#define CLK_SDPHY_APB 37 +#define CLK_ALG_IO_APB 38 +#define CLK_GPU_CORE 39 +#define CLK_GPU_SOC 40 +#define CLK_MM_EMC 41 +#define CLK_MM_AHB 42 +#define CLK_BPC 43 +#define CLK_DCAM_IF 44 +#define CLK_ISP 45 +#define CLK_JPG 46 +#define CLK_CPP 47 +#define CLK_SENSOR0 48 +#define CLK_SENSOR1 49 +#define CLK_SENSOR2 50 +#define CLK_MM_VEMC 51 +#define CLK_MM_VAHB 52 +#define CLK_VSP 53 +#define CLK_CORE0 54 +#define CLK_CORE1 55 +#define CLK_CORE2 56 +#define CLK_CORE3 57 +#define CLK_CORE4 58 +#define CLK_CORE5 59 +#define CLK_CORE6 60 +#define CLK_CORE7 61 +#define CLK_SCU 62 +#define CLK_ACE 63 +#define CLK_AXI_PERIPH 64 +#define CLK_AXI_ACP 65 +#define CLK_ATB 66 +#define CLK_DEBUG_APB 67 +#define CLK_GIC 68 +#define CLK_PERIPH 69 +#define CLK_AON_CLK_NUM (CLK_VSP + 1) + +#define CLK_OTG_EB 0 +#define CLK_DMA_EB 1 +#define CLK_CE_EB 2 +#define CLK_NANDC_EB 3 +#define CLK_SDIO0_EB 4 +#define CLK_SDIO1_EB 5 +#define CLK_SDIO2_EB 6 +#define CLK_EMMC_EB 7 +#define CLK_EMMC_32K_EB 8 +#define CLK_SDIO0_32K_EB 9 +#define CLK_SDIO1_32K_EB 10 +#define CLK_SDIO2_32K_EB 11 +#define CLK_NANDC_26M_EB 12 +#define CLK_DMA_EB2 13 +#define CLK_CE_EB2 14 +#define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1) + +#define CLK_GPIO_EB 0 +#define CLK_PWM0_EB 1 +#define CLK_PWM1_EB 2 +#define CLK_PWM2_EB 3 +#define CLK_PWM3_EB 4 +#define CLK_KPD_EB 5 +#define CLK_AON_SYST_EB 6 +#define CLK_AP_SYST_EB 7 +#define CLK_AON_TMR_EB 8 +#define CLK_EFUSE_EB 9 +#define CLK_EIC_EB 10 +#define CLK_INTC_EB 11 +#define CLK_ADI_EB 12 +#define CLK_AUDIF_EB 13 +#define CLK_AUD_EB 14 +#define CLK_VBC_EB 15 +#define CLK_PIN_EB 16 +#define CLK_AP_WDG_EB 17 +#define CLK_MM_EB 18 +#define CLK_AON_APB_CKG_EB 19 +#define CLK_CA53_TS0_EB 20 +#define CLK_CA53_TS1_EB 21 +#define CLK_CS53_DAP_EB 22 +#define CLK_PMU_EB 23 +#define CLK_THM_EB 24 +#define CLK_AUX0_EB 25 +#define CLK_AUX1_EB 26 +#define CLK_AUX2_EB 27 +#define CLK_PROBE_EB 28 +#define CLK_EMC_REF_EB 29 +#define CLK_CA53_WDG_EB 30 +#define CLK_AP_TMR1_EB 31 +#define CLK_AP_TMR2_EB 32 +#define CLK_DISP_EMC_EB 33 +#define CLK_ZIP_EMC_EB 34 +#define CLK_GSP_EMC_EB 35 +#define CLK_MM_VSP_EB 36 +#define CLK_MDAR_EB 37 +#define CLK_RTC4M0_CAL_EB 38 +#define CLK_RTC4M1_CAL_EB 39 +#define CLK_DJTAG_EB 40 +#define CLK_MBOX_EB 41 +#define CLK_AON_DMA_EB 42 +#define CLK_AON_APB_DEF_EB 43 +#define CLK_CA5_TS0_EB 44 +#define CLK_DBG_EB 45 +#define CLK_DBG_EMC_EB 46 +#define CLK_CROSS_TRIG_EB 47 +#define CLK_SERDES_DPHY_EB 48 +#define CLK_ARCH_RTC_EB 49 +#define CLK_KPD_RTC_EB 50 +#define CLK_AON_SYST_RTC_EB 51 +#define CLK_AP_SYST_RTC_EB 52 +#define CLK_AON_TMR_RTC_EB 53 +#define CLK_AP_TMR0_RTC_EB 54 +#define CLK_EIC_RTC_EB 55 +#define CLK_EIC_RTCDV5_EB 56 +#define CLK_AP_WDG_RTC_EB 57 +#define CLK_CA53_WDG_RTC_EB 58 +#define CLK_THM_RTC_EB 59 +#define CLK_ATHMA_RTC_EB 60 +#define CLK_GTHMA_RTC_EB 61 +#define CLK_ATHMA_RTC_A_EB 62 +#define CLK_GTHMA_RTC_A_EB 63 +#define CLK_AP_TMR1_RTC_EB 64 +#define CLK_AP_TMR2_RTC_EB 65 +#define CLK_DXCO_LC_RTC_EB 66 +#define CLK_BB_CAL_RTC_EB 67 +#define CLK_GNU_EB 68 +#define CLK_DISP_EB 69 +#define CLK_MM_EMC_EB 70 +#define CLK_POWER_CPU_EB 71 +#define CLK_HW_I2C_EB 72 +#define CLK_MM_VSP_EMC_EB 73 +#define CLK_VSP_EB 74 +#define CLK_CSSYS_EB 75 +#define CLK_DMC_EB 76 +#define CLK_ROSC_EB 77 +#define CLK_S_D_CFG_EB 78 +#define CLK_S_D_REF_EB 79 +#define CLK_B_DMA_EB 80 +#define CLK_ANLG_EB 81 +#define CLK_ANLG_APB_EB 82 +#define CLK_BSMTMR_EB 83 +#define CLK_AP_AXI_EB 84 +#define CLK_AP_INTC0_EB 85 +#define CLK_AP_INTC1_EB 86 +#define CLK_AP_INTC2_EB 87 +#define CLK_AP_INTC3_EB 88 +#define CLK_AP_INTC4_EB 89 +#define CLK_AP_INTC5_EB 90 +#define CLK_SCC_EB 91 +#define CLK_DPHY_CFG_EB 92 +#define CLK_DPHY_REF_EB 93 +#define CLK_CPHY_CFG_EB 94 +#define CLK_OTG_REF_EB 95 +#define CLK_SERDES_EB 96 +#define CLK_AON_AP_EMC_EB 97 +#define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1) + +#define CLK_MAHB_CKG_EB 0 +#define CLK_MDCAM_EB 1 +#define CLK_MISP_EB 2 +#define CLK_MAHBCSI_EB 3 +#define CLK_MCSI_S_EB 4 +#define CLK_MCSI_T_EB 5 +#define CLK_DCAM_AXI_EB 6 +#define CLK_ISP_AXI_EB 7 +#define CLK_MCSI_EB 8 +#define CLK_MCSI_S_CKG_EB 9 +#define CLK_MCSI_T_CKG_EB 10 +#define CLK_SENSOR0_EB 11 +#define CLK_SENSOR1_EB 12 +#define CLK_SENSOR2_EB 13 +#define CLK_MCPHY_CFG_EB 14 +#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1) + +#define CLK_SIM0_EB 0 +#define CLK_IIS0_EB 1 +#define CLK_IIS1_EB 2 +#define CLK_IIS2_EB 3 +#define CLK_SPI0_EB 4 +#define CLK_SPI1_EB 5 +#define CLK_SPI2_EB 6 +#define CLK_I2C0_EB 7 +#define CLK_I2C1_EB 8 +#define CLK_I2C2_EB 9 +#define CLK_I2C3_EB 10 +#define CLK_I2C4_EB 11 +#define CLK_UART0_EB 12 +#define CLK_UART1_EB 13 +#define CLK_UART2_EB 14 +#define CLK_UART3_EB 15 +#define CLK_UART4_EB 16 +#define CLK_SIM0_32K_EB 17 +#define CLK_SPI3_EB 18 +#define CLK_I2C5_EB 19 +#define CLK_I2C6_EB 20 +#define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1) + +#endif /* _DT_BINDINGS_CLK_SC9863A_H_ */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index a8ac4cfcdcbc..318eb15c414c 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -46,6 +46,7 @@ #define CLK_PLL_VIDEO0 7 #define CLK_PLL_PERIPH0 11 +#define CLK_CPUX 21 #define CLK_BUS_MIPI_DSI 28 #define CLK_BUS_CE 29 #define CLK_BUS_DMA 30 @@ -130,7 +131,7 @@ #define CLK_AVS 109 #define CLK_HDMI 110 #define CLK_HDMI_DDC 111 - +#define CLK_MBUS 112 #define CLK_DSI_DPHY 113 #define CLK_GPU 114 diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h index c5d13340184a..39878d9dce9f 100644 --- a/include/dt-bindings/clock/sun6i-a31-ccu.h +++ b/include/dt-bindings/clock/sun6i-a31-ccu.h @@ -49,6 +49,8 @@ #define CLK_PLL_VIDEO1_2X 13 +#define CLK_PLL_MIPI 15 + #define CLK_CPU 18 #define CLK_AHB1_MIPIDSI 23 diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h index f8222b6b2cc3..eb524d0bbd01 100644 --- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h +++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h @@ -43,6 +43,8 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ #define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ +#define CLK_PLL_MIPI 13 + #define CLK_CPUX 18 #define CLK_BUS_MIPI_DSI 23 diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h index f9e15a235626..d7337b55a4ef 100644 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ b/include/dt-bindings/clock/sun8i-r40-ccu.h @@ -176,7 +176,7 @@ #define CLK_AVS 152 #define CLK_HDMI 153 #define CLK_HDMI_SLOW 154 - +#define CLK_MBUS 155 #define CLK_DSI_DPHY 156 #define CLK_TVE0 157 #define CLK_TVE1 158 diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index bb5c2c999c05..df59aaf5bf34 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -228,6 +228,8 @@ #define TEGRA114_CLK_CLK_M 201 #define TEGRA114_CLK_CLK_M_DIV2 202 #define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_OSC_DIV2 202 +#define TEGRA114_CLK_OSC_DIV4 203 #define TEGRA114_CLK_PLL_REF 204 #define TEGRA114_CLK_PLL_C 205 #define TEGRA114_CLK_PLL_C_OUT1 206 @@ -274,7 +276,7 @@ #define TEGRA114_CLK_CLK_OUT_2 246 #define TEGRA114_CLK_CLK_OUT_3 247 #define TEGRA114_CLK_BLINK 248 -/* 249 */ +#define TEGRA114_CLK_OSC 249 /* 250 */ /* 251 */ #define TEGRA114_CLK_XUSB_HOST_SRC 252 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 0c4f5be0a742..2a9acd592bff 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -227,6 +227,8 @@ #define TEGRA124_CLK_CLK_M 201 #define TEGRA124_CLK_CLK_M_DIV2 202 #define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_OSC_DIV2 202 +#define TEGRA124_CLK_OSC_DIV4 203 #define TEGRA124_CLK_PLL_REF 204 #define TEGRA124_CLK_PLL_C 205 #define TEGRA124_CLK_PLL_C_OUT1 206 @@ -273,7 +275,7 @@ #define TEGRA124_CLK_CLK_OUT_2 246 #define TEGRA124_CLK_CLK_OUT_3 247 #define TEGRA124_CLK_BLINK 248 -/* 249 */ +#define TEGRA124_CLK_OSC 249 /* 250 */ /* 251 */ #define TEGRA124_CLK_XUSB_HOST_SRC 252 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 44f60623f99b..7a8f10b9a66d 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -262,6 +262,8 @@ #define TEGRA210_CLK_CLK_M 233 #define TEGRA210_CLK_CLK_M_DIV2 234 #define TEGRA210_CLK_CLK_M_DIV4 235 +#define TEGRA210_CLK_OSC_DIV2 234 +#define TEGRA210_CLK_OSC_DIV4 235 #define TEGRA210_CLK_PLL_REF 236 #define TEGRA210_CLK_PLL_C 237 #define TEGRA210_CLK_PLL_C_OUT1 238 @@ -355,7 +357,7 @@ #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 /* 325 */ -/* 326 */ +#define TEGRA210_CLK_OSC 326 /* 327 */ /* 328 */ /* 329 */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 3c90f1535551..7b542c10fc27 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -196,6 +196,8 @@ #define TEGRA30_CLK_CLK_M 171 #define TEGRA30_CLK_CLK_M_DIV2 172 #define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_OSC_DIV2 172 +#define TEGRA30_CLK_OSC_DIV4 173 #define TEGRA30_CLK_PLL_REF 174 #define TEGRA30_CLK_PLL_C 175 #define TEGRA30_CLK_PLL_C_OUT1 176 @@ -243,7 +245,7 @@ #define TEGRA30_CLK_HCLK 217 #define TEGRA30_CLK_PCLK 218 /* 219 */ -/* 220 */ +#define TEGRA30_CLK_OSC 220 /* 221 */ /* 222 */ /* 223 */ diff --git a/include/dt-bindings/clk/ti-dra7-atl.h b/include/dt-bindings/clock/ti-dra7-atl.h index 42dd4164f6f4..42dd4164f6f4 100644 --- a/include/dt-bindings/clk/ti-dra7-atl.h +++ b/include/dt-bindings/clock/ti-dra7-atl.h diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h new file mode 100644 index 000000000000..264d634d226e --- /dev/null +++ b/include/dt-bindings/clock/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Xilinx Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_VERSAL_H +#define _DT_BINDINGS_CLK_VERSAL_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/include/dt-bindings/display/sdtv-standards.h b/include/dt-bindings/display/sdtv-standards.h new file mode 100644 index 000000000000..fbc1a3db2ea7 --- /dev/null +++ b/include/dt-bindings/display/sdtv-standards.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only or X11 */ +/* + * Copyright 2019 Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +#ifndef _DT_BINDINGS_DISPLAY_SDTV_STDS_H +#define _DT_BINDINGS_DISPLAY_SDTV_STDS_H + +/* + * Attention: Keep the SDTV_STD_* bit definitions in sync with + * include/uapi/linux/videodev2.h V4L2_STD_* bit definitions. + */ +/* One bit for each standard */ +#define SDTV_STD_PAL_B 0x00000001 +#define SDTV_STD_PAL_B1 0x00000002 +#define SDTV_STD_PAL_G 0x00000004 +#define SDTV_STD_PAL_H 0x00000008 +#define SDTV_STD_PAL_I 0x00000010 +#define SDTV_STD_PAL_D 0x00000020 +#define SDTV_STD_PAL_D1 0x00000040 +#define SDTV_STD_PAL_K 0x00000080 + +#define SDTV_STD_PAL (SDTV_STD_PAL_B | \ + SDTV_STD_PAL_B1 | \ + SDTV_STD_PAL_G | \ + SDTV_STD_PAL_H | \ + SDTV_STD_PAL_I | \ + SDTV_STD_PAL_D | \ + SDTV_STD_PAL_D1 | \ + SDTV_STD_PAL_K) + +#define SDTV_STD_PAL_M 0x00000100 +#define SDTV_STD_PAL_N 0x00000200 +#define SDTV_STD_PAL_Nc 0x00000400 +#define SDTV_STD_PAL_60 0x00000800 + +#define SDTV_STD_NTSC_M 0x00001000 /* BTSC */ +#define SDTV_STD_NTSC_M_JP 0x00002000 /* EIA-J */ +#define SDTV_STD_NTSC_443 0x00004000 +#define SDTV_STD_NTSC_M_KR 0x00008000 /* FM A2 */ + +#define SDTV_STD_NTSC (SDTV_STD_NTSC_M | \ + SDTV_STD_NTSC_M_JP | \ + SDTV_STD_NTSC_M_KR) + +#define SDTV_STD_SECAM_B 0x00010000 +#define SDTV_STD_SECAM_D 0x00020000 +#define SDTV_STD_SECAM_G 0x00040000 +#define SDTV_STD_SECAM_H 0x00080000 +#define SDTV_STD_SECAM_K 0x00100000 +#define SDTV_STD_SECAM_K1 0x00200000 +#define SDTV_STD_SECAM_L 0x00400000 +#define SDTV_STD_SECAM_LC 0x00800000 + +#define SDTV_STD_SECAM (SDTV_STD_SECAM_B | \ + SDTV_STD_SECAM_D | \ + SDTV_STD_SECAM_G | \ + SDTV_STD_SECAM_H | \ + SDTV_STD_SECAM_K | \ + SDTV_STD_SECAM_K1 | \ + SDTV_STD_SECAM_L | \ + SDTV_STD_SECAM_LC) + +/* Standards for Countries with 60Hz Line frequency */ +#define SDTV_STD_525_60 (SDTV_STD_PAL_M | \ + SDTV_STD_PAL_60 | \ + SDTV_STD_NTSC | \ + SDTV_STD_NTSC_443) + +/* Standards for Countries with 50Hz Line frequency */ +#define SDTV_STD_625_50 (SDTV_STD_PAL | \ + SDTV_STD_PAL_N | \ + SDTV_STD_PAL_Nc | \ + SDTV_STD_SECAM) + +#endif /* _DT_BINDINGS_DISPLAY_SDTV_STDS_H */ diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h new file mode 100644 index 000000000000..54858ff7674d --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sc7180.h b/include/dt-bindings/interconnect/qcom,sc7180.h new file mode 100644 index 000000000000..f9970f6032eb --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sc7180.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm SC7180 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7180_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QSPI 1 +#define MASTER_QUP_0 2 +#define MASTER_SDCC_2 3 +#define MASTER_EMMC 4 +#define MASTER_UFS_MEM 5 +#define SLAVE_A1NOC_SNOC 6 +#define SLAVE_SERVICE_A1NOC 7 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_USB3 3 +#define MASTER_CRYPTO 4 +#define MASTER_IPA 5 +#define MASTER_QDSS_ETR 6 +#define SLAVE_A2NOC_SNOC 7 +#define SLAVE_SERVICE_A2NOC 8 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_HF1_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define SLAVE_CAMNOC_UNCOMP 3 + +#define MASTER_NPU 0 +#define MASTER_NPU_PROC 1 +#define SLAVE_CDSP_GEM_NOC 2 + +#define MASTER_SNOC_CNOC 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AHB2PHY_SOUTH 4 +#define SLAVE_AHB2PHY_CENTER 5 +#define SLAVE_AOP 6 +#define SLAVE_AOSS 7 +#define SLAVE_BOOT_ROM 8 +#define SLAVE_CAMERA_CFG 9 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 10 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 11 +#define SLAVE_CLK_CTL 12 +#define SLAVE_RBCPR_CX_CFG 13 +#define SLAVE_RBCPR_MX_CFG 14 +#define SLAVE_CRYPTO_0_CFG 15 +#define SLAVE_DCC_CFG 16 +#define SLAVE_CNOC_DDRSS 17 +#define SLAVE_DISPLAY_CFG 18 +#define SLAVE_DISPLAY_RT_THROTTLE_CFG 19 +#define SLAVE_DISPLAY_THROTTLE_CFG 20 +#define SLAVE_EMMC_CFG 21 +#define SLAVE_GLM 22 +#define SLAVE_GFX3D_CFG 23 +#define SLAVE_IMEM_CFG 24 +#define SLAVE_IPA_CFG 25 +#define SLAVE_CNOC_MNOC_CFG 26 +#define SLAVE_CNOC_MSS 27 +#define SLAVE_NPU_CFG 28 +#define SLAVE_NPU_DMA_BWMON_CFG 29 +#define SLAVE_NPU_PROC_BWMON_CFG 30 +#define SLAVE_PDM 31 +#define SLAVE_PIMEM_CFG 32 +#define SLAVE_PRNG 33 +#define SLAVE_QDSS_CFG 34 +#define SLAVE_QM_CFG 35 +#define SLAVE_QM_MPU_CFG 36 +#define SLAVE_QSPI_0 37 +#define SLAVE_QUP_0 38 +#define SLAVE_QUP_1 39 +#define SLAVE_SDCC_2 40 +#define SLAVE_SECURITY 41 +#define SLAVE_SNOC_CFG 42 +#define SLAVE_TCSR 43 +#define SLAVE_TLMM_WEST 44 +#define SLAVE_TLMM_NORTH 45 +#define SLAVE_TLMM_SOUTH 46 +#define SLAVE_UFS_MEM_CFG 47 +#define SLAVE_USB3 48 +#define SLAVE_VENUS_CFG 49 +#define SLAVE_VENUS_THROTTLE_CFG 50 +#define SLAVE_VSENSE_CTRL_CFG 51 +#define SLAVE_SERVICE_CNOC 52 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_APPSS_PROC 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_SNOC_GC_MEM_NOC 6 +#define MASTER_SNOC_SF_MEM_NOC 7 +#define MASTER_GFX3D 8 +#define SLAVE_MSS_PROC_MS_MPU_CFG 9 +#define SLAVE_GEM_NOC_SNOC 10 +#define SLAVE_LLCC 11 +#define SLAVE_SERVICE_GEM_NOC 12 + +#define MASTER_IPA_CORE 0 +#define SLAVE_IPA_CORE 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP0 4 +#define MASTER_ROTATOR 5 +#define MASTER_VIDEO_P0 6 +#define MASTER_VIDEO_PROC 7 +#define SLAVE_MNOC_HF_MEM_NOC 8 +#define SLAVE_MNOC_SF_MEM_NOC 9 +#define SLAVE_SERVICE_MNOC 10 + +#define MASTER_NPU_SYS 0 +#define MASTER_NPU_NOC_CFG 1 +#define SLAVE_NPU_CAL_DP0 2 +#define SLAVE_NPU_CP 3 +#define SLAVE_NPU_INT_DMA_BWMON_CFG 4 +#define SLAVE_NPU_DPM 5 +#define SLAVE_ISENSE_CFG 6 +#define SLAVE_NPU_LLM_CFG 7 +#define SLAVE_NPU_TCM 8 +#define SLAVE_NPU_COMPUTE_NOC 9 +#define SLAVE_SERVICE_NPU_NOC 10 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define SLAVE_QUP_CORE_0 2 +#define SLAVE_QUP_CORE_1 3 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define SLAVE_APPSS 5 +#define SLAVE_SNOC_CNOC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_IMEM 9 +#define SLAVE_PIMEM 10 +#define SLAVE_SERVICE_SNOC 11 +#define SLAVE_QDSS_STM 12 +#define SLAVE_TCU 13 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h index 7b2393be7361..290be38f40e6 100644 --- a/include/dt-bindings/interconnect/qcom,sdm845.h +++ b/include/dt-bindings/interconnect/qcom,sdm845.h @@ -10,134 +10,139 @@ #define __DT_BINDINGS_INTERCONNECT_QCOM_SDM845_H #define MASTER_A1NOC_CFG 0 -#define MASTER_BLSP_1 1 -#define MASTER_TSIF 2 -#define MASTER_SDCC_2 3 -#define MASTER_SDCC_4 4 -#define MASTER_UFS_CARD 5 -#define MASTER_UFS_MEM 6 -#define MASTER_PCIE_0 7 -#define MASTER_A2NOC_CFG 8 -#define MASTER_QDSS_BAM 9 -#define MASTER_BLSP_2 10 -#define MASTER_CNOC_A2NOC 11 -#define MASTER_CRYPTO 12 -#define MASTER_IPA 13 -#define MASTER_PCIE_1 14 -#define MASTER_QDSS_ETR 15 -#define MASTER_USB3_0 16 -#define MASTER_USB3_1 17 -#define MASTER_CAMNOC_HF0_UNCOMP 18 -#define MASTER_CAMNOC_HF1_UNCOMP 19 -#define MASTER_CAMNOC_SF_UNCOMP 20 -#define MASTER_SPDM 21 -#define MASTER_TIC 22 -#define MASTER_SNOC_CNOC 23 -#define MASTER_QDSS_DAP 24 -#define MASTER_CNOC_DC_NOC 25 -#define MASTER_APPSS_PROC 26 -#define MASTER_GNOC_CFG 27 -#define MASTER_LLCC 28 -#define MASTER_TCU_0 29 -#define MASTER_MEM_NOC_CFG 30 -#define MASTER_GNOC_MEM_NOC 31 -#define MASTER_MNOC_HF_MEM_NOC 32 -#define MASTER_MNOC_SF_MEM_NOC 33 -#define MASTER_SNOC_GC_MEM_NOC 34 -#define MASTER_SNOC_SF_MEM_NOC 35 -#define MASTER_GFX3D 36 -#define MASTER_CNOC_MNOC_CFG 37 -#define MASTER_CAMNOC_HF0 38 -#define MASTER_CAMNOC_HF1 39 -#define MASTER_CAMNOC_SF 40 -#define MASTER_MDP0 41 -#define MASTER_MDP1 42 -#define MASTER_ROTATOR 43 -#define MASTER_VIDEO_P0 44 -#define MASTER_VIDEO_P1 45 -#define MASTER_VIDEO_PROC 46 -#define MASTER_SNOC_CFG 47 -#define MASTER_A1NOC_SNOC 48 -#define MASTER_A2NOC_SNOC 49 -#define MASTER_GNOC_SNOC 50 -#define MASTER_MEM_NOC_SNOC 51 -#define MASTER_ANOC_PCIE_SNOC 52 -#define MASTER_PIMEM 53 -#define MASTER_GIC 54 -#define SLAVE_A1NOC_SNOC 55 -#define SLAVE_SERVICE_A1NOC 56 -#define SLAVE_ANOC_PCIE_A1NOC_SNOC 57 -#define SLAVE_A2NOC_SNOC 58 -#define SLAVE_ANOC_PCIE_SNOC 59 -#define SLAVE_SERVICE_A2NOC 60 -#define SLAVE_CAMNOC_UNCOMP 61 -#define SLAVE_A1NOC_CFG 62 -#define SLAVE_A2NOC_CFG 63 -#define SLAVE_AOP 64 -#define SLAVE_AOSS 65 -#define SLAVE_CAMERA_CFG 66 -#define SLAVE_CLK_CTL 67 -#define SLAVE_CDSP_CFG 68 -#define SLAVE_RBCPR_CX_CFG 69 -#define SLAVE_CRYPTO_0_CFG 70 -#define SLAVE_DCC_CFG 71 -#define SLAVE_CNOC_DDRSS 72 -#define SLAVE_DISPLAY_CFG 73 -#define SLAVE_GLM 74 -#define SLAVE_GFX3D_CFG 75 -#define SLAVE_IMEM_CFG 76 -#define SLAVE_IPA_CFG 77 -#define SLAVE_CNOC_MNOC_CFG 78 -#define SLAVE_PCIE_0_CFG 79 -#define SLAVE_PCIE_1_CFG 80 -#define SLAVE_PDM 81 -#define SLAVE_SOUTH_PHY_CFG 82 -#define SLAVE_PIMEM_CFG 83 -#define SLAVE_PRNG 84 -#define SLAVE_QDSS_CFG 85 -#define SLAVE_BLSP_2 86 -#define SLAVE_BLSP_1 87 -#define SLAVE_SDCC_2 88 -#define SLAVE_SDCC_4 89 -#define SLAVE_SNOC_CFG 90 -#define SLAVE_SPDM_WRAPPER 91 -#define SLAVE_SPSS_CFG 92 -#define SLAVE_TCSR 93 -#define SLAVE_TLMM_NORTH 94 -#define SLAVE_TLMM_SOUTH 95 -#define SLAVE_TSIF 96 -#define SLAVE_UFS_CARD_CFG 97 -#define SLAVE_UFS_MEM_CFG 98 -#define SLAVE_USB3_0 99 -#define SLAVE_USB3_1 100 -#define SLAVE_VENUS_CFG 101 -#define SLAVE_VSENSE_CTRL_CFG 102 -#define SLAVE_CNOC_A2NOC 103 -#define SLAVE_SERVICE_CNOC 104 -#define SLAVE_LLCC_CFG 105 -#define SLAVE_MEM_NOC_CFG 106 -#define SLAVE_GNOC_SNOC 107 -#define SLAVE_GNOC_MEM_NOC 108 -#define SLAVE_SERVICE_GNOC 109 -#define SLAVE_EBI1 110 -#define SLAVE_MSS_PROC_MS_MPU_CFG 111 -#define SLAVE_MEM_NOC_GNOC 112 -#define SLAVE_LLCC 113 -#define SLAVE_MEM_NOC_SNOC 114 -#define SLAVE_SERVICE_MEM_NOC 115 -#define SLAVE_MNOC_SF_MEM_NOC 116 -#define SLAVE_MNOC_HF_MEM_NOC 117 -#define SLAVE_SERVICE_MNOC 118 -#define SLAVE_APPSS 119 -#define SLAVE_SNOC_CNOC 120 -#define SLAVE_SNOC_MEM_NOC_GC 121 -#define SLAVE_SNOC_MEM_NOC_SF 122 -#define SLAVE_IMEM 123 -#define SLAVE_PCIE_0 124 -#define SLAVE_PCIE_1 125 -#define SLAVE_PIMEM 126 -#define SLAVE_SERVICE_SNOC 127 -#define SLAVE_QDSS_STM 128 -#define SLAVE_TCU 129 +#define MASTER_TSIF 1 +#define MASTER_SDCC_2 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_CARD 4 +#define MASTER_UFS_MEM 5 +#define MASTER_PCIE_0 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 +#define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_CNOC_A2NOC 2 +#define MASTER_CRYPTO 3 +#define MASTER_IPA 4 +#define MASTER_PCIE_1 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_USB3_0 7 +#define MASTER_USB3_1 8 +#define SLAVE_A2NOC_SNOC 9 +#define SLAVE_ANOC_PCIE_SNOC 10 +#define SLAVE_SERVICE_A2NOC 11 + +#define MASTER_SPDM 0 +#define MASTER_TIC 1 +#define MASTER_SNOC_CNOC 2 +#define MASTER_QDSS_DAP 3 +#define SLAVE_A1NOC_CFG 4 +#define SLAVE_A2NOC_CFG 5 +#define SLAVE_AOP 6 +#define SLAVE_AOSS 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_CDSP_CFG 10 +#define SLAVE_RBCPR_CX_CFG 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_DCC_CFG 13 +#define SLAVE_CNOC_DDRSS 14 +#define SLAVE_DISPLAY_CFG 15 +#define SLAVE_GLM 16 +#define SLAVE_GFX3D_CFG 17 +#define SLAVE_IMEM_CFG 18 +#define SLAVE_IPA_CFG 19 +#define SLAVE_CNOC_MNOC_CFG 20 +#define SLAVE_PCIE_0_CFG 21 +#define SLAVE_PCIE_1_CFG 22 +#define SLAVE_PDM 23 +#define SLAVE_SOUTH_PHY_CFG 24 +#define SLAVE_PIMEM_CFG 25 +#define SLAVE_PRNG 26 +#define SLAVE_QDSS_CFG 27 +#define SLAVE_BLSP_2 28 +#define SLAVE_BLSP_1 29 +#define SLAVE_SDCC_2 30 +#define SLAVE_SDCC_4 31 +#define SLAVE_SNOC_CFG 32 +#define SLAVE_SPDM_WRAPPER 33 +#define SLAVE_SPSS_CFG 34 +#define SLAVE_TCSR 35 +#define SLAVE_TLMM_NORTH 36 +#define SLAVE_TLMM_SOUTH 37 +#define SLAVE_TSIF 38 +#define SLAVE_UFS_CARD_CFG 39 +#define SLAVE_UFS_MEM_CFG 40 +#define SLAVE_USB3_0 41 +#define SLAVE_USB3_1 42 +#define SLAVE_VENUS_CFG 43 +#define SLAVE_VSENSE_CTRL_CFG 44 +#define SLAVE_CNOC_A2NOC 45 +#define SLAVE_SERVICE_CNOC 46 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_MEM_NOC_CFG 2 + +#define MASTER_APPSS_PROC 0 +#define MASTER_GNOC_CFG 1 +#define SLAVE_GNOC_SNOC 2 +#define SLAVE_GNOC_MEM_NOC 3 +#define SLAVE_SERVICE_GNOC 4 + +#define MASTER_TCU_0 0 +#define MASTER_MEM_NOC_CFG 1 +#define MASTER_GNOC_MEM_NOC 2 +#define MASTER_MNOC_HF_MEM_NOC 3 +#define MASTER_MNOC_SF_MEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_GFX3D 7 +#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +#define SLAVE_MEM_NOC_GNOC 9 +#define SLAVE_LLCC 10 +#define SLAVE_MEM_NOC_SNOC 11 +#define SLAVE_SERVICE_MEM_NOC 12 +#define MASTER_LLCC 13 +#define SLAVE_EBI1 14 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP0 4 +#define MASTER_MDP1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 +#define MASTER_CAMNOC_HF0_UNCOMP 13 +#define MASTER_CAMNOC_HF1_UNCOMP 14 +#define MASTER_CAMNOC_SF_UNCOMP 15 +#define SLAVE_CAMNOC_UNCOMP 16 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GNOC_SNOC 3 +#define MASTER_MEM_NOC_SNOC 4 +#define MASTER_ANOC_PCIE_SNOC 5 +#define MASTER_PIMEM 6 +#define MASTER_GIC 7 +#define SLAVE_APPSS 8 +#define SLAVE_SNOC_CNOC 9 +#define SLAVE_SNOC_MEM_NOC_GC 10 +#define SLAVE_SNOC_MEM_NOC_SF 11 +#define SLAVE_IMEM 12 +#define SLAVE_PCIE_0 13 +#define SLAVE_PCIE_1 14 +#define SLAVE_PIMEM 15 +#define SLAVE_SERVICE_SNOC 16 +#define SLAVE_QDSS_STM 17 +#define SLAVE_TCU 18 #endif diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h index 9e1256a7c1bf..0ce7dfc00dcb 100644 --- a/include/dt-bindings/leds/common.h +++ b/include/dt-bindings/leds/common.h @@ -6,6 +6,7 @@ * Author: Jacek Anaszewski <j.anaszewski@samsung.com> * * Copyright (C) 2019 Jacek Anaszewski <jacek.anaszewski@gmail.com> + * Copyright (C) 2020 Pavel Machek <pavel@ucw.cz> */ #ifndef __DT_BINDINGS_LEDS_H @@ -32,16 +33,38 @@ #define LED_COLOR_ID_MAX 8 /* Standard LED functions */ +/* Keyboard LEDs, usually it would be input4::capslock etc. */ +/* Obsolete equivalent: "shift-key-light" */ +#define LED_FUNCTION_CAPSLOCK "capslock" +#define LED_FUNCTION_SCROLLLOCK "scrolllock" +#define LED_FUNCTION_NUMLOCK "numlock" +/* Obsolete equivalents: "tpacpi::thinklight" (IBM/Lenovo Thinkpads), + "lp5523:kb{1,2,3,4,5,6}" (Nokia N900) */ +#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" + +/* System LEDs, usually found on system body. + platform::mute (etc) is sometimes seen, :mute would be better */ +#define LED_FUNCTION_POWER "power" +#define LED_FUNCTION_DISK "disk" + +/* Obsolete: "platform:*:charging" (allwinner sun50i) */ +#define LED_FUNCTION_CHARGING "charging" +/* Used RGB notification LEDs common on phones. + Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4), + "lp5523:{r,g,b}" (Nokia N900) */ +#define LED_FUNCTION_STATUS "status" + +#define LED_FUNCTION_MICMUTE "micmute" +#define LED_FUNCTION_MUTE "mute" + +/* Miscelleaus functions. Use functions above if you can. */ #define LED_FUNCTION_ACTIVITY "activity" #define LED_FUNCTION_ALARM "alarm" #define LED_FUNCTION_BACKLIGHT "backlight" #define LED_FUNCTION_BLUETOOTH "bluetooth" #define LED_FUNCTION_BOOT "boot" #define LED_FUNCTION_CPU "cpu" -#define LED_FUNCTION_CAPSLOCK "capslock" -#define LED_FUNCTION_CHARGING "charging" #define LED_FUNCTION_DEBUG "debug" -#define LED_FUNCTION_DISK "disk" #define LED_FUNCTION_DISK_ACTIVITY "disk-activity" #define LED_FUNCTION_DISK_ERR "disk-err" #define LED_FUNCTION_DISK_READ "disk-read" @@ -50,21 +73,14 @@ #define LED_FUNCTION_FLASH "flash" #define LED_FUNCTION_HEARTBEAT "heartbeat" #define LED_FUNCTION_INDICATOR "indicator" -#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" #define LED_FUNCTION_LAN "lan" #define LED_FUNCTION_MAIL "mail" #define LED_FUNCTION_MTD "mtd" -#define LED_FUNCTION_MICMUTE "micmute" -#define LED_FUNCTION_MUTE "mute" -#define LED_FUNCTION_NUMLOCK "numlock" #define LED_FUNCTION_PANIC "panic" #define LED_FUNCTION_PROGRAMMING "programming" -#define LED_FUNCTION_POWER "power" #define LED_FUNCTION_RX "rx" #define LED_FUNCTION_SD "sd" -#define LED_FUNCTION_SCROLLLOCK "scrolllock" #define LED_FUNCTION_STANDBY "standby" -#define LED_FUNCTION_STATUS "status" #define LED_FUNCTION_TORCH "torch" #define LED_FUNCTION_TX "tx" #define LED_FUNCTION_USB "usb" diff --git a/include/dt-bindings/media/tvp5150.h b/include/dt-bindings/media/tvp5150.h index 01eedf4985b8..dda00c038530 100644 --- a/include/dt-bindings/media/tvp5150.h +++ b/include/dt-bindings/media/tvp5150.h @@ -14,8 +14,6 @@ #define TVP5150_COMPOSITE1 1 #define TVP5150_SVIDEO 2 -#define TVP5150_INPUT_NUM 3 - /* TVP5150 HW outputs */ #define TVP5150_NORMAL 0 #define TVP5150_BLACK_SCREEN 1 diff --git a/include/dt-bindings/memory/tegra186-mc.h b/include/dt-bindings/memory/tegra186-mc.h index 64813536aec9..82a1e27f7357 100644 --- a/include/dt-bindings/memory/tegra186-mc.h +++ b/include/dt-bindings/memory/tegra186-mc.h @@ -108,4 +108,143 @@ #define TEGRA186_SID_SE_VM6 0x4e #define TEGRA186_SID_SE_VM7 0x4f +/* + * memory client IDs + */ + +/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +#define TEGRA186_MEMORY_CLIENT_PTCR 0x00 +/* PCIE reads */ +#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e +/* High-definition audio (HDA) reads */ +#define TEGRA186_MEMORY_CLIENT_HDAR 0x15 +/* Host channel data reads */ +#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16 +#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c +/* SATA reads */ +#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f +/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27 +#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b +/* PCIE writes */ +#define TEGRA186_MEMORY_CLIENT_AFIW 0x31 +/* High-definition audio (HDA) writes */ +#define TEGRA186_MEMORY_CLIENT_HDAW 0x35 +/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39 +/* SATA writes */ +#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d +/* ISP Read client for Crossbar A */ +#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44 +/* ISP Write client for Crossbar A */ +#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46 +/* ISP Write client Crossbar B */ +#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47 +/* XUSB reads */ +#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a +/* XUSB_HOST writes */ +#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b +/* XUSB reads */ +#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c +/* XUSB_DEV writes */ +#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d +/* TSEC Memory Return Data Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54 +/* TSEC Memory Write Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55 +/* 3D, ltcx reads instance 0 */ +#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58 +/* 3D, ltcx writes instance 0 */ +#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59 +/* sdmmca memory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60 +/* sdmmcbmemory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61 +/* sdmmc memory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62 +/* sdmmcd memory read client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmca memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64 +/* sdmmcb memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65 +/* sdmmc memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66 +/* sdmmcd memory write client */ +#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d +/* VI Write client */ +#define TEGRA186_MEMORY_CLIENT_VIW 0x72 +#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79 +/* Audio Processing (APE) engine reads */ +#define TEGRA186_MEMORY_CLIENT_APER 0x7a +/* Audio Processing (APE) engine writes */ +#define TEGRA186_MEMORY_CLIENT_APEW 0x7b +#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e +#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f +/* SE Memory Return Data Client Description */ +#define TEGRA186_MEMORY_CLIENT_SESRD 0x80 +/* SE Memory Write Client Description */ +#define TEGRA186_MEMORY_CLIENT_SESWR 0x81 +/* ETR reads */ +#define TEGRA186_MEMORY_CLIENT_ETRR 0x84 +/* ETR writes */ +#define TEGRA186_MEMORY_CLIENT_ETRW 0x85 +/* TSECB Memory Return Data Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86 +/* TSECB Memory Write Client Description */ +#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87 +/* 3D, ltcx reads instance 1 */ +#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88 +/* 3D, ltcx writes instance 1 */ +#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89 +/* AXI Switch read client */ +#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c +/* AXI Switch write client */ +#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d +/* EQOS read client */ +#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e +/* EQOS write client */ +#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f +/* UFSHC read client */ +#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90 +/* UFSHC write client */ +#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91 +/* NVDISPLAY read client */ +#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92 +/* BPMP read client */ +#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96 +/* AON read client */ +#define TEGRA186_MEMORY_CLIENT_AONR 0x97 +/* AON write client */ +#define TEGRA186_MEMORY_CLIENT_AONW 0x98 +/* AONDMA read client */ +#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99 +/* AONDMA write client */ +#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a +/* SCE read client */ +#define TEGRA186_MEMORY_CLIENT_SCER 0x9b +/* SCE write client */ +#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c +/* SCEDMA read client */ +#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d +/* SCEDMA write client */ +#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e +/* APEDMA read client */ +#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f +/* APEDMA write client */ +#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0 +/* NVDISPLAY read client instance 2 */ +#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2 +#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3 + #endif diff --git a/include/dt-bindings/memory/tegra194-mc.h b/include/dt-bindings/memory/tegra194-mc.h new file mode 100644 index 000000000000..eed48b746bc9 --- /dev/null +++ b/include/dt-bindings/memory/tegra194-mc.h @@ -0,0 +1,410 @@ +#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H +#define DT_BINDINGS_MEMORY_TEGRA194_MC_H + +/* special clients */ +#define TEGRA194_SID_INVALID 0x00 +#define TEGRA194_SID_PASSTHROUGH 0x7f + +/* host1x clients */ +#define TEGRA194_SID_HOST1X 0x01 +#define TEGRA194_SID_CSI 0x02 +#define TEGRA194_SID_VIC 0x03 +#define TEGRA194_SID_VI 0x04 +#define TEGRA194_SID_ISP 0x05 +#define TEGRA194_SID_NVDEC 0x06 +#define TEGRA194_SID_NVENC 0x07 +#define TEGRA194_SID_NVJPG 0x08 +#define TEGRA194_SID_NVDISPLAY 0x09 +#define TEGRA194_SID_TSEC 0x0a +#define TEGRA194_SID_TSECB 0x0b +#define TEGRA194_SID_SE 0x0c +#define TEGRA194_SID_SE1 0x0d +#define TEGRA194_SID_SE2 0x0e +#define TEGRA194_SID_SE3 0x0f + +/* GPU clients */ +#define TEGRA194_SID_GPU 0x10 + +/* other SoC clients */ +#define TEGRA194_SID_AFI 0x11 +#define TEGRA194_SID_HDA 0x12 +#define TEGRA194_SID_ETR 0x13 +#define TEGRA194_SID_EQOS 0x14 +#define TEGRA194_SID_UFSHC 0x15 +#define TEGRA194_SID_AON 0x16 +#define TEGRA194_SID_SDMMC4 0x17 +#define TEGRA194_SID_SDMMC3 0x18 +#define TEGRA194_SID_SDMMC2 0x19 +#define TEGRA194_SID_SDMMC1 0x1a +#define TEGRA194_SID_XUSB_HOST 0x1b +#define TEGRA194_SID_XUSB_DEV 0x1c +#define TEGRA194_SID_SATA 0x1d +#define TEGRA194_SID_APE 0x1e +#define TEGRA194_SID_SCE 0x1f + +/* GPC DMA clients */ +#define TEGRA194_SID_GPCDMA_0 0x20 +#define TEGRA194_SID_GPCDMA_1 0x21 +#define TEGRA194_SID_GPCDMA_2 0x22 +#define TEGRA194_SID_GPCDMA_3 0x23 +#define TEGRA194_SID_GPCDMA_4 0x24 +#define TEGRA194_SID_GPCDMA_5 0x25 +#define TEGRA194_SID_GPCDMA_6 0x26 +#define TEGRA194_SID_GPCDMA_7 0x27 + +/* APE DMA clients */ +#define TEGRA194_SID_APE_1 0x28 +#define TEGRA194_SID_APE_2 0x29 + +/* camera RTCPU */ +#define TEGRA194_SID_RCE 0x2a + +/* camera RTCPU on host1x address space */ +#define TEGRA194_SID_RCE_1X 0x2b + +/* APE DMA clients */ +#define TEGRA194_SID_APE_3 0x2c + +/* camera RTCPU running on APE */ +#define TEGRA194_SID_APE_CAM 0x2d +#define TEGRA194_SID_APE_CAM_1X 0x2e + +#define TEGRA194_SID_RCE_RM 0x2f +#define TEGRA194_SID_VI_FALCON 0x30 +#define TEGRA194_SID_ISP_FALCON 0x31 + +/* + * The BPMP has its SID value hardcoded in the firmware. Changing it requires + * considerable effort. + */ +#define TEGRA194_SID_BPMP 0x32 + +/* for SMMU tests */ +#define TEGRA194_SID_SMMU_TEST 0x33 + +/* host1x virtualization channels */ +#define TEGRA194_SID_HOST1X_CTX0 0x38 +#define TEGRA194_SID_HOST1X_CTX1 0x39 +#define TEGRA194_SID_HOST1X_CTX2 0x3a +#define TEGRA194_SID_HOST1X_CTX3 0x3b +#define TEGRA194_SID_HOST1X_CTX4 0x3c +#define TEGRA194_SID_HOST1X_CTX5 0x3d +#define TEGRA194_SID_HOST1X_CTX6 0x3e +#define TEGRA194_SID_HOST1X_CTX7 0x3f + +/* host1x command buffers */ +#define TEGRA194_SID_HOST1X_VM0 0x40 +#define TEGRA194_SID_HOST1X_VM1 0x41 +#define TEGRA194_SID_HOST1X_VM2 0x42 +#define TEGRA194_SID_HOST1X_VM3 0x43 +#define TEGRA194_SID_HOST1X_VM4 0x44 +#define TEGRA194_SID_HOST1X_VM5 0x45 +#define TEGRA194_SID_HOST1X_VM6 0x46 +#define TEGRA194_SID_HOST1X_VM7 0x47 + +/* SE data buffers */ +#define TEGRA194_SID_SE_VM0 0x48 +#define TEGRA194_SID_SE_VM1 0x49 +#define TEGRA194_SID_SE_VM2 0x4a +#define TEGRA194_SID_SE_VM3 0x4b +#define TEGRA194_SID_SE_VM4 0x4c +#define TEGRA194_SID_SE_VM5 0x4d +#define TEGRA194_SID_SE_VM6 0x4e +#define TEGRA194_SID_SE_VM7 0x4f + +#define TEGRA194_SID_MIU 0x50 + +#define TEGRA194_SID_NVDLA0 0x51 +#define TEGRA194_SID_NVDLA1 0x52 + +#define TEGRA194_SID_PVA0 0x53 +#define TEGRA194_SID_PVA1 0x54 +#define TEGRA194_SID_NVENC1 0x55 +#define TEGRA194_SID_PCIE0 0x56 +#define TEGRA194_SID_PCIE1 0x57 +#define TEGRA194_SID_PCIE2 0x58 +#define TEGRA194_SID_PCIE3 0x59 +#define TEGRA194_SID_PCIE4 0x5a +#define TEGRA194_SID_PCIE5 0x5b +#define TEGRA194_SID_NVDEC1 0x5c + +#define TEGRA194_SID_XUSB_VF0 0x5d +#define TEGRA194_SID_XUSB_VF1 0x5e +#define TEGRA194_SID_XUSB_VF2 0x5f +#define TEGRA194_SID_XUSB_VF3 0x60 + +#define TEGRA194_SID_RCE_VM3 0x61 +#define TEGRA194_SID_VI_VM2 0x62 +#define TEGRA194_SID_VI_VM3 0x63 +#define TEGRA194_SID_RCE_SERVER 0x64 + +/* + * memory client IDs + */ + +/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ +#define TEGRA194_MEMORY_CLIENT_PTCR 0x00 +/* MSS internal memqual MIU7 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01 +/* MSS internal memqual MIU7 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02 +/* High-definition audio (HDA) read clients */ +#define TEGRA194_MEMORY_CLIENT_HDAR 0x15 +/* Host channel data read clients */ +#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16 +#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c +/* SATA read clients */ +#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f +/* Reads from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27 +#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b +/* High-definition audio (HDA) write clients */ +#define TEGRA194_MEMORY_CLIENT_HDAW 0x35 +/* Writes from Cortex-A9 4 CPU cores via the L2 cache */ +#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39 +/* SATA write clients */ +#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d +/* ISP read client for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44 +/* ISP read client 1 for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45 +/* ISP Write client for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46 +/* ISP Write client Crossbar B */ +#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47 +/* XUSB_HOST read clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a +/* XUSB_HOST write clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b +/* XUSB read clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c +/* XUSB_DEV write clients */ +#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d +/* sdmmca memory read client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60 +/* sdmmc memory read client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62 +/* sdmmcd memory read client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmca memory write client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64 +/* sdmmc memory write client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66 +/* sdmmcd memory write client */ +#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d +/* VI Write client */ +#define TEGRA194_MEMORY_CLIENT_VIW 0x72 +#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79 +/* Audio Processing (APE) engine read clients */ +#define TEGRA194_MEMORY_CLIENT_APER 0x7a +/* Audio Processing (APE) engine write clients */ +#define TEGRA194_MEMORY_CLIENT_APEW 0x7b +#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e +#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f +/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ +#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82 +/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ +#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83 +/* ETR read clients */ +#define TEGRA194_MEMORY_CLIENT_ETRR 0x84 +/* ETR write clients */ +#define TEGRA194_MEMORY_CLIENT_ETRW 0x85 +/* AXI Switch read client */ +#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c +/* AXI Switch write client */ +#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d +/* EQOS read client */ +#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e +/* EQOS write client */ +#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f +/* UFSHC read client */ +#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90 +/* UFSHC write client */ +#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91 +/* NVDISPLAY read client */ +#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92 +/* BPMP read client */ +#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96 +/* AON read client */ +#define TEGRA194_MEMORY_CLIENT_AONR 0x97 +/* AON write client */ +#define TEGRA194_MEMORY_CLIENT_AONW 0x98 +/* AONDMA read client */ +#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99 +/* AONDMA write client */ +#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a +/* SCE read client */ +#define TEGRA194_MEMORY_CLIENT_SCER 0x9b +/* SCE write client */ +#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c +/* SCEDMA read client */ +#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d +/* SCEDMA write client */ +#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e +/* APEDMA read client */ +#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f +/* APEDMA write client */ +#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0 +/* NVDISPLAY read client instance 2 */ +#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1 +#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2 +#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3 +/* MSS internal memqual MIU0 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6 +/* MSS internal memqual MIU0 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7 +/* MSS internal memqual MIU1 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8 +/* MSS internal memqual MIU1 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9 +/* MSS internal memqual MIU2 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae +/* MSS internal memqual MIU2 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf +/* MSS internal memqual MIU3 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0 +/* MSS internal memqual MIU3 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1 +/* MSS internal memqual MIU4 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2 +/* MSS internal memqual MIU4 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3 +#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4 +#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5 +#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6 +#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7 +#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8 +#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9 +#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba +#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb +/* VI FLACON read clients */ +#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc +/* VIFAL write clients */ +#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd +/* DLA0ARDA read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe +/* DLA0 Falcon read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf +/* DLA0 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0 +/* DLA0 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1 +/* DLA1ARDA read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2 +/* DLA1 Falcon read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3 +/* DLA1 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4 +/* DLA1 write clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5 +/* PVA0RDA read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6 +/* PVA0RDB read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7 +/* PVA0RDC read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8 +/* PVA0WRA write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9 +/* PVA0WRB write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca +/* PVA0WRC write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb +/* PVA1RDA read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc +/* PVA1RDB read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd +/* PVA1RDC read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce +/* PVA1WRA write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf +/* PVA1WRB write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0 +/* PVA1WRC write clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1 +/* RCE read client */ +#define TEGRA194_MEMORY_CLIENT_RCER 0xd2 +/* RCE write client */ +#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3 +/* RCEDMA read client */ +#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4 +/* RCEDMA write client */ +#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5 +#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6 +#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7 +/* PCIE0 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8 +/* PCIE0 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9 +/* PCIE1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda +/* PCIE1 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb +/* PCIE2 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc +/* PCIE2 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd +/* PCIE3 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde +/* PCIE3 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf +/* PCIE4 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0 +/* PCIE4 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1 +/* PCIE5 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2 +/* PCIE5 write clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3 +/* ISP read client 1 for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4 +#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5 +#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6 +#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7 +#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8 +/* DLA0ARDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9 +/* DLA1ARDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea +/* PVA0RDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb +/* PVA0RDB1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec +/* PVA1RDA1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed +/* PVA1RDB1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee +/* PCIE5r1 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef +#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0 +#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1 +/* ISP read client for Crossbar A */ +#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2 +/* PCIE0 read clients */ +#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3 +#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4 +#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5 +#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6 +#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7 +#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8 +#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9 +#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa +#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb +/* MSS internal memqual MIU5 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc +/* MSS internal memqual MIU5 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd +/* MSS internal memqual MIU6 read clients */ +#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe +/* MSS internal memqual MIU6 write clients */ +#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff + +#endif diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h new file mode 100644 index 000000000000..6cf50bfb8ccf --- /dev/null +++ b/include/dt-bindings/power/meson-a1-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. + * Author: Jianxin Pan <jianxin.pan@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_A1_POWER_H +#define _DT_BINDINGS_MESON_A1_POWER_H + +#define PWRC_DSPA_ID 8 +#define PWRC_DSPB_ID 9 +#define PWRC_UART_ID 10 +#define PWRC_DMC_ID 11 +#define PWRC_I2C_ID 12 +#define PWRC_PSRAM_ID 13 +#define PWRC_ACODEC_ID 14 +#define PWRC_AUDIO_ID 15 +#define PWRC_OTP_ID 16 +#define PWRC_DMA_ID 17 +#define PWRC_SD_EMMC_ID 18 +#define PWRC_RAMA_ID 19 +#define PWRC_RAMB_ID 20 +#define PWRC_IR_ID 21 +#define PWRC_SPICC_ID 22 +#define PWRC_SPIFC_ID 23 +#define PWRC_USB_ID 24 +#define PWRC_NIC_ID 25 +#define PWRC_PDMIN_ID 26 +#define PWRC_RSA_ID 27 +#define PWRC_MAX_ID 28 + +#endif diff --git a/include/dt-bindings/power/mt6765-power.h b/include/dt-bindings/power/mt6765-power.h new file mode 100644 index 000000000000..d347b4ee9eed --- /dev/null +++ b/include/dt-bindings/power/mt6765-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT6765_POWER_H +#define _DT_BINDINGS_POWER_MT6765_POWER_H + +#define MT6765_POWER_DOMAIN_CONN 0 +#define MT6765_POWER_DOMAIN_MM 1 +#define MT6765_POWER_DOMAIN_MFG_ASYNC 2 +#define MT6765_POWER_DOMAIN_ISP 3 +#define MT6765_POWER_DOMAIN_MFG 4 +#define MT6765_POWER_DOMAIN_MFG_CORE0 5 +#define MT6765_POWER_DOMAIN_CAM 6 +#define MT6765_POWER_DOMAIN_VCODEC 7 + +#endif /* _DT_BINDINGS_POWER_MT6765_POWER_H */ diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index f05f8b1808ec..3f74096d5a7c 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -15,12 +15,36 @@ #define SDM845_GFX 7 #define SDM845_MSS 8 +/* SM8150 Power Domain Indexes */ +#define SM8150_MSS 0 +#define SM8150_EBI 1 +#define SM8150_LMX 2 +#define SM8150_LCX 3 +#define SM8150_GFX 4 +#define SM8150_MX 5 +#define SM8150_MX_AO 6 +#define SM8150_CX 7 +#define SM8150_CX_AO 8 +#define SM8150_MMCX 9 +#define SM8150_MMCX_AO 10 + +/* SC7180 Power Domain Indexes */ +#define SC7180_CX 0 +#define SC7180_CX_AO 1 +#define SC7180_GFX 2 +#define SC7180_MX 3 +#define SC7180_MX_AO 4 +#define SC7180_LMX 5 +#define SC7180_LCX 6 +#define SC7180_MSS 7 + /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L1 192 +#define RPMH_REGULATOR_LEVEL_SVS_L2 224 #define RPMH_REGULATOR_LEVEL_NOM 256 #define RPMH_REGULATOR_LEVEL_NOM_L1 320 #define RPMH_REGULATOR_LEVEL_NOM_L2 336 diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h new file mode 100644 index 000000000000..9e7ee762f076 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt2712-resets.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Yong Liang <yong.liang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 + +#define MT2712_TOPRGU_INFRA_SW_RST 0 +#define MT2712_TOPRGU_MM_SW_RST 1 +#define MT2712_TOPRGU_MFG_SW_RST 2 +#define MT2712_TOPRGU_VENC_SW_RST 3 +#define MT2712_TOPRGU_VDEC_SW_RST 4 +#define MT2712_TOPRGU_IMG_SW_RST 5 +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 +#define MT2712_TOPRGU_USB_SW_RST 9 +#define MT2712_TOPRGU_APMIXED_SW_RST 10 + +#define MT2712_TOPRGU_SW_RST_NUM 11 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h index 8804e34ebdd4..a1bbd41e0d12 100644 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ b/include/dt-bindings/reset-controller/mt8183-resets.h @@ -78,4 +78,21 @@ #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 +#define MT8183_INFRACFG_SW_RST_NUM 128 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 + +#define MT8183_TOPRGU_SW_RST_NUM 19 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ diff --git a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h new file mode 100644 index 000000000000..df088e68a9ba --- /dev/null +++ b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2019 Nuvoton Technology corporation. + +#ifndef _DT_BINDINGS_NPCM7XX_RESET_H +#define _DT_BINDINGS_NPCM7XX_RESET_H + +#define NPCM7XX_RESET_IPSRST1 0x20 +#define NPCM7XX_RESET_IPSRST2 0x24 +#define NPCM7XX_RESET_IPSRST3 0x34 + +/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */ +#define NPCM7XX_RESET_FIU3 1 +#define NPCM7XX_RESET_UDC1 5 +#define NPCM7XX_RESET_EMC1 6 +#define NPCM7XX_RESET_UART_2_3 7 +#define NPCM7XX_RESET_UDC2 8 +#define NPCM7XX_RESET_PECI 9 +#define NPCM7XX_RESET_AES 10 +#define NPCM7XX_RESET_UART_0_1 11 +#define NPCM7XX_RESET_MC 12 +#define NPCM7XX_RESET_SMB2 13 +#define NPCM7XX_RESET_SMB3 14 +#define NPCM7XX_RESET_SMB4 15 +#define NPCM7XX_RESET_SMB5 16 +#define NPCM7XX_RESET_PWM_M0 18 +#define NPCM7XX_RESET_TIMER_0_4 19 +#define NPCM7XX_RESET_TIMER_5_9 20 +#define NPCM7XX_RESET_EMC2 21 +#define NPCM7XX_RESET_UDC4 22 +#define NPCM7XX_RESET_UDC5 23 +#define NPCM7XX_RESET_UDC6 24 +#define NPCM7XX_RESET_UDC3 25 +#define NPCM7XX_RESET_ADC 27 +#define NPCM7XX_RESET_SMB6 28 +#define NPCM7XX_RESET_SMB7 29 +#define NPCM7XX_RESET_SMB0 30 +#define NPCM7XX_RESET_SMB1 31 + +/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */ +#define NPCM7XX_RESET_MFT0 0 +#define NPCM7XX_RESET_MFT1 1 +#define NPCM7XX_RESET_MFT2 2 +#define NPCM7XX_RESET_MFT3 3 +#define NPCM7XX_RESET_MFT4 4 +#define NPCM7XX_RESET_MFT5 5 +#define NPCM7XX_RESET_MFT6 6 +#define NPCM7XX_RESET_MFT7 7 +#define NPCM7XX_RESET_MMC 8 +#define NPCM7XX_RESET_SDHC 9 +#define NPCM7XX_RESET_GFX_SYS 10 +#define NPCM7XX_RESET_AHB_PCIBRG 11 +#define NPCM7XX_RESET_VDMA 12 +#define NPCM7XX_RESET_ECE 13 +#define NPCM7XX_RESET_VCD 14 +#define NPCM7XX_RESET_OTP 16 +#define NPCM7XX_RESET_SIOX1 18 +#define NPCM7XX_RESET_SIOX2 19 +#define NPCM7XX_RESET_3DES 21 +#define NPCM7XX_RESET_PSPI1 22 +#define NPCM7XX_RESET_PSPI2 23 +#define NPCM7XX_RESET_GMAC2 25 +#define NPCM7XX_RESET_USB_HOST 26 +#define NPCM7XX_RESET_GMAC1 28 +#define NPCM7XX_RESET_CP 31 + +/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */ +#define NPCM7XX_RESET_PWM_M1 0 +#define NPCM7XX_RESET_SMB12 1 +#define NPCM7XX_RESET_SPIX 2 +#define NPCM7XX_RESET_SMB13 3 +#define NPCM7XX_RESET_UDC0 4 +#define NPCM7XX_RESET_UDC7 5 +#define NPCM7XX_RESET_UDC8 6 +#define NPCM7XX_RESET_UDC9 7 +#define NPCM7XX_RESET_PCI_MAILBOX 9 +#define NPCM7XX_RESET_SMB14 12 +#define NPCM7XX_RESET_SHA 13 +#define NPCM7XX_RESET_SEC_ECC 14 +#define NPCM7XX_RESET_PCIE_RC 15 +#define NPCM7XX_RESET_TIMER_10_14 16 +#define NPCM7XX_RESET_RNG 17 +#define NPCM7XX_RESET_SMB15 18 +#define NPCM7XX_RESET_SMB8 19 +#define NPCM7XX_RESET_SMB9 20 +#define NPCM7XX_RESET_SMB10 21 +#define NPCM7XX_RESET_SMB11 22 +#define NPCM7XX_RESET_ESPI 23 +#define NPCM7XX_RESET_USB_PHY_1 24 +#define NPCM7XX_RESET_USB_PHY_2 25 + +#endif diff --git a/include/dt-bindings/reset/qcom,gcc-ipq6018.h b/include/dt-bindings/reset/qcom,gcc-ipq6018.h new file mode 100644 index 000000000000..02a220ad0105 --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-ipq6018.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H +#define _DT_BINDINGS_RESET_IPQ_GCC_6018_H + +#define GCC_BLSP1_BCR 0 +#define GCC_BLSP1_QUP1_BCR 1 +#define GCC_BLSP1_UART1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_UART2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_UART3_BCR 6 +#define GCC_BLSP1_QUP4_BCR 7 +#define GCC_BLSP1_UART4_BCR 8 +#define GCC_BLSP1_QUP5_BCR 9 +#define GCC_BLSP1_UART5_BCR 10 +#define GCC_BLSP1_QUP6_BCR 11 +#define GCC_BLSP1_UART6_BCR 12 +#define GCC_IMEM_BCR 13 +#define GCC_SMMU_BCR 14 +#define GCC_APSS_TCU_BCR 15 +#define GCC_SMMU_XPU_BCR 16 +#define GCC_PCNOC_TBU_BCR 17 +#define GCC_SMMU_CFG_BCR 18 +#define GCC_PRNG_BCR 19 +#define GCC_BOOT_ROM_BCR 20 +#define GCC_CRYPTO_BCR 21 +#define GCC_WCSS_BCR 22 +#define GCC_WCSS_Q6_BCR 23 +#define GCC_NSS_BCR 24 +#define GCC_SEC_CTRL_BCR 25 +#define GCC_DDRSS_BCR 26 +#define GCC_SYSTEM_NOC_BCR 27 +#define GCC_PCNOC_BCR 28 +#define GCC_TCSR_BCR 29 +#define GCC_QDSS_BCR 30 +#define GCC_DCD_BCR 31 +#define GCC_MSG_RAM_BCR 32 +#define GCC_MPM_BCR 33 +#define GCC_SPDM_BCR 34 +#define GCC_RBCPR_BCR 35 +#define GCC_RBCPR_MX_BCR 36 +#define GCC_TLMM_BCR 37 +#define GCC_RBCPR_WCSS_BCR 38 +#define GCC_USB0_PHY_BCR 39 +#define GCC_USB3PHY_0_PHY_BCR 40 +#define GCC_USB0_BCR 41 +#define GCC_USB1_BCR 42 +#define GCC_QUSB2_0_PHY_BCR 43 +#define GCC_QUSB2_1_PHY_BCR 44 +#define GCC_SDCC1_BCR 45 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 46 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 47 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 48 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 49 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 50 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 51 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 52 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 53 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 54 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 55 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 56 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 58 +#define GCC_UNIPHY0_BCR 59 +#define GCC_UNIPHY1_BCR 60 +#define GCC_CMN_12GPLL_BCR 61 +#define GCC_QPIC_BCR 62 +#define GCC_MDIO_BCR 63 +#define GCC_WCSS_CORE_TBU_BCR 64 +#define GCC_WCSS_Q6_TBU_BCR 65 +#define GCC_USB0_TBU_BCR 66 +#define GCC_PCIE0_TBU_BCR 67 +#define GCC_PCIE0_BCR 68 +#define GCC_PCIE0_PHY_BCR 69 +#define GCC_PCIE0PHY_PHY_BCR 70 +#define GCC_PCIE0_LINK_DOWN_BCR 71 +#define GCC_DCC_BCR 72 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73 +#define GCC_SMMU_CATS_BCR 74 +#define GCC_UBI0_AXI_ARES 75 +#define GCC_UBI0_AHB_ARES 76 +#define GCC_UBI0_NC_AXI_ARES 77 +#define GCC_UBI0_DBG_ARES 78 +#define GCC_UBI0_CORE_CLAMP_ENABLE 79 +#define GCC_UBI0_CLKRST_CLAMP_ENABLE 80 +#define GCC_UBI0_UTCM_ARES 81 +#define GCC_NSS_CFG_ARES 82 +#define GCC_NSS_NOC_ARES 83 +#define GCC_NSS_CRYPTO_ARES 84 +#define GCC_NSS_CSR_ARES 85 +#define GCC_NSS_CE_APB_ARES 86 +#define GCC_NSS_CE_AXI_ARES 87 +#define GCC_NSSNOC_CE_APB_ARES 88 +#define GCC_NSSNOC_CE_AXI_ARES 89 +#define GCC_NSSNOC_UBI0_AHB_ARES 90 +#define GCC_NSSNOC_SNOC_ARES 91 +#define GCC_NSSNOC_CRYPTO_ARES 92 +#define GCC_NSSNOC_ATB_ARES 93 +#define GCC_NSSNOC_QOSGEN_REF_ARES 94 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 95 +#define GCC_PCIE0_PIPE_ARES 96 +#define GCC_PCIE0_SLEEP_ARES 97 +#define GCC_PCIE0_CORE_STICKY_ARES 98 +#define GCC_PCIE0_AXI_MASTER_ARES 99 +#define GCC_PCIE0_AXI_SLAVE_ARES 100 +#define GCC_PCIE0_AHB_ARES 101 +#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102 +#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103 +#define GCC_PPE_FULL_RESET 104 +#define GCC_UNIPHY0_SOFT_RESET 105 +#define GCC_UNIPHY0_XPCS_RESET 106 +#define GCC_UNIPHY1_SOFT_RESET 107 +#define GCC_UNIPHY1_XPCS_RESET 108 +#define GCC_EDMA_HW_RESET 109 +#define GCC_ADSS_BCR 110 +#define GCC_NSS_NOC_TBU_BCR 111 +#define GCC_NSSPORT1_RESET 112 +#define GCC_NSSPORT2_RESET 113 +#define GCC_NSSPORT3_RESET 114 +#define GCC_NSSPORT4_RESET 115 +#define GCC_NSSPORT5_RESET 116 +#define GCC_UNIPHY0_PORT1_ARES 117 +#define GCC_UNIPHY0_PORT2_ARES 118 +#define GCC_UNIPHY0_PORT3_ARES 119 +#define GCC_UNIPHY0_PORT4_ARES 120 +#define GCC_UNIPHY0_PORT5_ARES 121 +#define GCC_UNIPHY0_PORT_4_5_RESET 122 +#define GCC_UNIPHY0_PORT_4_RESET 123 +#define GCC_LPASS_BCR 124 +#define GCC_UBI32_TBU_BCR 125 +#define GCC_LPASS_TBU_BCR 126 +#define GCC_WCSSAON_RESET 127 +#define GCC_LPASS_Q6_AXIM_ARES 128 +#define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129 +#define GCC_LPASS_Q6SS_TRIG_ARES 130 +#define GCC_LPASS_Q6_ATBM_AT_ARES 131 +#define GCC_LPASS_Q6_PCLKDBG_ARES 132 +#define GCC_LPASS_CORE_AXIM_ARES 133 +#define GCC_LPASS_SNOC_CFG_ARES 134 +#define GCC_WCSS_DBG_ARES 135 +#define GCC_WCSS_ECAHB_ARES 136 +#define GCC_WCSS_ACMT_ARES 137 +#define GCC_WCSS_DBG_BDG_ARES 138 +#define GCC_WCSS_AHB_S_ARES 139 +#define GCC_WCSS_AXI_M_ARES 140 +#define GCC_Q6SS_DBG_ARES 141 +#define GCC_Q6_AHB_S_ARES 142 +#define GCC_Q6_AHB_ARES 143 +#define GCC_Q6_AXIM2_ARES 144 +#define GCC_Q6_AXIM_ARES 145 +#define GCC_UBI0_CORE_ARES 146 + +#endif diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h new file mode 100644 index 000000000000..a99a457471ee --- /dev/null +++ b/include/dt-bindings/soc/tegra-pmc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H +#define _DT_BINDINGS_SOC_TEGRA_PMC_H + +#define TEGRA_PMC_CLK_OUT_1 0 +#define TEGRA_PMC_CLK_OUT_2 1 +#define TEGRA_PMC_CLK_OUT_3 2 +#define TEGRA_PMC_CLK_BLINK 3 + +#define TEGRA_PMC_CLK_MAX 4 + +#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ diff --git a/include/dt-bindings/sound/meson-aiu.h b/include/dt-bindings/sound/meson-aiu.h new file mode 100644 index 000000000000..1051b8af298b --- /dev/null +++ b/include/dt-bindings/sound/meson-aiu.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_AIU_H +#define __DT_MESON_AIU_H + +#define AIU_CPU 0 +#define AIU_HDMI 1 +#define AIU_ACODEC 2 + +#define CPU_I2S_FIFO 0 +#define CPU_SPDIF_FIFO 1 +#define CPU_I2S_ENCODER 2 +#define CPU_SPDIF_ENCODER 3 + +#define CTRL_I2S 0 +#define CTRL_PCM 1 +#define CTRL_OUT 2 + +#endif /* __DT_MESON_AIU_H */ diff --git a/include/dt-bindings/sound/meson-g12a-toacodec.h b/include/dt-bindings/sound/meson-g12a-toacodec.h new file mode 100644 index 000000000000..69d7a75592a2 --- /dev/null +++ b/include/dt-bindings/sound/meson-g12a-toacodec.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_MESON_G12A_TOACODEC_H +#define __DT_MESON_G12A_TOACODEC_H + +#define TOACODEC_IN_A 0 +#define TOACODEC_IN_B 1 +#define TOACODEC_IN_C 2 +#define TOACODEC_OUT 3 + +#endif /* __DT_MESON_G12A_TOACODEC_H */ |