wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-01-18	dt-bindings: clock: versaclock5: Document 5P49V60 compatible string	Lars-Peter Clausen	1	-0/+1
2022-12-16	dt-bindings: drop redundant part of title (beginning)	Krzysztof Kozlowski	1	-1/+1
2022-10-04	Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' into clk-next	Stephen Boyd	1	-0/+2
2022-10-03	dt-bindings: clock: vc5: Add 5P49V6975	Matthias Fend	1	-0/+2
2022-08-22	dt-bindings: clock: Move versaclock.h to dt-bindings/clock	Lukas Bulwahn	1	-2/+2
2022-06-06	dt-bindings: update Luca Ceresoli's e-mail address	Luca Ceresoli	1	-1/+1
2022-03-24	dt-bindings: clock: drop useless consumer example	Krzysztof Kozlowski	1	-7/+0
2021-08-28	dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin	Sean Anderson	1	-0/+40
2021-07-03	Merge tag 'devicetree-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux	Linus Torvalds	1	-3/+4
2021-06-21	dt-bindings: clk: vc5: Fix example	Sean Anderson	1	-3/+4
2021-05-17	dt-bindings: More removals of type references on common properties	Rob Herring	1	-2/+0
2021-02-11	dt-bindings: clk: versaclock5: Add optional load capacitance property	Adam Ford	1	-0/+6
2020-10-06	dt-bindings: Another round of adding missing 'additionalProperties'	Rob Herring	1	-9/+11
2020-08-14	dt-bindings: Whitespace clean-ups in schema files	Rob Herring	1	-4/+4
2020-07-23	dt-bindings: clk: versaclock5: convert to yaml	Luca Ceresoli	1	-0/+154