wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2024-02-06	dt-bindings: firmware: xilinx: Describe soc-nvmem subnode	Michal Simek	1	-0/+18
2024-01-22	dt-bindings: firmware: xilinx: Sort node names (clock-controller)	Michal Simek	1	-9/+9
2024-01-22	dt-bindings: firmware: xilinx: Describe missing child nodes	Michal Simek	1	-0/+50
2024-01-22	dt-bindings: firmware: xilinx: Fix versal-fpga node name	Michal Simek	1	-2/+2
2024-01-22	dt-bindings: firmware: versal: add versal-net compatible string	Jay Buddhabhatti	1	-0/+6
2023-12-17	dt-bindings: Remove alt_ref from versal	Shubhrajyoti Datta	1	-2/+2
2023-08-18	dt-bindings: power: xilinx: merge zynqmp-genpd.txt with firmware binding	Naman Trivedi Manojbhai	1	-0/+14
2023-06-05	dt-bindings: xilinx: Switch xilinx.com emails to amd.com	Michal Simek	1	-1/+1
2021-07-21	dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt file	Nava kishore Manne	1	-44/+0
2021-07-21	dt-bindings: firmware: Add bindings for xilinx firmware	Nava kishore Manne	1	-0/+89
2019-10-16	dt-bindings: firmware: Add bindings for Versal firmware	Jolly Shah	1	-1/+15
2019-03-18	dt-bindings: xilinx: Separate clock binding from firmware doc	Rajan Vaja	1	-53/+1
2019-03-18	include: dt-binding: clock: Rename zynqmp header file	Jolly Shah	1	-1/+1
2018-10-09	dt-bindings: clock: Add bindings for ZynqMP clock driver	Rajan Vaja	1	-0/+53
2018-09-26	dt-bindings: firmware: Add bindings for ZynqMP firmware	Rajan Vaja	1	-0/+29