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9 daysMerge tag 'char-misc-7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-miscLinus Torvalds4-1/+299
Pull char/misc/IIO/etc driver updates from Greg KH: "Here is the big set of char, misc, iio, counter, fpga, and other small driver subsystems for 7.3-rc1. Overall, due to some driver removals we only added a bit more code than removed, which was a nice change. Highlights in this merge request are: - Loads of IIO driver updates and additions - binder driver updates (more on that below...) - Removal of the SGI XP and GRU drivers as they are not used anymore and turn out to be pretty insecure overall - Removal of the obsolete ibmasm driver as it's not being used anymore - Coresight driver updates and additions - Mei driver udpates - Counter driver updates - FPGA driver updates - ICC driver updates - lots and lots of other tiny driver updates to resolve reported issues All of these have been in linux-next for a while" * tag 'char-misc-7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (513 commits) iio: chemical: atlas-sensor: use iio_trigger_poll_nested() to fix remove UAF iio: adc: pac1921: fix wrong channel used in trigger handler read iio: light: gp2ap002: re-enable irq if runtime suspend fails iio: light: gp2ap002: Fix unbalanced runtime PM on repeated event writes iio: light: apds9306: fix PM reference leak in apds9306_read_data() iio: gyro: mpu3050: fix sign of raw angular velocity readings iio: srf04: fix pm_runtime handling on probe error path iio: adc: ad4080: configure backend data size iio: adc: adi-axi-adc: add data size support for AD408X backend iio: chemical: atlas-sensor: fix PM reference leak in buffer postenable iio: dac: ad5446: fix OF module device table iio: light: opt4001: Fix reversed GENMASK() arguments in fault count mask iio: light: opt4001: Reject integration times with a non-zero seconds part iio: light: opt4001: Fix incompatible pointer type passed to div_u64_rem() iio: light: opt4001: Fix power down clearing bits of the wrong register iio: light: opt4060: Fix incorrect register name in threshold read error message iio: light: opt4060: Fix pointer type passed to div_u64_rem() iio: light: opt4060: Reject integration times with a non-zero seconds part iio: light: ltrf216a: fix runtime PM reference leak in error path iio: pressure: dps310: fix NULL pointer dereference on ACPI probe ...
2026-08-15dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatibleYijie Yang1-0/+1
Add the Qualcomm Maili SoC compatible string for the CPU bandwidth monitor (BWMONv4). This falls back to the sdm845-bwmon compatible, consistent with the existing pattern used by other recent SoCs such as sm8750 and kaanapali. Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Link: https://patch.msgid.link/20260811-bwmon-v2-1-80f7f150ab9e@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-07-22Merge branch 'icc-maili' into icc-nextGeorgi Djakov1-0/+127
Add interconnect bindings and RPMh-based interconnect driver support for the upcoming Qualcomm Maili SoC. * icc-maili dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC interconnect: qcom: add Maili interconnect provider driver Link: https://patch.msgid.link/20260622-maili_icc-v2-0-18b5ac08c04f@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-07-22Merge branch 'icc-shikra' into icc-nextGeorgi Djakov1-0/+2
Add Epoch Subsystem (EPSS) L3 scaling support on Qualcomm Shikra SoC. EPSS hardware on Shikra is similar to other SoCs but supports only twelve L3 frequency entries (LUT). Reading the LUT beyond supported frequencies can expose incorrect frequencies. Introduce new compatible to represent this constrained variant of EPSS. * icc-shikra dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-0-3c2e0b796e78@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-07-14dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatibleSayantan Chakraborty1-0/+1
Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR bandwidth monitor. Shikra has a BWMONv5 for CPU. Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://patch.msgid.link/20260714-shikra-dt-m1-v6-1-bee265d3499b@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-07-14dt-bindings: interconnect: qcom-bwmon: Document Eliza BWMONs compatibleAbel Vesa1-0/+2
Document Eliza BWMONs which has a BWMONv4 for CPU-LLCC and a BWMONv5 for DDR-LLCC paths, same as SM8550. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260708-bindings-llcc-bwmon-eliza-v1-1-3c7dbcbae87a@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-07-07dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoCRaviteja Laggyshetty1-0/+127
Document the RPMh Network-On-Chip interconnect for the Qualcomm Maili SoC. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260622-maili_icc-v2-1-18b5ac08c04f@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-07-07dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoCRaviteja Laggyshetty1-0/+2
Document the EPSS L3 interconnect provider binding for Qualcomm Shikra SoC. The Shikra EPSS L3 block is similar to existing Qualcomm EPSS/OSM L3 providers, but supports only up to 12 frequency lookup table entries. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-1-3c2e0b796e78@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-07-07Merge branch 'icc-x1e80100' into icc-nextGeorgi Djakov1-0/+72
This series enables QoS configuration for QNOC type device which can be found on X1E80100 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-x1e80100 dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS interconnect: qcom: x1e80100: enable QoS configuration Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-07-07dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoSRaviteja Laggyshetty1-0/+72
Some interconnect nodes on X1E80100 have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock-gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-1-305c6539e6d2@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-07-07dt-bindings: interconnect: qcom,sc8280xp-rpmh: Add reg and clocks for QoSXilin Wu1-1/+98
Add the register range and clock properties needed for programming NoC QoS configuration on SC8280XP. Require a register range for the real NoC providers, require QoS clocks for aggre1_noc and aggre2_noc, and keep the virtual clk_virt and mc_virt providers without MMIO resources or clocks. Signed-off-by: Xilin Wu <sophon@radxa.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260507-sc8280xp-qos-v1-1-15135858cd98@radxa.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-06-30dt-bindings: Drop incorrect usage of double '::'Krzysztof Kozlowski2-8/+8
There is no use of double colon '::' in YAML. OTOH, the literal style block, e.g. using '|' treats all characters as content [1] therefore single use of ':' in descriptions is perfectly fine, whenever '|' is used. Cleanup existing code, so the confusing style won't be re-used in new contributions. Link: https://yaml.org/spec/1.2.2/#literal-style [1] Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20260623054842.21831-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-22Merge branch 'icc-misc' into icc-nextGeorgi Djakov2-18/+28
* icc-misc interconnect: Do not create empty devres on missing interconnects interconnect: Move MODULE_DEVICE_TABLE next to the table itself dt-bindings: interconnect: qcom,sdm660: Disallow clocks when appropriate dt-bindings: interconnect: qcom,sm6115: Drop incorrect children if:then: block dt-bindings: interconnect: qcom,sm6115: Restrict children and clocks interconnect: qcom: Fix indentation interconnect: qcom: Restrict drivers per ARM/ARM64 Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-21Merge branch 'icc-hawi' into icc-nextGeorgi Djakov2-0/+133
Add interconnect bindings and RPMh-based interconnect driver support for the upcoming Qualcomm Hawi SoC. * icc-hawi dt-bindings: interconnect: qcom-bwmon: Add Hawi cpu-bwmon compatible dt-bindings: interconnect: qcom-bwmon: Add Hawi llcc-bwmon compatible dt-bindings: interconnect: qcom: document the RPMh NoC for Hawi SoC interconnect: qcom: add Hawi interconnect provider driver Link: https://patch.msgid.link/20260506-icc-hawi-v4-0-35447fdc482b@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-21dt-bindings: interconnect: qcom: document the RPMh NoC for Hawi SoCVivek Aknurwar1-0/+131
Document the RPMh Network-On-Chip interconnect for the Qualcomm Hawi SoC. Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> Link: https://patch.msgid.link/20260506-icc-hawi-v4-1-35447fdc482b@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-21dt-bindings: interconnect: qcom-bwmon: Add Hawi llcc-bwmon compatibleMukesh Ojha1-0/+1
Document BWMONv5 instance present on Hawi SoC for monitoring bandwidth LLCC to DDR. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260520122219.2372694-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-21Merge branch 'icc-nord' into icc-nextGeorgi Djakov1-0/+131
This adds RPMh-based interconnect support for the Qualcomm Nord SoC. The Nord SoC features a rich Network-on-Chip topology comprising 19 NoCs including aggregate NoCs, a high-speed configuration NoC (HSCNOC), a multimedia NoC, four NSP data NoCs for AI/ML workloads, PCIe inbound and outbound NoCs, a system NoC, and virtual clock/MC nodes. Bandwidth requests are communicated to the RPMh hardware through Bus Clock Manager (BCM) resources via the Resource State Coordinator (RSC). * icc-nord dt-bindings: interconnect: Document RPMh Network-On-Chip for Qualcomm Nord SoC interconnect: qcom: Add interconnect provider driver for Nord SoC Link: https://patch.msgid.link/20260510020607.1129773-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-10dt-bindings: interconnect: qcom,sm6115: Restrict children and clocksKrzysztof Kozlowski1-4/+15
Some interconnect devices described in the binding have children and some have clocks. The devices which do not have them, should have this restricted (disallowed). qcom,sm6115-cnoc has a clock, thus also extend the example to be complete for this device. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260503161653.60785-6-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-10dt-bindings: interconnect: qcom,sm6115: Drop incorrect children if:then: blockKrzysztof Kozlowski1-14/+0
This binding has children, so any if:then: block restricting them, cannot be defined in top-level allOf:if:then:properties:, because it simply does not match these children. The block, if it was useful, should be defined within patternProperties for the children, however since child nodes do not have clocks at all, there is little point in disallowing them in the first place. Remove completely redundant and ineffective piece of code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260503161653.60785-5-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-10dt-bindings: interconnect: qcom,sdm660: Disallow clocks when appropriateKrzysztof Kozlowski1-0/+13
Only qcom,sdm660-mnoc and qcom,sdm660-a2noc devices from what is covered by this binding have clocks. Others do not, so restrict the schema to be more accurate. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260503161653.60785-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-10dt-bindings: interconnect: qcom-bwmon: Add Hawi cpu-bwmon compatibleMukesh Ojha1-0/+1
Add the Qualcomm Hawi SoC compatible string for the CPU bandwidth monitor and there is single instance present globally to monitor the traffic from CPU to LLCC. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260427182255.3649922-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-10dt-bindings: interconnect: Document RPMh Network-On-Chip for Qualcomm Nord SoCOdelu Kukatla1-0/+131
Add RPMh Network-On-Chip interconnect bindings for Qualcomm Nord SoC. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260510020607.1129773-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-05-10dt-bindings: interconnect: document the RPM Network-On-Chip interconnect in Shikra SoCRaviteja Laggyshetty1-0/+134
Document the RPM Network-On-Chip Interconnect for the Qualcomm Shikra platform. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Link: https://patch.msgid.link/20260505-shikra_icc-v3-1-8e03ff27c007@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-27Merge branch 'icc-msm8974' into icc-nextGeorgi Djakov1-12/+16
Commit d6edc31f3a68 ("clk: qcom: smd-rpm: Separate out interconnect bus clocks") moved control over several RPM resources from the clk-smd-rpm driver to the icc-rpm.c interconnect helpers. Most of the platforms were fixed before that commit or shortly after. However the MSM8974 was left as a foster child in broken state. Fix the loose ends and reenable interconnects on that platform. * icc-msm8974 dt-bindings: interconnect: qcom,msm8974: drop bus clocks dt-bindings: interconnect: qcom,msm8974: use qcom,rpm-common interconnect: qcom: drop unused is_on flag interconnect: qcom: icc-rpm: allow overwriting get_bw callback interconnect: qcom: define OCMEM bus resource interconnect: qcom: let platforms declare their bugginess interconnect: qcom: msm8974: switch to the main icc-rpm driver interconnect: qcom: msm8974: expand DEFINE_QNODE macros Link: https://msgid.link/20260324-msm8974-icc-v2-0-527280043ad8@oss.qualcomm.com Tested-by: Alexandre Messier <alex@me.ssier.org> Tested-by: Luca Weiss <luca.weiss@fairphone.com> # fairphone-fp2 Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-26dt-bindings: interconnect: qcom,msm8974: use qcom,rpm-commonDmitry Baryshkov1-5/+2
Use qcom,rpm-common schema to declare interconnects property instead describing it again. In future this will allow the platform to switch to the two-cell interconnects, adding the tag to the specification. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://msgid.link/20260324-msm8974-icc-v2-2-527280043ad8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-26dt-bindings: interconnect: qcom,msm8974: drop bus clocksDmitry Baryshkov1-7/+14
Remove the wrong internal RPM bus clock representation that we've been carrying for years. They are an internal part of the interconnect fabric. They are not exported by any device and are not supposed to be used. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://msgid.link/20260324-msm8974-icc-v2-1-527280043ad8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-17Merge branch 'icc-qcs615' into icc-nextGeorgi Djakov1-0/+23
This series enables QoS configuration for QNOC type device which can be found on QCS615 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-qcs615 dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS interconnect: qcom: qcs615: enable QoS configuration Link: https://msgid.link/20260311103548.1823044-1-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-17dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoSOdelu Kukatla1-0/+23
Aggre1-noc interconnect node on QCS615 has QoS registers located inside a block whose interface is clock-gated. Accessing these registers requires the corresponding clock(s) to be enabled. Update the bindings to include the 'clocks' property. Ensure that only aggre1-noc interconnect node uses this property by explicitly forbidding it for all other interconnect nodes. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260311103548.1823044-2-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06Merge branch 'icc-qcs8300' into icc-nextGeorgi Djakov1-0/+63
This series enables QoS configuration for QNOC type device which can be found on QCS8300 platform. It enables QoS configuration for master ports with predefined priority and urgency forwarding. This helps in prioritizing the traffic originating from different interconnect masters at NOC (Network On Chip). The system may function normally without this feature. However, enabling QoS helps optimize latency and bandwidth across subsystems like CPU, GPU, and multimedia engines, which becomes important in high-throughput scenarios. This is a feature aimed at performance enhancement to improve system performance under concurrent workloads. * icc-qcs8300 dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS interconnect: qcom: qcs8300: enable QoS configuration Link: https://msgid.link/20260127090116.1438780-1-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06Merge branch 'icc-mahua' into icc-nextGeorgi Djakov1-25/+111
Mahua is a derivative of the Glymur SoC and shares a significant portion of its interconnect topology with Glymur. As such, this series extends the existing Glymur interconnect driver to support Mahua, reusing common definitions where possible and adding SoC-specific configurations where necessary. * icc-mahua dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC interconnect: qcom: glymur: Add Mahua SoC support Link: https://msgid.link/20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06Merge branch 'icc-eliza' into icc-nextGeorgi Djakov2-0/+143
Add interconnect support for the Qualcomm Eliza SoC. * icc-eliza dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC interconnect: qcom: Add Eliza interconnect provider driver dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatible Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoCOdelu Kukatla1-0/+142
Document the RPMh Network-On-Chip Interconnect of the Eliza platform. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://msgid.link/20260224-eliza-interconnect-v4-1-ad75855d5018@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatibleAbel Vesa1-0/+1
Eliza, similarly to SM8650, uses EPSS hardware for L3 scaling. Document it. Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260302-eliza-bindings-interconnect-epss-l3-v2-1-05b1848b98cc@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: qcom,glymur-rpmh: De-acronymize SoC nameKrzysztof Kozlowski1-1/+1
Glymur is a codename of Qualcomm SoC, not an acronym. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://msgid.link/20260217130035.281752-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatibleAaron Kling1-0/+1
Document the OSM L3 found in the Qualcomm SM8550 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://msgid.link/20260219-sm8550-ddr-bw-scaling-v3-1-75c19152e921@gmail.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoSOdelu Kukatla1-0/+63
Some QCS8300 interconnect nodes have QoS registers located inside a block whose interface is clock-gated. For those nodes, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock‑gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260127090116.1438780-2-odelu.kukatla@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-03-06dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoCRaviteja Laggyshetty1-25/+111
Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm Mahua platform. Mahua is a derivative of the Glymur SoC. Many interconnect nodes are identical and continue to use Glymur fallback compatibles. Mahua introduces SoC-specific configurations and topologies for several NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs. This updates the existing Glymur yaml schema to include Mahua-specific compatible strings, using two-cell "fallback" compatibles wherever the hardware is identical with Glymur. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://msgid.link/20260209-mahua_icc-v3-1-c65f3dfd72c8@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-01-30Merge tag 'icc-6.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-nextGreg Kroah-Hartman3-2/+2
Georgi writes: interconnect changes for 6.20 This pull request contains the interconnect changes for the 6.20-rc1 merge window. The core and driver changes are listed below. Core changes: - Add KUnit tests for core functionality Driver changes: - New driver for MediaTek MT8196 EMI - MediaTek driver fixes - Support for Glymur BWMONs - QCS8300 driver topology fix - Misc cleanups Signed-off-by: Georgi Djakov <djakov@kernel.org> * tag 'icc-6.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc: interconnect: qcom: msm8974: drop duplicated RPM_BUS_{MASTER,SLAVE}_REQ defines interconnect: qcom: smd-rpm: drop duplicated QCOM_RPM_SMD_KEY_RATE define dt-bindings: interconnect: qcom-bwmon: Document Glymur BWMONs interconnect: qcom: qcs8300: fix the num_links for nsp icc node interconnect: Add kunit tests for core functionality dt-bindings: interconnect: qcom,qcs615-rpmh: Drop IPA interconnects interconnect: mediatek: Aggregate bandwidth with saturating add interconnect: mediatek: Don't hijack parent device interconnect: mediatek: Add support for MediaTek MT8196 EMI ICC dt-bindings: interconnect: mt8183-emi: Add support for MT8196 EMI
2026-01-21dt-bindings: interconnect: qcom-bwmon: Document Glymur BWMONsPragnesh Papaniya1-0/+1
Document Glymur BWMONs, which has multiple (one per cluster) BWMONv4 instances for the CPU->DDR path. Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260120-glymur_bwmon_binding-v1-1-57848445eccf@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-01-13Merge branch 'icc-mtk' into icc-nextGeorgi Djakov1-0/+1
This series is a combination of binding changes, driver cleanups and new driver code to enable the interconnect on the MediaTek MT8196 SoC. * icc-mtk dt-bindings: interconnect: mt8183-emi: Add support for MT8196 EMI interconnect: mediatek: Add support for MediaTek MT8196 EMI ICC interconnect: mediatek: Don't hijack parent device interconnect: mediatek: Aggregate bandwidth with saturating add Link: https://lore.kernel.org/r/20251124-mt8196-dvfsrc-v2-0-d9c1334db9f3@collabora.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2026-01-13dt-bindings: interconnect: qcom,qcs615-rpmh: Drop IPA interconnectsKonrad Dybcio1-2/+0
This has been agreed to be characterized as a clock resource, not an interconnect provider. Bring QCS615 in line with the expectation. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250627-topic-qcs615_icc_ipa-v1-3-dc47596cde69@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-12-21dt-bindings: interconnect: mt8183-emi: Add support for MT8196 EMIAngeloGioacchino Del Regno1-0/+1
Add a new compatible for the External Memory Interface Interconnect found on the MediaTek MT8196 Chromebook SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20251124-mt8196-dvfsrc-v2-3-d9c1334db9f3@collabora.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-12-19dt-bindings: interconnect: qcom,sa8775p-rpmh: Fix incorrectly added reg and clocksKrzysztof Kozlowski1-0/+31
Commit 8a55fbe4c94d ("dt-bindings: interconnect: add reg and clocks properties to enable QoS on sa8775p") claims that all interconnects have clocks and MMIO address space, but that is just not true. Only few have. Bindings should restrict properties and should not allow specifying non-existing hardware description, so fix missing constraints for 'reg' and 'clocks'. Fixes: 8a55fbe4c94d ("dt-bindings: interconnect: add reg and clocks properties to enable QoS on sa8775p") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251129094612.16838-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-12-06Merge tag 'char-misc-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-miscLinus Torvalds4-12/+228
Pull char/misc/IIO driver updates from Greg KH: "Here is the big set of char/misc/iio driver updates for 6.19-rc1. Lots of stuff in here including: - lots of IIO driver updates, cleanups, and additions - large interconnect driver changes as they get converted over to a dynamic system of ids - coresight driver updates - mwave driver updates - binder driver updates and changes - comedi driver fixes now that the fuzzers are being set loose on them - nvmem driver updates - new uio driver addition - lots of other small char/misc driver updates, full details in the shortlog All of these have been in linux-next for a while now" * tag 'char-misc-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (304 commits) char: applicom: fix NULL pointer dereference in ac_ioctl hangcheck-timer: fix coding style spacing hangcheck-timer: Replace %Ld with %lld hangcheck-timer: replace printk(KERN_CRIT) with pr_crit uio: Add SVA support for PCI devices via uio_pci_generic_sva.c dt-bindings: slimbus: fix warning from example intel_th: Fix error handling in intel_th_output_open misc: rp1: Fix an error handling path in rp1_probe() char: xillybus: add WQ_UNBOUND to alloc_workqueue users misc: bh1770glc: use pm_runtime_resume_and_get() in power_state_store misc: cb710: Fix a NULL vs IS_ERR() check in probe() mux: mmio: Add suspend and resume support virt: acrn: split acrn_mmio_dev_res out of acrn_mmiodev greybus: gb-beagleplay: Fix timeout handling in bootloader functions greybus: add WQ_PERCPU to alloc_workqueue users char/mwave: drop typedefs char/mwave: drop printk wrapper char/mwave: remove printk tracing char/mwave: remove unneeded fops char/mwave: remove MWAVE_FUTZ_WITH_OTHER_DEVICES ifdeffery ...
2025-11-19dt-bindings: interconnect: qcom,sm6350-rpmh: Add clocks for QoSLuca Weiss1-11/+54
Add the clocks for some interconnects to the bindings that are required to set up the QoS correctly. Update one of the examples to aggre2_noc to have an example with clocks. Also while we're at it, remove #interconnect-cells: true as that's already provided from qcom,rpmh-common.yaml. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-1-6af348cb9c69@fairphone.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-11-19Merge branch 'icc-kaanapali' into icc-nextGeorgi Djakov2-0/+125
Add interconnect dt-bindings and driver support for Qualcomm Kaanapali SoC. * icc-kaanapali dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Kaanapali SoC interconnect: qcom: add Kaanapali interconnect provider driver dt-bindings: interconnect: qcom-bwmon: Document Kaanapali BWMONs Link: https://lore.kernel.org/r/20251031-knp-interconnect-v4-0-568bba2cb3e5@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-11-19dt-bindings: interconnect: qcom-bwmon: Document Kaanapali BWMONsAmir Vajid1-0/+1
Document the Kaanapali BWMONs, which have one instance per cluster of BWMONv4. Signed-off-by: Amir Vajid <amir.vajid@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250924-knp-bwmon-v1-1-56a9cdda7d72@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-11-17dt-bindings: Remove extra blank linesRob Herring (Arm)1-1/+0
Generally at most 1 blank line is the standard style for DT schema files. Remove the few cases with more than 1 so that the yamllint check for this can be enabled. Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> # remoteproc Acked-by: Georgi Djakov <djakov@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for allwinner,sun4i-a10-pwm.yaml Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> # For PCI controller bindings Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-11-17dt-bindings: Update Krzysztof Kozlowski's emailKrzysztof Kozlowski1-1/+1
Update Krzysztof Kozlowski's email address to kernel.org account to stay reachable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251021095354.86455-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-10-31dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Kaanapali SoCRaviteja Laggyshetty1-0/+124
Document the RPMh Network-On-Chip Interconnect of the Kaanapali platform. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251031-knp-interconnect-v4-1-568bba2cb3e5@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
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