wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-06-21	mips: ralink: mt7620: remove clock related code	Sergio Paracuellos	1	-35/+0
2023-03-14	mips: ralink: mt7620: define MT7620_SYSC_BASE with __iomem	Sergio Paracuellos	1	-1/+2
2021-06-07	pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file	Sergio Paracuellos	1	-46/+7
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	Thomas Gleixner	1	-3/+1
2017-01-03	MIPS: ralink: Add missing pinmux.	John Crispin	1	-1/+6
2016-05-13	mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type	Sashka Nochkin	1	-0/+1
2016-05-13	MIPS: Change my email address	John Crispin	1	-1/+1
2015-11-11	MIPS: ralink: Unify SoC id handling	John Crispin	1	-7/+0
2015-11-11	MIPS: ralink: Add support for mt7688	John Crispin	1	-0/+1
2014-11-24	MIPS: ralink: add mt7628an support	John Crispin	1	-0/+11
2014-11-24	MIPS: ralink: add support for MT7620n	John Crispin	1	-5/+2
2014-11-24	MIPS: ralink: cleanup the soc specific pinmux data	John Crispin	1	-11/+30
2014-11-24	MIPS: ralink: add a helper for reading the ECO version	John Crispin	1	-0/+5
2013-09-04	MIPS: ralink: mt7620: Improve clock frequency detection	Gabor Juhos	1	-8/+32
2013-05-08	MIPS: ralink: add memory definition for MT7620	John Crispin	1	-0/+8
2013-05-08	MIPS: ralink: adds support for MT7620 SoC family	John Crispin	1	-0/+76