wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2024-03-19	Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc	Linus Torvalds	1	-0/+45
2024-03-06	Merge tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late	Arnd Bergmann	1	-0/+45
2024-03-05	riscv: dts: starfive: jh7100: fix root clock names	Krzysztof Kozlowski	1	-0/+4
2024-02-13	riscv: dts: starfive: replace underscores in node names	Krzysztof Kozlowski	1	-6/+6
2024-01-31	riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes	Cristian Ciocaltea	1	-0/+36
2024-01-22	riscv: dts: starfive: jh7100: Add PWM node and pins configuration	William Qiu	1	-0/+9
2023-12-13	riscv: dts: starfive: Add JH7100 MMC nodes	Emil Renner Berthing	1	-0/+26
2023-12-13	riscv: dts: starfive: Add JH7100 cache controller	Emil Renner Berthing	1	-0/+13
2023-12-13	riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs	Emil Renner Berthing	1	-0/+1
2023-12-13	riscv: dts: starfive: Group tuples in interrupt properties	Geert Uytterhoeven	1	-4/+4
2023-10-15	riscv: dts: starfive: convert isa detection to new properties	Conor Dooley	1	-0/+6
2023-07-25	riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones	Hal Feng	1	-0/+37
2023-05-15	riscv: dts: starfive: jh7100: Add watchdog node	Xingyu Wu	1	-0/+10
2022-08-11	riscv: dts: starfive: correct number of external interrupts	Mark Kettenis	1	-1/+1
2022-07-14	riscv: dts: starfive: Add JH7100 CPU topology	Jonas Hahnfeld	1	-2/+14
2021-12-16	RISC-V: Add initial StarFive JH7100 device tree	Emil Renner Berthing	1	-0/+230