wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2022-10-27	RISC-V: Cache SBI vendor values	Heiko Stuebner	1	-0/+5
2022-08-11	RISC-V: Improve SBI definitions	Atish Patra	1	-2/+16
2022-08-11	RISC-V: Move counter info definition to sbi header file	Atish Patra	1	-0/+14
2022-03-25	Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux	Linus Torvalds	1	-0/+95
2022-03-21	RISC-V: Add RISC-V SBI PMU extension definitions	Atish Patra	1	-0/+95
2022-03-11	RISC-V: Add SBI HSM suspend related defines	Anup Patel	1	-5/+22
2022-01-20	RISC-V: Do not use cpumask data structure for hartid bitmap	Atish Patra	1	-9/+10
2022-01-19	Merge tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux	Linus Torvalds	1	-0/+24
2022-01-11	RISC-V: Use SBI SRST extension when available	Anup Patel	1	-0/+24
2022-01-06	RISC-V: KVM: Add SBI HSM extension in KVM	Atish Patra	1	-0/+1
2022-01-06	RISC-V: KVM: Add SBI v0.2 base extension	Atish Patra	1	-0/+8
2021-05-06	Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux	Linus Torvalds	1	-0/+3
2021-04-26	riscv: Add 3 SBI wrapper functions to get cpu manufacturer information	Vincent Chen	1	-0/+3
2021-03-09	RISC-V: correct enum sbi_ext_rfence_fid	Heinrich Schuchardt	1	-2/+2
2021-02-22	RISC-V: Add a non-void return for sbi v02 functions	Atish Patra	1	-5/+5
2021-01-07	riscv: Cleanup sbi function stubs when RISCV_SBI disabled	Kefeng Wang	1	-7/+3
2020-03-31	RISC-V: Add SBI HSM extension definitions	Atish Patra	1	-0/+14
2020-03-31	RISC-V: Export SBI error to linux error mapping function	Atish Patra	1	-0/+2
2020-03-31	RISC-V: Implement new SBI v0.2 extensions	Atish Patra	1	-0/+14
2020-03-31	RISC-V: Introduce a new config for SBI v0.1	Atish Patra	1	-0/+2
2020-03-31	RISC-V: Add SBI v0.2 extension definitions	Atish Patra	1	-0/+21
2020-03-31	RISC-V: Add basic support for SBI v0.2	Atish Patra	1	-71/+68
2020-03-31	RISC-V: Mark existing SBI as 0.1 SBI.	Atish Patra	1	-19/+22
2019-11-17	riscv: provide native clint access for M-mode	Christoph Hellwig	1	-0/+2
2019-11-13	riscv: add support for MMIO access to the timer registers	Christoph Hellwig	1	-1/+2
2019-11-13	riscv: implement remote sfence.i using IPIs	Christoph Hellwig	1	-0/+3
2019-11-13	riscv: poison SBI calls for M-mode	Christoph Hellwig	1	-2/+3
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-16	riscv: fix sbi_remote_sfence_vma{,_asid}.	Gary Guo	1	-7/+12
2017-09-26	RISC-V: Device, timer, IRQs, and the SBI	Palmer Dabbelt	1	-0/+100