wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2025-01-18	riscv: vector: Support xtheadvector save/restore	Charlie Jenkins	1	-1/+1
2024-10-24	riscv: Add support for userspace pointer masking	Samuel Holland	1	-0/+11
2024-10-05	riscv: Add support for per-thread envcfg CSR values	Samuel Holland	1	-0/+8
2024-04-18	riscv: Include riscv_set_icache_flush_ctx prctl	Charlie Jenkins	1	-0/+23
2024-01-16	riscv: fpu: drop SR_SD bit checking	Andy Chiu	1	-2/+1
2023-11-09	riscv: Rearrange hwcap.h and cpufeature.h	Xiao Wang	1	-1/+1
2023-06-08	riscv: Add task switch support for vector	Greentime Hu	1	-0/+3
2023-06-08	riscv: Rename __switch_to_aux() -> fpu	Guo Ren	1	-3/+3
2023-01-31	riscv: fpu: switch has_fpu() to riscv_has_extension_likely()	Jisheng Zhang	1	-1/+2
2022-06-16	riscv: switch has_fpu() to the unified static key mechanism	Jisheng Zhang	1	-2/+2
2021-05-25	riscv: Turn has_fpu into a static key if FPU=y	Jisheng Zhang	1	-3/+8
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-5/+5
2019-10-28	riscv: add missing header file includes	Paul Walmsley	1	-0/+1
2019-08-14	riscv: Make __fstate_clean() work correctly.	Vincent Chen	1	-1/+1
2019-08-14	riscv: Correct the initialized flow of FP register	Vincent Chen	1	-0/+6
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2018-10-22	Auto-detect whether a FPU exists	Alan Kao	1	-4/+4
2018-10-22	Allow to disable FPU support	Alan Kao	1	-0/+10
2017-09-26	RISC-V: Task implementation	Palmer Dabbelt	1	-0/+69