wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-09-08	Merge patch series "Add non-coherent DMA support for AX45MP"	Palmer Dabbelt	1	-0/+5
2023-09-01	riscv: errata: Add Andes alternative ports	Lad Prabhakar	1	-0/+5
2023-09-01	RISC-V: alternative: Remove feature_probe_func	Evan Green	1	-19/+0
2023-04-25	RISC-V: hwprobe: Remove __init on probe_vendor_features()	Evan Green	1	-2/+2
2023-04-18	RISC-V: hwprobe: Support probing of misaligned access performance	Evan Green	1	-0/+19
2023-02-21	riscv: alternative: proceed one more instruction for auipc/jalr pair	Jisheng Zhang	1	-0/+1
2023-01-31	riscv: alternative: patch alternatives in the vDSO	Jisheng Zhang	1	-0/+29
2023-01-24	riscv: fix jal offsets in patched alternatives	Jisheng Zhang	1	-0/+27
2022-12-29	RISC-V: fix auipc-jalr addresses in patched alternatives	Heiko Stuebner	1	-0/+56
2022-06-16	riscv: make patch-function pointer more generic in cpu_manufacturer_info struct	Heiko Stuebner	1	-9/+9
2022-05-11	riscv: add memory-type errata for T-Head	Heiko Stuebner	1	-0/+26
2022-05-11	riscv: don't use global static vars to store alternative data	Heiko Stuebner	1	-27/+24
2022-05-11	riscv: add RISC-V Svpbmt extension support	Heiko Stuebner	1	-0/+2
2022-05-11	riscv: implement module alternatives	Heiko Stuebner	1	-4/+14
2022-05-11	riscv: allow different stages with alternatives	Heiko Stuebner	1	-9/+17
2022-05-11	riscv: integrate alternatives better into the main architecture	Heiko Stuebner	1	-0/+75