wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-06-21	clk: at91: clk-utmi: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-system: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-programmable: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-peripheral: add support for parent_hw	Claudiu Beznea	1	-2/+2
2023-06-21	clk: at91: clk-master: add support for parent_hw	Claudiu Beznea	1	-2/+2
2023-06-21	clk: at91: clk-generated: add support for parent_hw	Claudiu Beznea	1	-1/+1
2023-06-21	clk: at91: clk-main: add support for parent_data/parent_hw	Claudiu Beznea	1	-2/+2
2023-01-09	clk: at91: mark ddr clocks as critical	Claudiu Beznea	1	-5/+17
2022-09-15	clk: at91: sama5d2: Add Generic Clocks for UART/USART	Sergiu Moga	1	-0/+10
2022-03-08	clk: at91: clk-master: remove dead code	Claudiu Beznea	1	-2/+1
2022-01-24	clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT	Zixun LI	1	-1/+3
2021-10-26	clk: at91: clk-master: add notifier for divider	Claudiu Beznea	1	-1/+1
2021-02-09	clk: at91: Fix the declaration of the clocks	Tudor Ambarus	1	-1/+2
2020-12-19	clk: at91: clk-master: re-factor master clock	Claudiu Beznea	1	-15/+27
2020-07-24	clk: at91: clk-programmable: add mux_table option	Claudiu Beznea	1	-1/+2
2020-07-24	clk: at91: clk-peripheral: add support for changeable parent rate	Claudiu Beznea	1	-2/+3
2020-07-24	clk: at91: clk-generated: add mux_table option	Claudiu Beznea	1	-1/+1
2020-07-24	clk: at91: clk-generated: pass the id of changeable parent at registration	Claudiu Beznea	1	-16/+15
2020-05-26	clk: at91: allow setting all PMC clock parents via DT	Michał Mirosław	1	-1/+5
2020-05-26	clk: at91: allow setting PCKx parent via DT	Michał Mirosław	1	-1/+3
2020-05-26	clk: at91: optimize pmc data allocation	Michał Mirosław	1	-1/+1
2020-05-26	clk: at91: Add peripheral clock for PTC	Codrin Ciubotariu	1	-0/+1
2019-12-16	clk: at91: fix possible deadlock	Alexandre Belloni	1	-1/+1
2019-09-17	clk: at91: allow 24 Mhz clock as input for PLL	Eugen Hristev	1	-1/+1
2019-05-07	Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next	Stephen Boyd	1	-1/+11
2019-04-25	clk: at91: Mark struct clk_range as const	Stephen Boyd	1	-1/+1
2019-04-25	clk: at91: allow configuring generated PCR layout	Alexandre Belloni	1	-0/+1
2019-04-25	clk: at91: allow configuring peripheral PCR layout	Alexandre Belloni	1	-0/+9
2019-03-18	clk: at91: fix programmable clock for sama5d2	Matthias Wieloch	1	-1/+9
2019-03-08	Merge branch 'clk-at91' into clk-next	Stephen Boyd	1	-1/+2
2019-02-20	clk: at91: fix masterck name	Alexandre Belloni	1	-2/+2
2019-01-09	clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2	Michał Mirosław	1	-1/+2
2018-10-17	clk: at91: add sama5d2 PMC driver	Alexandre Belloni	1	-0/+336