wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2022-06-15	clk: mediatek: reset: Add new register reset function with device	Rex-BC Chen	1	-2/+2
2022-06-15	clk: mediatek: reset: Support nonsequence base offsets of reset registers	Rex-BC Chen	1	-4/+7
2022-06-15	clk: mediatek: reset: Revise structure to control reset register	Rex-BC Chen	1	-2/+17
2022-06-15	clk: mediatek: reset: Merge and revise reset register function	Rex-BC Chen	1	-2/+2
2022-05-19	clk: mediatek: Replace 'struct clk' with 'struct clk_hw'	Chen-Yu Tsai	1	-14/+14
2022-05-18	clk: mediatek: use en_mask as a pure div_en_mask	Chun-Jie Chen	1	-15/+15
2022-02-17	clk: mediatek: pll: Split definitions into separate header file	Chen-Yu Tsai	1	-1/+2
2019-10-16	clk: mediatek: mt2712: use devm_platform_ioremap_resource() to simplify code	YueHaibing	1	-4/+2
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	Thomas Gleixner	1	-9/+1
2019-03-08	Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip' into clk-next	Stephen Boyd	1	-2/+6
2019-02-22	clk: mediatek: fix platform_no_drv_owner.cocci warnings	YueHaibing	1	-1/+0
2019-02-05	clk: mediatek: update clock driver of MT2712	Weiyi Lu	1	-2/+6
2018-03-19	clk: mediatek: update clock driver of MT2712	Weiyi Lu	1	-14/+55
2017-11-02	clk: mediatek: Add MT2712 clock support	weiyi.lu@mediatek.com	1	-0/+1435