wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-10-18	clk: mediatek: clk-mt7629-eth: Add check for mtk_alloc_clk_data	Jiasheng Jiang	1	-0/+4
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	1	-2/+0
2023-03-13	clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriate	AngeloGioacchino Del Regno	1	-0/+1
2023-03-13	clk: mediatek: Add MODULE_LICENSE() where missing	AngeloGioacchino Del Regno	1	-0/+1
2023-03-13	clk: mediatek: Consistently use GATE_MTK() macro	AngeloGioacchino Del Regno	1	-16/+4
2023-01-30	clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates()	AngeloGioacchino Del Regno	1	-3/+4
2022-06-15	clk: mediatek: reset: Add new register reset function with device	Rex-BC Chen	1	-1/+1
2022-06-15	clk: mediatek: reset: Support nonsequence base offsets of reset registers	Rex-BC Chen	1	-2/+4
2022-06-15	clk: mediatek: reset: Revise structure to control reset register	Rex-BC Chen	1	-1/+7
2022-06-15	clk: mediatek: reset: Merge and revise reset register function	Rex-BC Chen	1	-1/+1
2022-05-19	clk: mediatek: Replace 'struct clk' with 'struct clk_hw'	Chen-Yu Tsai	1	-4/+4
2018-11-29	clk: mediatek: add clock support for MT7629 SoC	Ryder Lee	1	-0/+159