| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2024-01-03 | clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 |   Sam Shih | 1 | -0/+1 |
| 2022-11-29 | clk: mediatek: Export PLL operations symbols |   Johnson Wang | 1 | -0/+55 |
| 2022-05-19 | clk: mediatek: Replace 'struct clk' with 'struct clk_hw' |   Chen-Yu Tsai | 1 | -3/+3 |
| 2022-02-17 | clk: mediatek: pll: Implement error handling in register API | Chen-Yu Tsai | 1 | -3/+3 |
| 2022-02-17 | clk: mediatek: pll: Implement unregister API | Chen-Yu Tsai | 1 | -0/+2 |
| 2022-02-17 | clk: mediatek: pll: Split definitions into separate header file | Chen-Yu Tsai | 1 | -0/+55 |
 |
index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
| aboutsummaryrefslogtreecommitdiffstatshomepage |