wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2024-12-02	module: Convert symbol namespace to string literal	Peter Zijlstra	1	-2/+2
2024-07-29	clk: meson: introduce symbol namespace for amlogic clocks	Jerome Brunet	1	-1/+2
2024-06-14	clk: meson: add missing MODULE_DESCRIPTION() macros	Jerome Brunet	1	-0/+2
2024-04-10	clk: meson: fix module license to GPL only	Neil Armstrong	1	-1/+1
2023-08-30	Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next	Stephen Boyd	1	-5/+4
2023-08-08	clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS	Neil Armstrong	1	-5/+4
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	1	-1/+1
2022-08-19	clk: meson: Hold reference returned by of_get_parent()	Liang He	1	-1/+4
2020-11-23	clk: meson: enable building as modules	Kevin Hilman	1	-0/+3
2019-07-29	clk: meson: remove ee input bypass clocks	Alexandre Mergnat	1	-10/+0
2019-05-20	clk: meson: eeclk: add init regs	Jerome Brunet	1	-0/+3
2019-02-04	clk: meson: factorise meson64 peripheral clock controller drivers	Jerome Brunet	1	-0/+63