wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2022-09-30	clk: mmp: pxa168: control shared SDH bits with separate clock	Doug Brown	1	-4/+7
2022-09-30	clk: mmp: pxa168: add clocks for SDH2 and SDH3	Doug Brown	1	-0/+6
2022-09-30	clk: mmp: pxa168: fix GPIO clock enable bits	Doug Brown	1	-1/+1
2022-09-30	clk: mmp: pxa168: add muxes for more peripherals	Doug Brown	1	-10/+32
2022-09-30	clk: mmp: pxa168: fix incorrect parent clocks	Doug Brown	1	-6/+6
2022-09-30	clk: mmp: pxa168: fix const-correctness	Doug Brown	1	-7/+7
2022-09-30	clk: mmp: pxa168: add new clocks for peripherals	Doug Brown	1	-0/+3
2022-09-30	clk: mmp: pxa168: fix incorrect dividers	Doug Brown	1	-2/+2
2022-09-30	clk: mmp: pxa168: add additional register defines	Doug Brown	1	-7/+24
2022-06-10	treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 2)	Thomas Gleixner	1	-4/+1
2016-11-01	clk: mmp: pxa168: fix return value check in pxa168_clk_init()	Wei Yongjun	1	-1/+1
2016-04-15	clk: mmp: Remove CLK_IS_ROOT	Stephen Boyd	1	-4/+4
2015-06-04	clk: mmp: add timer clock for pxa168/mmp2/pxa910	Chao Xie	1	-0/+7
2015-06-04	clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168	Chao Xie	1	-0/+1
2014-11-12	clk: mmp: add pxa168 DT support for clock driver	Chao Xie	1	-0/+279